Deep learning accelerator with camera interface and random access memory

Abstract

The present disclosure relates to systems, devices, and methods related to deep learning accelerators and memory. An integrated circuit can be configured to execute instructions with matrix operands and configured with a random access memory configured to store instructions executable by the deep learning accelerator and matrices of an artificial neural network, a connection between the random access memory and the deep learning accelerator, a first interface to a memory controller of a central processing unit, and a second interface to an image generator, such as a camera. While the deep learning accelerator processes a current input to the artificial neural network using the random access memory to generate a current output from the artificial neural network, the deep learning accelerator can concurrently load a next input from the camera into the random access memory; meanwhile, the central processing unit can concurrently retrieve a previous output from the random access memory.

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