Error correction code system with enhanced detection features

Abstract

Error correction code systems with enhanced detection features are disclosed. Various embodiments include error correction code (ECC) systems that provide protection against various errors in addition to data bit errors. Typically, ECC codes protect against data bit errors, where one or more data bits in a data word contain an erroneous value. ECC codes are based on the original data bits, such that a data bit error results in a data word that is inconsistent with an ECC code generated for and stored with the data word. Embodiments generate ECC codes based on address information and / or ordering information in addition to the data bits in the data word. Thus, embodiments detect bit errors in this address information and / or ordering information. Such errors include write address decode errors, read address decode errors, write enable errors, and stale data errors.

Description

TECHNICAL FIELD

[0001] Various embodiments relate generally to computer memory systems, and more particularly to error correction code systems with enhanced detection features. BACKGROUND

[0002] Among other things, a computer system typically includes one or more processors, such as central processing units (CPUs) and / or graphics processing units (GPUs), and one or more memory subsystems. The CPUs and / or GPUs can be integrated with other connection circuitry on a single chip to form a system on a chip (SoC). The memory subsystems store instructions that the processors execute to perform various tasks. During execution of these instructions, the processors store data in the memory subsystems and retrieve data from the memory subsystems. This data includes values that the processors access to perform tasks as specified by the instructions.

[0003] Embedded memories in SOCs are subject to transient errors and permanent faults. Transient errors, referred to herein as “soft errors,” are temporary errors that intermittently corrupt one or more data bits stored in a memory cell or that intermittently corrupt address decodes and / or related logic that determine which memory cells are written to during a store operation and read from during a load operation. In one example, a soft error occurs when an alpha particle strikes a memory cell or a portion of the logic circuitry that stores data in and loads data from the memory cell. Permanent errors, referred to herein as “hard errors,” are hardware errors that permanently damage a memory cell or address decodes and / or related logic. Typically, hard errors are repaired prior to shipment of the memory device, or alternatively, the memory device is discarded as a defective product. Even so, hard errors can occur in a memory system after the hardware is shipped. These soft and hard errors can cause corruption of instructions and / or associated data, resulting in unpredictable behavior. Accordingly, computer systems often employ mechanisms to mitigate soft and hard errors, especially in applications where security is of utmost concern, such as self-driving vehicles and other automotive applications. Further, these types of errors are more likely to occur as the size of the memory system increases.

[0004] To mitigate such errors, memory systems typically include error correcting code (ECC) systems. ECC systems detect and correct certain types of soft errors that occur within a particular group of memory cells that store data. The ECC system generates an ECC code that is stored when the associated data is written during a data store operation. When the data is subsequently read during a load operation, the ECC code is regenerated and compared to the ECC code stored in memory. A discrepancy in the data and / or the ECC code indicates an error. Certain ECC systems can detect and correct a single error bit, also referred to herein as a "corrupt bit," and can detect but not correct two or more error bits in a code word. This type of ECC system is referred to as a single error correction double error detection (SECDED) system. More advanced ECC systems can correct and / or detect 1-bit errors, 2-bit errors, 3-bit errors, etc. in a data word, depending on the complexity of the correction and / or detection scheme implemented.

[0005] One drawback of conventional ECC systems is that such ECC systems are typically capable of detecting errors in only one data word at any given time and are only capable of detecting data errors. Conventional ECC systems are not capable of detecting errors in multiple data words at the same time. Further, conventional ECC systems are not capable of detecting other types of errors, such as address decoder or other logic errors. These types of errors can cause a store operation to store correct data at an incorrect address or not store data at all in which it is supposed to be stored. Due to these types of errors, the data in memory is consistent with the associated ECC code, and thus the ECC system is not capable of detecting the data in memory, even though a memory error has occurred. One solution to this problem is to add additional memory to store additional ECC code associated with the address bits. If the address bits for a particular memory location and the ECC code associated with the address bits are not consistent, then an address error is detectable. However, this solution requires additional memory to store the ECC code, resulting in higher cost, more surface area, and higher power consumption.

[0006] Another drawback of conventional ECC systems is that when a computer system is first powered on, the memory typically contains random data. Thus, when the computer system is first powered on, the memory that stores data and the memory that stores the ECC code are typically not consistent with each other. As a result, the ECC system generates false ECC errors when reading the uninitialized memory. One solution to this problem is to initialize the memory when the computer system is first powered on by writing data along with consistent ECC code to each memory location. However, this initialization process can be time consuming, particularly for large memory systems, resulting in a long boot time.

[0007] As previously described, what is needed in the art is a more efficient technique for detecting memory failures in large computing systems. SUMMARY

[0008] Various embodiments of the present disclosure set forth a computer-implemented method for detecting errors in memory. The method includes retrieving first data associated with a first storage operation directed to a memory address. The method also includes generating a first error-correcting code (ECC) code based on the first data and at least one of address information and ordering information associated with the first storage operation. The method also includes storing the first data and the first ECC code at the memory address.

[0009] Other embodiments include, without limitation, systems implementing one or more aspects of the disclosed technology, and one or more computer-readable media comprising instructions for performing one or more aspects of the disclosed technology, and methods for performing one or more aspects of the disclosed technology.

[0010] At least one technical advantage of the disclosed technology over the prior art is that, with the disclosed technology, memory errors other than data errors are detectable by an ECC system without requiring additional memory to detect such errors. Thus, in addition to data errors, address decoder errors and memory write failures are detectable without substantially increasing cost, SoC surface area, or power consumption. Another technical advantage of the disclosed technology over the prior art is that false memory errors associated with uninitialized memory are suppressed, mitigating the need to initialize all memory locations when a computer system is first powered on. Thus, start-up time can be reduced relative to existing ECC methods. These advantages represent one or more technical improvements over prior art methods. BRIEF DESCRIPTION OF DRAWINGS

[0011] For a more detailed description of the relevant features of the various embodiments described above, reference is made to the detailed description of the invention concepts set forth above, which is to be read in connection with the various embodiments, some of which are illustrated in the drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments of the invention concepts and are therefore not to be considered limiting of their scope, for the invention concepts can admit to other equally effective embodiments.

[0012] Figure 1 is a block diagram of a computer system configured to implement one or more aspects of the various embodiments;

[0013] Figure 2 is a block diagram of a parallel processing unit (PPU) included in a parallel processing subsystem of Figure 1 is a block diagram of a parallel processing unit (PPU) included in a parallel processing subsystem of

[0014] Figure 3 is a block diagram of an error-correcting code (ECC) system associated with a computer system of Figure 1 is a block diagram of an error-correcting code (ECC) system associated with a computer system of

[0015] Figure 4 is a block diagram of an ECC generation circuit included in an ECC system according to various embodiments; Figure 3

[0016] Figure 5 is a block diagram of one of the ECC termination circuits included in an ECC system according to various embodiments; Figure 3

[0017] Figure 6 is a state diagram of a line buffer memory of an ECC system according to various embodiments; Figure 3

[0018] Figure 7 is a diagram of a memory access pipeline for a line buffer memory of an ECC system according to various embodiments; Figure 3

[0019] Figure 8 is a diagram of an organization of a line buffer memory included in an ECC system according to various embodiments; Figure 3

[0020] Figure 9 is a diagram of a memory write access pattern for a line buffer memory included in an ECC system according to various embodiments; Figure 3

[0021] Figure 10 is a diagram of a memory read access pattern for a line buffer memory included in an ECC system according to various embodiments; Figure 3

[0022] Figure 11 is a flowchart of method steps for generating an ECC code during a store operation of an ECC system according to various embodiments; and Figure 3

[0023] proposes a flowchart of method steps for generating and verifying an ECC code during a load operation of an ECC system according to various embodiments. Figures 12A-12B DETAILED DESCRIPTION Figure 3 In the following description, numerous specific details are set forth to provide a more thorough understanding of the embodiments. However, it will be apparent to one of skill in the art that the inventive concept can be practiced without one or more of these specific details.

[0024] System Overview

[0025] System Overview

[0026] Figure 1 ​​​​​​​​is a block diagram of a computer system 100 configured to implement one or more aspects of the various embodiments. As shown, the computer system 100 includes, but is not limited to, a central processing unit (CPU) 102, a system memory 104, which is coupled via a memory bridge 105 and communication path 113 to a parallel processing subsystem 112. The memory bridge 105 is further coupled via a communication path 106 to an I / O (input / output) bridge 107, which is in turn coupled to a switch 116.

[0027] In operation, the I / O bridge 107 is configured to receive user input information from input devices 108, such as a keyboard or mouse, and to forward the input information via the communication path 106 and the memory bridge 105 to the CPU 102 for processing. The switch 116 is configured to provide connectivity between the I / O bridge 107 and other components of the computer system 100, such as a network adapter 118 and various add-in cards 120 and 121.

[0028] Also as shown, the I / O bridge 107 is coupled to a system disk 114, which can be configured to store content, applications, and data for use by the CPU 102 and the parallel processing subsystem 112. In general, the system disk 114 provides non-transitory storage for applications and data, and can include a fixed or removable hard disk drive, flash memory device, and CD-ROM (compact disk - read only memory), DVD-ROM (digital versatile disk - ROM), Blu-ray, HD-DVD (high definition DVD) or other magnetic, optical, or solid state storage devices. Finally, while not explicitly shown, other components such as universal serial bus or other port connections, optical disk drives, digital versatile disk drives, tape storage devices, etc. can also be connected to the I / O bridge 107.

[0029] In various embodiments, the memory bridge 105 can be a northbridge chip, and the I / O bridge 107 can be a southbridge chip. Further, the communication paths 106 and 113, as well as other communication paths within the computer system 100, can be implemented in any technically suitable protocol, including but not limited to AGP (accelerated graphics port), HyperTransport, or any other bus or point-to-point communication protocol known in the art.

[0030] In some embodiments, the parallel processing subsystem 112 includes a graphics subsystem that delivers pixels to a display device 110, which can be any conventional cathode ray tube, liquid crystal display, light emitting diode display, or the like. In such embodiments, the parallel processing subsystem 112 incorporates circuitry optimized for graphics and video processing, including, for example, a video output circuit. As Figure 2As described in more detail in , such circuitry may be incorporated across one or more parallel processing units (PPUs) included in parallel processing subsystem 112. In other embodiments, parallel processing subsystem 112 incorporates circuitry optimized for general-purpose and / or computational processing. Likewise, such circuitry may be incorporated across one or more PPUs included in parallel processing subsystem 112 that are configured to perform such general-purpose and / or computational operations. In other embodiments, one or more PPUs included in parallel processing subsystem 112 may be configured to perform graphics processing, general-purpose processing, and computational processing operations. System memory 104 includes at least one device driver 103 that is configured to manage processing operations of one or more PPUs in parallel processing subsystem 112.

[0031] In various embodiments, the parallel processing subsystem 112 may be configured to Figure 1 For example, parallel processing subsystem 112 may be integrated with CPU 102 and other connected circuits on a single chip to form a system on a chip (SoC).

[0032] It should be understood that the system shown herein is illustrative, and variations and modifications are possible. The connection topology (including the number and arrangement of bridges, the number of CPUs 102, and the number of parallel processing subsystems 112) can be modified as needed. For example, in some embodiments, system memory 104 can be directly connected to CPU 102, rather than being connected to CPU 102 through memory bridge 105, and other devices will communicate with system memory 104 via memory bridge 105 and CPU 102. In other alternative topologies, parallel processing subsystem 112 can be connected to I / O bridge 107 or directly to CPU 102, rather than being connected to memory bridge 105. In other embodiments, I / O bridge 107 and memory bridge 105 can be integrated into a single chip, rather than existing as one or more discrete devices. Finally, in some embodiments, Figure 1 One or more of the components shown may not be present. For example, switch 116 may be eliminated, with network adapter 118 and add-in cards 120 and 121 connected directly to I / O bridge 107.

[0033] Figure 2 According to various embodiments Figure 1 A block diagram of a parallel processing unit (PPU) 202 included in the parallel processing subsystem 112 of FIG. Figure 2One PPU 202 is depicted, as described above, but the parallel processing subsystem 112 may include any number of PPUs 202. As shown, the PPU 202 is coupled to a local parallel processing ("PP") memory 204. The PPU 202 and the PP memory 204 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application-specific integrated circuit (ASIC), or a memory device, or in any other technically feasible manner.

[0034] In some embodiments, PPU 202 includes a graphics processing unit ("GPU") that can be configured to implement a graphics rendering pipeline to perform various operations related to generating pixel data based on graphics data provided by CPU 102 and / or system memory 104. When processing graphics data, PP memory 204 can be used as graphics memory to store one or more conventional frame buffers (and, if desired, one or more other render targets). PP memory 204 can be used to, among other things, store and update pixel data and transmit the final pixel data, or display frame, to display device 110 for display. In some embodiments, PPU 202 can also be configured for general processing and computational operations.

[0035] In operation, CPU 102 is the main processor of computer system 100, controlling and coordinating the operations of other system components. In particular, CPU 102 issues commands that control the operation of PPU 202. In some embodiments, CPU 102 writes a command stream for PPU 202 into a data structure ( Figure 1 or Figure 2 The data structure may be located in system memory 104, PP memory 204, or another storage location accessible to both CPU 102 and PPU 202 (not explicitly shown). A pointer to the data structure is written to a push buffer to initiate processing of the command stream in the data structure. PPU 202 reads the command stream from the push buffer and then executes the commands asynchronously with respect to the operation of CPU 102. In embodiments where multiple push buffers are generated, the application can specify an execution priority for each push buffer via device driver 103 to control the scheduling of the different push buffers.

[0036] As also shown, PPU 202 includes an I / O (input / output) unit 205 that communicates with the rest of computer system 100 via communication path 113 and memory bridge 105. I / O unit 205 generates data packets (or other signals) to be transmitted on communication path 113 and also receives all incoming data packets (or other signals) from communication path 113, directing the incoming data packets to the respective components of PPU 202. For example, commands related to processing tasks can be directed to host interface 206, while commands related to memory operations (e.g., reading from or writing to PP memory 204) can be directed to crossbar unit 210. Host interface 206 reads each push buffer and sends the command stream stored in the push buffer to front end 212.

[0037] As described above in connection with Figure 1 The connection of PPU 202 to the rest of computer system 100 can vary in different embodiments. In some embodiments, parallel processing subsystem 112, which includes at least one PPU 202, is implemented as an add-in card that can be inserted into a expansion slot of computer system 100. In other embodiments, PPU 202 can be integrated on a

[0038] In operation, front end 212 sends processing tasks received from host interface 206 to a work distribution unit (not shown) within task / work unit 207. The work distribution unit receives pointers to processing tasks, which are encoded as task metadata ("TMD") and stored in memory. The pointers to the TMD are included in the command stream that is stored as a push buffer and received by front end unit 212 from host interface 206. The processing tasks that can be encoded as TMD include an index associated with data to be processed, as well as state parameters and commands that define how the data is to be processed. For example, the state parameters and commands can define a program to be executed on the data. Task / work unit 207 receives tasks from front end 212 and ensures that GPCs 208 are configured in an effective state before starting a processing task specified by each TMD. A priority can be specified for each TMD that is used to schedule execution of the processing tasks. Processing tasks can also be received from processing cluster array 230. Optionally, the TMD can include a parameter that controls whether the TMD is added to the head or tail of a list of processing tasks (or a list of pointers to processing tasks), thereby providing another level of control over the priority of execution.

[0039] PPU 202 advantageously implements a highly parallel processing architecture based on an array of processing clusters 230, which includes a group of C processing clusters (GPCs) 208, where C > 1. Each GPC 208 is capable of simultaneously executing a large number (e.g., hundreds or thousands) of threads, where each thread is an instance of a program. In various applications, different GPCs 208 can be allocated to processing different types of programs or performing different types of computations. The allocation of GPCs 208 can vary depending on the workload of each type of program or computation.

[0040] Memory interface 214 includes a set of D partition units 215, where D > 1. Each partition unit 215 is coupled to one or more dynamic random access memories (DRAMs) 220 that reside within PPM memory 204. In one embodiment, the number of partition units 215 is equal to the number of DRAMs 220, with each partition unit 215 coupled to a different DRAM 220. In other embodiments, the number of partition units 215 can be different from the number of DRAMs 220. One of ordinary skill in the art will recognize that DRAMs 220 can be replaced by any other technically suitable storage device. In operation, various render targets, such as texture maps and frame buffers, can be stored across DRAMs 220, allowing partition units 215 to write portions of each render target in parallel, thereby effectively using the available bandwidth of PPM memory 204.

[0041] A given GPC 208 can process data to be written to any of the DRAMs 220 within PPM memory 204. Crossbar unit 210 is configured to route the output of each GPC 208 to the input of any partition unit 215 or any other GPC 208 for further processing. GPCs 208 communicate with memory interface 214 via crossbar unit 210 to read from or write to various DRAMs 220. In one embodiment, crossbar unit 210 connects GPCs 208, via memory interface 214, with PP memory 204, thereby enabling processing cores within the different GPCs 208 to communicate with system memory 104 or other memory that is not local to PPU 202. In Figure 2 In embodiments, crossbar unit 210 is connected with I / O unit 205. In various embodiments, crossbar unit 210 can use virtual channels to separate traffic between GPCs 208 and partition units 215.

[0042] Likewise, GPC 208 can be programmed to perform processing tasks related to a wide variety of applications, including, but not limited to, linear and nonlinear data transforms, filtering of video and / or audio data, modeling operations (e.g., application of physical laws such as fluid mechanics to determine the efficiency of an internal combustion engine), image rendering operations (e.g., use of vertex and fragment shader programs to determine visual appearance of a scene), general compute operations, etc. In operation, PPU 202 is configured to transfer data from system memory 104 and / or PP memory 204 to one or more on-chip memory units, process the data, and write results to system memory 104 and / or PP memory 204. Other system components (including CPU 102, another PPU 202 in parallel processing subsystem 112, or another parallel processing subsystem 112 in computer system 100) can access the results data.

[0043] As noted above, any number of PPUs 202 can be included in parallel processing subsystem 112. For example, a plurality of PPUs 202 can be provided on a single add-in card, or multiple add-in cards can be connected to communication path 113, or one or more PPUs 202 can be integrated into a

[0044] Although Figure 2not shown, but each processor within GPC 208 includes a level one (LI) cache or uses spaces in a corresponding LI cache external to the processor to support load and store operations particularly executed by the execution unit. Each processor within GPC 208 can also access a level two (L2) cache (not shown) shared between all GPCs 208 in PPU 202. The L2 cache can be used to transfer data between threads executing on the same GPC 208. Finally, a processor within GPC 208 can also access off-chip “global” memory, which can include PP memory 204 and / or system memory 104. It should be understood that any memory external to PPU 202 can be used as global memory. Further, a level one and a half (LI.5) cache (not shown) can be included within GPC 208 and configured to receive and hold data requested from memory by processors within GPC 208 via memory interface 214. Such data can include, without limitation, instructions, uniform data, and constant data. In embodiments having multiple processors within GPC 208, these processors can beneficially share common instructions and data cached in the LI.5 cache.

[0045] It should be understood that the core architecture described herein is illustrative, and variations and modifications are possible. For example, any number of processing units can be included in GPC 208. Further, as described above in connection with Figure 2 the PPU 202 can include any number of GPCs 208 configured to be functionally similar to one another such that the execution behavior is not dependent on which GPC 208 receives a particular processing task. Further, each GPC 208 operates independently of the other GPCs 208 in PPU 202 to execute one or more applications task. In light of the foregoing, those of ordinary skill in the art will appreciate Figures 1-2 the architecture described in the foregoing is in no way limiting to the scope of various embodiments of the present disclosure.

[0046] Note that, as used herein, a reference to shared memory can include any one or more technically feasible memories, including but not limited to local memory shared by one or more processors within GPC 208, or memory accessible via memory interface 214, such as cache memory, parallel processing memory 204, or system memory 104. Also note that, as used herein, a reference to cache memory can include any one or more technically feasible memories, including but not limited to LI cache, LI.5 cache, and L2 cache.

[0047] Error correction code system with enhanced detection features

[0048] An error correction code (ECC) system is disclosed that can detect various system errors in addition to data bit errors. More specifically, the ECC system detects write address decode errors, read address decode errors, write enable errors, stale data errors, and the like. Write address decode errors cause data to be written to an incorrect memory address during a store operation. Similarly, read address decode errors cause data to be read from an incorrect memory address during a load operation. Write enable failures cause one or more devices to be unable to write data during a store operation or to read data during a load operation. A stale data error occurs when a successfully written memory location is subjected to a completely failed subsequent write. This condition leaves a memory address with data from the first write. In some embodiments, the disclosed ECC system can detect one error of any type at a given time. In some embodiments, the disclosed ECC system can detect certain combinations of multiple such errors. Conventional ECC systems cannot detect these additional types of errors unless the ECC code is stored in a separate memory and separate writes to that separate memory do not fail.

[0049] Additional errors are detected by relying on two properties. First, the ECC system disclosed herein generates an ECC code from address and ordering information as well as from data bits. In addition to data bits, the input to the ECC system is augmented to include a read address, a write address, and a write enable mask (in the case of a line buffer memory) or a write pointer and a read pointer (in the case of a first-in-first-out (FIFO) memory). The input to the ECC system is further augmented to include ordering information such as a line number, a loop pixel block count, and a frame count (in the case of a line buffer memory) or a sequence number (in the case of a FIFO memory). More specifically, in a FIFO memory, the write pointer and the read pointer, which specify addresses within the FIFO memory, are augmented with one or more bits that indicate a loop count.

[0050] Second, certain memories, such as line buffer memories and FIFO memories, have regular, predictable write access patterns and read access patterns. In such memories, the address and ordering information generated during a store operation can be regenerated during a load operation. Thus, the address and ordering information need not be stored in the memory, even though the address and ordering information are used to generate the ECC code. Instead, only the data bits and the ECC code are stored in the memory. The disclosed techniques are applicable to any memory system that has a regular or predictable access pattern, such as line buffer memories, FIFO memories, read-modify-write memory systems, and / or the like.

[0051] Further, certain memories, such as line buffer memories, have one storage circuit but have multiple load circuits. This feature allows multiple memory lines, such as 20 memory lines, to be read simultaneously during a load operation. The disclosed ECC system includes one ECC generation circuit that serves multiple memory lines and a separate ECC termination circuit for each memory line. Thus, the ECC system is able to correct and / or detect multiple errors per memory load operation - one error per memory line stored in the line buffer memory. Because only one ECC generation circuit on the storage side of the line buffer memory is needed to support multiple ECC termination circuits on the load side of the line buffer memory, the hardware cost in terms of die area and power consumption is roughly half that of the conventional approach that includes one ECC generation circuit and one ECC termination circuit for each memory line in the line buffer memory.

[0052] In addition, the ECC system generates an active indicator based on the tracking word mask. ECC errors are enabled for memory lines that are determined to be active and ECC errors are disabled for memory lines that are determined to be inactive. Thus, the ECC system eliminates the need for an initialization pass at boot-up or system power-up. If a portion of the memory that is not initialized is read, any false errors due to the uninitialized memory are filtered by the tracking word mask.

[0053] Figure 3 is a block diagram of an error-correcting code (ECC) system 300 associated with the computer system 100 in accordance with various embodiments. Figure 1 is a block diagram of an error-correcting code (ECC) system 300 associated with the computer system 100 in accordance with various embodiments.

[0054] In operation, the enhancement data generator 310 generates enhancement data for the store operation, including address information and sequencing information. As shown, the enhancement data generator 310 generates a block number T[7:0] 308, a Y coordinate Y[6:0] 306, a write address WA[8:0] 304, and a write enable 334. In some embodiments, the write enable 334 can be a 20-bit field, where different bits of the write enable 334 are sent to each of different ones of the line buffer memories 330. In such embodiments, the 20-bit write enable 334 20-bit field can be a copy of the WE[19:0] bits 312 sent to the error injection port, as described herein. The block number T[7:0] 308 is an 8-bit rolling counter that cycles every 256 blocks. In image processing, images are often divided into rectangular blocks arranged in horizontal and vertical grids. The block number identifies which block in the image is currently being processed. The Y coordinate [6:0] 306 includes the 7 least significant bits of the Y coordinate within the image being written to the line buffer memory 330. Additionally or alternatively, the Y coordinate [6:0] 306 contains the 7 least significant bits of the Y coordinate within the block. The write address WA[8:0] 304 includes the 9 least significant bits of the address being written in the line buffer memory 330. Because the X coordinate within a block is typically incremented in the same step size as the write address, the least significant bits of the write address WA[8:0] 304 represent the X coordinate within the block being written to the line buffer memory 330. The write enable WE 334 enables writing to the appropriate memory address in the line buffer memory 330. The enhancement data generator 310 sends the block number T[7:0] 308, the Y coordinate Y[6:0] 306, and the write address WA[8:0] 304 to the ECC generation circuit 320. In addition, the enhancement data generator 310 sends the write address WA[8:0] 304 and the write enable 334 to the line buffer memory 330.

[0055] In operation, the ECC generation circuit 320 generates an ECC code from a 96-bit word of pixel data PD[95:0] 302 and from the block number T[7:0] 308, Y coordinate Y[6:0] 306, and write address WA[8:0] 304 received from the enhancement data generator 310. The 96-bit data word represents two pixels of 48 bits per pixel. Typically, a pixel is represented by three components of 16 bits each. In some embodiments, the three components can include Y, U, and V components, where Y is a 16-bit luminance value and U and V are 16-bit color difference components. In some embodiments, the three components can include R, G, and B components, where R, G, and B are red, green, and blue color components, respectively. In some embodiments, the number of bits in each data word, the number of components in each data word, and the number of bits in each component of a data word can be any technically feasible amount. Further, the data stored within each data word can be pixel data in any technically feasible format and / or non-pixel data in any technically feasible combination.

[0056] The number of error bits required to generate a SECDEC ECC code is X = log2(number of protected bits) + 1, rounded up to the next whole number. As shown, for a total of 96 + 8 + 7 + 9 = 120 protected bits, the number of protected bits is 96 data bits, 8 block number bits, 7 Y address bits, and 9 write address bits. Thus, the ECC code is X = log2(120) + 1 = 8 bits when rounded up. By including 8 block number bits, 7 Y address bits, and 9 write address bits in the generation of the ECC code, the ECC code protects against errors in those additional fields. Errors in the block number, Y address, and / or write address can cause address decoding errors, write enable masking errors, stale data errors, and / or similar errors. In addition to data bit errors, the ECC generation circuit 320 protects against these types of errors. In various embodiments, the ECC code can include any technically feasible number of bits, depending on the number of detectable error bits, the number of correctable error bits, and the encoding scheme used for the ECC code.

[0057] As a point of comparison, if only 96-bit data words are protected, the ECC code would be X = log2(96) + 1 = 8 bits after rounding up. Thus, protecting against errors in the additional block number bits, Y address bits, and write address bits does not result in additional bits in the ECC code. Thus, no additional memory is needed to protect the additional block number bits, Y address bits, and write address bits. More generally, when the rounding up result of X = log2(number of protected bits) + 1 is increased by 1 to the next integer, the number of ECC bits in the ECC code is increased by 1. This condition is referred to as crossing a binary, where a binary is a range that is a power of 2. For example, from 64 to 127 is a binary that represents 7 bits (corresponding to an 8-bit ECC code). The next binary, from 128 to 255, represents 8 bits (corresponding to a 9-bit ECC code). The next binary, from 256 to 511, represents 9 bits (corresponding to a 10-bit ECC code), and so on. With this approach, if the enhanced data field is added to the data bits without crossing a binary, no additional bits are needed in the ECC code.

[0058] Additionally or alternatively, the ECC generation circuit 320 can generate the ECC code via any technically feasible technique. In some embodiments, the ECC generation circuit 320 can employ a Reed-Solomon code to generate the ECC code. In such embodiments, the number of bits in the ECC code can differ from the number of bits using the approach described above for a given number of protected bits. Even so, any reasonable approach to generating the ECC code results in no or a small number of additional ECC code bits in order to protect the enhanced data in addition to the input data.

[0059] The ECC generation circuit 320 includes error injection ports for testing purposes. Error injection is selected on a per-line basis, each line having separate injection controls for single error injection and double error injection. The WE[19:0] bits 312 select a memory line in the line buffer memory 330 to receive an injected error. When the WE[19:0] bits 312 are asserted, the corresponding injection SE[19:0] inputs 314 cause the ECC generation circuit 320 to inject a single-bit error into the selected memory line. Similarly, when the WE[19:0] bits 312 are asserted, the corresponding injection DE[19:0] inputs 316 cause the ECC generation circuit 320 to inject a double-bit error into the selected memory line. If, for the currently asserted bit in the WE[19:0] bits 312, the corresponding injection SE[19:0] inputs 314 are free of errors, then no single-bit error is injected into the selected memory line. Similarly, if, for the currently asserted bit in the WE[19:0] bits 312, the corresponding injection DE[19:0] inputs 316 are free of errors, then no double-bit error is injected into the selected memory line.

[0060] In generating the ECC code, the ECC generation circuit 320 sends only the 96-bit data word and the 8-bit ECC code as RAM data in [103:0] 342 to the line buffer memory 330. The extra 24 bits of the block number, Y address, and write address are removed and are not stored in the line buffer memory 330.

[0061] In operation, the line buffer memory 330 stores the pixel data and ECC code received from the ECC generation circuit 320. Each write to the line buffer memory 330 stores 96 bits of pixel data (two pixels) and 8 bits of ECC code in [103:0] 342 as RAM data. The ECC code protects against errors in the data bits as well as against errors in the additional fields from which the ECC code was generated, including the block address bits, Y coordinate bits, and write address bits. During a store operation, the line buffer memory 330 stores 96 bits of pixel data and 8 bits of ECC code in one of 20 memory lines 332(0), 332(1),... 332(19), also referred to herein as RAM lines 332. The line buffer memory 330 stores the pixel data and ECC code in a particular memory line 332 specified by the write address WA[8:0] 304 and the write enable 334. During a load operation, the line buffer memory 330 sends 96 bits of pixel data and 8 bits of ECC code in all 20 memory lines 332(0), 332(1),... 332(19). The line buffer memory 330 loads the pixel data and ECC code from a particular memory line 332 as specified by the read address RA[8:0] 354. The line buffer memory 330 presents 104 bits (2080 bits total) of each of the 20 memory lines 332 as RAM data out[2079:0] 352.

[0062] In operation, the enhancement data regenerator 340 regenerates the enhancement data for the load operation, including the address information and the sequencing information. As shown, the enhancement data regenerator 340 generates the block number T[7:0] 358, the 20 Y coordinates Y[6:0] 356 of the 20 memory lines 332, and the read address RA[8:0] 304. Because the read access pattern of the line buffer memory 330 is the same as the write access pattern of the line buffer memory 330, the enhancement data regenerator 340 regenerates the same enhancement data in the same order as generated by the enhancement data generator 310 during the store operation.

[0063] In addition, the enhanced data regenerator 340 generates 20 valid bits 362 for the 20 memory lines 332. During certain image processing operations, data is read from multiple memory lines 332 that represent pixels from image lines above the current pixel and from image lines below the current pixel as well as from the same image line as the current pixel. For example, when processing a 21 x 21 pixel region, data is read from 10 image lines above the current pixel and 10 image lines below the pixel in addition to data from the image line that includes the current pixel. As shown, pixel data and ECC codes are read from all 20 memory lines 332 simultaneously and sent to the respective ECC termination circuits 350.

[0064] However, when processing pixels at the top of the image, there can be fewer than 10 image lines above the current pixel. Similarly, when processing pixels at the bottom of the image, there can be fewer than 10 image lines below the current pixel. For example, if the current pixel is on line 0, the first line of the image, then the ten lines above the current pixel are invalid, while the ten lines below the current pixel are valid. If the current pixel is on line 5, the sixth line of the image, then the five lines above the current pixel (lines 0 through 4) are valid, but the five lines above line 0 are invalid. Similarly, if the current pixel is on the last line of the image, then the ten lines below the current pixel are invalid, while the ten lines above the current pixel are valid. If the current pixel is on the sixth line at the bottom of the image, then the five lines below the current pixel are valid, but the five lines below the last line of the image are invalid.

[0065] Accordingly, the enhanced data regenerator 340 generates a valid bit 362 for each of the 20 memory lines 332. If the valid bit is set for a particular memory line 332, then the data stored in that memory line 332 includes image data from an actual image line. If the valid bit is not set for a particular memory line 332, then the data stored in that memory line 332 can be random or stale because the memory line 332 is above the first line of the image or below the last line of the image. By generating the valid bits, the enhanced data regenerator 340 eliminates the need for an initialization pass to store valid pixel data and ECC codes in the line buffer memory 330 at boot or power up.

[0066] The enhanced data regenerator 340 sends the block number T[7:0] 358, the Y coordinate 20 x Y[6:0] 356, the read address RA[8:0] 354, and the 20 valid bits 362 to the ECC termination circuits 350. In addition, the enhanced data regenerator 340 sends the read address RA[8:0] 354 to the line buffer memory 330.

[0067] In operation, each of the ECC termination circuits 350(0), 350(1),... 350(19) verifies the ECC code for the corresponding memory line 332(0), 332(1),... 332(19). The ECC termination circuit 350 generates the ECC code from a 96-bit word of pixel data received from the corresponding memory line 332 and the block number T[7:0] 358, the Y coordinate Y[6:0] 356, and the read address RA[8:0] 354 received from the enhanced data regenerator 340. The 96-bit data word represents two pixels of 48 bits per pixel. The ECC termination circuit 350 compares the generated ECC code to the ECC code received from the corresponding memory line 332. If the generated ECC code is equal to the ECC code received from the corresponding memory line 332, the ECC termination circuit 350 indicates that no memory error has occurred. If the generated ECC code is not equal to the ECC code received from the corresponding memory line 332, the ECC termination circuit 350 indicates that a memory error has occurred.

[0068] If the memory error is a data bit error, the ECC termination circuit 350 detects and / or corrects the error depending on the ability of the ECC termination circuit 350 to detect and correct 1-bit errors, 2-bit errors, 3-bit errors, etc. If the memory error is an error in the enhanced addressing and sequencing information, the error can be more severe, such as writing a data word to an incorrect memory address or failing to write data to memory. Thus, if the memory error is an error in the enhanced addressing and sequencing information, the ECC termination circuit 350 forces a double-bit error or otherwise indicates that the detected error is uncorrectable. If the ECC termination circuit 350 detects and corrects a single-bit error, the ECC termination circuit 350 sends an indicator on the corresponding bit in the single-bit error correction field SECout[19:0] 384. If the ECC termination circuit 350 detects a double-bit error or otherwise forces a double-bit error, the ECC termination circuit 350 sends an indicator on the corresponding bit in the double-bit error detection field DED out[19:0] 386.

[0069] The ECC termination circuit 350 also receives a valid bit 362 from the enhanced data regenerator 340. If the valid bit 362 is set, the ECC termination circuit 350 validates the ECC code as described herein. If the valid bit 362 is not set, the pixel data and / or the ECC code received from the memory line 332 is not initialized or otherwise invalid. In such a case, the ECC termination circuit 350 did not detect and / or correct any memory errors during the corresponding load operation. After validating the ECC code, or ignoring the ECC code if the valid bit is not set, the ECC termination circuit 350 sends the 96-bit pixel data word to the line rotation circuit 360. In total, the ECC termination circuit 350 sends 20 x 96-bit = 1920-bit pixel data as raw data out[1919:0] 372 to the line rotation circuit 360.

[0070] In operation, the line rotation circuit 360 performs a barrel shift on the pixel data received from the ECC termination circuit 350 as raw data out[1919:0]. In certain image processing operations, the current pixel is advantageously in a particular location in the pixel array, while other pixels (e.g., pixels from image lines above and / or below the current pixel) are in certain other locations. However, the pixel data received from the various ECC termination circuits 350 can not have the current pixel in the proper location. Accordingly, the line rotation circuit 360 rotates the raw data out[1919:0] received from the ECC termination circuit 350 to place the current pixel in the proper location. After rotating the raw data out[1919:0], the line rotation circuit 360 sends data out[1919:0] 382 with the current pixel in the correct location.

[0071] Figure 4 is included in a system according to various embodiments Figure 30] 304 . The ECC generation circuit 320 is a block diagram of an ECC generation circuit 320 in an ECC system 300. As shown, the ECC generation circuit 320 includes, but is not limited to, an ECC generator 410 and an injection selector 420. As described herein, the ECC generation circuit 320 receives pixel data PD[95:0] 302 representing three 16-bit pixel components for each of two pixels in an image. Furthermore, the ECC generation circuit 320 receives a block number T[7:0] 308, a Y coordinate Y[6:0] 306, and a write address WA[8:0] 304 from the enhancement data generator 310. The ECC generation circuit 320 generates an ECC code based on the pixel data PD[95:0] 302, as well as the block number T[7:0] 308, the Y coordinate Y[6:0] 306, and the write address WA[8:0] 304. The ECC generation circuit 320 transmits the ECC code as ECC out[7:0] 426. The ECC generation circuit 320 also transmits the received pixel data and additional data as data out[119:96] 422 and data out[95:0] 424 .

[0072] The ECC generation circuit 320 is capable of injecting errors for testing purposes into specific memory lines 332 of the line buffer memory 330 via an injection selector 420. During normal operation, the write enable [19:0] 312 is inactive, and the ECC generation circuit 320 generates ECC codes as described herein. To inject an error on one of the twenty memory lines 332, the corresponding write enable [19:0] 312 is asserted, and an error input is presented on the corresponding injection SE [19:0] input 314 or injection DE [19:0] input 316. To inject a single-bit error, the injection selector selects the corresponding injection SE [19:0] input 314 and sends the injection SE [19:0] input 314 to the ECC generator 410 as injection SE sel 414. When the ECC generator 410 generates an ECC code for the selected memory line 332, the ECC generator 410 intentionally generates an ECC code indicating a single-bit error. Similarly, to inject a double-bit error, the injection selector selects the corresponding injection DE[19:0] input 316 and sends the injection DE[19:0] input 314 to the ECC generator 410 as injection DE sel 416. When the ECC generator 410 generates an ECC code for the selected memory line 332, the ECC generator 410 purposefully generates an ECC code indicating a double-bit error.

[0073] After generating the ECC code and optionally injecting a single-bit error or a double-bit error in the ECC code, the ECC generation circuit 320 sends the data out[95:0] 424 representing the pixel data to the line buffer memory 330. The ECC generation circuit 320 discards the data out[119:96] 422 representing the block number T[7:0] 308, the Y coordinate Y[6:0] 306, and the write address WA[8:0] 304. The ECC generation circuit 320 combines the ECC out[7:0] and the data out[95:0] 424 and sends the combined data as the RAM data in[103:0] to the line buffer memory 330.

[0074] Figure 5 is included in a device according to various embodiments Figure 3FIG. 5 is a block diagram of one of the ECC termination circuits 350 in the ECC system 300. As shown, the ECC termination circuit 350 includes, but is not limited to, an ECC terminator 510. The ECC termination circuit 350 receives the RAM data out [103:0] from the corresponding memory line 332. The ECC termination circuit 350 separates the RAM data out [103:0] into two fields. The first field is the ECC in [7:0] 502, which represents the ECC code stored in the corresponding memory line 332. The second field is the data in [95:0] 504, which represents the pixel data stored in the corresponding memory line 332. In addition, the ECC termination circuit 350 receives the block number T [7:0] 358 sent from the enhancement data regenerator 340, the corresponding Y coordinate Y [6:0] 356 of the corresponding memory line 332, the read address RA [8:0] 354, and the corresponding valid bit 362. The ECC termination circuit 350 generates the ECC code from the data in [95:0] 504 received from the respective memory line 332 and the block number T [7:0] 358, the Y coordinate Y [6:0] 356, and the read address RA [8:0] 354 received from the enhancement data regenerator 340. The ECC termination circuit 350 compares the generated ECC code to the ECC code received from the corresponding memory line 332. If the generated ECC code is equal to the ECC code received from the corresponding memory line 332, the ECC termination circuit 350 indicates that no memory error has occurred. If the generated ECC code is not equal to the ECC code received from the corresponding memory line 332, the ECC termination circuit 350 indicates that a memory error has occurred. If the ECC termination circuit 350 detects and corrects a single-bit error, the ECC termination circuit 350 sends an indication on the SEC out [1:0] 384. If the ECC termination circuit 350 detects a double-bit error, the ECC termination circuit 350 sends an indication on the DED out [1:0] 386. Further, as described herein, if the memory error is an error in the enhanced addressing and sequencing information, the error can be more severe, such as writing a data word to an incorrect memory address or failing to write data to the memory. Accordingly, if the memory error is an error in the enhanced addressing and sequencing information, the ECC termination circuit 350 forces a double-bit error or otherwise indicates that the detected error is uncorrectable.

[0075] The ECC termination circuit 350 also receives a valid bit 362 from the enhanced data regenerator 340. If the valid bit 362 is set, the ECC termination circuit 350 verifies the ECC code as described herein. If the valid bit 362 is not set, the pixel data and / or ECC code received from the memory line 332 is not initialized or is otherwise invalid. In this case, the ECC termination circuit 350 does not detect and / or correct any memory errors during the corresponding load operation. After verifying the ECC code, or ignoring the ECC code if the valid bit is not set, the ECC termination circuit 350 sends the 96-bit pixel data word to the line rotation circuit 360. The ECC termination circuit 350 sends the data, including the corrections to the data, as raw data out[95:0] 372 to the line rotation circuit 360.

[0076] It will be understood that the systems shown herein are illustrative and that variations and modifications are possible. Figures 4-6 As shown in FIG, the ECC system 300 generates and verifies the ECC code based on 96 data bits, 8 block number bits, 7 Y coordinate bits, and 9 write / read address bits. However, within the scope of the present disclosure, the ECC system 300 may generate and verify the ECC code based on fewer or more bits of one or more of these fields. Further, the ECC system 300 may generate and verify the ECC code based on more than Figures 4-6 The ECC code may be generated and verified with fewer or more fields than those shown in the example. Additional fields may include a write enable 334, a field number, and the like. In one example, the ECC system 300 may include a frame number that is sequenced across multiple image frames. For example, a two-digit frame number would count over a sequence of four frames. Within a given image frame, each pixel has a unique block number, Y coordinate, and write / read address (i.e., X coordinate). Adding frame numbers to the ECC system 300 additionally provides temporal protection for multiple image frames, such as failure to store a pixel in a particular frame. Such failures can be detected during a subsequent frame load operation, where stale pixel data is loaded from a previous image frame. In another example, the ECC system 300 may include a stream number that identifies the source of data stored in the line buffer memory 330 of the ECC system 300. For example, if the ECC system 300 receives data from up to eight cameras, a stream number comprising at least three digits can identify the camera that sent a particular data set to the ECC system 300. If ECC system 300 receives data from eight cameras in a particular pattern, such as a cyclic pattern that cycles through the eight cameras, the stream numbers need not be stored in line buffer memory 330. Instead, the stream numbers may be regenerated by enhanced data regenerator 340 in the manner described herein.

[0077] like Figures 4-6As shown in FIG. 3, the line buffer includes one ECC generation circuit 320 and 20 ECC termination circuits 350 to support 20 memory lines 332 in the line buffer 330. Thus, the ECC system 300 simultaneously detects and / or corrects one ECC error in each of the 20 memory lines 332, or simultaneously detects and / or corrects up to 20 ECC errors. Alternatively, it is within the scope of the present disclosure for the ECC system 300 to include any technically feasible number of ECC generation circuits 320, ECC termination circuits 350, and / or memory lines 332.

[0078] The technology disclosed herein is deployed in the context of a line buffer 330, such as for image processing and similar applications. However, the disclosed technology can be deployed in any memory system having regular, predictable write and read access patterns, such as a first-in-first-out (FIFO) memory, a read-modify-write memory system, and the like. In a particular example, a FIFO memory is essentially a circular buffer that traverses a circular memory. Initially, when the FIFO memory is empty, a write pointer is set to zero. As data is stored in memory addresses in the FIFO memory, the write pointer is incremented to point to the next available memory address. When the last memory address of the FIFO memory is written to, the write pointer is reset or loops back to the first memory address in the FIFO memory. Similarly, when the FIFO memory is initially empty, a corresponding read pointer is set to zero. Data is stored in the FIFO memory by the write pointer, and subsequently the data is loaded from the FIFO memory by the read pointer. As data is loaded from memory addresses in the FIFO memory, the read pointer is incremented to point to the next memory address with stored data. When the last memory address of the FIFO memory is read, the read pointer is reset or loops back to the first memory address in the FIFO memory.

[0079] When data is stored in the FIFO memory and later loaded from the FIFO memory, an empty condition is indicated when the read pointer and the write pointer are equal, thereby pointing to the same buffer address on the same access cycle of the FIFO memory. Similarly, a full condition is indicated when the read pointer and the write pointer are equal, thereby pointing to the same buffer address, but with the write pointer one access cycle ahead of the read pointer.

[0080] The ECC system can generate the ECC code based on both the data stored in the FIFO memory and the write / read pointers. However, because the pattern of the write and read pointers is regular and predictable, the write / read pointers need not be stored in memory. Instead, the write pointer can be generated and the read pointer regenerated in a similar manner to the techniques described in connection with the ECC system 300 of FIG. 3. Figures 4-6

[0081] ​In addition, the ECC code can be further based on a sequence number that is ordered over multiple cycles or that traverses the FIFO memory. The sequence number starts at 0, increments through multiple values, and then resets or cycles back to 0. As an example, a four-bit FIFO memory pointer can be used for a FIFO memory that includes eight entries. The three least significant bits of the FIFO memory pointer can represent the read pointer buffer address or the write pointer buffer address. The most significant bit of the FIFO memory pointer will indicate whether the FIFO memory pointer corresponds to an odd iteration (or cycle) of the FIFO memory buffer or an even iteration (or cycle) of the FIFO memory buffer. For example, if the FIFO memory read pointer RDPTR[3:0] = 1101 and the FIFO memory write pointer WRPTR[3:0] = 0101, then the read pointer buffer address and the write pointer buffer address are equal to the value 101. However, the FIFO memory read pointer indicates an odd iteration, while the FIFO memory write pointer indicates an even iteration. This condition, in which the read pointer buffer address is equal to the write pointer buffer address but the read pointer and the write pointer are on different iterations, indicates a FIFO full condition because the write pointer is eight entries ahead of the read pointer. Conversely, if the FIFO memory read pointer RDPTR[3:0] = 0101 and the FIFO memory write pointer WRPTR[3:0] = 0101, then the read pointer buffer address and the write pointer buffer address are equal, and the read pointer and the write pointer are both on even iterations. This condition, in which the read pointer buffer address and the write pointer buffer address are equal and the read pointer and the write pointer are on the same iteration, indicates a FIFO empty condition because the read pointer has caught up to the write pointer. Additionally, in some embodiments, the number of data entries in the FIFO memory can not be a power of two. In such embodiments, the write pointer and the read pointer do not cycle back to 0 from the maximum value of the write pointer and the read pointer. Rather, the write pointer and the read pointer cycle back to 0 after reaching a value that represents the last data entry in the FIFO memory.

[0082] Additionally or alternatively, the ECC system can generate the ECC code for the FIFO memory based on any technically feasible addressing and / or encoding technique. In some embodiments, the FIFO memory can be asynchronous. In such embodiments, the read pointer buffer address and the write pointer buffer address can follow a Gray coding scheme. For a Gray coding scheme, only one bit of the pointer address changes between values of adjacent addresses as the FIFO memory cycles through the pointer addresses. Certain Gray coding schemes can not include a zero value for the read pointer buffer address and the write pointer buffer address. In some examples, the FIFO memory uses an n = 3-bit cyclic encoding to cycle through n = 3 FIFO addresses FIFO(address 0, 1, and 2). The addresses in these examples are as follows, shown in Table 1:

[0083]

[0084] Table 1: Example FIFO memory address Gray coding scheme

[0085] In some embodiments, a full condition can be determined when the read pointer address and the write pointer address are equal to each other. In such embodiments, a full condition can be determined when the read pointer address and the write pointer address are equal to the bit complement of each other, for example, when one pointer address is 001, 011, 111, 110, 100, or 000, and when the other pointer address is 110, 100, 000, 001, 011, or 111, respectively. If the least significant bit (LSB) of the pointer address is set to 1, an even pass is indicated, while if the LSB of the pointer address is set to 0, an odd pass is indicated. Such techniques can be advantageously used for small FIFO memories, which typically exhibit very high speeds. Generally speaking, these addressing techniques determine the next value of the pointer address by shifting the most significant bit complement to the least significant bit. A change from an odd address to an even address, and / or vice versa, can occur when all bits included in the pointer address are the same (e.g., 000 or 111).

[0086] In some embodiments, one or both of the read pointer address and the write pointer address can employ other encoding techniques, including cyclic encoding, unary encoding, ring counters, Johnson-style counters, and / or the like. Generally speaking, the disclosed techniques are applicable to any method that preserves a Hamming distance of 1 between adjacent pointer codes and when looping from the last pointer address back to the first pointer address. As used herein, the Hamming distance between two bit addresses is a value indicating the number of positions in which the bit values in the two bit addresses differ.

[0087] Figure 6 is an ECC system 300 according to various embodiments Figure 3 State diagram 600 for line buffer memory 330 of ECC system 300. State diagram 600 illustrates the ordering of operations for ECC computation. State diagram 600 processes an NxN pixel region or kernel for image processing operations performed on a center pixel in the kernel. In one example, the NxN kernel is a 21 pixel by 21 pixel region. State diagram 600 begins in an IDLE state 610, which is considered a reset state. When ECC system 300 receives a frame initialization flag 630 indicating the start of an image processing operation, state diagram 600 transitions from IDLE state 610 to a SPOOL state 612.

[0088] In SPOOL state 612, ECC system 300 buffers at least the first (N-1) / 2 memory lines. For an NxN = 21x21 kernel, ECC system 300 buffers at least the first (21-1) / 2 = 10 memory lines. If the image processing operation preserves the over-fetch of the top lines, then ECC system 300 buffers the first (N-1) / 2 memory lines during SPOOL state 612. If, on the other hand, the image processing operation removes and does not preserve the over-fetch of the top lines, then ECC system 300 buffers the first (N-1) memory lines during SPOOL state 612. In such a case, for an NxN = 21x21 kernel, ECC system 300 buffers at least the first (21-1) = 20 memory lines. During SPOOL state 612, ECC system 300 buffers the memory lines, but does not send the pixels. Once the first (N-1) / 2 or (N-1) memory lines have been buffered 632, state diagram 600 transitions from SPOOL state 612 to TRANSFER state 614.

[0089] In TRANSFER state 614, as the image processing operation proceeds, ECC system 300 reads and sends the pixels as ECC system 300 receives additional memory lines. TRANSFER state 614 begins after (N-1) / 2 memory lines if the top over-fetch is preserved, or (N-1) memory lines if the top over-fetch is removed. TRANSFER state 614 completes (N-1) / 2 memory lines before the end of the block on the output of line buffer memory 330. For an NxN = 21x21 kernel, TRANSFER state 614 completes (N-1) / 2 = 10 memory lines before the end of the block.

[0090] When the last pixel of the last memory line is received on the non-delayed input, there are still (N-1) / 2 = 10 lines remaining in line buffer memory 330 due to the accumulation during SPOOL state 612. This condition is caused by the (N-1) / 2 = 10 line lag between the input and output of line buffer memory 330. If the remaining memory lines are bottom over-fetches (e.g., the last row of the block), and the over-fetchs are not preserved 638, then these memory lines are not transferred as center pixels of the kernel. In such a case, state diagram 600 transitions from TRANSFER state 614 to end of block (EOT) state 618. If the remaining memory lines are not bottom over-fetches (e.g., the last row of the block) or the over-fetchs are preserved 634, then state diagram 600 transitions from TRANSFER state 614 to DRAIN state 616.

[0091] In the DRAIN state 616, the ECC machine sends data on the remaining (N-1) / 2=10 lines of the block as the center pixel of the kernel. During the DRAIN state 616, the last (N-1) / 2=10 memory lines of the block are sent as the center pixel, and no additional input data is accepted. The DRAIN state 616 is completed when the last pixel of the last line is detected at the output pixel. Since all input data is blocked, the termination packet that ends the image processing operation is also blocked for the duration of the DRAIN state 616. After the last line is drained 636, the state diagram 600 transitions from the DRAIN state 616 to the EOT state 618.

[0092] The state machine 600 enters the EOT state 618 from either the TRANSFER state 614 or the DRAIN state 616, depending on whether the bottom over-take is retained or whether the ECC system 300 has processed the last row of the block. If the state machine 600 enters the EOT state 618 from the TRANSFER state 614, over-take is not retained, and the prompt for termination is the last pixel last line on the input pixels. If the state machine 600 enters the EOT state 618 from the DRAIN state 616, over-take is retained, and the prompt for termination is the last pixel last line on the output pixels. In either case, when the ECC system detects the termination of operation 640, the state diagram 600 transitions from the EOT state 618 to the FLUSH state 620.

[0093] During the FLUSH state 620, the ECC system flushes the Figure 7 When the memory access pipeline is flushed 642 , the state machine 600 returns to the IDLE state 610 .

[0094] Figure 7 According to various embodiments, Figure 3 FIGURE 7 illustrates a memory access pipeline 700 for the line buffer memory 330 of the ECC system 300. In various embodiments, RAM load operations have a read latency 720 of two cycles. Therefore, the memory access pipeline 700 includes three stages. The first stage, S0 710, issues a read of a specific memory address A. The second stage, S1 712, and the third stage, S2 714, collect the results of the read of memory address A. RAM store operations, on the other hand, complete on the same cycle in which the RAM store operation is issued. During the TRANSFER state 614, the read and write addresses point to the same memory address A in the circular buffer, except that the write points to a line exactly 21 lines away from the read.

[0095] A read of memory address A is performed on the most recent memory line in stage S0 710 and passes through stages S1 712 and S2 714, while a write to memory address A is performed in stage S1 712. As a result, the old data in the memory line at memory address A is read in stage S0 before the new data is written to the same memory address A in stage S1 712. The old data is passed through the memory access pipeline 700 as a "hot line" because the memory line is no longer in the line buffer memory 330 after stage S1 712. After a two-cycle read latency 720, the hot line data from the read is collected. Interleaving reads and writes to the same address in the memory access pipeline 700 allows a single line to be stored in the buffer. Thus, a line buffer memory 330 comprising 20 memory lines 332 effectively acts as a line buffer memory 330 comprising 21 memory lines 332, the 20 lines in the line buffer memory 330, plus the hot line flowing through the memory access pipeline 700.

[0096] Figure 8 According to various embodiments, Figure 3 FIG2 is a diagram illustrating the organization of the line buffer memory 330 in the ECC system 300. As shown, the line buffer memory 330 includes memory lines 332(0), 332(1), 332(2), ... 332(N-3), 332(N-2), also referred to herein as RAM lines 332. As described herein, the total number of lines N includes N-1 lines in the line buffer memory 330 plus the hot lines. Thus, an NxN=21x21 pixel kernel includes N-1=20 memory lines 332 (numbered from 0 to 19) plus the hot lines, for a total of 21 memory lines. Each memory line 332 stores 512 pixel pairs for a total of 1024 pixels. Each pixel pair includes 96 bits, 48 ​​bits for each pixel in the pixel pair. Accordingly, the 512 pixel pairs in the memory lines 332 are addressable via a D=9-bit address. Each memory line stores 96 bits of a pixel pair plus 8 bits of ECC code, for a total of E=104 bits. The ECC code is based on the data bits of the pixel pair and enhanced address and ordering information, as described herein. During a store operation, a 96-bit pixel pair and an 8-bit corresponding ECC code are written to a memory address in one memory line 332. To prevent data from being stored in other memory lines, the enhancement data generator 310 generates a write enable WE 334 for each memory line 332 in the line buffer memory 330. The enhancement data generator 310 only asserts the write enable 334 for the memory line 332 used to store the pixel pair data and ECC code. During a load operation, a 96-bit pixel pair and an 8-bit corresponding ECC code are read from each memory line 332 for a total of W = (N-1) x E = 20 x 104 = 2080 bits.

[0097] Figure 9 According to various embodiments, Figure 3 Figure 3 illustrates a memory write access pattern for line buffer memory 330 included in ECC system 300. Generally speaking, the write access pattern follows the raster order of blocks in an image frame, where each block has a block width of TW pixel pairs and a block height of TH lines. Following the raster order, ECC system 300 first traverses the pixels along the width of a memory line 332 by advancing the write address (X coordinate) horizontally, then moves vertically to the next memory line 332 by advancing the Y coordinate. Because the width of line buffer memory 330 is greater than or equal to TW, the memory address represents the position of the pixel pair relative to the block in the direction of the X coordinate. Furthermore, TH is typically greater than the line buffer height of (N-1)=20 memory lines 332. Therefore, for every (N-1)=20 lines, the write access pattern completes a full cycle of all memory lines 332 in line buffer memory 330 before beginning to write the previous data in the memory line 332, thereby forming a circular buffer. Thus, the write access pattern resembles a modulo (N-1) operation on the Y coordinate to determine the write enable mask for the memory line being written for a particular memory operation. The write enable mask WE[19:0] 1020 is generated according to the formula WE=1<<(Ymod(N-1)).

[0098] Figure 10 According to various embodiments, Figure 3 Figure 3 illustrates a memory read access pattern for line buffer memory 330 in ECC system 300. Unlike the write access mode, which writes data one pixel pair at a time, the read access mode reads data across the entire width of line buffer memory 330, one pixel pair per memory line 332. The read access mode reads all memory lines 332 simultaneously without any read masking, except for valid bits to identify non-existent image lines at the top and bottom edges of the image block that do not yet hold valid data. The outgoing read data RD is a column of N-1=20 pixel pairs, W=Ex(N-1)104x20=2080 bits. The read address RA[8:0] is the outgoing X coordinate of the column of memory line 332 being read. To form a pixel column representing raster order with pixel pairs in the previous position, the outgoing data is rotated by line rotation circuit 360 to reflect the order of the data as written via the write access mode. The rotation factor is a value from 0 to N-2=19, derived from the Y coordinate of the centerline of the column. The X coordinates of the consistent load and store operations match, so RA[8:0] matches WA[8:0]. After rotating the original data out[1919:0], the line rotation circuit 360 sends the data out[1919:0] 382 with the current pixel in the correct position.

[0099] Figure 11are for use in ECC systems 300 in accordance with various embodiments Figure 3 is a flowchart of method steps for generating an ECC code during a store operation of an ECC system 300 in accordance with various embodiments. Although the method steps are described in connection with the system of Figures 1-10 of the present disclosure.

[0100] As shown, the method 1100 begins at step 1102 where the ECC generation circuit 320 included in the ECC system 300 determines that a store operation to a memory location is in progress. The store operation is to a memory having a regular write access pattern and a read access pattern, such as a line buffer memory, FIFO memory, read-modify-write memory, etc. In some embodiments, the store operation is to store pixel data for performing image processing on an image frame.

[0101] At step 1104, the ECC generation circuit 320 retrieves the data to be stored at the memory location in the line buffer memory, FIFO memory, read-modify-write memory, or other memory system. In some embodiments, the store operation is to a 96-bit data word of data including pairs of pixels in an image. Each pixel is represented by three components of 16 bits each. In some embodiments, the three components can include Y, U, and V components, where Y is a 16-bit luminance value and U and V are 16-bit color difference components. In some embodiments, the three components can include R, G, and B components, where R, G, and B are red, green, and blue color components, respectively.

[0102] At step 1106, the ECC generation circuit 320 retrieves address information and / or ordering information associated with the store operation from the enhancement data generator 310. The address information and / or ordering information can include the block number T[7:0] 308, the Y coordinate Y[6:0] 306, and the write address WA[8:0] 304. The block number T[7:0] 308 is an 8-bit rolling counter that cycles every 256 tiles. In image processing, it is common to divide an image into rectangular blocks arranged in a horizontal and vertical grid. The block number identifies which block in the image is currently being processed. The Y coordinate [6:0] 306 includes the 7 least significant bits of the Y coordinate within the image being written into the line buffer memory 330. Additionally or alternatively, the Y coordinate [6:0] 306 contains the 7 least significant bits of the Y coordinate within the block. The write address WA[8:0] 304 includes the 9 least significant bits of the address being written in the line buffer memory 330. Because the X coordinate within a block is typically incremented by the same step size as the write address, the least significant bits of the write address WA[8:0] 304 represent the X coordinate within the block being written into the line buffer memory 330. Additionally or alternatively, the address information and / or ordering information can include a frame number, a write enable mask, and / or the like. Additionally or alternatively, the address information and / or ordering information can include information related to the FIFO memory, such as a write pointer, a sequence number, and / or the like.

[0103] At step 1108, the ECC generation circuit 320 generates an ECC code based on the data to be stored at the memory location and at least one of the address information and / or ordering information associated with the store operation. The number of bits in the ECC code depends on the total number of bits being protected, including the data bits, the address information, and the ordering information. For example, the number of error bits required to generate a SECDEC ECC code is X = log2(number of protected bits) + 1, rounded up to the next highest integer. In one example, for a total of 96 + 8 + 7 + 9 = 120 protected bits, the number of protected bits is 96 data bits, 8 block number bits, 7 Y address bits, and 9 write address bits. Thus, the ECC code is X = log2(120) + 1 = 8 bits after rounding up. By including the 8 block number bits, 7 Y address bits, and 9 write address bits in the generation of the ECC code, the ECC code protects against errors in those additional fields. Errors in the block number, Y address, and / or write address can cause address decoding errors, write enable mask errors, stale data errors, and the like. In addition to data bit errors, the ECC generation circuit 320 protects against these types of errors. In different embodiments, the ECC code can include any technically feasible number of bits, depending on the number of error bits that can be detected, the number of error bits that can be corrected, and the encoding scheme used for the ECC code.

[0104] At step 1110, the ECC generation circuit 320 discards data representing address information and / or sequencing information. For example, the ECC generation circuit 320 discards the block number T[7:0] 308, the Y coordinate Y[6:0] 306, and the write address WA[8:0] 304. Although the ECC generation circuit 320 generates the ECC code based on this address information and / or sequencing information, the address information and / or sequencing information is regular and predictable. Thus, the address information and / or sequencing information can be regenerated during a subsequent load operation without storing the address information and / or sequencing information in memory.

[0105] At step 1112, the ECC generation circuit 320 stores the data with the ECC code in a line buffer memory, FIFO memory, read-modify-write memory, or other memory system. When the data and ECC code are subsequently read during a load operation, the ECC code stored in memory is verified by regenerating the address information and / or sequence information. A new ECC code is generated based on this data and the regenerated address information and / or sequence information. If the ECC code stored in memory is not equal to the new ECC code, a memory error has occurred. Because the ECC code is based on the address information and / or sequence information, different errors can be detected in addition to data errors. Such errors include write address decode errors, read address decode errors, write enable errors, stale data errors, and the like. After storing the data and ECC code, the method 1100 subsequently terminates.

[0106] Figures 12A-12B A method of generating and verifying ECC codes during a load operation of an ECC system 300 according to various embodiments is presented. Although the method steps are described in conjunction with the system of Figure 3 FIG. 12 is a flowchart of method steps for generating and verifying ECC codes during a load operation of an ECC system 300 according to various embodiments. Although the method steps are described in conjunction with the system of Figures 1-10 FIG. 12 is a flowchart of method steps for generating and verifying ECC codes during a load operation of an ECC system 300 according to various embodiments. Although the method steps are described in conjunction with the system of

[0107] As shown, the method 1200 begins at step 1202 where the ECC terminal circuit 350 included in the ECC system 300 determines that a load operation from a memory location is in progress. The load operation is directed to a memory having a regular write access pattern and read access pattern, such as a line buffer memory, FIFO memory, read-modify-write memory, and the like. In some embodiments, the load operation involves loading pixel data for performing image processing on an image frame.

[0108] At step 1204, the ECC termination circuit 350 determines whether the load operation is directed to a valid memory line 332. During certain image processing operations, data is read from multiple memory lines 332, the data representing pixels from image lines above and below the current pixel as well as from the same image line as the current pixel. For example, when processing a 21 x 21 pixel region, data is read from 10 image lines above and 10 image lines below the current pixel in addition to data from the image line including the current pixel. As shown, pixel data and ECC codes are read from all 20 memory lines 332 simultaneously and sent to the respective ECC termination circuits 350.

[0109] However, when processing pixels at the top of the image, there can be fewer than 10 image lines above the current pixel. Similarly, when processing pixels at the bottom of the image, there can be fewer than 10 image lines below the current pixel. If the valid bit is set for the memory line 332 to which the current load operation is directed, the data stored in the corresponding memory line 332 includes image data from an actual image line. If the valid bit is not set for the memory line 332 to which the current load operation is directed, the data stored in that memory line 332 can be random or stale because the memory line 332 is above the first line of the image or below the last line of the image.

[0110] If the load operation is directed to a non-valid memory line 332, the method proceeds to step 1206, where the ECC termination circuit 350 indicates that no ECC error occurred. Thus, the ECC termination circuit 350 is prevented from generating false errors due to uninitialized memory. As a result, the ECC system 300 eliminates the need for an initialization pass to write good data to memory at startup or system power-up. The method 1200 then terminates.

[0111] If at step 1204, the load operation is directed to a valid memory line 332, the method proceeds to step 1208, where the ECC termination circuit 350 retrieves the data stored at the memory location. Additionally or alternatively, the ECC termination circuit 350 retrieves the data stored at corresponding memory locations in different memory lines 332. The corresponding memory locations can be in memory lines 332 different from the memory line 332 of the load operation and at the same relative location within the memory lines 332.

[0112] The ECC terminal circuit 350 retrieves data at memory locations stored in an online buffer memory, FIFO memory, read-modify-write memory, or other memory system. In some embodiments, the load operation is for a 96-bit data word that includes data for a pair of pixels in an image. Each pixel is represented by three components of 16 bits each. In some embodiments, the three components can include Y, U, and V components, where Y is a 16-bit luminance value and U and V are 16-bit color difference components. In some embodiments, the three components can include R, G, and B components, where R, G, and B are red, green, and blue color components, respectively.

[0113] At step 1210, the ECC terminal circuit 350 receives regenerated address information and / or sequencing information from the enhanced data regenerator 340. The address information and / or sequencing information can include the block number T[7:0] 308, the Y coordinate Y[6:0] 306, and the write address WA[8:0] 304. The block number T[7:0] 308 is an 8-bit rolling counter that cycles every 256 blocks. In image processing, an image is often divided into rectangular blocks arranged in horizontal and vertical grids. The block number identifies which block in the image is currently being processed. The Y coordinate [6:0] 306 includes the 7 least significant bits of the Y coordinate within the image being written into the line buffer memory 330. Additionally or alternatively, the Y coordinate [6:0] 306 contains the 7 least significant bits of the Y coordinate within the block. The write address WA[8:0] 304 includes the 9 least significant bits of the address being written in the line buffer memory 330. Because the X coordinate within a block is typically incremented by the same step size as the write address, the least significant bits of the write address WA[8:0] 304 represent the X coordinate within the block being written into the line buffer memory 330. Additionally or alternatively, the address information and / or sequencing information can include a frame number, a write enable mask, and / or the like. Additionally or alternatively, the address information and / or sequencing information can include information related to a FIFO memory, such as a write pointer, a sequence number, and / or the like.

[0114] At step 1212, the ECC termination circuit 350 generates an ECC code based on the data stored at the memory location and at least one of the regenerated address information and / or the ordering information associated with the load operation. The number of bits in the ECC code depends on the total number of bits being protected, including the data bits, the address information, and the ordering information. For example, the number of error bits required to generate a SECDEC ECC code is X = log2(number of protected bits) + 1, rounded up to the next highest integer. In one example, for a total of 96 + 8 + 7 + 9 = 120 protected bits, the number of protected bits is 96 data bits, 8 block number bits, 7 Y address bits, and 9 write address bits. Thus, the ECC code is X = log2(120) + 1 = 8 bits, rounded up. By including the 8 block number bits, 7 Y address bits, and 9 write address bits in the generation of the ECC code, the ECC code protects against errors in those additional fields. Errors in the block number, Y address, and / or write address can cause address decoding errors, write enable mask errors, stale data errors, etc. The ECC termination circuit 350 protects against these types of errors in addition to data bit errors. In different embodiments, the ECC code can include any technically feasible number of bits, depending on the number of error bits that can be detected, the number of error bits that can be corrected, and the encoding scheme used for the ECC code.

[0115] At step 1214, the ECC termination circuit 350 compares the ECC code generated in step 1212 to the ECC code stored in the memory at the memory location of the load operation. At step 1216, the ECC termination circuit 350 determines whether the ECC code generated in step 1212 is equal to the ECC code stored in the memory. If the ECC code generated in step 1212 is equal to the ECC code stored in the memory, the method 1200 proceeds to step 1218, where the ECC termination circuit 350 indicates that no memory error has occurred. The method 1200 then terminates.

[0116] If, at step 1216, the ECC code generated in step 1212 does not equal the ECC code stored in the memory, method 1200 proceeds to step 1220, where the ECC termination circuit 350 indicates that a memory error has occurred. If the memory error is a data bit error, the ECC termination circuit 350 detects and / or corrects the error based on the ECC termination circuit 350's ability to detect and correct a 1-bit error, a 2-bit error, a 3-bit error, etc. If the memory error is an error in the enhanced addressing and sequencing information, the error may be more severe, such as writing a data word to an incorrect memory address or failing to write data to the memory. Therefore, if the memory error is an error in the enhanced addressing and sequencing information, the ECC termination circuit 350 forces a double-bit error or otherwise indicates that the detected error is uncorrectable. If the ECC termination circuit 350 detects and corrects a single-bit error, the ECC termination circuit 350 sends an indicator [19:0] 384 on the corresponding bit of the single-bit error correction field SEC. If the ECC termination circuit 350 detects a double bit error or otherwise forces a double bit error, the ECC termination circuit 350 sends an indicator on the corresponding bit of the double bit error detection field DED out[19:0] 386. The method 1200 then terminates.

[0117] In summary, various embodiments include an error correction code (ECC) system capable of detecting various systematic errors in addition to data bit errors. More specifically, the ECC system is capable of detecting write address decoding errors, read address decoding errors, write enable errors, stale data errors, and the like. A write address decoding error causes data to be written to an incorrect memory address during a storage operation. Similarly, a read address decoding error causes data to be read from an incorrect memory address during a load operation. A write enable failure causes one or more devices to be unable to write data during a storage operation or to be unable to read data during a load operation. A stale data error occurs when a successfully written memory location is subjected to a subsequent write that completely fails. This leaves a memory address with data from the first write. Conventional ECC systems cannot detect these additional types of errors.

[0118] Additional errors are detected by relying on two attributes. First, the ECC system disclosed herein generates ECC codes from address and ordering information as well as from data bits. In addition to data bits, the input to the ECC generator is augmented to include the read address, write address, and write enable mask (in the case of a line buffer memory) or write pointer and read pointer (in the case of a first-in-first-out (FIFO) memory). The input to the ECC generator is further augmented to include ordering information such as line number, cycle pixel block count, and frame count (in the case of a line buffer memory) or sequence number (in the case of a FIFO memory). Second, certain memories such as line buffer memories and FIFO memories have regular, predictable write access patterns and read access patterns. In such memories, the address and ordering information generated during a store operation can be regenerated during a load operation. Thus, the address and ordering information need not be stored in the memory even though the address and ordering information are used to generate the ECC code. Instead, only the data bits and the ECC code are stored in the memory. The disclosed technique is applicable to any memory system having a regular or predictable access pattern such as line buffer memories, FIFO memories, read-modify-write memory systems, and the like.

[0119] Further, certain memories such as line buffer memories have one store circuit and multiple load circuits. This feature allows multiple memory lines to be read during a load operation, for example, 20 memory lines. The disclosed ECC system includes one ECC generation circuit on the store side of the memory and a separate ECC termination circuit on the load side of the memory for each memory line. Thus, the ECC system is able to correct and / or detect multiple errors per memory load operation - one error per memory line stored in the line buffer memory. Because only one ECC generation circuit on the store side of the line buffer memory is needed to support multiple ECC termination circuits on the load side of the line buffer memory, the hardware cost in terms of die area and power consumption is about half that of a conventional approach that includes one ECC generation circuit and one ECC termination circuit for each memory line in the line buffer memory.

[0120] In addition, the ECC system generates a valid indicator based on the tracking word mask. ECC errors are enabled for memory lines that are determined to be valid and disabled for memory lines that are determined to be invalid. Thus, the ECC system eliminates the need for an initialization pass at boot-up or system power-up. If a portion of the memory that is not initialized is read, any false errors due to the uninitialized memory are filtered by the tracking word mask.

[0121] At least one technical advantage of the disclosed technology over the prior art is that with the disclosed technology, memory errors other than data errors can be detected by the ECC system without requiring additional memory to detect such errors. Thus, in addition to data errors, address decoder errors and memory write failures are detectable without substantially increasing cost, SoC surface area, or power consumption. Another technical advantage of the disclosed technology over the prior art is that false memory errors associated with uninitialized memory are suppressed, mitigating the need to initialize all memory locations when a computer system is first powered on. Thus, start-up time can be reduced relative to prior ECC approaches. These advantages represent one or more technical improvements over prior art approaches.

[0122] Any and all combinations of any claim elements recited in any manner in any claim and / or described herein fall within the scope of the disclosure and the corresponding protective scope of the claims.

[0123] The description of the various embodiments has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those skilled in the art, without departing from the scope and spirit of the described embodiments.

[0124] Aspects of the embodiments can be implemented in a system, a method or a computer program product. Accordingly, aspects of the present disclosure can take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that can all generally be referred to herein as a "module," or "system." Furthermore, aspects of the present disclosure can take the form of a computer program product on one or more computer readable medium(s) having computer readable program code embodied in the medium.

[0125] Any combination of one or more computer readable medium(s) can be utilized. The computer readable medium can be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium can be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

[0126] Aspects of the disclosure are presented with reference to methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / acts specified in the flowchart and / or block diagram block or blocks. Such processors can be, without limitation, general purpose processors, application-specific processors, application-specific integrated circuits (ASICs), or field programmable gate arrays (FPGAs). The instructions can be executed by one or more processors, such as one or more central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), systems on a chip (SoCs), systems in a package (SiPs), or the like.

[0127] The flow and block diagrams in the figures illustrate the architecture, functionality, and operations of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flow and block diagrams can represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical functions (acts). It should also be noted that in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or combinations of special purpose hardware and computer instructions.

[0128] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments can be devised without departing from the basic scope thereof, which scope is determined by the claims that follow.

Claims

1. A computer-implemented method for detecting errors in a memory, the method comprising: retrieving first data associated with a first store operation directed to a memory address generated according to a memory access pattern; generating a first error correction code (ECC) code based on the first data and at least one of address information and ordering information associated with the first store operation; storing the first data and the first ECC code at the memory address, in response to a load operation, reading the first data and the first ECC code from the memory address; and regenerating the at least one of the address information and the ordering information associated with the first store operation based on the memory access pattern.

2. The computer-implemented method of claim 1, further comprising: retrieving the first data associated with a load operation directed to the memory address; retrieving the first ECC code from the memory address; generating a second ECC code based on the first data and at least one of regenerated address information and regenerated ordering information associated with the load operation; determining that the first ECC code is not equal to the second ECC code; and indicating that an ECC error has occurred associated with the load operation. the memory address is directed to a first memory line included in a plurality of memory lines associated with a line buffer memory, and the method further comprises combining the first data with second data retrieved from a memory line included in the plurality of memory lines that is different than the first memory line to generate combined data.

3. The computer-implemented method of claim 2, wherein, the ECC error comprises a write address decode error that caused the first data to be stored to an incorrect memory address during the first store operation.

4. The computer-implemented method of claim 2, wherein, the ECC error comprises a read address decode error that caused the first data to be loaded from an incorrect memory address during the load operation.

5. The computer-implemented method of claim 2, wherein, the ECC error comprises a write enable decode error that caused the first data to fail to be stored in the memory address during the first store operation.

6. The computer-implemented method of claim 2, wherein, the ECC error comprises a stale data error that caused data from a second store operation prior to the first store operation to be loaded.

7. The computer-implemented method of claim 2, wherein, the memory comprises a line buffer memory, and the at least one of address information and ordering information comprises at least one of a block number, a Y coordinate, an X coordinate, a frame number, or a write enable mask.

8. The computer-implemented method of claim 1, wherein, the memory comprises a first-in-first-out memory, and the at least one of address information and ordering information comprises at least one of a write pointer or a sequence number.

9. The computer-implemented method of claim 1, wherein, the at least one of address information and ordering information comprises a stream number that identifies a source of the first data stored at the memory address.

10. The computer-implemented method of claim 1, wherein, 11. One or more non-transitory computer-readable media storing program instructions that, when executed by one or more processors, cause the one or more processors to perform the steps of: ​ retrieving first data associated with a first store operation directed to a memory address, wherein the memory address is generated according to a memory access pattern; generating a first error correction code (ECC) code based on the first data and at least one of address information and ordering information associated with the first store operation; storing the first data and the first ECC code at the memory address, reading the first data and the first ECC code from the memory address in response to a load operation; and re-generating the at least one of the address information and the ordering information associated with the first store operation based on the memory access pattern. the steps further comprising:

12. The one or more non-transitory computer-readable media of claim 11, wherein, retrieving the first data associated with a load operation directed to the memory address; retrieving the first ECC code from the memory address; generating a second ECC code based on the first data and at least one of re-generated address information and re-generated ordering information associated with the load operation; determining that the first ECC code is not equal to the second ECC code; and indicating that an ECC error has occurred in association with the load operation. the memory address is directed to a first memory line included in a plurality of memory lines associated with a line buffer memory, and wherein the steps further comprise combining the first data with second data retrieved from a memory line included in the plurality of memory lines that is different from the first memory line to generate combined data.

13. The one or more non-transitory computer-readable media of claim 12, wherein, the ECC error comprises a write address decode error that caused the first data to be stored to an incorrect memory address during the first store operation.

14. The one or more non-transitory computer-readable media of claim 12, wherein, the ECC error comprises a read address decode error that caused the first data to be loaded from an incorrect memory address during the load operation.

15. The one or more non-transitory computer-readable media of claim 12, wherein, the ECC error comprises a write enable decode error that caused the first data to fail to be stored in the memory address during the first store operation.

16. The one or more non-transitory computer-readable media of claim 12, wherein, the ECC error comprises a stale data error that caused data from a second store operation prior to the first store operation to be loaded.

17. The one or more non-transitory computer-readable media of claim 12, wherein, the memory comprises a line buffer memory, and the at least one of address information and ordering information comprises at least one of a block number, a Y coordinate, an X coordinate, a frame number, or a write enable mask.

18. The one or more non-transitory computer-readable media of claim 11, wherein, the memory comprises a first-in-first-out memory, and the at least one of address information and ordering information comprises at least one of a write pointer or a sequence number.

19. The one or more non-transitory computer-readable media of claim 11, wherein, 20. A system comprising: a memory including storage for data and error correction code (ECC) codes; a data memory including a plurality of data bits; and an ECC subsystem that: retrieves data associated with a first store operation directed to a memory address within the memory, wherein the memory address is generated according to a memory access pattern; generates a first ECC code based on the data and at least one of address information and ordering information associated with the first store operation; ​ ​ storing the data and the first ECC code at the memory address, in response to a load operation, reading the data and the first ECC code from the memory address; and based on the memory access pattern, regenerating the at least one of the address information and the ordering information associated with the first store operation.

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