Countermeasures for resolving adjacent-plane interference conditions in non-volatile memory architectures

Abstract

A countermeasure method for programming a defect-free plane of a non-volatile memory experiencing adjacent-plane interference includes: upon determining that a first plane has completed programming of its current state, but not all planes therein have completed programming, incrementing a loop count and determining whether the loop count exceeds a threshold. If so, programming of the (multiple) incomplete planes is stopped, and programming of the (multiple) completed planes is resumed by pausing the loop count and bit scan mode, and a predetermined rollback voltage is applied on the next programming pulse to reduce the programming voltage bias. When the loop count is last incremented, once the threshold voltage level equals the programming voltage bias, the loop count and bit scan mode are resumed. The BSPF standard applies to each programming state. The next loop is only advanced if it is determined that the programming state is incomplete.

Description

Technical Field

[0001] This disclosure relates to non-volatile memory storage systems in solid-state drives or other devices, including but not limited to flash drives or embedded / removable flash packages. More specifically, this disclosure relates to systems and methods for programming non-volatile memory structures. Background Technology

[0002] Driven by emerging technologies and market forces, solid-state drives (SSDs) are steadily replacing traditional data storage systems (such as hard disk drives) that previously relied on the rotation of magnetic media to read and write data. Solid-state storage does not contain any mechanical or moving parts; instead, it comprises integrated circuit components or interconnecting flash components to provide non-volatile storage, meaning that stored data is persistently retained in non-volatile memory even during planned or unplanned power outages. Therefore, compared to disk-based storage, solid-state drives are inherently faster, more robust (i.e., less susceptible to data loss and corruption), consume less power, and are more compact. Thus, non-volatile memory is a robust storage solution for many types of computing, consumer electronics, and standalone external storage devices (such as USB drives).

[0003] For some flash memory types, each individual memory cell includes a floating gate located above and isolated from the channel region of the semiconductor substrate, wherein the floating gate is situated between the source and drain regions. Furthermore, a control gate is provided above the floating gate and isolated from it. Therefore, the threshold voltage (V0) of the resulting transistor... th The threshold voltage characteristic of a transistor is controlled by and depends on the amount of charge held on the floating gate. Specifically, in a switch-like manner, the minimum voltage that must be applied to the control gate before the transistor is activated to allow conduction between its source and drain is determined by the level of charge held on the floating gate. Therefore, by changing the level of charge on the floating gate to change the threshold voltage characteristic of the transistor, bit-value data can be programmed onto and erased from the memory cell.

[0004] As explained in detail below, the number of bits that can be stored in a single memory cell depends on the number of different voltage ranges that can be divided within the threshold voltage window of that memory cell. For example, to store a data bit (called binary data), the possible threshold voltage (Vth) of the memory cell is divided into two ranges, which are assigned to logic data "1" and "0" respectively. Memory cells characterized by this type of storage density can be called "single-level cells" or SLCs.

[0005] By further dividing the threshold voltage window of a memory cell into additional different voltage ranges, multi-level information can be stored. Such a memory cell can be called a "multi-state cell." For example, to store two bits of data, the threshold voltage window of the cell can be divided into four different voltage ranges (or states), where each range is assigned a specific bit value, equal to, for example, "11", "10", "01", and "00". Therefore, after an erase operation, the threshold voltage is negative and can thus be defined as logic "11". Positive threshold voltages can therefore be used for states "10", "01", and "00". Memory cells of this storage density can be called, for example, "multi-level cell" or MLC. In another example, to store three bits of data, the voltage threshold window of the cell can be divided into eight different voltage ranges (or states), where each range is assigned a specific bit value, equal to, for example, "111", "110", "100", "010", "011", "000", "001", and "101". Memory cells of this storage density can be called, for example, "three-level" or "three-level cell" (TLC). In another example, to store four bits of data, the voltage threshold window of the memory cell can be divided into 16 different voltage ranges (or states), where each voltage range is assigned a specific bit value, equal to, for example, "1111", "1110", "1100", "1000", "0111", "0011", "0001", "0000", "0000", "1001", "1101", "1011", "0110", "0100", "0101", and "1010". Memory cells of this type of storage density can be referred to, for example, as "Quadruple Level Cell" (QLC).

[0006] The specific relationship between the data programmed into the memory cell and the threshold voltage level of the memory cell depends on the data encoding scheme used by the memory cell.

[0007] In addition to increasing storage density relative to individual memory cells, advancements in non-volatile memory array structures have led to the vertical stacking of memory cells relative to the semiconductor substrate, creating three-dimensional array structures in contrast to planar two-dimensional array structures. However, the lack of separation between charge trapping regions of memory cells in three-dimensional array structures presents further challenges to the reliability and retention of programmed data.

[0008] Therefore, as the industry continues to achieve smaller memory cells with increased storage density to store more data, this scaling introduces certain performance and durability risks. To achieve the advantage of higher memory capacity within a fixed die size, smaller memory cells must be packaged more tightly together. However, doing so can lead to an increase in the number of manufacturing, memory operation, and performance errors. For example, potentially catastrophic structural defects occurring between adjacent components, such as electrical short circuits between adjacent word lines, are more likely to occur in compact spaces. The following description primarily addresses the detrimental effects of having one or more defective memory planes in a multi-plane memory architecture. More specifically, based on various observations, the presence of defective memory planes in scalable memory architectures can disrupt (e.g., pull down) the programming voltage (VPGM) applied during programming operations, thereby preventing further programming and completion of programming on the downstream (multiple) defect-free planes. Consequently, programming operations fail or are incomplete, and although a portion of the memory sector contains (multiple) defect-free planes, it remains unused. This situation can be termed Adjacent Plane Disturbances (NPD). In response, various countermeasures can be employed to detect one or more defective memory planes and isolate them from the surrounding memory structure, thereby restoring or allowing programming operations on the defect-free plane(s). For example, where applicable, such countermeasures can utilize comparisons between certain parameters of successive programming loops occurring between multiple planes and impose failure criteria as a deterministic outcome. In particular, it would be beneficial to derive an on-chip device pattern that can detect and isolate defective plane(s) within the memory structure and allow continued successful programming operations on the defect-free plane(s) within the memory structure. Furthermore, such countermeasure device patterns can be further optimized to account for or counteract any residual artifacts (e.g., data reliability and accuracy) of device patterns that may present programming performance problems. Summary of the Invention

[0009] Various embodiments include a countermeasure method for programming a defect-free memory plane of a non-volatile memory structure experiencing adjacent-plane interference (NPD) conditions, wherein the method includes: initiating a programming pulse for a current programming state according to an initial programming sequence and subsequently initiating a programming verification operation, in which a bit scan mode is applied according to one or more bit scan failure criteria. Further, once it is determined that a first memory plane of the memory structure has completed programming to its current programming state according to one or more bit scan failure criteria, a determination is made as to whether all memory planes of the memory structure have completed programming to their current programming state. If not all memory planes have completed programming to their current programming state, a loop count is incremented and a determination is made as to whether the resulting loop count exceeds a predetermined threshold. If the loop count exceeds a predetermined threshold, programming of one or more memory planes that are currently incomplete programming is stopped, and programming of one or more memory planes that are currently incomplete programming is resumed by: temporarily pausing loop counting and bit scan mode, and applying a predetermined rollback voltage value on the next programming pulse according to the initial programming sequence to reduce the programming voltage bias level originally expected during the programming pulse; resuming loop counting and bit scan mode once the programming threshold voltage level is equal to the programming voltage bias level reached when the loop count was last increased; applying one or more bit scan failure criteria to each programming state; and proceeding to the next programming loop only if it is determined that the programming state is incomplete according to one or more bit scan failure criteria.

[0010] Other embodiments include a memory controller for a non-volatile memory system, wherein the memory controller includes a first port configured to be coupled to the non-volatile memory, wherein the memory includes a memory structure. Further, the memory controller is configured to perform countermeasures during programming of the memory structure, wherein the memory structure experiences adjacent plane interference (NPD). Specifically, the memory structure is configured to initiate a programming pulse for the current programming state based on an initial programming sequence and subsequently initiate a programming verification operation, in which a bit scan mode is applied based on one or more bit scan failure criteria. Further, based on one or more bit scan failure criteria, once it is determined that a first memory plane of the memory structure has completed programming to the current programming state, the memory controller is configured to determine whether all memory planes of the memory structure have completed programming to the current programming state. If not all memory planes have completed programming to the current programming state, the memory controller is configured to increment a loop count and determine whether the resulting loop count exceeds a predetermined threshold. If the loop count exceeds a predetermined threshold, the memory controller is configured to stop one or more memory planes that are currently incomplete programming and resume programming one or more memory planes that are currently incomplete programming by: temporarily pausing the loop count and bit scan mode, and applying a predetermined rollback voltage value on the next programming pulse to decrement the programming voltage bias level originally expected during the programming pulse, based on the initial programming sequence; resuming the loop count and bit scan mode once the programming threshold voltage level is equal to the programming voltage bias level reached when the loop count was last incremented; applying one or more bit scan pass failure criteria to each programming state; and proceeding to the next programming loop only if it is determined that the programming state is incomplete, based on one or more bit scan pass failure criteria.

[0011] An additional embodiment includes a non-volatile memory storage system comprising a memory structure and a memory controller coupled to the memory structure. Based on an initial programming sequence, the memory controller initiates a programming pulse for the current programming state and subsequently initiates a programming verification operation. In the programming verification operation, a bit scan mode is applied based on one or more bit scan failure criteria. Further, based on one or more bit scan failure criteria, once it is determined that a first memory plane of the memory structure has completed programming to the current programming state, the memory controller determines whether all memory planes of the structure have completed programming to the current programming state. If not all memory planes have completed programming to the current programming state, the memory controller increments a loop count and determines whether the resulting loop count exceeds a predetermined threshold. If the loop count exceeds a predetermined threshold, the memory controller stops programming one or more memory planes whose programming state is incomplete and resumes programming one or more memory planes whose programming state is complete by: temporarily pausing the loop count and bit scan mode, and applying a predetermined rollback voltage value on the next programming pulse to decrement the programming voltage bias level originally expected during the programming pulse, based on the initial programming sequence; resuming the loop count and bit scan mode once the programming threshold voltage level is equal to the programming voltage bias level reached when the loop count was last incremented; applying one or more bit scan failure criteria to each programming state; and proceeding to the next programming cycle only if it is determined that the programming state is incomplete based on one or more bit scan failure criteria. Attached Figure Description

[0012] The following description, with reference to the exemplary embodiments depicted in the accompanying drawings, will be presented in more detail. It should be understood that these drawings merely depict exemplary embodiments of the present disclosure and should therefore not be considered as limiting its scope. The present disclosure is described and explained with additional features and details using the accompanying drawings, wherein:

[0013] Figure 1 This is a block diagram of a memory system according to an example embodiment;

[0014] Figure 2 This is a schematic diagram of a non-volatile memory cell according to an example embodiment;

[0015] Figure 3 The source-drain currents I of four different charges Q1-Q4 according to an exemplary embodiment are depicted. D and control gate voltage V CG The relationship between the four charges is such that the floating gate of the non-volatile memory cell can selectively store the four different charges at any given time with a fixed drain voltage.

[0016] Figure 4AA series of NAND-type memory cells organized into a string according to an example embodiment is schematically depicted;

[0017] Figure 4B An array of memory cells according to an example embodiment is schematically depicted, comprising multiple NAND-type strings, such as Figure 4A The types described in the text;

[0018] Figure 5 A page of a memory cell that is sensed or programmed in parallel according to an example embodiment is depicted, and the page of the memory cell is associated with a memory array organized in a NAND-type configuration;

[0019] Figures 6A-6C The stages of programming multiple MLC NAND type memory cells according to an example embodiment are described;

[0020] Figures 7A-7C The stages of programming multiple MLC NAND type memory cells according to an example embodiment are described;

[0021] Figure 8 A vertical NAND string is depicted according to an example embodiment;

[0022] Figure 9 This is a perspective view of a representative sub-part of a monolithic three-dimensional NAND-type memory array according to an example embodiment;

[0023] Figure 10 A configuration of a non-volatile memory array accessible by read / write circuitry via row and column decoders according to an example embodiment is schematically depicted;

[0024] Figure 11 This is a block diagram of a separate read / write module according to an example embodiment;

[0025] Figure 12A A memory device having a set of partitioned read / write stacks is schematically depicted according to an example embodiment;

[0026] Figure 12B A slightly different configuration according to the example embodiment is illustrated schematically. Figure 12A Memory devices;

[0027] Figure 13 A read / write stack (such as...) according to an example embodiment is illustrated schematically. Figure 12A The various components of the read / write stack (described in the text);

[0028] Figure 14A An arrangement according to an example embodiment is schematically depicted in a memory device (such as...) Figure 12AMultiple read / write stacks between read / write circuits of the memory device depicted in the diagram;

[0029] Figure 14B It is a description of the read / write stack (such as) according to the example embodiment. Figure 12A A block diagram of the sensing block (the read / write stack) depicted in the diagram;

[0030] Figure 15A The effects of adjacent-plane interference conditions during programming operations on a representative portion of a three-dimensional NAND-type memory structure, according to an example embodiment, are generally described.

[0031] Figure 15B The general description of the example embodiment is as follows: Figure 15A The effects of adjacent plane interference conditions during programming verification operations of a representative memory portion depicted in the figure;

[0032] Figure 16A This is a flowchart according to an example embodiment, which generally illustrates the steps of a process for identifying one or more defective planes within a memory structure during programming and programming verification operations;

[0033] Figure 16B The flowchart is based on an example embodiment and generally illustrates the steps of a countermeasure pattern for programming and programming verification operations to isolate (multiple) identified defective planes of a memory structure and re-establish (multiple) defect-free planes within the memory structure.

[0034] Figure 17A This is a diagram illustrating an example of programming operations in a programmable state of a defect-free plane according to an example embodiment, in which adjacent plane interference conditions do not exist in the memory structure;

[0035] Figure 17B It is a description based on the example embodiment Figure 17A The diagram shows an example of programming operations on the programmable state of the example plane of interest, where the programming operations are affected by adjacent plane interference conditions present in the memory structure.

[0036] Figure 18A It is a description based on the example embodiment Figure 17B The graph shows examples of programming operations on the programmable state of the example plane, where the strategy pattern is initiated.

[0037] Figure 18B It is a description based on the example embodiment Figure 18A The diagram shows examples of programming operations for programmable states of the example plane of interest, where fault recovery mode is incorporated into countermeasure mode;

[0038] Figure 19This is a flowchart based on an example embodiment, which generally illustrates... Figure 18B The steps shown are used to complete the programming operation of the defect-free plane of the memory structure after the fault recovery mode is completed;

[0039] Figure 20 It is a depiction of the example embodiment in Figure 18B After the fault recovery mode described in the text is completed and during the process Figure 19 The comparison of programming threshold voltages (V) of multiple memory cells during the programming operation described in the figure th A curve showing the distribution of )

[0040] Figure 21A This is a flowchart based on an example embodiment, which generally illustrates the completion of... Figure 18B The step of bit scan mode in the programming operation of the defect-free plane of the memory structure, as shown in the fault recovery mode, is completed after the fault recovery mode; and

[0041] Figure 21B This is a flowchart according to another example embodiment, which generally illustrates the completion of Figure 18B The step of bit scan mode in the programming operation of the defect-free plane of the memory structure is completed after the fault recovery mode described in the diagram. Detailed Implementation

[0042] The following describes various exemplary embodiments with respect to this disclosure. While one or more of these embodiments may be preferred, the disclosed embodiments should not be construed as limiting the scope of this disclosure, including the claims. Furthermore, those skilled in the art will understand that the following description has broad application, and the detailed explanation of any particular embodiment is intended only as an example of that embodiment and is not intended to imply that the scope of this disclosure, including the claims, is limited to that particular embodiment.

[0043] Several aspects of this disclosure may be embodied in the form of an apparatus, system, method, or computer program process. Therefore, aspects of this disclosure may be entirely in the form of a hardware or software embodiment (including, but not limited to, firmware, resident software, microcode, etc.), or may be a combination of hardware and software components, which may generally be collectively referred to as a "circuit," "module," "apparatus," or "system." Furthermore, aspects of this disclosure may be in the form of a computer program process embodied in one or more non-transitory computer-readable storage media, for example, storing computer-readable and / or executable program code.

[0044] Furthermore, various terms are used herein to refer to specific system components. Different companies may use different names to refer to the same or similar components, and this description is not intended to distinguish between components with different names but the same function. Within the scope of the various functional units described in the following disclosure, referred to as “modules,” such characterization is intended not to unduly limit the scope of potential implementation mechanisms. For example, a “module” can be implemented as hardware circuitry comprising custom-designed very large-scale integrated circuits (VLSI) or gate arrays, or off-the-shelf semiconductors comprising logic chips, transistors, or other discrete components. In further examples, modules can also be implemented in programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic, programmable logic devices, etc. Additionally, modules can also be implemented, at least in part, by software executed by various types of processors. For example, a module may include a segment of executable code that constitutes one or more physical or logical blocks of computer instructions that translate into objects, procedures, or functions. Furthermore, it is not required that the executable portions of such modules be physically located together, but rather that they may include different instructions stored in different locations, and when executed together, these instructions include the identified module and achieve the module’s intended purpose. Executable code may consist of a single instruction or a set of instructions, and may be distributed across different code segments, different programs, or multiple memory devices. In software, or partial software, or module implementations, the software portion may be stored on one or more computer-readable and / or executable storage media, including but not limited to electronic, magnetic, optical, electromagnetic, infrared, or semiconductor-based systems, devices, or apparatuses, or any suitable combination thereof. Generally, for the purposes of this disclosure, computer-readable and / or executable storage media may consist of any tangible and / or non-transitory medium capable of containing and / or storing programs for use thereon or for use in conjunction with instructions executed by a system, device, processor, or apparatus.

[0045] Similarly, for the purposes of this disclosure, the term "component" can include any tangible, physical, and non-transitory device. For example, a component can be in the form of hardware logic circuitry consisting of custom VLSI circuitry, gate arrays, or other integrated circuits, or of off-the-shelf semiconductors including logic chips, transistors, or other discrete components, or any other suitable mechanical and / or electronic device. Furthermore, components can also be implemented in programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic, programmable logic devices, etc. Additionally, a component can consist of one or more silicon-based integrated circuit devices (such as chips, dies, die planes, and packages, or other discrete electrical devices) that are in an electrically communicative configuration with one or more other components via electrical conductors such as printed circuit boards (PCBs). Therefore, modules as defined above can be embodied in or implemented as components in some embodiments, and in some cases, the terms module and component are used interchangeably.

[0046] As used herein, the term "circuit" includes one or more electrical and / or electronic components that form one or more conductive paths that allow current to flow. A circuit can be in the form of a closed-loop configuration or an open-loop configuration. In a closed-loop configuration, circuit components can provide a return path for current. In contrast, in an open-loop configuration, although a return path for current is not included, the circuit components can still be considered to form a circuit. For example, an integrated circuit is referred to as a circuit regardless of whether it is coupled to ground (as a return path for current). In some example embodiments, a circuit may include a collection of integrated circuits, a single integrated circuit, or a portion of an integrated circuit. For example, a circuit may include custom VLSI circuitry, gate arrays, logic circuits, and / or other forms of integrated circuits, and may include off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices. In further examples, a circuit may include one or more silicon-based integrated circuit devices, such as chips, dies, die planes and packages, or other discrete electrical devices, which are in an electrically communicative configuration with one or more other components via electrical conductors such as printed circuit boards (PCBs). The circuit can also be implemented as a composite circuit relative to programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic, and / or programmable logic devices. In other example embodiments, the circuit may include a network of non-integrated electrical and / or electronic components (with or without integrated circuit devices). Therefore, modules as defined above can be embodied in or implemented as circuits in some embodiments.

[0047] It should be understood that the exemplary embodiments disclosed herein may consist of one or more microprocessors and specific stored computer program instructions that control one or more microprocessors in combination with certain non-processor circuitry and other components to implement some, most, or all of the functions disclosed herein. Alternatively, some or all of the functions may be implemented by a state machine without stored program instructions, or in one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs), wherein each function or some combinations of certain functions is implemented as custom logic. Combinations of these methods may also be used. Therefore, methods and means for these functions are described herein. Furthermore, the following reference to “controller” should be defined to include a single circuit component, an application-specific integrated circuit (ASIC), a microcontroller with control software, a digital signal processor (DSP), a field-programmable gate array (FPGA), and / or a processor with control software, or a combination thereof.

[0048] Furthermore, as used herein, the terms “program,” “software,” “software application,” etc., refer to a sequence of instructions designed to execute on a computer-implemented system. Therefore, “program,” “software,” “application,” “computer program,” or “software application” can include subroutines, functions, procedures, object methods, object implementations, executable applications, applets, service applets, source code, object code, shared libraries / dynamically loaded libraries, and / or other specific sequences of instructions designed to execute on a computer system.

[0049] Furthermore, the terms “coupled,” “coupled,” or “coupled” as used herein are intended to indicate a direct or indirect connection. Thus, if a first device is coupled or coupled to a second device, the connection can be either a direct connection or an indirect connection via other devices (or components).

[0050] The use of terms such as “embodiment,” “one embodiment,” “example embodiment,” “specific embodiment,” or other similar terms in this document is intended to indicate a particular feature, structure, function, operation, or characteristic described in connection with an embodiment present in at least one embodiment of this disclosure. Therefore, the appearance of phrases such as “in one embodiment,” “in an embodiment,” “in an example embodiment,” etc., may, but does not necessarily, refer to the same embodiment, but rather to “one or more, but not all, embodiments,” unless expressly stated otherwise. Furthermore, the terms “comprising,” “having,” “including,” and variations thereof are used in an open-ended manner and should therefore be interpreted as “including, but not limited to…” unless expressly stated otherwise. Moreover, without further limitations, an element beginning with “comprising…” does not exclude the presence of additional identical elements in the subject matter process, method, system, article, or apparatus that includes that element.

[0051] Unless otherwise expressly stated, the terms “a,” “an,” and “the” also mean “one or more.” Furthermore, the phrase “at least one of A and B,” as may be used herein and / or in the following claims, indicates a choice of A or B, or both A and B, similar to the phrase “and / or,” where A and B are variables indicating a particular object or property. If there are more than two variables in the phrase, the phrase is defined herein as including only one variable, any one of the variables, any combination (or subcombination) of any variables, and all variables.

[0052] Furthermore, as used herein, the terms “approximately” or “around” apply to all numerical values, whether explicitly indicated or not. These terms generally refer to a range of numerical values ​​that a person skilled in the art would consider equivalent to the stated values ​​(e.g., having the same function or result). In some cases, these terms may include numerical values ​​rounded to the nearest significant digit.

[0053] Furthermore, unless otherwise expressly stated, any list of items presented herein does not imply that any or all of the listed items are mutually exclusive and / or mutually inclusive. Additionally, unless otherwise expressly stated, the term "set" as used herein should be interpreted as "one or more," and in the case of "multiple sets," according to set theory, it should be interpreted as a multiple (or many) of "one or more," "one or more," and / or "multiple or many."

[0054] Various elements of this disclosure are described below with reference to schematic flowcharts and / or block diagrams depicting methods, apparatus, systems, and computer program processes according to exemplary embodiments of this disclosure, wherein each block or combination of blocks in the schematic flowcharts and / or block diagrams may be implemented by specially written computer program instructions. As understood in the art, the computer program instructions are executed by a designated processor of a computer or other programmable data processing apparatus to create mechanisms for implementing the functions, actions, and / or operations specifically set forth in one or more blocks in the schematic flowcharts and / or block diagrams. Furthermore, it should be noted that in some alternative process implementations, the functions specified in the blocks may not occur in the exact order depicted in the schematic flowcharts and / or block diagrams. For example, two blocks described as occurring consecutively in the figures may actually be executed substantially simultaneously (i.e., concurrently), or even in reverse order, depending on the functions involved. Furthermore, other processing steps and methods that are functionally, logically, or effectively equivalent to one or more blocks or portions thereof in the figures can be conceived and contemplated within the scope of this disclosure. Additionally, while the schematic diagrams may depict various arrow types and directions and line types as illustrative, they are not intended to limit the scope of the respective embodiments. For example, arrows may represent or indicate a waiting or monitoring period of unspecified duration between the enumerated steps of the illustrated example embodiment.

[0055] In the following detailed description, reference is made to the accompanying drawings, which form part of the description. It should be understood that the above overview is illustrative only and is not intended to be limiting in any way. In addition to the illustrative aspects, exemplary embodiments, and features described above, other aspects, exemplary embodiments, and features will become apparent from the accompanying drawings and the following detailed description. The description of elements in each figure may be referenced to elements in the preceding figures. The same reference numerals may refer to the same elements in the figures, including alternative exemplary embodiments of the same elements.

[0056] Now refer to the attached diagram for details and from... Figure 1 The illustration begins by depicting an example embodiment of the memory system 90 and illustrating its main hardware components. In this particular embodiment, the memory system 90 operates and communicates with a host device 80 via a host interface. Furthermore, the memory system 90 includes a memory device 102 whose operation is controlled by a controller 100. The host device 80 may include any device or system utilizing the memory system 90 (e.g., a computing device). Thus, the memory system 90 may be in the form of a removable memory card or an embedded memory system. For example, the memory system 90 may be embedded in a solid-state drive installed in a laptop computer. In another example, the memory system 90 may be embedded within the host device 80, such that the host 80 and the memory system 90 (including the controller 100) are formed on a single integrated circuit chip. In embodiments where the memory system 90 is implemented within a memory card, the host device 80 may include a built-in slot (e.g., a Universal Serial Bus (USB) port, or a memory card slot) for one or more types of memory cards or flash drives. Additionally, the host 80 may use an adapter in which a memory card is inserted.

[0057] Still referencing Figure 1 As described in detail below, memory device 102 may include one or more memory arrays of multiple non-volatile memory cells distributed across one or more integrated circuit chips. Furthermore, according to this particular embodiment, controller 100 may include a number of components, including but not limited to interface circuitry 110, processor 120, ROM (Read-Only Memory) 122, RAM (Random Access Memory) 130, programmable non-volatile memory 124, and additional components. For example, controller 100 may be in the form of one or more application-specific integrated circuits (ASICs), including components in such ASICs that typically depend on the specific application.

[0058] Regarding the memory device 102 itself, Figure 2This is a schematic diagram of a single non-volatile memory cell 10 according to an example embodiment. As described above, the memory cell 10 can be implemented by a field-effect transistor having a charge storage cell 20 (such as a floating gate or a dielectric layer). Furthermore, the memory cell 10 includes a source region 14 and a drain region 16. Additionally, a control gate 30 is located above the floating gate 20. Example types of non-volatile memory cells with this general structure include, but are not limited to, electrically erasable programmable read-only memories (EEPROMs) and flash EEPROMs, NAND (NOT-AND) type cells, and those utilizing dielectric storage elements (e.g., NROMs). TM The memory device is described above. In operation, according to certain embodiments, when a reference voltage is applied to the control gate 30, the memory state of the cell can be read (e.g., programmed or erased) by sensing the on-state current across the source and drain electrodes of the memory cell. More specifically, for each given charge on the floating gate 20 of the memory cell, a corresponding on-state current relative to a fixed reference control gate voltage can be detected. Thus, as described above, a range of charges programmable to the floating gate defines a corresponding threshold voltage window or a corresponding on-state current window for the memory cell 10. Alternatively, instead of detecting the on-state current within a defined current window, a threshold voltage can be set at the control gate 30 for a given measured memory state, and the resulting on-state current can be detected as being higher or lower than the threshold current (i.e., the cell read reference current). In one such example implementation, the detection of the on-state current relative to the threshold current is accomplished by examining the discharge rate of the on-state current through the bit line capacitance.

[0059] Figure 3 Provides source-drain current I D and control gate voltage V CG A graphical illustration of the correlation between them, for example, a non-volatile memory cell 10 with four different charge states Q1-Q4 that can be selectively stored at any given time with a floating gate. As shown, under a fixed drain voltage bias, there are four I values ​​representing the four charge levels. D For V CG The solid line represents four charge levels that can be programmed on the floating gate of a memory cell, with each of the four charge levels corresponding to one of eight possible memory states. Therefore, as an example, the threshold voltage window for multiple memory cells can range from 0.5V to 3.5V. In such an example, seven programmed memory states are assigned as "0", "1", "2", "3", "4", "5", "6" and one erase state. Figure 3 (Not shown in the figure) can be calibrated by dividing the threshold window into regions with a 0.5V interval. Therefore, if a reference current I of 2μA is used as shown in the figure... REFTherefore, the cell programmed using the Q1 voltage can be considered to be in memory state "1" because its curve intersects with IREF in the threshold window region, which is defined by the voltage range V. CG =0.5V and 1.0V calibration. Similarly, Q4 is in memory state "5".

[0060] Therefore, as described above, the more states the memory cell 10 stores, the finer its threshold voltage window becomes. For example, in a memory cell 10 with a threshold voltage window range of -1.5V to 5V, thus providing a maximum possible width of 6.5V, and to store 16 memory states, each state could occupy only a voltage range of 200mV to 300mV. Such a narrow voltage range would require higher precision in programming and reading operations to achieve the desired resolution.

[0061] Individual memory cells 10 are organized into a string, wherein the memory cells are arranged in series. For example, Figure 4A The illustration depicts an example embodiment including a string 50 of NAND-type memory cells, in which corresponding transistor elements M1, M2, ..., Mn (where "n" can be equal to 4, 8, 16 or higher) of the cell series are connected in a daisy-chain manner relative to their source and drain. Furthermore, as per [reference to...] Figure 3 As discussed, each memory transistor 10 in string 50 has a charge storage element 20 (e.g., a floating gate) for storing a certain amount of charge to represent the expected memory state of the cell. Furthermore, as explained in more detail below, each memory transistor 10 includes a control gate 30 that allows control of read and write operations. Present at the source terminal 54 and drain terminal 56 of string 50 are select transistors S1 and S2, which control the connection of the transistor elements to the peripheral memory array. Specifically, when the source select transistor S1 is turned on, the source terminal 54 is coupled to the source line. Similarly, when the drain select transistor S2 is turned on, the drain terminal 56 is coupled to the bit line of the memory array.

[0062] Expand the hierarchy outwards. Figure 4B It is a description of Figure 4AThis is a schematic diagram of an example embodiment of a memory array 210 consisting of multiple NAND strings 50 of the type shown. Along each column of the NAND strings 50, a bit line 36 is coupled to the drain terminal 56 of each NAND string. Furthermore, along each group of NAND strings 50, a source line 34 is coupled to the source terminal 54 of each NAND string. Additionally, the control gate 30 of the memory transistor 10 in a row of memory cells within a group of NAND strings 50 is connected to the same word line 42. Therefore, when an addressed memory transistor 10 within a NAND string 50 is read or verified during a programming operation, an appropriate voltage is applied to its control gate 30. Simultaneously, by applying sufficient voltage to their respective control gates 30, the remaining unaddressed memory transistors 10 within the NAND string 50 are fully turned on. Thus, conductive paths are created from the source of the addressed memory transistor 10 to the source terminal 54 of the NAND string 50 and from the drain of the addressed memory transistor 10 to the drain terminal 56 of the cell.

[0063] Furthermore, the control gates 32 of the select transistors S1, S2 of each NAND string 50 in the memory array 210 provide controllable access to the NAND string at the source terminal 54 and the drain terminal 56. The control gates 32 of the select transistors S1, S2 along one row of a set of NAND strings 50 are connected to the same select line 44. Therefore, an entire row of memory cells 10 in a set of NAND strings 50 can be addressed by applying appropriate voltages to the word line 42 and the select line 44 of that set of NAND strings 50.

[0064] Turn now Figure 5 It depicts a detailed illustration of a set of NAND strings 50 of a memory array 210 according to an example embodiment of the present invention. This view is particularly useful in visualizing the row-by-row configuration of the memory array 210, where each row of the array 210 may be referred to as a “page”. Thus, physical pages (such as…) Figure 5 Page 60 (represented in the original text) is a set of memory cells 10 that can be sensed or programmed in parallel. In fact, a page is the smallest unit of a memory device that can be programmed or written to. Programming pages is accomplished by the corresponding pages of the sense amplifiers 212, where each sense amplifier can be programmed via bit lines (e.g., see...). Figure 5 The corresponding bit lines BL0, BL1, BL2, BL3, BL4, BL5, ..., BLm-1 and BLm shown are coupled to the corresponding NAND string 50. Therefore, page 60 is enabled by the control gates of the plurality of memory cells 10 in page 60, which are connected to the common word line 42, and each memory cell 10 of page 60 can be accessed via bit line 36 by a sense amplifier. Thus, when page 60 of memory cells 10 is programmed or sensed, a programming or sense voltage is applied together with an appropriate voltage on the bit line to the common word line (e.g., relative to word line WL3 of page 60).

[0065] Regarding the method of programming and erasing data, it is important to note that for flash memory, memory cells must be programmed from an erased state. In other words, before a subsequent programming operation can add the required amount of charge back to the floating gate 20, the charge on the floating gate 20 must first be cleared, thus placing the memory cell in an erased state. Therefore, the charge level on the floating gate 20 cannot be gradually increased or decreased from its previously programmed level. Consequently, updated data cannot overwrite existing data in the memory cell 10. Instead, updated data must be programmed to a location that has not been previously written to.

[0066] To improve performance during erase operations, the array 210 of memory cells 10 is, for example, divided into a large number of memory cell blocks, where a block is the smallest unit of a memory device, and the memory cells contained in the memory device can be erased together. Furthermore, each block in the memory cells 10 can be divided into multiple physical pages 60, where, as described above, programming operations are performed page-by-page. Therefore, a logical page is a unit containing a number of bits equal to the number of memory cells 10 in a given physical page for programming or reading. For example, in an SLC-type memory device where each memory cell 10 stores one data bit, one physical page 60 stores one logical page of data. Therefore, in an MLC-type memory device where each memory cell 10 stores two data bits, one physical page 60 can store two logical pages of data. Thus, one or more logical pages of data are typically stored in a row of memory cells (i.e., page 60). A page 60 can store one or more sectors, where one sector consists of user data and overhead data. In an example embodiment, a single page 60 can be divided into segments, each segment containing the minimum number of memory cells 10 that can be written to at once in a basic programming operation.

[0067] To illustrate an example embodiment of the programming phase of an MLC-type memory device comprising multiple four-state memory cells, refer to... Figures 6A to 6C .exist Figure 6A The diagram depicts multiple memory cells, in which a characteristic threshold voltage window is divided into four different voltage distributions, each corresponding to a programmable memory state (i.e., memory states "0", "1", "2", and "3"). Figure 6B The diagram illustrates the initial distribution of the "erase" threshold voltage for an erased memory. Figure 6CIn this configuration, most of the memory cell group is programmed such that the initial "erase" threshold voltage of a given memory cell 10 is shifted to a higher value, to one of three divided voltage regions defined by verification levels vV1, vV2, and vV3. Therefore, each memory cell can be programmed into one of three programmable states "1", "2", and "3", or remain in the "erase" state. At the bit level, each of the four memory states can be represented using a 2-bit code with lower and higher bits. For example, as... Figure 6C As shown, bit values ​​“11”, “01”, “00”, and “10” can be assigned to memory states “0”, “1”, “2”, and “3”, respectively. In such an example, two bits of data can be read from the memory in “full sequence” mode, where the two bits are sensed together by sensing the corresponding read calibration threshold voltages rV1, rV2, and rV3 in the three sub-passes, respectively.

[0068] Similarly, Figures 7A to 7C The programming phase of a TLC-type memory device is illustrated. This TLC-type memory device includes multiple eight-state memory cells, which, according to this particular embodiment, can be programmed to represent memory states "0", "1", "2", "3", "4", "5", "6", and "7" respectively, according to eight different threshold voltage distributions. Figure 7A (As shown in the image). Therefore, Figure 7B The initial distribution of the "erase" threshold voltage of the erased memory is depicted. Furthermore, Figure 7C An example of memory after many memory cells have been programmed is depicted. Therefore, the threshold voltage of the cell rises to one of the different voltage ranges calibrated by levels V1, V2, V3, V4, V5, V6, and V7. Thus, each memory cell can be programmed into one of the seven programming states "1" to "7", or it can remain unprogrammed in an "erase" state. As a result of programming, such as Figure 7B The initial distribution of the "erased" states shown becomes narrower, as... Figure 7C The “0” state indicates this. In this case, each memory state (i.e., “111”, “011”, “001”, “101”, “100”, “000”, “010”, and “110”) can be represented by a 3-bit code with a lower bit, a middle bit, and a higher bit. The 3-bit data can also be read from memory by sensing in “full sequence” mode, where the three bits are sensed together by sensing the calibration thresholds V1 to V7 in the seven self-passes.

[0069] exist Figures 4A to 4B and Figure 5As described in the preceding discussion, a two-dimensional (or planar) memory array 210 (e.g., located in the xy-plane) is generally described, which may include NAND-type memory cells. However, in an alternative configuration, the memory array may be in the form of a three-dimensional array, which, unlike those formed on a flat surface of a semiconductor wafer, extends upward from the wafer surface and includes stacks or columns of memory cells extending vertically upward (e.g., in the z-direction perpendicular to the xy-plane). For example, in Figure 8 An example embodiment of a NAND string 701 is depicted, which operates in a manner similar to a planar two-dimensional NAND string (such as NAND string 50 described above). In this configuration, memory cells are formed at the junction of vertical bit lines (see, for example, local bit line 703) and word lines (see, for example, word lines WL0, WL1, etc.), wherein a charge trapping layer is located between the local bit line 703 and the intersecting word lines that store charge (determining the threshold voltage of the transistor formed by the word line-gate-coupled to the vertical bit line-channel). To form such a vertical string 701, a stack of word lines is formed and memory vias are etched at appropriate locations where cells will be formed, wherein each memory via is lined with a charge trapping layer and filled with a suitable local bit line / channel material. A dielectric layer is included for necessary isolation. Furthermore, at either end of the NAND string 701 are select gates 705 and 707, which allow selective connection to or isolation from external components 709 and 711. External components 709 and 711 include conductors such as common source lines or bit lines serving the large number of strings 701 in the array. Figure 8 In the specific embodiment shown, the vertical NAND string 701 has 32 memory cells connected in series (i.e., at the junction between local bit line 703 and word line 0 to word line 31). However, the NAND string 701 may include any suitable number of memory cells.

[0070] As described above, the memory cells of memory structure 200 can be arranged in an ordered two-dimensional array of multiple rows and / or columns within a single memory device level. Alternatively, a three-dimensional memory array can be arranged such that the memory cells occupy multiple planes or multiple memory device levels, thereby forming a structure with three dimensions (e.g., in the x, y, and z directions, where the z direction is substantially perpendicular to the main surface of the semiconductor substrate, and the x and y directions are substantially parallel to the main surface of the semiconductor substrate). In some example embodiments, the three-dimensional memory structure 200 can be vertically arranged as a stack of multiple two-dimensional memory array device levels. In other example embodiments, the three-dimensional memory structure 200 is arranged as multiple vertical columns (where each column is substantially perpendicular to the main surface of the substrate, i.e., extending in the z direction), with each column having multiple memory cells. In this example, the vertical columns can be arranged in a two-dimensional configuration (i.e., in the xy plane) to form a three-dimensional arrangement in which the memory cells are on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three-dimensional memory array. However, in general, this can be achieved by tilting the two-dimensional memory structure in the vertical direction (i.e., the z-direction) perpendicular to the xy-plane (such as...). Figures 4A to 4B Structure 50 and Figure 5 The structure 210) is used to construct a three-dimensional NAND array, such that each yz plane of the three-dimensional structure corresponds to Figure 5 The page structure, where each plane is located at a different position along the x-axis. Therefore, the global bitline (e.g., Figure 5 Each of the BL0, ..., BLm lines travels across the top of the memory structure to its associated sense amplifier (e.g., SA0, ..., SAm). Therefore, word lines (e.g., ...) Figure 5 The WL0, ..., WLn) and source lines and select lines (e.g., SSL0, ..., SSLn and DSL0, ..., DSLn respectively) extend in the x direction, with the bottom of each NAND string (e.g., string 50) connected to a common source line.

[0071] Now for reference Figure 9 This image depicts a perspective view of an example sub-section of an embodiment of a three-dimensional NAND memory array 600 of the bit-cost scalable (“BiCS”) type, wherein one or more memory device stages are formed on a single substrate. The example sub-section corresponds to... Figure 4BThe two page structures shown can each correspond to a separate memory block or, depending on a particular embodiment, can be different extensions of the same block. According to this embodiment, the NAND strings are not located in the same yz plane, but are compressed in the y direction, resulting in an interleaved configuration of the NAND strings in the x direction. Furthermore, at the top of array 600, the NAND strings are connected along global bit lines (BLs), which span multiple sub-sections of array 600 traveling in the x direction. Additionally, global common source lines (SLs) also travel across multiple sub-sections of memory array 600 in the x direction and are connected to the sources at the bottom of the NAND strings via local interconnects (LIs), which operate as a single extended local common source line. However, depending on the embodiment, the global source line (SL) may span the entire or only a sub-section of memory array 600. Figure 9 The right side depicts a schematic diagram of one of the basic elements of a vertical NAND string 610 of a memory array 600. Similar to... Figure 4A The NAND strings 50 and 610 consist of a series of interconnected memory cells. String 610 is connected to an associated bit line (BL) via a drain-select gate (SGD). A source-select gate (SDS) connects string 610 to a global source line (SL) via an associated local source line (LI). In this particular embodiment, several dummy cells are also included at the ends of string 610. Because they are close to the select gates (SGD, SDS), they are sensitive to interference, and the dummy cells are not used to store user data.

[0072] Return to reference, for example Figure 1 The overall architecture of the memory system described in the text, Figure 10 The diagram illustrates a typical arrangement of such a memory array. In this example embodiment, a non-volatile memory array 200 is shown that can be accessed by read / write circuitry 170 via row decoder 140 and column decoder 160. As previously described, individual memory cells of memory array 200 can be addressed via a set of selected word lines(multiple) and bit lines(multiple) of word lines(multiple). Therefore, row decoder 140 selects one or more word lines and column decoder 160 selects one or more bit lines to apply an appropriate voltage to the corresponding gate of the addressed memory cell. Furthermore, read / write circuitry 170 is provided to read or write the memory state of the addressed memory cell, wherein read / write circuitry 170 includes several read / write modules that can be connected to the memory elements of array 200 via bit lines. According to its example embodiment, in Figure 11A schematic block diagram of this read / write module 190 is provided. In operation, during a read or verification step, a sense amplifier 150 determines the current flowing through the drain of the addressed memory cell connected via a select line. The level detected by the sense amplifier 150 is converted by level-to-bit conversion logic into a set of data bits to be stored in a data latch 155. Now return to the reference. Figure 10 The read / write circuits 170 are organized into groups of read / write stacks 180, where each read / write stack 180 is a stack of read / write modules 190.

[0073] Now for reference Figure 12A The illustration shows a memory device (e.g., such as a non-volatile memory array 300, which may include NAND-type SLC, MLC, TLC and / or QLC memory cells in a two-dimensional or three-dimensional configuration), control circuitry 310, and read / write circuitry 370. Figure 1 The example embodiment of memory device 102 is shown. Furthermore, as depicted, the read / write circuitry 370 comprises one or more sets of partitioned read / write stacks 400, thereby allowing parallel reading or programming of blocks (or “pages”) of memory cells, wherein, according to the example embodiment, the “pages” of memory cells constitute contiguous rows of memory cells. The memory array 300 is addressable by word lines via a row decoder 330 and by bit lines via a column decoder 360. Alternatively, the memory array 300 may comprise multiple rows of memory cells partitioned into multiple blocks or pages. Therefore, in such an example embodiment, a block multiplexer 350 is provided to multiplex the read / write circuitry 370 across the individual blocks.

[0074] Regarding control circuitry 310, it operates in conjunction with read / write circuitry 370 to perform memory operations on memory array 300. In this particular embodiment, control circuitry 310 includes state machine 312, on-chip address decoder 314, and power controller 316. State machine 312 provides chip-level control of memory operations. On-chip decoder 314 provides an address interface between addresses used by the host or memory controller and hardware addresses used by decoders 330, 360. Finally, power controller 316 controls the power and voltage supplied to word lines and bit lines during memory operations.

[0075] Figure 12B Depicting Figure 12A A slightly different example embodiment of the memory device. In this particular embodiment, access to the memory array 300 by various peripheral circuits is implemented symmetrically on opposite sides of the memory array 300. Therefore, compared with Figure 12ACompared to the previous configuration, the number of access lines and circuitry on each side of the memory array 300 is reduced by half. Specifically, the row decoder 330 is divided into multiple row decoders 330A and 330B, and the column decoder 360 is divided into multiple column decoders 360A and 360B. Furthermore, in an embodiment where one row of memory cells is divided into multiple blocks, the block multiplexer 350 is divided into multiple block multiplexers 350A and 350B. Similarly, the read / write circuitry 370 is divided into read / write circuitry 370A (connected to the bit lines from the bottom of the memory array 300) and read / write circuitry 370B (connected to the bit lines from the top of the memory array 300). Therefore, the density of the read / write modules (and the divided read / write stack 400) is substantially reduced by half.

[0076] Now for reference Figure 13 This illustrates an example embodiment of certain components in the read / write stack, such as... Figure 12A The read / write stack 400. According to this particular architecture, the read / write stack 400 includes a stack of sense amplifiers 212 for sensing “k” bit lines, I / O modules 440 for inputting or outputting data via I / O bus 231, a stack of data latches 430 for storing input and / or output data, a common processor 500 for processing and storing data between the read / write stacks 400, and a stack bus 421 for communication between the components of the read / write stack 400. Furthermore, a stack bus controller provides control and timing signals via line 411 to control the various components of the read / write stack 400. Figure 14A Describing the use of Figure 13 The read / write stack 400 of the embodiment is incorporated Figures 12A to 12BAn example embodiment of the read / write circuitry 370 of the memory device depicted is shown above. Each of the read / write stacks 400 operates in parallel on a set of "k" bit lines. Therefore, if a page in the memory array 300 has p = r * k bit lines, there will be "r" read / write stacks, i.e., read / write stacks 400-1, ..., 400-r. Thus, the entire set of partitioned read / write stacks 400-1, ..., 400-r operating in parallel allows for parallel reading or programming of blocks (or pages) of p cells along a row, with p read / write modules available for the entire row of cells. Since each read / write stack 400-1, ..., 400-r serves "k" memory cells, the total number of read / write stacks in the set can be expressed as r = p / k. Furthermore, according to this example, each read / write stack correspondingly has a stack of sense amplifiers 212-1, ..., 212-k, which serve in parallel segments of "k" memory cells. Furthermore, each read / write stack has a corresponding stack of data latches 430-1, ..., 430-k, each data latch being associated with a memory cell. Therefore, there exists an I / O module 440 that enables the data latches 430-1, ..., 430-k to exchange data externally via the I / O bus 231.

[0077] Still referencing Figure 14A The diagram also shows a stack bus controller 410, which receives signals from the memory controller 310 (via line 311) and subsequently provides control and timing signals to the read / write circuitry 370 via line 411. Communication between the read / write stacks 400 is achieved via an interconnect stack bus controlled by the stack bus controller 410. Therefore, control line 411 provides control and clock signals from the stack bus controller 410 to components of the read / write stacks 400-1, ..., 400-r. In this particular example, the interconnect stack bus is divided into SABus 422 and DBus 423, where SABus 422 provides communication between the common processor 500 and the stack sense amplifiers 212-1, ..., 212-k, and DBus 423 provides a communication path between the common processor 500 and the stacks of data latches 430-1, ..., 430-k. Regarding the common processor 500, it also includes an output 507 for outputting status signals for memory operations (such as error conditions). Figure 14A As shown, the status signal can, for example, be used to drive the gate of an n-transistor 550 connected to a flag bus 509 in a line OR configuration, wherein the flag bus 509 is precharged by the controller 310 and pulled down when asserted by any of the read / write stacks 400-1, ..., 400-r.

[0078] also, Figure 14BAn example embodiment of a single sensing block (such as that contained within a read / write stack 400) is depicted. Sensing block 400 is divided into one or more core portions including sensing modules 480 or sensing amplifiers, and a common portion is referred to as management circuitry 490. In one embodiment, there is a separate sensing module 480 for each bit line, and a common management circuitry 490 for a set of multiple (e.g., four or eight) sensing modules 480. Each sensing module in the set communicates with its associated management circuitry via a data bus 472. Thus, there are one or more management circuitries communicating with the set of sensing modules of storage element 10.

[0079] The sensing module 480 includes a sensing circuit 470 that senses whether the on-state current in the connected bit line is higher or lower than a predetermined threshold level. The sensing module 480 also includes a bit line latch 482 for setting voltage conditions on the connected bit line. For example, a predetermined state latched in the bit line latch 482 will cause the connected bit line to be pulled to a specified programming-disabled state (e.g., 1.5-3V). For example, flag = 0 disables programming, while flag = 1 does not disable programming.

[0080] exist Figure 14B In an example embodiment, management circuitry 490 includes a processor 492, four example sets 494, 495, 496, and 497 of example data latches, and an I / O interface 496 coupled between sets 494 to 497 of data latches and a data bus 231. A set of data latches may be provided for each sensing module 480, and each set may provide data latches identified by XDL, DDL, ADL, BDL, and CDL.

[0081] In some cases, additional data latches may be used. In one example approach, in a memory device using eight data states, XDL stores user data, DDL stores instructions on whether to use fast write programming, ADL stores the lower pages of data, BDL stores the middle pages of data, and CDL stores the higher pages of data.

[0082] Processor 492 performs calculations, such as determining data stored in the sensed storage element and storing the determined data in a set of data latches. Each set of data latches 494 to 497 is used to store data bits determined by processor 492 during a read operation and data bits imported from data bus 231 during a programming operation, representing data to be written into memory. I / O interface 496 provides an interface between data latches 494 to 497 and data bus 231.

[0083] During the read operation, the system operates under the control of state machine 312, which controls the supply of different control gate voltages to the addressed storage element 10. As predetermined control gate voltages corresponding to various memory states supported by the memory are progressively applied, the sensing module 480 can trip at one of these voltages, and the corresponding output is provided from the sensing module 480 to the processor 492 via bus 472. At this time, the processor 492 determines the resulting memory state by considering the tripping events(s) of the sensing module and information about the control gate voltages applied from the state machine via input line 493. The processor 492 then calculates the binary code of the memory state and stores the resulting data bits in data latches 494-497. In another embodiment of the management circuitry 490, the bit line latch 482 operates with dual-tasking capability, acting both as a latch for latching the output of the sensing module 480 and as a bit line latch as described above.

[0084] During programming or verification operations, the data to be programmed (written) is stored in sets 494 to 497 of data latches on data bus 231. Under the control of state machine 312, the programming operation includes a series of programming voltage pulses applied to the control gate of the addressed storage element. Each programming pulse is followed by a readback (verification) to determine whether the storage element has been programmed to the desired memory state. In some cases, processor 492 monitors the readback memory state relative to the desired memory state. When both are in agreement, processor 492 proceeds to set bit line latch 482 to pull the bit line to a specified programming-inhibited state. This prevents further programming of the storage element coupled to the bit line, even if the programming pulse appears on the control gate of the storage element. In other embodiments, the processor initially loads bit line latch 482 and sensing circuitry sets it to an inhibited value during the verification process.

[0085] As described above, each set of data latches 494 to 497 can be implemented as a stack of data latches for each sensing module. In one example embodiment, each sensing module 480 has three data latches. In some implementations, the data latches are implemented according to shift registers, such that parallel data stored therein is converted into serial data for the data bus 231 and vice versa. For example, all the data latches corresponding to a read / write block of M storage elements can be linked together to form a block shift register, thereby allowing input or output data blocks to be transmitted serially. In particular, groups of read / write modules can be adapted so that each of its data latches shifts data sequentially into or out of the data bus as if they were part of the shift register of the entire read / write block.

[0086] Data latches identify when an associated storage element 10 has reached certain milestones in a programming operation. For example, a latch can identify the V of a storage element. th Whether it is below a specific verification level. The data latch indicates whether the storage element is currently storing one or more bits from a data page. For example, with regard to an example embodiment, the ADL latch is toggled (e.g., from 0 to 1) when lower page bits are stored in the associated storage element. Furthermore, the BDL latch is toggled when middle page bits are stored in the associated storage element. And the CDL latch is toggled when higher page bits are stored in the associated storage element. When V th When the associated verification level is exceeded, the bit is stored in the storage element.

[0087] As mentioned above, these high-density memory structures, such as those related to... Figure 9 The BiCS type described in the example embodiments shown has relatively small spacing between adjacent memory cells and relatively small tolerances for each cell across discrete voltage ranges of memory function. Therefore, there are competing disadvantages and drawbacks in improving the effective storage capacity within a fixed die size. Consequently, various methods, as well as corrective and compensatory measures, can be employed to improve the accuracy, reliability, and efficiency of memory operation. For example, such measures aim to minimize interference between adjacent word lines (WLs) and enhance short-term data retention for scalable memory structures. Particularly interesting here is the reduction of adjacent-plane interference (NPD) due to one or more defective planes within a scalable memory structure. Generally, Figure 15A and 15B The illustration shows the potential impact of NPD conditions within a representative portion 800 of, for example, a three-dimensional NAND-type memory array. In this representative portion 800, two adjacent planes 810 and 820 are depicted. A series of common word lines, referred to as WLn+1, WLn, and WLn-1, are further depicted, which are also shared by the two planes 810 and 820. In this particular example, plane 810 is defect-free, while plane 820 is defective. The defective plane may be the result of various manufacturing or operational defects, such as, for example, a short circuit 824 between actual word lines or between a word line and a memory via. Figure 15A The potential impact of a defective plane 820 during standard programming operations is depicted. For example, biasing the programming voltage (V) PGM During programming operations applied to the representative word line WLn, the programming voltage bias (V) can be pulled up or down in the direction of arrow 822. PGM (For example, reduced to Vss or ground), a defective plane 820 is encountered at location 802. Relatedly, Figure 15BThe potential impact of the defective plane 820 during subsequent programming verification operations, in which the programming verification voltage bias (V) is depicted. VFY )830 is applied to the representative word line WLn. As indicated, the programming verification voltage bias (V) can be dragged upwards in the direction of arrow 832. VFY (For example, pulled up to VREAD), a defective plane 820 is encountered at location 802. Therefore, due to these interruptions in the programming / verification voltage bias, all planes in the programming sequence occurring after point 802 will fail overall, regardless of whether the downstream plane itself is defective. As mentioned above, this potentially catastrophic situation is commonly referred to as an adjacent plane interference (NPD) condition. Various methods, as well as corrective and compensatory measures, can be used to counteract programming interference or failures arising from NPD conditions within a multi-plane memory structure.

[0088] For example, now refer to Figure 16A and Figure 16B The example embodiment depicted illustrates a flowchart of a general framework for detecting and isolating one or more defective planes within a multi-plane memory structure operating in real time, such as during a programming verification operation. As described above, this particular device pattern is derived from observed electrical behavior, where defective planes (and, by extension, defect-free planes) require a specially extended sequence of programming cycles before reaching the expected verification threshold voltage level of the programming state (if any), due to the NPD condition causing the memory structure to actually undergo a programming voltage bias (V). PGM The downward skew of the device pattern. Furthermore, the disclosed device pattern reconstructs the normal programming operation of the (multiple) defect-free planes of the memory structure. Starting at step 900, a multi-plane, multi-state (e.g., MLC, TLC, QLC, etc.) type programming sequence or operation begins. Therefore, based on the current programming state (S)... X A programming pulse is initiated, followed by a programming verification operation (see step 902). Specifically, in the programming verification operation, a sensing operation is performed on each memory cell to determine the actual threshold voltage (V) of the memory cell. th Relative to the current programming state (S) X Is it higher or lower than the expected programming verification voltage level? Then, according to the bit scan mode operation, a threshold voltage (V) lower than the expected programming verification voltage level is applied. th The number of memory cells is counted and then compared with a bit scan using a failure criterion to determine whether programming has succeeded or failed. Furthermore, if, during the programming verification operation, the actual programming threshold voltage (V) of the memory plane(s) of the memory structure is detected or confirmed, the programming is considered successful. th If the voltage level is higher than the expected programming verification voltage level, then the current programming state (S) is...X The programming operation is considered successful (completed), and the corresponding status can be set to "passed". However, if the actual programming threshold voltage is detected or confirmed to be lower than the expected programming verification voltage level, and there is a threshold voltage (V) lower than the verification voltage level, the programming operation will be considered successful (completed). th If the number of memory cells is greater than the bit scan failure criterion, then the current programming state (S) is considered to be... X The programming operation was not completed, and the corresponding status can be set to "failed".

[0089] Still referencing Figure 16A In one embodiment, after each programming cycle (see step 902), based on the result of the programming verification operation / bit scan mode, it is determined whether the current programming state (S) has been completed for any memory plane of the subject memory structure. X The programming makes a determination (see step 904). If no plane has yet completed the current state (S) X If the programming of a plane is completed, a subsequent programming loop is initiated (see 901). This programming loop continues until at least one plane has completed its current programming state (S). X The programming of ) is then performed. At this point, it is determined whether the current programming state (S) of each plane of the subject memory structure has been completed. X Further determination is made regarding the programming of the planes (see step 906). If all planes have completed the current programming state (S)... X If the programming operation sequence continues to the next programming state (i.e., S), then the programming operation sequence continues to the next programming state. X =S X+1 And the programming loop count is reset in order to program the next state (S). X+1 Cataloging is performed (see step 908). This healthy progress in the programming state likely indicates that adjacent plane interference (NPD) conditions are not present in the subject memory structure. Conversely, if the determination made at step 906 indicates that the current programming state (S) is still not complete relative to one or more planes... X If the programming lag is not specified, it may be a result of an adjacent plane interference (NPD) condition. Thus, as described in detail below, the loop count is incremented by 1 as a mechanism to identify the possibility of an NPD condition and to effectively manage potentially defective planes (see step 910). At each increment of the loop count, it is determined whether the loop count exceeds a predetermined maximum (threshold) count (see step 912). If the loop count is below the threshold, a subsequent program loop is initiated (see 911) to continue attempting to reach the current state (S). X The programming operation. This programming cycle continues until all planes reach a completed programming state (i.e., relative to the current state (S)). X(Pass), or until the increased loop count exceeds a predetermined threshold. If the threshold count is exceeded, the programming operation enters the countermeasure mode (see step 914).

[0090] Continue forward to Figure 16B This describes the general framework of this countermeasure mode according to its example embodiments. Upon entering the countermeasure mode (see step 914), an initial determination is made as to whether to perform a complete failure measure (“all failure”), in which all memory planes of the subject memory structure are assigned a “failure” state and the memory structure is isolated from further programming operations (see step 916). This determination can be made based on predetermined criteria or a set of criteria derived from, for example, experimental observations, data, and results. Therefore, if the predetermined criteria or set of criteria is affirmatively satisfied, a complete failure measure is performed in general with respect to all memory planes (see step 918). However, if the predetermined criteria or set of criteria is not satisfied at step 916, then in the next action, only if the loop count exceeds a predetermined maximum count threshold (refer to reference)... Figure 16A Step 912) has the current programming state (S) X One or more planes that are not fully programmed are isolated and designated as “failed” under the assumption that they are defective (see step 920). By identifying and electrically isolating the defective planes only from the entire memory structure, normal programming operations can be resumed relative to the other “good” (i.e., defect-free) planes (see step 922).

[0091] Continue according to Figure 16B Before proceeding with further steps of the countermeasures mode of the example embodiments outlined herein, it may be helpful to provide additional explanations of the potential impact of adjacent plane interference (NPD) conditions on good or healthy (i.e., defect-free) planes within a multiplane memory structure. First, Figure 17A The current state (S) is described X The normal or expected programming operation of the memory is related to a healthy plane in the memory structure, where there are no material adjacent plane interference conditions. In this particular example, the initial programming voltage bias (V) PGM The initial programming voltage bias is 12.0 volts, and increases in 0.5 volt steps in each programming cycle until the programming verification operation indicates the threshold voltage (V) for programming the memory cells including that plane. th The expected programming verification voltage bias (V) has been passed. VFY This completes the programming of the current state (S). X As depicted, according to this example, the programmed voltage bias (V) PGM Once the voltage reaches 14.5 volts, the expected programming verification voltage bias (V) is finally achieved. VFYTherefore, upon completing the programming of the current state (S) X Previously, six programming loops were required. In contrast, due to the potential impact of material adjacent plane interference conditions, Figure 17B The text depicts Figure 17A The programming operation considered in the above description involves the skewness or alteration of the same plane. For example, a possible implication of a word line to memory hole short circuit or word line to word line short circuit in a defective plane is the programming voltage bias (V) experienced by a nearby good or healthy plane. PGM (This refers to) manual pulling or pulling. Therefore, such as Figure 17B As shown, with Figure 17A Compared to the expected 12.0 volts depicted, the actual initial programming voltage bias (V) as seen in this specific example from a healthy (defect-free) plane is... PGM It is 10.0 volts. This is due to the reduced programming voltage bias (V). PGM Now, an increased number of programming cycles is needed to reach the required 14.5 volts, thereby programming the threshold voltage (Vth) of the memory cell to a level higher than the expected target threshold voltage (Vth) (approximately 14.1 volts) with a set step size of 0.5 volts per programming cycle. Therefore, instead of just six programming cycles under normal operation, ten programming cycles are now required.

[0092] Now for reference Figure 18A ,use Figures 17A to 17B The example shown serves as background and generally depicts the intended programming operation of initiating a countermeasure pattern to stop programming one or more defective planes and restore (multiple) defect-free planes within the memory structure (see [link to example]). Figure 16B The effects of steps 920 and 922) on the healthy (defect-free) plane. Therefore, as Figure 17B As shown, Figure 18A The health plane is depicted as the current programmed state (S) X During this period, the initial programming voltage bias was artificially reduced by 10.0 volts (V). PGM Furthermore, in this particular example, a countermeasure mode is triggered based on a predetermined maximum count threshold after the sixth programming loop is completed (see, for example...). Figure 16A Steps 912 and 914). As described above, at the end of the sixth cycle, the programming threshold voltage (V) of the memory cell in the healthy plane. th It only reached 12.5 volts, thus failing to reach the expected programming verification voltage bias of approximately 14.1 volts (V). VFY Therefore, normal programming of the healthy plane is restored. Since, as a countermeasure mode function, the (multiple) defective planes are now electrically isolated from the programming operation, the healthy plane suddenly experiences a full or expected programming voltage bias (V) in the subsequent seventh programming cycle. PGMThe full or expected programmed voltage bias (V) PGM The initial programming voltage bias level is 12.0 volts, plus the sum of six progressively increasing increments of 0.5 volts, which equals the applied programming voltage bias of 15.0 volts (V). PGM Therefore, the current state (S) is reached during the seventh programming loop. X The expected programming threshold voltage (V) is approximately 14.5 volts. th In comparison, such as Figure 17B As shown, without introducing the game pattern, it would take ten programming loops to program the current state (S). X Therefore, the countermeasure pattern has proven to be a beneficial mechanism for effectively allowing the normal programming of other healthy planes within the memory structure to be restored, regardless of whether adjacent plane interference (NPD) conditions occur.

[0093] While game patterns offer significant improvements to memory device performance, further improvements to these game patterns can be identified to compensate for any potential inefficiencies that might result from the introduction of game patterns that depend on the parameters and environment in which the memory device is being programmed. For example, as in... Figure 18A As demonstrated in the example described, when the countermeasure mode is applied, the healthy plane may experience a programming voltage bias (V) due to the electrical isolation of one or more defect-free planes. PGM A sudden and significant increase in the level. Figure 18A In the illustrative example, the health plane experiences a sudden 2.5-volt jump immediately after initiating the countermeasure pattern in the next (seventh) programming loop. This 2.5-volt jump (“ΔV”) PGM This significantly exceeds the programmed voltage bias (V) in each cycle. PGM The normal gradual increase of 0.5 volts in the voltage range is as follows: Therefore, compared to... Figure 17A The "ideal case" described in the text (where the expected programming verification voltage bias (V) is reached during the sixth programming cycle) VFY Compared to the current state (S), the 15.0 volt programming voltage in the seventh programming cycle substantially exceeds the current state (S). X The expected programming voltage (V) is approximately 14.5 volts. th The voltage level is 0.5V. Therefore, depending on specific programming conditions, this type of countermeasure mode may introduce the risk of overprogramming relative to any given programming state. To mitigate this risk, a "rollback" or "fault recovery" mode can be incorporated into the countermeasure mode, designed to initially reduce the recovery programming voltage bias (V) when the countermeasure mode is activated. PGM And re-establish the programmed voltage bias (V) for each cycle. PGM The expectations in the text gradually increase. Therefore, attention returns to... Figure 16BThe further "fault recovery" mode is incorporated into the overall framework of this particular embodiment of the countermeasure mode. Specifically, when determining the plane through which the recovery programming(s) pass (see step 922), it is further determined whether to apply the "fault recovery" mode (see step 924).

[0094] Under certain predetermined conditions (e.g., in △V) PGM If the value is below a certain threshold, the resulting determination (at step 922) may be to not apply the "fault recovery" mode and continue programming (multiple) through the plane (e.g., according to the initial programming protocol) without applying the "fault recovery" mode. Figure 18A (See step 926). However, if the decision is to trigger the "fault recovery" mode, the loop counting and bit scan modes are temporarily paused, and the applied programming voltage bias (V) is applied immediately after the next programming cycle occurs following the initiation of the countermeasure mode. PGM The predetermined "rollback" voltage value will be decremented (see step 928). Furthermore, although the cycle count remains static (does not increase) during this "rollback," continuous programming cycles can be performed until the programming voltage bias (V) is reached. PGM The circuit catches up to the level reached during the last recording or incrementing of the loop count. At this point, the "rollback" cycle is complete, and loop counting and bit scan mode can be immediately resumed in the next programming cycle after the "rollback" cycle is completed. As a result of this "fault recovery" mode, it prevents the sudden application of a relatively significantly increased programming voltage bias (i.e., a relatively large ΔV). PGM ), and mitigate the unnecessarily large margin of overshoot expected programming verification voltage (V). VFY The risk of voltage level fluctuations. It should be noted that the predetermined "rollback" voltage value can be derived and optimized from experimental data and observations. For example, the predetermined "rollback" voltage value could be equivalent to a programming voltage bias (V) applied for one, two, four, or eight programming cycles before initiating the countermeasure mode. PGM The voltage level of ). To illustrate with an example, Figure 18B This demonstrates applying the "fault recovery" mode to... Figure 18A The problematic plane in an example embodiment of the game pattern depicted in the diagram. Again, in the current state (S X The countermeasure mode is initiated when the sixth programming cycle during the programming operation is completed, where the programmed threshold voltage (V) is... th The expected programming verification voltage (V) has not yet been reached. VFY (Level). Similar to the programming sequence. Figure 18A In contrast to the seventh programming loop described in the text, the "fault recovery" mode is initiated immediately after the countermeasure mode is initiated (i.e., between the recorded sixth and seventh programming loops) (see...). Figure 16BStep 928). The loop counting and bit scan mode are paused (remaining static in the sixth programming loop), and in this particular example, the programming voltage bias (V) is... PGM The decrementing or "rollback" is equivalent to two programming cycles (i.e., down to 12.0 volts). Thereafter, the programming voltage bias (V) is adjusted according to the intended programming protocol. PGM The voltage level increases in 0.5-volt increments until the programming voltage (V) is reached. PGM The level is reached during the last programming loop before initiating the countermeasure mode. Figure 18B In the illustrative example, the programming voltage bias (V) is applied just before entering the countermeasure mode. PGM The voltage level is 12.5 volts. Therefore, the programmed threshold voltage (V) th Once 12.5 volts is reached, the cycle counting and bit scan mode resumes to complete the current state (S). X Programming of ) (see Figure 16B Step 930). Therefore, when a programming voltage bias of 14.5 volts (V) is applied... PGM In the tenth program loop, the expected programmed verification voltage (V) is more carefully approached and stably reached. VFY The level, which would normally be present without the "fault recovery" mode (see...). Figure 18A The applied 15.0 volts are compared to a programming voltage bias of 14.5 volts (V). PGM ) is a significantly low voltage level.

[0095] Now for reference Figure 19 Once the "fault recovery" mode is completed and the loop counting and bit scan modes are restored (see step 930), normal programming and verification operations on the (multiple) health planes can continue until all programmable states are completed. More specifically, according to its example embodiment, in each programming loop, whether programming has passed with respect to the current state (S) X One or more bit scans of the current state (S) are determined by a failure criterion (see step 932). If not, an application of the current state (S) is made in the next programming loop. X The bit scan mode is applied to all programmable states, and the loop is repeated if necessary until a "pass" state is obtained (see step 934). Thereafter, a failure criterion is determined for programming with respect to one or more bit scans of all programmable states (see step 936). If a "pass" state is established for all programmable states, the programming memory plane is completed (see step 940). However, if a "pass" state is not established for each programmable state, the bit scan mode is also applied to the next programmable state in the next programming cycle (S). X =S X+1(See step 938). Therefore, in this particular embodiment, the bit scan mode is not applied to multiple programming states in each programming cycle, in order to save programming time, for example.

[0096] However, according to various observations, a side effect of incorporating "fault recovery" mode is that the erase state of memory cells in memory structures where "fault recovery" mode is applied exhibits a tailing threshold voltage (V). th This distribution reduces the reliability and accuracy of the programming data. (Return to reference) Figure 18B As mentioned above, when in "fault recovery" mode, the state machine is effectively frozen, pausing both loop counting and bit scan modes. Therefore, in this "fault recovery" mode, no determination is made regarding whether a programmable state has been completed (i.e., whether a "pass" state has been obtained). Consequently, when leaving "fault recovery" mode, state checks may lag behind by several loops in determining whether any programmable state has been completed. This is because, according to, for example... Figure 19 The normal programming and verification operations described herein determine the pass / fail status of only a single programmable state in each programming loop, and the current programmable state (S) X Once completed (i.e., passing the failure criterion through one or more bit scans), the bit scan mode only transitions gradually to the next programmable state (S). X+1 Therefore, after completing the "fault recovery" mode, a large series of additional programming cycles are required to catch up with determining the state of all programmable states. Thus, although the erase state is correctly disabled for each memory cell, the additional programming cycles may establish a higher than expected programming voltage bias (V). PGM The level of the signal can unintentionally erase the programmable state. To illustrate this phenomenon, Figure 20 The threshold voltage (V) of multiple memory cells including a given memory structure is described. th Example of a distribution graph. In this particular example, the memory cells have a TLC-type density. Therefore, the distribution graph indicates eight programmable states, namely "erase" and states A, B, C, D, E, F, and G. Figure 20 As shown, a distinguishable threshold voltage (V) appears for a memory cell in an "erased" state. th The distribution of memory cells shows an increase relative to the increase in the number of additional programming cycles imposed by the "fault recovery" mode. The graph points with the darkest color approximately represent the threshold voltage (V) expected under proper erase state disable conditions. th The distribution is as follows. In contrast, as the number of additional programming cycles increases, the threshold voltage (V) of the cell in the "erase" state increases. thThe distribution is unintentionally disturbed and potentially reaches a higher state (see hypothetical lines 950, 952). Therefore, a memory cell in the "erased" state may be misread as being programmed to a higher state.

[0097] To address the tailing threshold voltage (V) during the erase state th This problem with bit distribution, once it emerges from the "fault recovery" mode and normal programming and verification operations begin, can trigger a "catch-up" type bit scan mode. For example, Figure 21A and Figure 21B The overall framework of two example embodiments of this bit scanning mode is outlined. For example... Figure 21A As described in [the text], when resuming cycle counting and bit scan modes (see [reference]). Figure 16B In step 930 of the initial programming loop, one or more bit scans are applied to the state of each programming operation via a failure criterion, instead of proceeding to the next consecutive programming loop, unless the bit scan pattern indicates the current state (S). X One or more criteria for obtaining a "pass" status have not yet been met (see...). Figure 21A Steps 1000, 1002, and 1004). Therefore, the programming verification operation is allowed to "catch up" during this first programming cycle to detect all completed programming states not determined during the "fault recovery" mode. In the current programming state (S) X If the program is determined to be incomplete during the initial programming loop, it will be resolved through successive programming loops (e.g., see...). Figure 19 Proceed to the necessary stage (see steps 932, 934, 936, 938 and...). Figure 21A Step 940).

[0098] Figure 21B Example embodiments of the bit scan mode depicted in the text and Figure 21A The embodiment shown is slightly different. In this particular embodiment, in each programming cycle, not only in the initial programming cycle after the start of normal programming operations, but also by applying one or more bit scans of the state of each programmable operation through a failure criterion without proceeding to the next programming cycle (see [link to previous embodiment]). Figure 21B Step 2000).

[0099] Importantly, although according to Figures 21A to 21B The scanning of multiple states in each program loop of the example embodiment can in practice minimize the increase in programming time or the reduction in memory device performance, but the end result is not significant because the expected frequency of entering the countermeasure mode is low.

[0100] In addition, it should be noted that, although Figure 16A and Figure 16BThe example implementation of the "fault recovery" mode section of the countermeasures pattern described in the text specifies a temporary pause in the cycle counting and bit scan mode (see...). Figure 16B In step 928), depending on the specific example embodiment, the loop counting can be paused only temporarily while the bit scan mode continues to be applied. This mitigates the problem of the additional programming loops required to verify the completion of the programming state when resuming programming (multiple) health planes.

[0101] The foregoing discussion is intended to illustrate the principles and various embodiments of the invention. Many variations and modifications will become apparent to those skilled in the art upon a full understanding of the foregoing disclosure. For example, although the memory controller has been described as performing or controlling the methods described above, any processor executing software within a host system can perform the methods described above without departing from the scope of this disclosure. In particular, the methods and techniques described herein, performed in memory controller(s), can also be performed in the host system. Furthermore, the methods and concepts disclosed herein can be applied to other types of persistent memory besides flash memory. The following claims are intended to be interpreted as encompassing all such variations and modifications.

Claims

1. A method for programming a defect-free memory plane of a non-volatile memory structure subjected to adjacent-plane interference conditions, the method comprising: Based on the initial programming sequence, initiate a programming pulse for the current programming state and then initiate a programming verification operation; Initiate bit scan mode based on the bit scan failure criterion; Based on the bit scan failure criterion, once it is determined that the first memory plane of the memory structure has completed the programming of the current programming state, it is determined whether all memory planes of the memory structure have completed the programming of the current programming state. If not all memory planes have completed programming to the current programming state, increment the loop count and determine whether the loop count exceeds a predetermined threshold. If the cycle count exceeds the predetermined threshold: Then programming of one or more memory planes that are not fully programmed and have the current programming state will be stopped; The programming of one or more memory planes that have been programmed and have the current programming state is restored by the following: Temporarily pause the loop counting and bit scan modes; According to the initial programming sequence, a predetermined rollback voltage value is applied on the next programming pulse to reduce the programming voltage bias level that was originally expected during the programming pulse; Once the programmed threshold voltage level is equal to the programmed voltage bias level reached when the loop count is last incremented, the loop count and bit scan mode are restored. For each programmed state, apply the bit scan to pass the failure criterion; as well as Based on the bit scan failure criteria, the program will only proceed to the next programming cycle if it is determined that the programming state is not complete.

2. The method of claim 1, wherein applying the bit scan for each programmed state through the failure criterion and advancing to the next programming cycle only when it is determined that the programming state is not complete occurs only in the initial programming cycle after the cycle count and bit scan mode are resumed.

3. The method of claim 1, wherein applying the bit scan for each programmed state through the failure criterion and advancing to the next programming cycle only when it is determined that the programming state is not complete occurs in each programming cycle after the cycle count and bit scan mode are resumed.

4. The method of claim 1, wherein a predetermined threshold cyclic count value indicates the adjacent plane interference condition.

5. The method of claim 1, wherein the predetermined rollback voltage value is optimized based on resolution and efficiency parameters.

6. The method of claim 1, wherein the predetermined rollback voltage value is associated with a step increase on the programming voltage bias level occurring during at least one of the following: Two programming loops; Four programming loops; and Eight programming loops.

7. The method according to claim 1, wherein the programming verification operation is a stage of a TLC-type programming sequence.

8. A memory controller, comprising: The first port is configured to be coupled to a non-volatile memory, which includes a memory structure; and The memory controller is configured to take countermeasures during programming of the memory structure under adjacent-plane interference conditions, including: Based on the initial programming sequence, initiate a programming pulse for the current programming state and then initiate a programming verification operation; Initiate bit scan mode based on the bit scan failure criterion; Based on the bit scan failure criterion, once it is determined that the first memory plane of the memory structure has completed the programming of the current programming state, it is then determined whether all memory planes of the memory structure have completed the programming of the current programming state. If not all memory planes have completed programming to the current programming state, increment the loop count and determine whether the loop count exceeds a predetermined threshold. If the cycle count exceeds the predetermined threshold: Then programming of one or more memory planes that are not fully programmed and have the current programming state will be stopped; The following steps are used to restore the programming of one or more memory planes that have been programmed and have the current programming state: Temporarily pause the loop counting and bit scan modes; According to the initial programming sequence, a predetermined rollback voltage value is applied on the next programming pulse to reduce the programming voltage bias level originally expected during the programming pulse; Once the programmed threshold voltage level is equal to the programmed voltage bias level reached when the loop count is last incremented, the loop count and bit scan mode are restored. Apply the bit scan to each programmed state via the failure criterion; and Based on the bit scan failure criteria, the program will only proceed to the next programming cycle if it is determined that the programming state is not complete.

9. The memory controller of claim 8, wherein applying the bit scan for each programmed state through the failure criterion and advancing to the next programming cycle only when it is determined that the programming state is not complete occurs only in the initial programming cycle after the cycle count and bit scan mode are resumed.

10. The memory controller of claim 8, wherein applying the bit scan for each programmed state through the failure criterion and advancing to the next programming cycle only when it is determined that the programming state is not complete occurs in each programming cycle after the cycle count and bit scan mode are resumed.

11. The memory controller of claim 8, wherein a predetermined threshold cycle count value indicates the adjacent plane interference condition.

12. The memory controller of claim 8, wherein the predetermined rollback voltage value is optimized according to resolution and efficiency parameters.

13. The memory controller of claim 8, wherein the predetermined rollback voltage value is associated with a step increase on the programming voltage bias level occurring during at least one of the following: Two programming loops; Four programming loops; and Eight programming loops.

14. The memory controller of claim 8, wherein the programming verification operation is a stage of a TLC-type programming sequence.

15. A non-volatile memory system, comprising: Memory structures that withstand adjacent-plane interference conditions; The memory controller is coupled to the memory structure and: Based on the initial programming sequence, initiate a programming pulse for the current programming state and then initiate a programming verification operation; Initiate bit scan mode based on the bit scan failure criterion; Based on the bit scan failure criterion, once it is determined that the first memory plane of the memory structure has completed the programming of the current programming state, it is then determined whether all memory planes of the memory structure have completed the programming of the current programming state. If not all memory planes have completed programming to the current programming state, increment the loop count and determine whether the loop count exceeds a predetermined threshold. If the cycle count exceeds the predetermined threshold: Then programming of one or more memory planes that are not fully programmed and have the current programming state will be stopped; The programming of one or more memory planes that have been programmed and have the current programming state is restored by the following: Temporarily pause the loop counting and bit scan modes; According to the initial programming sequence, a predetermined rollback voltage value is applied on the next programming pulse to reduce the programming voltage bias level originally expected during the programming pulse; Once the programmed threshold voltage level is equal to the programmed voltage bias level reached when the loop count is last incremented, the loop count and bit scan mode are restored. For each programmed state, apply the bit scan to pass the failure criterion; as well as Based on the bit scan failure criteria, the program will only proceed to the next programming cycle if it is determined that the programming state is not complete.

16. The non-volatile memory system of claim 15, wherein applying the bit scan for each programmed state through the failure criterion and advancing to the next programming cycle only when it is determined that the programming state is not complete occurs only in the initial programming cycle after the cycle count and bit scan mode are restored.

17. The non-volatile memory system of claim 15, wherein applying the bit scan for each programmed state through the failure criterion and advancing to the next programming cycle only when it is determined that the programming state is not complete occurs in each programming cycle after the cycle count and bit scan mode are resumed.

18. The non-volatile memory system of claim 15, wherein a predetermined threshold cycle count value indicates the adjacent plane interference condition.

19. The non-volatile memory system of claim 15, wherein the predetermined rollback voltage value is optimized according to resolution and efficiency parameters.

20. The non-volatile memory system of claim 15, wherein the predetermined rollback voltage value is associated with a step increase on the programming voltage bias level occurring during at least one of the following: Two programming loops; Four programming loops; and Eight programming loops.

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