Method for preparing semiconductor structure and semiconductor structure

Abstract

The present invention relates to a method for manufacturing a semiconductor structure and a semiconductor structure. The method includes: providing a preliminary body of a semiconductor device, where the preliminary body of the semiconductor device includes a conductive lead-out surface; performing a sputtering coating process at a first preset power to form a first metal layer on the conductive lead-out surface; performing a sputtering coating process at a second preset power to form a second metal layer on the first metal layer; the settings of the first preset power and the second preset power satisfy: making the grain size of the first metal layer larger than the grain size of the second metal layer; performing an annealing treatment at a first preset temperature; the setting of the first preset temperature satisfies: making the first metal layer establish an ohmic contact with the conductive lead-out surface. The method for manufacturing a semiconductor structure and the semiconductor structure provided by the present invention enable the semiconductor device to have more stable performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular, to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] A fast recovery diode (FRD) is a semiconductor diode with good switching characteristics and short reverse recovery time. It is mainly used in electronic circuits such as switching power supplies, pulse width modulation (PWM) converters, and frequency converters as a high-frequency rectifier diode, a freewheeling diode, or a damping diode. The internal structure of the fast recovery diode is different from that of an ordinary PN junction diode. It belongs to a PIN junction diode, that is, a base region I is added between the P-type silicon material and the N-type silicon material to form a PIN silicon wafer. Because the base region is very thin and the reverse recovery charge is very small, the reverse recovery time of the fast recovery diode is short, the forward voltage drop is low, and the reverse breakdown voltage is high.

[0003] Sputter coating refers to a technique in a vacuum chamber where energetic particles bombard the surface of a target, causing the bombarded target ions to deposit on a substrate. In fact, it uses the sputtering phenomenon to achieve the purpose of producing various thin films. Due to its good morphology and electrical properties, aluminum-silicon alloy (AlSi) is formed as the electrode of the FRD on a silicon-based semiconductor structure through the sputter coating process, which is widely used in the industry. For high-frequency usage scenarios or scenarios that require fast switching speed, the FRD needs to use a silicon-based semiconductor substrate with a low surface doping concentration. For a silicon-based semiconductor substrate with a low surface doping concentration, in order to form a good ohmic contact with the electrode, the aluminum-silicon alloy layer formed by sputter coating needs to be annealed at a high process temperature, which results in the recrystallization of the aluminum-silicon alloy and the appearance of weak points at the grain boundaries. In the subsequent process of strong alkali and acid, the aluminum-silicon alloy is corroded through, and the strong alkali and acid penetrate through the aluminum-silicon alloy into the silicon-based semiconductor substrate, resulting in void defects in the silicon-based semiconductor substrate and affecting the performance of the FRD. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a method for preparing a semiconductor structure and a semiconductor structure to solve at least one problem in the background art.

[0005] To achieve the above object, the technical solution of the present application is realized as follows:

[0006] In a first aspect, embodiments of the present application provide a method for preparing a semiconductor structure, the method comprising:

[0007] Providing a semiconductor device precursor, the semiconductor device precursor including a conductive lead-out surface;

[0008] Perform a sputtering coating process at a first preset power to form a first metal layer on the conductive lead-out surface;

[0009] Perform a sputtering coating process at a second preset power to form a second metal layer on the first metal layer; the settings of the first preset power and the second preset power satisfy: making the grain size of the grains in the first metal layer larger than the grain size of the grains in the second metal layer;

[0010] Perform an annealing treatment at a first preset temperature; the setting of the first preset temperature satisfies: making the first metal layer establish an ohmic contact with the conductive lead-out surface.

[0011] Optionally, the material of the semiconductor device body includes silicon.

[0012] Optionally, the materials of both the first metal layer and the second metal layer include aluminum-silicon alloy.

[0013] Optionally, the first preset power is 13KW - 16KW, and the second preset power is 8KW - 12KW.

[0014] Optionally, the first preset temperature is greater than or equal to 450 degrees Celsius.

[0015] In a second aspect, an embodiment of the present application provides a semiconductor structure, and the semiconductor structure includes:

[0016] A semiconductor device body, and the semiconductor device body includes a conductive lead-out surface;

[0017] A first metal layer, located on the conductive lead-out surface and in ohmic contact with the conductive lead-out surface;

[0018] A second metal layer, located on the first metal layer and conductively connected to the first metal layer; the grain size of the grains in the first metal layer is larger than the grain size of the grains in the second metal layer.

[0019] Optionally, the thickness of the first metal layer is greater than or equal to 2 microns.

[0020] Optionally, the thickness of the second metal layer is greater than or equal to 2 microns.

[0021] Optionally, the material of the semiconductor device body includes silicon.

[0022] Optionally, the materials of both the first metal layer and the second metal layer include aluminum-silicon alloy.

[0023] A method for preparing a semiconductor structure and a semiconductor structure provided by an embodiment of the present application include: providing a semiconductor device body; performing a sputtering coating process at a first preset power to form a first metal layer on a conductive lead-out surface of the semiconductor device body; the conductive lead-out surface is formed on the semiconductor device body; performing a sputtering coating process at a second preset power to form a second metal layer on the first metal layer; the settings of the first preset power and the second preset power satisfy: making the grain size of the grains of the first metal layer larger than the grain size of the grains of the second metal layer; performing an annealing treatment at a first preset temperature; the setting of the first preset temperature satisfies: making the first metal layer establish an ohmic contact with the conductive lead-out surface. Among them, after the first metal layer is subjected to an annealing treatment at the first preset temperature, it can establish an ohmic contact with the conductive lead-out surface; and the second metal layer, due to having grains with a smaller size than the first metal layer, is not prone to having weak points at the grain boundaries even when subjected to an annealing treatment at the first preset temperature, and has a stronger ability to resist strong alkali and acid. Thus, the method for preparing a semiconductor structure and the semiconductor structure provided by an embodiment of the present application enable the semiconductor structure to have a stronger ability to resist strong alkali and acid, and enable the semiconductor device to have more stable performance.

[0024] Additional aspects and advantages of the present application will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings described herein are used to provide a further understanding of the present application, constitute a part of the present application, and the schematic embodiments and descriptions thereof of the present application are used to explain the present application, and do not constitute an improper limitation to the present application. In the drawings:

[0026] Figure 1 is a schematic flowchart of the method for preparing a semiconductor structure provided by an embodiment of the present application;

[0027] Figure 2 is a schematic cross-sectional view of a semiconductor structure provided by an embodiment of the present application;

[0028] Figure 3 is an electron microscope photograph of the metallographic structure of a semiconductor substrate after a semiconductor structure including a semiconductor substrate with a low doping concentration and a metal layer sputtered at a low power has undergone high-temperature annealing and strong alkali immersion;

[0029] Figure 4 is an electron microscope photograph of the metallographic structure of a semiconductor substrate after a semiconductor structure including a semiconductor substrate with a low doping concentration and a metal layer sputtered at a high power has undergone high-temperature annealing and strong alkali immersion;

[0030] Figure 5SEM micrograph of the metallographic structure of a semiconductor substrate after high-temperature annealing and strong alkali immersion of a semiconductor structure fabricated by the method for fabricating a semiconductor structure provided by an embodiment of the present application.

[0031] Description of reference numerals:

[0032] 20. Initial body of semiconductor device; 21. Conductive lead-out surface; 30. First metal layer; 40. Second metal layer. Detailed implementation manners

[0033] Exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present application can be more thoroughly understood and the scope of the present application disclosed can be fully conveyed to those skilled in the art.

[0034] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. However, it will be apparent to one of ordinary skill in the art that the present application may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present application; that is, not all features of actual embodiments are described here, and well-known functions and structures are not described in detail.

[0035] In the drawings, for clarity, the dimensions of layers, regions, elements and their relative dimensions may be exaggerated. The same reference numerals throughout the drawings denote the same elements.

[0036] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, without departing from the teachings of the present application, the first element, component, region, layer or portion discussed below may be referred to as the second element, component, region, layer or portion. And when discussing the second element, component, region, layer or portion, it does not necessarily mean that the present application necessarily has a first element, component, region, layer or portion.

[0037] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures with other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms are also intended to include different orientations of the device in use and operation. For example, if the device in the attached drawings is flipped, then an element or feature described as "under other elements" or "beneath it" or "under it" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both the upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0038] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0039] To fully understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solutions of the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may have other embodiments.

[0040] In view of the technical problems in the prior art, an embodiment of the present application provides a method for preparing a semiconductor structure. Figure 1 is a schematic flow chart of the method for preparing a semiconductor structure provided by an embodiment of the present application. Figure 2 is a cross-sectional schematic diagram of a semiconductor structure provided by an embodiment of the present application, in combination with Figure 1 and Figure 2 , the method includes:

[0041] Step 101: Provide a semiconductor device precursor 20, and the semiconductor device precursor 20 includes a conductive lead-out surface 21;

[0042] Step 102: Perform a sputtering coating process at a first preset power to form a first metal layer 30 on the conductive lead-out surface 21;

[0043] Step 103: Perform a sputtering coating process at a second preset power to form a second metal layer 40 on the first metal layer 30; the settings of the first preset power and the second preset power satisfy: making the grain size of the first metal layer 30 larger than the grain size of the second metal layer 40;

[0044] Step 104: Perform an annealing treatment at a first preset temperature; the setting of the first preset temperature satisfies: making the first metal layer 30 establish an ohmic contact with the conductive lead-out surface 21.

[0045] The method for preparing a semiconductor structure provided by the embodiments of the present application can be used for the preparation of FRD or other semiconductor devices. Below, taking FRD as an example, the above steps will be introduced in detail.

[0046] In the above step 101, the semiconductor device body 20 can be a semi-finished product in the processing of a semiconductor device. In this embodiment, the semiconductor device body 20 may include a semiconductor substrate and a conductive lead-out surface 21 formed on the semiconductor substrate. In some embodiments, the material of the semiconductor device body 20 includes silicon. Specifically, the semiconductor substrate may be composed of silicon. In this embodiment, the surface doping concentration of the conductive lead-out surface 21 is relatively low, that is, the conductive lead-out surface 21 is a low-doped surface.

[0047] In the above step 102, the first metal layer 30 is formed by a sputtering coating process. The first metal layer 30 is formed on the conductive lead-out surface 21 of the semiconductor device body 20 to establish an electrical connection with the conductive lead-out surface 21. The thickness of the first metal layer 30 can be formed in one sputtering or accumulated in multiple sputterings. In this way, the method for preparing a semiconductor structure according to the embodiments of the present application can be performed under various production conditions and has stronger adaptability.

[0048] In the above step 103, the second metal layer 40 is formed by a sputtering coating process. The second metal layer 40 is formed on the first metal layer 30 to establish an electrical connection with the first metal layer 30. The thickness of the second metal layer 40 can be formed in one sputtering or accumulated in multiple sputterings.

[0049] Exemplarily, the power of sputtering coating is mainly set according to the material to be sputtered, the material to be coated, and the preset size of the grains of the sputtered film layer. In this embodiment, compared with the corresponding material to be sputtered, the material to be coated, and the grain size of the conventional sputtered film layer, the first preset power is similar to the conventional sputtering coating power, while the second preset power is lower than the conventional sputtering coating power. And the size of the sputtering coating power will directly affect the grain size of the sputtered film layer. Therefore, the above settings can make the settings of the first preset power and the second preset power satisfy: making the grain size of the first metal layer 30 larger than the grain size of the second metal layer 40. It can be understood that in some cases, the second preset power may be higher than the conventional sputtering coating power, because only within a certain power range, the grain size is positively correlated with the sputtering coating power. Beyond this range, the grain size may be negatively correlated with the sputtering coating power or have other relationships.

[0050] Exemplarily, there may be multiple second metal layers 40, and correspondingly, there may also be multiple second preset powers. For example, one second metal layer is formed under one second preset power, and another second metal layer is formed under another second preset power, and so on. Multiple second metal layers can form a composite film layer composed of multiple film layers with different grain sizes.

[0051] In some embodiments, the materials of the first metal layer 30 and the second metal layer 40 may both include aluminum-silicon alloy. Specifically, both the first metal layer 30 and the second metal layer 40 may be film layers composed of aluminum-silicon alloy. Exemplarily, in the sputtering process, the target material is aluminum-silicon alloy, and the material to be coated is silicon. During the sputtering process, energetic particles bombard the aluminum-silicon alloy, and the ions of the bombarded aluminum-silicon alloy leave the target and deposit on the surface of the material to be coated, silicon. In this embodiment, the aluminum-silicon alloy is a conductive wiring layer with a semiconductor structure, which not only has good conductivity but also can be well compatible with silicon.

[0052] In the above step 104, annealing treatment is performed at a first preset temperature, and the purpose is to establish an ohmic contact between the first metal layer 30 and the conductive lead-out surface 21. Annealing uses thermal energy to eliminate some defects that cause internal stress in the object due to ion implantation or other reasons. The applied energy will increase the vibration and diffusion of lattice atoms and defects in the object, enabling the rearrangement of atomic arrangements. To achieve the purpose of establishing an ohmic contact between the first metal layer 30 and the conductive lead-out surface 21, the first preset temperature is set to: a temperature value that can establish a better ohmic contact between the first metal layer 30 and the conductive lead-out surface 21. In some embodiments, the first preset temperature may be a temperature value higher than the normal annealing temperature or equal to the upper limit of normal annealing, which is simply referred to as high-temperature annealing. Exemplarily, performing annealing treatment at the first preset temperature can establish a better ohmic contact between the first metal layer 30 and the conductive lead-out surface 21. However, it is also easy for the first metal layer 30 to have weak points at the grain boundaries during the recrystallization process, resulting in being corroded and penetrated by strong alkali or acid substances in subsequent processes, allowing the strong alkali or acid substances to enter the interior of the semiconductor structure and affecting the performance of the semiconductor device. In the semiconductor structure preparation method provided by the embodiments of the present application, a second metal layer 40 is added on the first metal layer 30. The grains of the second metal layer 40 are small, that is, the grains are finer and the film layer is denser. In this way, even after high-temperature annealing and recrystallization, it is not easy to generate weak points at the grain boundaries, making the semiconductor structure have stronger resistance to strong alkali or acid. The strong alkali or acid can be any one of strong alkali or strong acid, or it can be strong alkali first and then strong acid, or strong acid first and then strong alkali. Further, if there are multiple second metal layers, the resistance to strong alkali or acid may be further enhanced.

[0053] Regarding the corrosion resistance of different metal layers coated on the semiconductor device body 20 after being soaked in strong alkali or acid substances, reference can be made to Figures 3 - 5 : Figure 3 is an electron microscope photograph of the metallographic structure of a semiconductor substrate after a semiconductor structure including a semiconductor substrate with a low doping concentration and a metal layer sputtered at low power has undergone high-temperature annealing and strong alkali immersion; Figure 4 is an electron microscope photograph of the metallographic structure of a semiconductor substrate after a semiconductor structure including a semiconductor substrate with a low doping concentration and a metal layer sputtered at high power has undergone high-temperature annealing and strong alkali immersion; Figure 5 is an electron microscope photograph of the metallographic structure of a semiconductor substrate after a semiconductor structure prepared by the semiconductor structure preparation method provided by the embodiments of the present application has undergone high-temperature annealing and strong alkali immersion. From Figure 3 it can be seen that Figure 3 there are no obvious corroded cavities in the metallographic structure of the semiconductor substrate in Figure 4 it can be seen thatFigure 4 The metallographic structure of the semiconductor substrate in the process has obvious corroded cavities, which will affect the performance of the semiconductor device. Figure 5 It can be seen that the same Figure 3 Similar to, different from Figure 4 , Figure 5 The metallographic structure of the semiconductor substrate has no obvious corroded voids, and the first metal layer 30 formed by sputtering at the first preset power in the embodiment of the present application can enable the conductive lead surface 21 to form a good ohmic contact with the conductive connection layer.

[0054] In order to further verify whether good ohmic contact is formed between the conductive lead surface 21 and the conductive connection layer in the semiconductor structure formed by the preparation method of the semiconductor structure of the embodiment of the present application, Table 1 below shows the forward transient voltage (VF) at a current of 40A in the intermediate test (CP) and the final test (FT).

[0055]

[0056] Table 1

[0057] In Table 1:

[0058] Low-power sputtering coating is a solution of forming a conductive wiring layer on the conductive lead-out surface 21 using only low-power sputtering coating, which is equivalent to forming only one second metal layer 40 using a second preset power sputtering coating.

[0059] High-power sputtering coating is a solution that only uses high-power sputtering coating to form a conductive connection layer on the conductive lead-out surface 21, which is equivalent to only forming a first metal layer 30 using a first preset power sputtering coating.

[0060] High-power sputtering coating + low-power sputtering coating is the solution adopted in the embodiment of the present application, that is, firstly a first preset power sputtering coating is adopted to form the first metal layer 30, and then a second preset power sputtering coating is adopted to form the second metal layer 40.

[0061] Because high-power sputtering can form good ohmic contact, high-power sputtering is used as the standard value in Table 1, used as the benchmark for evaluating the other two solutions. As can be seen from Table 1, the low-power sputtering solution suffers from a large VF voltage difference caused by poor ohmic contact, while the solution of the embodiment of the present application passed both the CP test and the FT test, with relatively small differences.

[0062] In some embodiments, the first preset power may be 13KW - 16KW, such as 13KW, 13.5KW, 14KW, 14.5KW, 15KW, 15.5KW, 16KW, etc. The second preset power may be 8KW - 12KW, such as 8KW, 8.5KW, 9KW, 9.5KW, 10KW, 10.5KW, 11KW, 11.5KW, 12KW, etc. That is, the second preset power is less than the first preset power, and within the power range included in the first preset power and the second preset power, the size of the grains of the metal layer formed by the sputtering coating process is positively correlated with the sputtering power. In this embodiment, the sputtering power range of 13KW - 16KW can not only enable the grain size of the first metal layer 30 to establish a better ohmic contact with the conductive lead-out surface 21 of the semiconductor device body 20, but also is a power range that is relatively easy to implement and energy-saving for the sputtering equipment. Similarly, the sputtering power range of 8KW - 12KW can not only enable the grain size of the second metal layer 40 to be less likely to generate weak points at the grain boundaries during high-temperature annealing, but also is a power range that is relatively easy to implement and energy-saving for the sputtering equipment. As mentioned above, the power of sputtering coating is mainly set according to the material to be sputtered, the material to be coated, and the preset size of the grains of the sputtered film layer. Therefore, it can be understood that when the materials of the first metal layer 30 and the second metal layer 40 both include aluminum-silicon alloy, and the material of the semiconductor substrate includes silicon, the first preset power can be further determined within a more appropriate range within the above range, such as 13KW - 14KW, etc.

[0063] In some embodiments, the first preset temperature may be greater than or equal to 450 degrees Celsius. This is an annealing temperature setting that can enable the first metal layer 30 to establish an ohmic contact with the conductive lead-out surface 21. At this annealing temperature or above, the first metal layer 30 can utilize more thermal energy to increase the vibration and diffusion of lattice atoms and defects in the object, so that the arrangement of atoms can be reorganized in a larger range. This makes the physical contact between the first metal layer 30 and the conductive lead-out surface 21 of the semiconductor device body 20 better, such as a larger contact area or closer contact, so that a better ohmic contact is established between the two. Generally, the setting of the annealing temperature also needs to consider the material to be annealed. For example, in the case where the materials of the first metal layer 30 and the second metal layer 40 both include aluminum-silicon alloy, the first preset temperature may be 450 degrees Celsius - 455 degrees Celsius, such as 450 degrees Celsius, 451 degrees Celsius, 452 degrees Celsius, 453 degrees Celsius, 454 degrees Celsius, 455 degrees Celsius, etc.

[0064] In some embodiments, the thickness of the first metal layer 30 may be greater than or equal to 2 micrometers. In this way, with sufficient thickness, it is easier to establish good ohmic contact with the conductive lead-out surface 21, and it will not excessively increase the sputtering coating time. Moreover, with sufficient thickness, there is also enough space for the atoms to vibrate and diffuse during high-temperature annealing. In actual implementation, the thickness of the first metal layer 30 may be equal to 2 micrometers. In this way, both the ohmic contact between the first metal layer 30 and the conductive lead-out surface 21 can be achieved, and the power consumption can be better reduced.

[0065] In some embodiments, the thickness of the second metal layer 40 is greater than or equal to 2 micrometers. In this way, with sufficient thickness, it can block the invasion of substances such as strong alkalis and strong acids by virtue of its finer crystal grains and other crystal characteristics, and it will not excessively increase the sputtering coating time. In actual implementation, the thickness of the second metal layer 40 may be greater than 2 micrometers. In this way, the second metal layer 40 can have stronger resistance to strong alkalis and strong acids.

[0066] The embodiment of the present application also provides a semiconductor structure, as Figure 5 shown, the semiconductor structure includes:

[0067] A semiconductor device body 20, the semiconductor device body 20 includes a conductive lead-out surface 21;

[0068] A first metal layer 30, located on the conductive lead-out surface 21, and in ohmic contact with the conductive lead-out surface 21;

[0069] A second metal layer 40, located on the first metal layer 30, and electrically connected to the first metal layer 30; the grain size of the first metal layer 30 is larger than the grain size of the second metal layer 40.

[0070] The semiconductor structure provided by the embodiment of the present application may be a partial structure of an FRD or a partial structure of other semiconductor devices. Below, taking the FRD as an example mainly, the above semiconductor structure will be introduced in detail.

[0071] Exemplarily, the semiconductor device body 20 may be a semi-finished product during the processing of a semiconductor device. In this embodiment, the semiconductor device body 20 may include a semiconductor substrate and a conductive lead-out surface 21 formed on the semiconductor substrate.

[0072] In some embodiments, the material of the semiconductor device body 20 includes silicon. Specifically, the semiconductor substrate may be composed of silicon. In this embodiment, the surface doping concentration of the conductive lead-out surface 21 is relatively low, that is, the conductive lead-out surface 21 is a low-doped surface.

[0073] Exemplarily, the first metal layer 30 is located on the conductive lead-out surface 21 of the semiconductor device body 20 and is in ohmic contact with the conductive lead-out surface 21 to establish a conductive connection with the conductive lead-out surface 21.

[0074] Exemplarily, the second metal layer 40 is formed on the first metal layer 30 to establish a conductive connection with the first metal layer 30. Exemplarily, there may be multiple second metal layers, and the multiple second metal layers may form a composite film layer composed of film layers with different grain sizes. It should be noted that in the figure, only one second metal layer 40 is shown. Figure 2 In the figure, only one second metal layer 40 is shown.

[0075] In some embodiments, the materials of the first metal layer 30 and the second metal layer 40 both include aluminum-silicon alloy. Specifically, both the first metal layer 30 and the second metal layer 40 may be film layers made of aluminum-silicon alloy. In this embodiment, the aluminum-silicon alloy is the conductive connection layer of the semiconductor structure, which not only has good conductivity but also is well compatible with silicon.

[0076] In some embodiments, the thickness of the first metal layer 30 is greater than or equal to 2 microns. In this way, with sufficient thickness, it is easier to establish good ohmic contact with the conductive lead-out surface 21, and it will not excessively increase the sputtering coating time. Moreover, with sufficient thickness, there is also enough space for atoms to vibrate and diffuse during high-temperature annealing. In actual implementation, the thickness of the first metal layer 30 may be equal to 2 microns. In this way, both the ohmic contact between the first metal layer 30 and the conductive lead-out surface 21 can be achieved, and the power consumption can be better reduced.

[0077] In some embodiments, the thickness of the second metal layer 40 is greater than or equal to 2 microns. In this way, with sufficient thickness, it can block the invasion of strong acids and alkalis by virtue of its finer crystal grains and other crystal characteristics, and it will not excessively increase the sputtering coating time. In actual implementation, the thickness of the second metal layer 40 may be greater than 2 microns. In this way, the second metal layer 40 can have stronger resistance to strong acids and alkalis.

[0078] For the semiconductor structure provided in the embodiments of the present application, a second metal layer 40 is added on the first metal layer 30. The grains of the second metal layer 40 are small in size, that is, the grains are finer and the film layer is denser. In this way, even after high-temperature annealing and recrystallization, it is not easy to generate weak points at the grain boundaries, making the semiconductor structure have stronger resistance to strong acids and alkalis. Further, if there are multiple second metal layers, the resistance to strong acids and alkalis may be further enhanced.

[0079] It should be noted that the semiconductor structure embodiments provided in this application and the semiconductor structure preparation method embodiments belong to the same concept; among the technical features in the technical solutions recorded in each embodiment, they can be arbitrarily combined without conflict. However, it should be further noted that for the semiconductor structure provided in the embodiments of this application, the combination of its various technical features can already solve the technical problems to be solved in this application; therefore, the semiconductor structure provided in the embodiments of this application may not be limited by the semiconductor structure preparation method provided in the embodiments of this application, and any semiconductor structure prepared by a preparation method that can form the semiconductor structure provided in the embodiments of this application is within the protection scope of this application.

[0080] It should be understood that the above embodiments are all exemplary and are not used to cover all possible implementation manners included in the claims. Various deformations and changes can be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments can also be arbitrarily combined to form other embodiments of the present invention that may not be clearly described. Therefore, the above embodiments only represent several implementation manners of the present invention and do not limit the protection scope of the present invention patent.

Claims

1. A method for preparing a semiconductor structure, characterized in that, The method includes: providing a semiconductor device body, the semiconductor device body including a conductive lead-out surface; performing a sputtering coating process at a first preset power to form a first metal layer on the conductive lead-out surface; performing a sputtering coating process at a second preset power to form a second metal layer on the first metal layer; the settings of the first preset power and the second preset power satisfy: making the grain size of the first metal layer larger than the grain size of the second metal layer; the ability of the second metal layer to resist strong alkali and acid is greater than that of the first metal layer; the number of the second metal layers is one or more; performing an annealing treatment at a first preset temperature; the setting of the first preset temperature satisfies: making the first metal layer establish an ohmic contact with the conductive lead-out surface.

2. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The material of the semiconductor device body includes silicon.

3. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The materials of the first metal layer and the second metal layer both include aluminum silicon alloy.

4. The method for preparing a semiconductor structure according to claim 1, wherein, The first preset power is 13KW to 16KW, and the second preset power is 8KW to 12KW.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first preset temperature is greater than or equal to 450 degrees Celsius.

6. A semiconductor structure, characterized in that, The semiconductor structure includes: a semiconductor device body, the semiconductor device body including a conductive lead-out surface; a first metal layer, located on the conductive lead-out surface and in ohmic contact with the conductive lead-out surface; a second metal layer, located on the first metal layer and electrically connected to the first metal layer; the grain size of the first metal layer is larger than the grain size of the second metal layer; the ability of the second metal layer to resist strong alkali and acid is greater than that of the first metal layer; the number of the second metal layers is one or more.

7. The semiconductor structure according to claim 6, wherein The thickness of the first metal layer is greater than or equal to 2 microns.

8. The semiconductor structure according to claim 6, wherein The thickness of the second metal layer is greater than or equal to 2 microns.

9. The semiconductor structure according to claim 6, wherein The material of the semiconductor device body includes silicon.

10. The semiconductor structure according to claim 6, wherein, The materials of the first metal layer and the second metal layer both include aluminum silicon alloy.

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