Array substrate and manufacturing method thereof

Abstract

The present invention discloses an array substrate and a manufacturing method thereof, wherein the array substrate comprises a substrate, a dielectric layer, an active component, a plurality of fan-out conductors and at least one dummy conductor. The substrate has a display area and a fan-out area. The dielectric layer is located on the substrate. The active component is on the display area of ​​the substrate. The plurality of fan-out conductors are electrically connected to the active component, a first gap is provided between two adjacent fan-out conductors, and a region of the dielectric layer corresponding to a vertical projection of the first gap comprises a first lightly doped region. At least one dummy conductor is located outside the fan-out conductor.

Description

Technical Field

[0001] The invention relates to an array substrate and a manufacturing method thereof. Background Art

[0002] The array substrate may include a display area and a non-display area. The display area may have pixels arranged in an array to display an image. The non-display area may have a driving circuit to drive the components in the display area. The driving circuit may be connected to the components in the display area through fan-out wires surrounding the periphery of the display area. The line spacing between the fan-out wires affects the number of fan-out wires per unit area. When the line spacing between the fan-out wires is narrower, the number of fan-out wires per unit area can be increased. Summary of the invention

[0003] Some embodiments of the present invention provide an array substrate, comprising a substrate, a dielectric layer, an active component, a plurality of fan-out conductors, and at least one dummy conductor. The substrate has a display area and a fan-out area. The dielectric layer is located on the substrate. The active component is on the display area of ​​the substrate. The plurality of fan-out conductors are electrically connected to the active component, a first gap is provided between two adjacent fan-out conductors, and an area of ​​the dielectric layer corresponding to a vertical projection of the first gap comprises a first lightly doped region. At least one dummy conductor is located outside the fan-out conductor.

[0004] In some embodiments, a second gap is provided between one of the dummy wire and the fan-out wire, and a region of the dielectric layer corresponding to a vertical projection of the second gap includes a second lightly doped region.

[0005] In some embodiments, the dielectric layer further includes a heavily doped region, the heavily doped region and the second lightly doped region are located on opposite sides of the dummy wire, and the ion concentration of the heavily doped region is higher than the ion concentration of the first lightly doped region and the second lightly doped region.

[0006] In some embodiments, a region of the dielectric layer corresponding to a vertical projection of the heavily doped region and the dummy wire includes a third lightly doped region, and an ion concentration of the heavily doped region is higher than an ion concentration of the third lightly doped region.

[0007] In some embodiments, the ion concentration of the first lightly doped region is substantially equal to the ion concentration of the third lightly doped region.

[0008] In some embodiments, the array substrate further includes a plurality of semiconductor layers in the dielectric layer and below the fan-out conductive lines.

[0009] In some embodiments, a plurality of edges of the semiconductor layer have a plurality of fourth lightly doped regions.

[0010] In some embodiments, the semiconductor layers are electrically connected to the fan-out conductive lines, respectively.

[0011] In some embodiments, the dummy conductive line is structurally separated from the active device.

[0012] In some embodiments, in the first lightly doped region, the concentration is substantially constant along the surface of the dielectric layer.

[0013] In some embodiments, the array substrate further includes a plurality of shielding metals between the dielectric layer and the substrate and under the fan-out conductive lines.

[0014] In some implementations, the shielding metals are electrically connected to the fan-out conductive lines, respectively.

[0015] In some implementations, the width of the dummy conductive line is smaller than the width of the fan-out conductive line.

[0016] Some embodiments of the present invention provide a method for manufacturing an array substrate, comprising forming a dielectric layer on a substrate. Forming a metal layer on the dielectric layer. Forming a photoresist layer on the metal layer. Exposing the photoresist layer through a halftone photomask to form a halftone photoresist layer on the metal layer, the halftone photoresist layer having a first portion with a higher height and a second portion with a lower height on a fan-out area of ​​the substrate, and the halftone photoresist layer exposing a portion of the metal layer. Performing a first wet etching to remove a portion of the metal layer through the halftone photoresist layer to form a metal pattern on the fan-out area of ​​the substrate and expose a first area of ​​the dielectric layer. Performing a heavily doped implantation to form a heavily doped area in the first area of ​​the dielectric layer. Removing a second portion of the halftone photoresist layer to expose a portion of the metal pattern. Performing a second wet etching to remove a portion of the metal pattern through the first portion of the halftone photoresist layer and forming a wire layer, the wire layer comprising a plurality of fan-out wires, and having an exposed second area of ​​the dielectric layer between the fan-out wires. Lightly doped implantation is performed to form lightly doped regions in the first region and the second region of the dielectric layer.

[0017] In some embodiments of the present invention, when forming the wire layer in the display area, a half-tone mask is also used to form the fan-out wires in the fan-out area of ​​the array substrate. When using the manufacturing process of some embodiments of the present invention, the line spacing between adjacent fan-out wires in the fan-out area can be shortened, for example, to a line spacing narrower than the exposure resolution. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1A is a top view of an array substrate according to some embodiments of the present invention;

[0019] Figure 1B for Figure 1A A top view of a region R1;

[0020] Figure 1C For along Figure 1BA cross-sectional view of line ABCD;

[0021] Figure 1D for Figure 1A A top view of a region R2;

[0022] Figures 2A to 15 is a cross-sectional view of a manufacturing process for forming an array substrate in some embodiments of the present invention;

[0023] FIG. 16A to FIG. 26C is a cross-sectional view of a manufacturing process for forming an array substrate in some other embodiments of the present invention;

[0024] Fig.26D is a top view of a fan-out region of an array substrate in some other embodiments of the present invention;

[0025] FIG. 27A to FIG. 35C is a cross-sectional view of a manufacturing process for forming an array substrate in some other embodiments of the present invention;

[0026] Fig.35D 1 is a top view of a fan-out region of an array substrate in some other embodiments of the present invention.

[0027] Explanation of symbols

[0028] 100: Array substrate

[0029] 100': Array substrate

[0030] 100”: Array substrate

[0031] 110: Substrate

[0032] 120: Buffer layer

[0033] 130: Metal shielding

[0034] 140: Dielectric layer

[0035] 150: Metal layer

[0036] 152: Wire layer

[0037] 154: Fan-out wire

[0038] 156: Virtual wire

[0039] 160: Interlayer dielectric layer

[0040] 170: Protective layer

[0041] 182: Lower pixel electrode

[0042] 184: Insulation layer

[0043] 186: Upper pixel electrode

[0044] 190: Semiconductor layer

[0045] 200: Metal layer

[0046] AA: Display area

[0047] BM: Binary Photomask

[0048] BM1: Transparent substrate

[0049] BM2: Opaque Pattern

[0050] DR: Drain

[0051] DL: Data Line

[0052] FO: Fan-out area

[0053] GA: gate

[0054] HM: Halftone Photomask

[0055] HM1: Transparent substrate

[0056] HM2: Opaque pattern

[0057] HM3: Halftone Film

[0058] N1: The first lightly doped region

[0059] N2: The second lightly doped region

[0060] N3: The third lightly doped region

[0061] N4: The fourth lightly doped region

[0062] N5: The fifth lightly doped region

[0063] O1: Closed opening

[0064] P: heavily doped region

[0065] P1: Part 1

[0066] P2: Part 2

[0067] PR1: Halftone photoresist layer

[0068] PR2: Binary photoresist layer

[0069] R1: Region

[0070] R2: Region

[0071] SL: Scan Line

[0072] SO: Source

[0073] SP: Sub-pixel area

[0074] TR: Active component DETAILED DESCRIPTION

[0075] In order to enable those skilled in the art to further understand the present invention, preferred embodiments of the present invention are listed below, and the components and intended effects of the present invention are described in detail with reference to the accompanying drawings.

[0076] In some embodiments of the present invention, when forming the wire layer in the display area, a half-tone mask is also used to form the fan-out wires in the fan-out area of ​​the array substrate. When using the manufacturing process of some embodiments of the present invention, the line spacing between adjacent fan-out wires in the fan-out area can be shortened, for example, the line spacing is narrower than the exposure resolution, so that the number of fan-out wires per unit area can be increased.

[0077] Figure 1A A top view of an array substrate 100 according to some embodiments of the present invention is shown. Figure 1B Draw Figure 1A An enlarged top view of region R1. Figure 1C Draw along Figure 1B Cross-sectional view of line ABCD. Figure 1D Draw Figure 1A A top view of region R2. Figures 1A to 1D , the array substrate 100 includes a substrate 110, which is a transparent substrate such as a glass plate, and the substrate 110 has a display area AA and a fan-out area FO. The fan-out area FO can be located in the non-display area of ​​the array substrate 100 and formed at the periphery of the display area AA, and can be used to connect the wires in the display area AA to the driving circuit. The array substrate 100 can be used in any suitable electronic device, such as a mobile phone, a tablet, a notebook computer, etc.

[0078] refer to Figure 1B to Figure 1CIn the display area AA, the substrate 110 of the array substrate 100 may include a plurality of active components TR, a plurality of scan lines SL, and a plurality of data lines DL. The active component TR may be a transistor, and includes a source SO, a drain DR, a gate GA, and a channel layer CH. The source SO and the drain DR of the active component TR are connected to the channel layer CH, and the gate GA of the active component TR is located above the channel layer CH. The active component TR is connected to the scan line SL and the data line DL, the scan line SL may be connected to the gate GA of the active component TR, and the data line DL may be connected to the source SO of the active component TR. The scan line SL and the data line DL may be arranged in different directions. In some embodiments, the scan line SL is arranged in a horizontal direction, and the data line DL is arranged in a vertical direction, and vice versa. The staggered scan lines SL and data lines DL may define a sub-pixel area SP of the display area AA, such as Figure 1B The sub-pixel region SP may include an upper pixel electrode 186, and the upper pixel electrode 186 may be connected to the drain DR of the active device TR.

[0079] The array substrate 100 may further include a buffer layer 120, a shielding metal 130, a dielectric layer 140, an interlayer dielectric layer 160, a lower pixel electrode 182, and an insulating layer 184. The positions of the above elements will be further described below. It should be noted that in order to simplify the drawings, Figure 1B Only the substrate 110 , the shielding metal 130 , the active device TR, the scan line SL, the data line DL and the upper pixel electrode 186 are shown. Figure 1B and Figure 1C It is shown that the upper pixel electrode 186 can be connected to the drain DR of the active device TR through the via V1 .

[0080] refer to Figure 1D , the fan-out conductor 154 and the dummy conductor 156 are on the fan-out area FO. The fan-out conductor 154 can be electrically connected to the active element TR, for example, through the data line DL or the scan line SL. The dummy conductor 156 is located outside the fan-out conductor 154 and is structurally separated from the active element TR. That is, the dummy conductor 156 is physically separated from the active element TR, so the dummy conductor 156 is not electrically connected to the active element TR. In some embodiments, the fan-out conductor 154 and the dummy conductor 156 and the scan line SL in the display area AA can be formed simultaneously by the same conductive layer. Compared with the display area AA, the fan-out area FO does not contain a sub-pixel area. In addition, compared with the adjacent scan lines SL in the display area AA, the distance between adjacent fan-out conductors 154 in the fan-out area FO is narrower to accommodate more fan-out conductors 154 in the fan-out area FO per unit area. In some embodiments, the distance between adjacent fan-out conductors 154 in the fan-out area FO is less than 2 microns.

[0081] Figures 2A to 15A cross-sectional view is shown of a manufacturing process of forming the array substrate 100 in some embodiments of the present invention. Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A and Fig. 12A For along Figure 1D A cross-sectional view of line EE in the fan-out area FO. Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig.13 , Fig.14 and Fig.15 For along Figure 1B A cross-sectional view of the display area AA along line ABCD. Figure 2A and Figure 2B , a buffer layer 120 is formed on the substrate 110. In the display area AA, before forming the buffer layer 120, a shielding metal 130 may be formed first. For example, a conductive layer (such as a metal layer) may be formed on the substrate 110, and then the conductive layer may be patterned to form the shielding metal 130. Then, the buffer layer 120 is formed to cover the shielding metal 130. On the other hand, in the fan-out area FO, the shielding metal 130 may not be formed. The shielding metal 130 may be used to shield light.

[0082] refer to Figure 3A and Figure 3B , a dielectric layer 140 is formed on the substrate 110 and the buffer layer 120. In the display area AA, before forming the dielectric layer 140, a channel layer CH may be formed first. For example, a semiconductor layer may be formed on the buffer layer 120 first, and then the semiconductor layer may be patterned to form the channel layer CH. Then, the dielectric layer 140 is formed to cover the channel layer CH. In some embodiments, the channel layer CH may be polysilicon. On the other hand, in the fan-out area FO, the channel layer CH may not be formed. Reference Figure 4A and Figure 4B , in the display area AA and the fan-out area FO, a metal layer 150 is formed on the dielectric layer 140, and a photoresist layer PR is formed on the metal layer 150. In some embodiments, the material of the metal layer 150 may include molybdenum or other suitable metal materials.

[0083] refer to Figure 5A and Figure 5B , the photoresist layer PR in the fan-out area FO is exposed through the half-tone photomask HM to form a half-tone photoresist layer PR1 on the metal layer 150. The half-tone photoresist layer PR1 has a first portion P1 with a higher height and a second portion P2 with a lower height on the fan-out area FO of the substrate 110, and the half-tone photoresist layer PR1 exposes a portion of the metal layer 150. Specifically, the half-tone photomask HM is made of a transparent substrate HM1, an opaque pattern HM2, and a half-tone film HM3. When light is irradiated to the transparent substrate HM1 not covered by the opaque pattern HM2 and the half-tone film HM3, the photoresist layer PR below can be 100% exposed. When light is irradiated to the transparent substrate HM1 covered by the half-tone film HM3, the exposure degree of the photoresist layer PR below is 20% to 50%. When light is irradiated to the transparent substrate HM1 covered by the opaque pattern HM2, the photoresist layer PR below is not exposed. When the photoresist layer PR is 100% exposed, no photoresist layer PR will remain after the photoresist layer PR is developed. When the exposure degree of the photoresist layer PR is 20% to 50%, after the photoresist layer PR is developed, a portion of the photoresist layer PR remains and the thickness of the photoresist layer PR is reduced, such as the first portion P1 of the photoresist layer PR. When the photoresist layer PR is not exposed, after the photoresist layer PR is developed, the photoresist layer PR will not be removed by the developer and will remain in place at the same height, such as the second portion P2 of the photoresist layer PR.

[0084] On the other hand, the photoresist layer PR in the display area AA is exposed through the binary photomask BM to form a binary photoresist layer PR2 on the metal layer 150, and the thickness of the binary photoresist layer PR2 is substantially the same. Specifically, the second portion P2 of the photoresist layer PR. The binary photomask BM is made of a transparent substrate BM1 and an opaque pattern BM2. The transparent substrate BM1 and the opaque pattern BM2 are similar to the transparent substrate HM1 and the opaque pattern HM2. Therefore, the thickness of the binary photoresist layer PR2 after development is substantially the same. It should be noted that Figure 5A and Figure 5B In the figure, the pattern sizes of the halftone mask HM and the binary mask BM are only for illustration and do not represent the actual sizes. For example, the pattern sizes of the halftone mask HM and the binary mask BM are larger than the halftone photoresist layer PR1 and the binary photoresist layer PR2, respectively.

[0085] When the half-tone mask HM is used, the width of the second portion P2 of the half-tone photoresist layer PR1 formed can be smaller than the exposure resolution. After the second portion P2 of the half-tone photoresist layer PR1 is removed in a subsequent manufacturing process, the first portion P1 of the half-tone photoresist layer PR1 can be used to manufacture a fan-out conductive line having a line width smaller than the exposure resolution.

[0086] refer to Fig. 6A and Figure 6B , a first wet etching is performed. In the fan-out area FO, part of the metal layer 150 is removed through the half-tone photoresist layer PR1 to form a metal pattern on the fan-out area FO of the substrate 110, and the first area of ​​the dielectric layer 140 of the fan-out area FO is exposed. Since the second part P2 of the half-tone photoresist layer PR1 does not expose the dielectric layer 140, the dielectric layer 140 below the second part P2 of the half-tone photoresist layer PR1 will not be removed. On the other hand, in the display area AA, part of the metal layer 150 is removed through the binary photoresist layer PR2 to form a metal pattern on the display area AA of the substrate 110, and the first area of ​​the dielectric layer 140 of the display area AA is exposed. Specifically, the metal layer 150 in the display area AA can be patterned in a subsequent manufacturing process to form a gate (for example Fig. 9B The gate GA) and the scan line (eg Figure 1B The scan line SL in the image is shown in FIG.

[0087] refer to Fig. 7A and Figure 7B , perform heavy doping implantation to form a heavily doped region P in the channel region CH. Specifically, the heavily doped region P may be implanted with different dopants according to the type of active device to be formed. For example, when an NMOS TFT is to be formed, N-type doping may be performed, and the concentration of the dopant, such as phosphorus, is about 1E19 atoms / cm3. When a PMOS TFT is to be formed, P-type doping may be performed, and the concentration of the dopant, such as boron, is about 1E19 atoms / cm3 to about 1E20 atoms / cm3.

[0088] In addition, when performing a heavy doping injection operation, part of the dopants will also be doped into the exposed portion of the dielectric layer 140 (and the buffer layer 120), so that a heavily doped region P will also be formed in the first area of ​​the dielectric layer 140 of the fan-out area FO and the display area AA (that is, the area exposed by the metal pattern).

[0089] refer to Fig. 8A and Figure 8B, by, for example, photoresist ashing, removing a portion of the halftone photoresist layer PR1 and the binary photoresist layer PR2. In the fan-out area FO, the second portion P2 of the halftone photoresist layer PR1 is removed to expose a portion of the metal pattern of the metal layer 150. Specifically, during the photoresist ashing, the outermost first portion P1 of the halftone photoresist layer PR1 is removed, so that the sidewall of the outermost first portion P1 of the halftone photoresist layer PR1 shrinks inward, and the outermost portion of the metal pattern of the metal layer 150 is exposed. At the same time, the second portion P2 of the halftone photoresist layer PR1 is also removed, so that the halftone photoresist layer PR1 is composed of only the first portion P1. In some embodiments, the photoresist ashing also simultaneously reduces the thickness of the first portion P1 of the halftone photoresist layer PR1. On the other hand, in the display area AA, the binary photoresist layer PR2 is partially removed from the sidewall, so that the sidewall of the binary photoresist layer PR2 shrinks inward, thereby exposing a portion of the metal layer 150 .

[0090] refer to Fig. 9A and Fig. 9B , a second wet etching is performed. In the fan-out area FO, a portion of the metal pattern of the metal layer 150 is removed by the first portion P1 of the half-tone photoresist layer PR1, and a wire layer 152 is formed. The wire layer 152 includes a plurality of fan-out wires 154 and a dummy wire 156, and there is a second area of ​​the dielectric layer 140 exposed between the fan-out wires 154. Since the photoresist ashing can effectively remove the second portion P2 of the half-tone photoresist layer PR1, etching can be used to manufacture the fan-out wires 154 with a line pitch smaller than the exposure resolution through the remaining first portion P1, and at the same time, the active element in the display area AA is formed. Since the second portion P2 of the half-tone photoresist layer PR1 is removed by wet etching, the line pitch between adjacent fan-out wires 154 can be smaller than the exposure resolution. Specifically, there is a first gap G1 between two adjacent fan-out wires 154, and the area of ​​the dielectric layer 140 corresponding to the vertical projection of the first gap G1 is the second area. The dummy wire 156 is located outside the fan-out wire 154, and a second gap G2 is formed between the dummy wire 156 and one of the fan-out wires 154. The area of ​​the dielectric layer 140 corresponding to the vertical projection of the second gap G2 is the third area. Fig. 7A and Figure 7B The heavily doped implant in the display area AA is covered by the halftone photoresist layer PR1, so the second area and the third area are undoped areas. In the display area AA, a portion of the metal pattern of the metal layer 150 is removed by the binary photoresist layer PR2, and the gate GA and the scan line SL are formed (see FIG. Figure 1B ). Fig. 7A and Figure 7BAfter the heavy doping is injected, the sidewall of the metal layer 150 shrinks, so the dielectric layer 140 is undoped between the dummy wire 156 and the vertical projection of the heavily doped region P, and between the gate GA and the vertical projection of the heavily doped region P. That is, the dielectric layer 140 outside the heavily doped region P is undoped. Since the sidewall of the outermost first portion P1 of the halftone photoresist layer PR1 shrinks inward during the photoresist ashing, when the outermost dummy wire 156 of the wire layer 152 is formed, the width of the dummy wire 156 is also smaller than the width of the fan-out wire 154.

[0091] refer to Fig. 10A and Fig. 10B After removing the halftone photoresist layer PR1 and the binary photoresist layer PR2, a lightly doped implantation is performed to form lightly doped regions in the first region, the second region, and the third region of the dielectric layer 140 of the fan-out region FO and the display region AA. Specifically, when performing the lightly doped implantation, dopants are implanted into the non-fan-out wires 154, the dummy wires 156, the gate GA, and the scan line SL (see FIG. Figure 1B ) covered. For example, the area of ​​the dielectric layer 140 corresponding to the vertical projection of the first gap G1 includes the first lightly doped region N1. The area of ​​the dielectric layer 140 corresponding to the vertical projection of the second gap G2 includes the second lightly doped region N2. The area between the dielectric layer 140 corresponding to the vertical projection of the heavily doped region P and the dummy wire 156 includes the third lightly doped region N3. In other words, the heavily doped region P and the second lightly doped region N2 are located on opposite sides of the dummy wire 156, and the third lightly doped region N3 is between the dummy wire 156 and the heavily doped region P. In addition, there will be no heavily doped region P on both sides of the fan-out wire 154.

[0092] Since the first lightly doped region N1, the second lightly doped region N2 and the third lightly doped region N3 are formed at the same time and the ions are uniformly implanted, the ion concentrations of the first lightly doped region N1, the second lightly doped region N2 and the third lightly doped region N3 are substantially the same, and the concentrations in the first lightly doped region N1, the second lightly doped region N2 and the third lightly doped region N3 along the surface of the dielectric layer 140 are substantially unchanged. The doping dose of the lightly doped implant is less than the doping dose of the heavily doped implant, for example, the doping dose of the lightly doped implant is one tenth of the doping dose of the heavily doped implant. Therefore, the heavily doped region P has a higher ion concentration than the first lightly doped region N1, the second lightly doped region N2 and the third lightly doped region N3. Different dopants can be implanted according to the type of active device to be formed. For example, when an NMOS TFT is to be formed, N-type doping can be performed, and the concentration of the dopant, such as phosphorus, is about 1E18 atoms / cm3. When a PMOS TFT is to be formed, P-type doping may be performed, and the concentration of a dopant, such as boron, is about 1E18 atoms / cm 3 to about 1E19 atoms / cm 3 .

[0093] refer to FIG. 11A to FIG. 15 More material layers are formed on the substrate 110. Fig.11A and Fig. 11B , on the substrate 110, the fan-out wire 154, the dummy wire 156, the gate GA and the scan line SL (see Figure 1B ), and a metal layer is formed on the interlayer dielectric layer 160 of the display area AA, and then the metal layer is patterned to form a source electrode SO and a drain electrode DR. While forming the source electrode SO and the drain electrode DR, a data line DL connected to the source electrode SO is also formed.

[0094] refer to Fig. 12A and Fig. 12B A protective layer 170 is formed on the interlayer dielectric layer 160, the source electrode SO, the drain electrode DR and the data line DL of the fan-out area FO and the display area AA, and then a through hole V1 is formed in the protective layer 170 to expose the drain electrode DR. Figures 13 to 15 , an electrode layer 180 is formed on the protective layer 170 of the display area AA. Fig.13 In the embodiment, the lower pixel electrode 182 is formed on the protective layer 170. For example, a transparent conductive layer is first formed on the protective layer 170, and then the transparent conductive layer is patterned to form the lower pixel electrode 182. The lower pixel electrode 182 has an opening, which is located directly above the through hole V1, and the size of the opening is larger than the size of the through hole V1. Fig.14In the embodiment, an insulating layer 184 is formed on the protective layer 170 and the lower pixel electrode 182, and an opening is formed in the insulating layer 184 to expose the drain electrode DR. Then, an upper pixel electrode 186 is formed on the insulating layer 184. The upper pixel electrode 186 penetrates the protective layer 170 and the insulating layer 184 and is connected to the drain electrode DR. For example, another transparent conductive layer is first formed on the insulating layer 184, and then the transparent conductive layer is patterned to form the upper pixel electrode 186. The upper pixel electrode 186 can be connected to the drain electrode DR through the through hole V1, and a portion of the upper pixel electrode 186 above the lower pixel electrode 182 has a plurality of closed openings O1, and these closed openings O1 are used to control the direction of the liquid crystal located above the array substrate 100.

[0095] FIG. 16A to FIG. 26C The cross-sectional views of the manufacturing process of forming the array substrate 100' in some other embodiments of the present invention are shown. FIG. 16A to FIG. 26B A top view of the fan-out region FO of the array substrate 100' formed in FIG. Fig.26D . Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A , Fig.22A , Fig.23A , Fig.24A , Fig.25A and Fig.26A For along Fig.26D Cross-sectional view of line FF in the fan-out region FO. Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B , Fig. 21B , Fig. 22B , Fig. 23B , Fig. 24B , Fig.25B and Fig.26B For along Figure 1B A cross-sectional view of line ABCD of display area AA in FIG. Fig. 16C , Fig. 17C , Fig.18C , Fig.19C , Fig. 20C , Fig. 21C , Fig. 22C , Fig.23C , Fig.24C , Fig.25C and Fig.26C For along Fig.26D A cross-sectional view of the fan-out region FO along line GG. FIG. 16A to FIG. 16C, a buffer layer 120 is formed on the substrate 110. In the display area AA, before forming the buffer layer 120, a shielding metal 130 may be formed first. FIG. 16A to FIG. 16C Steps and Figure 2A and Figure 2B The details are similar.

[0096] refer to FIG. 17A to FIG. 17C , a dielectric layer 140 is formed on the substrate 110 and the buffer layer 120. In the display area AA, a channel layer CH may be formed before forming the dielectric layer 140. Then, the dielectric layer 140 is formed to cover the channel layer CH. FIG. 17A to FIG. 17C and Figure 3A and Figure 3B The difference is that, while forming the channel layer CH, the semiconductor layer 190 is also formed under the dielectric layer 140 in the fan-out region FO, so the semiconductor layer 190 is formed in the dielectric layer 140. The semiconductor layer 190 and the channel layer CH are patterned from the same semiconductor layer. The semiconductor layer 190 in the fan-out region FO can be used to reduce the resistance of the fan-out wire formed subsequently.

[0097] refer to 18A to 18C In the display area AA and the fan-out area FO, a metal layer 150 is formed on the dielectric layer 140 and the semiconductor layer 190 , and a photoresist layer PR is formed on the metal layer 150 . 18A to 18C Steps and Figure 4A and Figure 4B The details are similar.

[0098] refer to FIG. 19A to FIG. 19C , the photoresist layer PR in the fan-out area FO is exposed through the half-tone photomask HM to form a half-tone photoresist layer PR1 on the metal layer 150. On the other hand, the photoresist layer PR in the display area AA is exposed through the binary photomask BM to form a binary photoresist layer PR2 on the metal layer 150. The semiconductor layer 190 is slightly wider than the first portion P1 of the half-tone photoresist layer PR1. The first portion P1 of the half-tone photoresist layer PR1 is on the semiconductor layer 190 and parallel to the semiconductor layer 190. FIG. 19A to FIG. 19C Steps and Figure 5A and Figure 5B In some embodiments, Fig.19C In the embodiment, the metal layer 150 is also partially removed to expose a portion of the dielectric layer 140 .

[0099] refer to FIG. 20A to FIG. 20C, a first wet etching is performed. In the fan-out area FO, a portion of the metal layer 150 is removed through the half-tone photoresist layer PR1 to form a metal pattern on the fan-out area FO of the substrate 110, and the first area of ​​the dielectric layer 140 of the fan-out area FO is exposed. On the other hand, in the display area AA, a portion of the metal layer 150 is removed through the binary photoresist layer PR2 to form a metal pattern on the display area AA of the substrate 110, and the first area of ​​the dielectric layer 140 of the display area AA is exposed. FIG. 20A to FIG. 20C Steps and Fig. 6A and Figure 6B The details are similar.

[0100] refer to FIG. 21A to FIG. 21C , perform heavy doping implantation to form a heavily doped region P in the channel region CH. The heavily doped region P is also formed in the first region (ie, the region exposed by the metal pattern) of the dielectric layer 140 in the fan-out region FO and the display region AA. FIG. 21A to FIG. 21C Steps and Fig. 7A and Figure 7B In some embodiments, Fig. 21C In the process, a heavily doped region P is also formed in the dielectric layer 140 .

[0101] refer to FIG. 22A to FIG. 22C , a portion of the halftone photoresist layer PR1 and the binary photoresist layer PR2 is removed by, for example, photoresist ashing. In the fan-out area FO, the second portion P2 of the halftone photoresist layer PR1 is removed to expose a portion of the metal pattern of the metal layer 150. On the other hand, in the display area AA, the binary photoresist layer PR2 is also partially removed from the sidewall, so that the sidewall of the binary photoresist layer PR2 is retracted inward, and a portion of the metal layer 150 is exposed. FIG. 22A to FIG. 22C Steps and Fig. 8A and Figure 8B In some embodiments, Fig. 22C The sidewalls of the half-tone photoresist layer PR1 also shrink inwards.

[0102] refer to FIG. 23A to FIG. 23C , a second wet etching is performed. In the fan-out area FO, a portion of the metal pattern of the metal layer 150 is removed by the first portion P1 of the half-tone photoresist layer PR1, and a wire layer 152 is formed. The wire layer 152 includes a plurality of fan-out wires 154 and a dummy wire 156. In the display area AA, a portion of the metal pattern of the metal layer 150 is removed by the binary photoresist layer PR2, and a gate GA and a scan line SL are formed (see FIG. Figure 1B ). FIG. 23A to FIG. 23C Steps and Fig. 9A and Fig. 9B The details are similar. FIG. 23A to FIG. 23C Steps and Fig. 9A and Fig. 9B The difference is that Fig.23A and Fig.23C , the semiconductor layer 190 is below the fan-out wire 154 and the dummy wire 156 and is parallel to the fan-out wire 154 and the dummy wire 156. In addition, Fig.23A and Fig.23C In some embodiments, the fan-out conductor 154 is not a continuous conductor. Fig.23C A portion of the fan-out conductor 154 in is also removed.

[0103] refer to FIG. 24A to FIG. 24C After removing the halftone photoresist layer PR1 and the binary photoresist layer PR2, lightly doped implantation is performed to form lightly doped regions in the first region, the second region, and the third region of the dielectric layer 140 in the fan-out region FO and the display region AA. FIG. 24A to FIG. 24C Steps and Fig. 9A and Fig. 9B The details are similar. FIG. 24A to FIG. 24C and Fig. 9A and Fig. 9B The difference is that when performing light doping, ions are implanted into the edge of the semiconductor layer 190, so the edge of the semiconductor layer 190 has a fourth lightly doped region N4. In some embodiments, after the light doping implantation, in the vertical direction, the lightly doped region has the highest doping concentration at the edge of the semiconductor layer 190 or slightly above the edge of the semiconductor layer 190. In some embodiments, the dielectric layer 140 and the semiconductor layer 190 have a fifth lightly doped region N5, which is located on the side of the fan-out wire 154, such as Fig.24C shown.

[0104] refer to FIG. 25A to FIG. 26C An interlayer dielectric layer 160 and a metal layer 200 are formed on the substrate 110, the fan-out wire 154, the dummy wire 156, the gate GA and the scan line, and a data line DL, a source electrode SO or a drain electrode DR are formed on the interlayer dielectric layer 160 in the display area AA. FIG. 25A to FIG. 25C Steps and Fig.11A and Fig. 11B The details are similar. FIG. 25A to FIG. 26C and Fig.11A and Fig. 11BThe difference is that, in the fan-out area FO, after the interlayer dielectric layer 160 is formed, a through hole V2 exposing the fan-out wire 154 and a through hole V3 exposing the semiconductor layer 190 are formed in the interlayer dielectric layer 160. Next, a metal layer 200 is formed on the interlayer dielectric layer 160. The metal layer 200 can be electrically connected to the fan-out wire 154 through the through hole V2, and connected to the semiconductor layer 190 through the through hole V3. The metal layer 200 and the data line DL, the source SO or the drain DR are made of the same conductive layer through patterning. The metal layer 200 in the fan-out area FO can be used to connect the fan-out wire 154 and the semiconductor layer 190 to further reduce the resistance of the fan-out wire 154. In some embodiments, the semiconductor layer 190 may not be electrically connected to the fan-out wire 154, so there is no other metal layer (such as the metal layer 200) on the fan-out wire 154. Next, other material layers can be formed on the fan-out area FO and the display area AA, and the relevant details are the same as Fig. 12A The same as for No. 15, will not be repeated here.

[0105] FIG. 27A to FIG. 35C A cross-sectional view of a manufacturing process for forming an array substrate 100" in some embodiments of the present invention is shown. FIG. 27A to FIG. 35C A top view of the fan-out region FO of the array substrate 100" formed in FIG. Fig.35D . Fig.27A , Fig.28A , Fig.29A , Fig. 30A , Fig.31A , Fig.32A , Fig.33A , Fig.34A and Fig.35A For along Fig.35D A cross-sectional view of line HH of the fan-out region FO in FIG. Fig.27B , Fig.28B , Fig.29B , Fig. 30B , Fig.31B , Fig.32B , Fig.33B , Fig.34B and Fig.35B For along Figure 1B A cross-sectional view of line ABCD of display area AA in FIG. Fig.27C , Fig.28C , Fig.29C , Fig. 30C , Fig. 31C , Fig.32C , Fig.33C , Fig.34C and Fig.35C For along Fig.35D A cross-sectional view of the fan-out region FO along line II. FIG. 27A to FIG. 27C , a buffer layer 120 is formed on the substrate 110 . FIG. 27A to FIG. 27C Steps and Figure 2A and Figure 2B The details are similar. FIG. 27A to FIG. 27C Steps and Figure 2A and Figure 2B The difference is that in the fan-out area FO, the shielding metal 130 may also be formed before forming the buffer layer 120. Therefore, the shielding metal 130 is formed between the buffer layer 120 and the substrate 110. The shielding metal 130 in the fan-out area FO and the display area AA is made of the same metal layer at the same time. In some embodiments, the shielding metal 130 can be used to reduce the resistance of the fan-out conductive line 154.

[0106] refer to FIG. 28A to FIG. 28C , a dielectric layer 140 is formed on the substrate 110 and the buffer layer 120. In the display area AA, a channel layer CH may be formed before forming the dielectric layer 140. Then, the dielectric layer 140 is formed to cover the channel layer CH. FIG. 28A to FIG. 28C Steps and Figure 3A and Figure 3B After forming the dielectric layer 140 , the dielectric layer 140 may be patterned to form a through hole V4 to expose the shielding metal 130 in the fan-out region FO.

[0107] refer to FIG. 29A to FIG. 29C , in the display area AA and the fan-out area FO, a metal layer 150 is formed on the dielectric layer 140 , and a photoresist layer PR is formed on the metal layer 150 . FIG. 29A to FIG. 29C Steps and Figure 4A and Figure 4B In the fan-out region FO, the metal layer 150 penetrates the dielectric layer 140 and the buffer layer 120 through the via V4 and contacts the shielding metal 130 .

[0108] refer to FIG. 30A to FIG. 30C , the photoresist layer PR in the fan-out area FO is exposed through the half-tone photomask HM to form a half-tone photoresist layer PR1 on the metal layer 150. On the other hand, the photoresist layer PR in the display area AA is exposed through the binary photomask BM to form a binary photoresist layer PR2 on the metal layer 150. The shielding metal 130 may be slightly wider than the first portion P1 of the half-tone photoresist layer PR1. The first portion P1 of the half-tone photoresist layer PR1 is on the shielding metal 130 and parallel to the shielding metal 130. FIG. 30A to FIG. 30C Steps and Figure 5A and Figure 5B The details are similar.

[0109] refer to FIG. 31A to FIG. 31C, a first wet etching is performed. In the fan-out area FO, a portion of the metal layer 150 is removed through the half-tone photoresist layer PR1 to form a metal pattern on the fan-out area FO of the substrate 110, and the first area of ​​the dielectric layer 140 of the fan-out area FO is exposed. On the other hand, in the display area AA, a portion of the metal layer 150 is removed through the binary photoresist layer PR2 to form a metal pattern on the display area AA of the substrate 110, and the first area of ​​the dielectric layer 140 of the display area AA is exposed. FIG. 20A to FIG. 20C Steps and Fig. 6A and Figure 6B The details are similar.

[0110] refer to FIG. 32A to FIG. 32C , perform heavy doping implantation to form a heavily doped region P in the channel region CH. The heavily doped region P is also formed in the first region (ie, the region exposed by the metal pattern) of the dielectric layer 140 in the fan-out region FO and the display region AA. FIG. 32A to FIG. 32C Steps and Fig. 7A and Figure 7B The details are similar.

[0111] refer to FIG. 33A to FIG. 33C , a portion of the halftone photoresist layer PR1 and the binary photoresist layer PR2 is removed by, for example, photoresist ashing. In the fan-out area FO, the second portion P2 of the halftone photoresist layer PR1 is removed to expose a portion of the metal pattern of the metal layer 150. On the other hand, in the display area AA, the binary photoresist layer PR2 is also partially removed from the sidewall, so that the sidewall of the binary photoresist layer PR2 is retracted inward, and a portion of the metal layer 150 is exposed. FIG. 22A to FIG. 22C Steps and Fig. 8A and Figure 8B The details are similar.

[0112] refer to FIG. 34A to FIG. 34C , a second wet etching is performed. In the fan-out area FO, a portion of the metal pattern of the metal layer 150 is removed by the first portion P1 of the half-tone photoresist layer PR1, and a wire layer 152 is formed. The wire layer 152 includes a plurality of fan-out wires 154 and a dummy wire 156. In the display area AA, a portion of the metal pattern of the metal layer 150 is removed by the binary photoresist layer PR2, and a gate GA and a scan line SL are formed (see FIG. Figure 1B ). FIG. 34A to FIG. 34C Steps and Fig. 9A and Fig. 9BThe shielding metal 130 is disposed between the fan-out conductor 154 and the dummy conductor 156 and is parallel to the fan-out conductor 154 and the dummy conductor 156. In some embodiments, the shielding metal 130 is slightly wider than the fan-out conductor 154 and the dummy conductor 156. The fan-out conductor 154 penetrates the dielectric layer 140 and the buffer layer 120 through the via V4 and contacts the shielding metal 130, and the fan-out conductor 154 is electrically connected to the shielding metal 130.

[0113] refer to FIG. 35A to FIG. 35C After removing the halftone photoresist layer PR1 and the binary photoresist layer PR2, lightly doped implantation is performed to form lightly doped regions in the first region, the second region, and the third region of the dielectric layer 140 in the fan-out region FO and the display region AA. FIG. 35A to FIG. 35C Steps and Fig. 10A and Fig. 10B Next, other material layers may be formed on the fan-out area FO and the display area AA. The relevant details are similar to those of FIG. 11A to FIG. 15 The same is not repeated here.

[0114] In summary, when a half-tone photomask is used to form a fan-out conductor in a fan-out region of an array substrate, the width of the second portion of the half-tone photomask can be formed to be smaller than the exposure resolution. Therefore, the line spacing between adjacent fan-out conductors formed can be shortened to a line spacing narrower than the exposure resolution. In addition, when forming the fan-out conductor, only one etching is performed, so the distance between the fan-out conductors will not be widened. In this way, the number of fan-out conductors can be increased per unit area of ​​the fan-out region.

[0115] Although the present invention is disclosed in conjunction with the above embodiments, they are not intended to limit the present invention. Any ordinary technician in the technical field may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the attached claims.

Claims

1. An array substrate, comprising: A substrate having a display area and a fan-out area; a dielectric layer disposed on the substrate; An active component is on the display area of ​​the substrate; A plurality of fan-out wires electrically connected to the active element, a first gap being formed between two adjacent fan-out wires, and a region of the dielectric layer corresponding to a vertical projection of the first gap comprising a first lightly doped region; and At least one dummy wire is located outside the fan-out wires, A second gap is provided between the dummy wire and one of the fan-out wires, and a region of the dielectric layer corresponding to a vertical projection of the second gap comprises a second lightly doped region.

2. The array substrate as described in claim 1, wherein the dielectric layer further includes a heavily doped region, the heavily doped region and the second lightly doped region are located on opposite sides of the dummy wire, and the ion concentration of the heavily doped region is higher than the ion concentration of the first lightly doped region and the second lightly doped region.

3. The array substrate as described in claim 2, wherein the area of ​​the dielectric layer corresponding to the heavily doped region and the vertical projection of the dummy wire includes a third lightly doped region, and the ion concentration of the heavily doped region is higher than the ion concentration of the third lightly doped region. 4 . The array substrate as claimed in claim 3 , wherein the ion concentration of the first lightly doped region is substantially equal to the ion concentration of the third lightly doped region. 5 . The array substrate as claimed in claim 1 , wherein the dummy conductive line is structurally separated from the active device. 6 . The array substrate as claimed in claim 1 , wherein in the first lightly doped region, a concentration in a direction along the surface of the dielectric layer is substantially constant.

7. An array substrate, comprising: A substrate having a display area and a fan-out area; a dielectric layer disposed on the substrate; An active component is on the display area of ​​the substrate; A plurality of fan-out wires electrically connected to the active element, a first gap being formed between two adjacent fan-out wires, and a region of the dielectric layer corresponding to a vertical projection of the first gap comprising a first lightly doped region; At least one dummy wire is located outside the fan-out wires; as well as A plurality of semiconductor layers are provided in the dielectric layer and below the fan-out conductive lines. 8 . The array substrate as claimed in claim 7 , wherein a plurality of edges of the semiconductor layers have a plurality of fourth lightly doped regions. 9 . The array substrate as claimed in claim 7 , wherein the semiconductor layers are electrically connected to the fan-out conductive lines respectively.

10. An array substrate, comprising: A substrate having a display area and a fan-out area; a dielectric layer disposed on the substrate; An active component is on the display area of ​​the substrate; A plurality of fan-out wires electrically connected to the active element, a first gap being formed between two adjacent fan-out wires, and a region of the dielectric layer corresponding to a vertical projection of the first gap comprising a first lightly doped region; At least one dummy wire is located outside the fan-out wires; as well as A plurality of shielding metals are between the dielectric layer and the substrate and below the fan-out conductors. 11 . The array substrate as claimed in claim 10 , wherein the shielding metals are electrically connected to the fan-out conductive lines respectively.

12. An array substrate, comprising: A substrate having a display area and a fan-out area; a dielectric layer disposed on the substrate; An active component is on the display area of ​​the substrate; A plurality of fan-out wires electrically connected to the active element, a first gap being formed between two adjacent fan-out wires, and a region of the dielectric layer corresponding to a vertical projection of the first gap comprising a first lightly doped region; At least one dummy conductive line is located outside the fan-out conductive lines, wherein the width of the dummy conductive line is smaller than the width of the fan-out conductive lines.

13. A method for manufacturing an array substrate, comprising: forming a dielectric layer on the substrate; forming a metal layer on the dielectric layer; forming a photoresist layer on the metal layer; Exposing the photoresist layer through a half-tone photomask to form a half-tone photoresist layer on the metal layer, wherein the half-tone photoresist layer has a first portion with a higher height and a second portion with a lower height on the fan-out region of the substrate, and the half-tone photoresist layer exposes a portion of the metal layer; performing a first wet etch to remove the portion of the metal layer through the half-tone photoresist layer to form a metal pattern on the fan-out region of the substrate and expose a first region of the dielectric layer; Performing a heavily doped implant to form a heavily doped region in the first region of the dielectric layer; removing the second portion of the halftone photoresist layer to expose a portion of the metal pattern; performing a second wet etch to remove the portion of the metal pattern through the first portion of the halftone photoresist layer and form a wiring layer, the wiring layer comprising a plurality of fan-out wirings having a second region of the dielectric layer exposed therebetween; as well as A lightly doped implantation is performed to form lightly doped regions in the first region and the second region of the dielectric layer.

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