Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, wherein the structure includes: a substrate including a base, an active region on the base, a shield region surrounding the active region, and a first insulating region surrounding the shield region, and the first insulating region is in contact with the shield region, and a second insulating region is between part of the active region and the shield region, the active region includes a first region and a second region separated from each other, and a third region surrounding the first region and the second region; a source in the first region; a drain in the second region; a shield structure in the shield region, the shield structure having shield ions therein; a gate on the third region, and part of the gate also extends onto the second insulating region, reducing the leakage between adjacent transistors while meeting the requirements of logic circuit design.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] Image sensors, as the core components of photoelectric imaging monitoring systems, have imaging and detection functions, and are widely used in industrial, scientific research, national defense, medical, aerospace and other fields. Complementary metal oxide semiconductor (CMOS) image sensors are currently the most promising and are considered to have the most development potential.

[0003] Generally, a single pixel of a CMOS image sensor is composed of a light-sensitive area (a PN junction as a light sensor) and a reading circuit (a transistor device as a selection switch). In a high radiation environment, during ionizing radiation, CMOS image sensors undergo atomic nucleus elastic collision, lattice displacement, resulting in defects, which in turn reduces the minority carrier lifetime, reduces the pure doping concentration, reduces the mobility, reduces the transistor current gain, and increases the leakage current. The oxide (SiO2) dielectric layer in the CMOS image sensor generates electron-hole pairs, electrons escape to the gate, and holes are transported to the SiO2 / Si interface, a part of which is captured by the defects at the interface, resulting in changes in transistor threshold, and the other part enters the light-sensitive area to produce serious dark current. Dark current will produce fixed pattern noise (FPN) on the image, and larger dark current will cause serious vertical fixed pattern noise, which deteriorates the image quality and limits the sensitivity and dynamic range of the image sensor. In summary, ionizing radiation will cause the performance of the CMOS image sensor to degrade, and even cause permanent damage.

[0004] Therefore, the image output quality of the CMOS image sensor in a high radiation environment needs to be improved. SUMMARY

[0005] The technical problem solved by the present application is to provide a semiconductor structure and a forming method thereof to improve the image output quality of the CMOS image sensor in a high radiation environment.

[0006] To solve the above technical problems, the technical scheme of the present application provides a semiconductor structure, comprising: a substrate, the substrate comprising a substrate, an active region on the substrate, a shielding region surrounding the active region, and a first insulating region surrounding the shielding region, and the first insulating region is in contact with the shielding region, and there is also a second insulating region between part of the active region and the shielding region, the active region comprises a first region and a second region separated from each other, and a third region surrounding the first region and the second region; a source electrode in the first region; a drain electrode in the second region; a shielding structure in the shielding region, the shielding structure has shielding ions; a gate electrode on the third region, and part of the gate electrode also extends onto the second insulating region.

[0007] Optionally, it also comprises: a contact layer on the second insulating region, and the contact layer is on the surface of the gate electrode.

[0008] Optionally, the source electrode and the drain electrode are N-type; the shielding ions are P-type conductive ions.

[0009] Optionally, the depth of the shielding structure ranges from 0 µm to 5 µm; the width of the shielding structure ranges from 0.05 µm to 5 µm.

[0010] Optionally, the size of the second insulating region in the extension direction of the gate electrode ranges from 0 µm to 5 µm.

[0011] Correspondingly, the technical scheme of the present application also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a substrate, an active region on the substrate, a shielding region surrounding the active region, and a first insulating region surrounding the shielding region, and the first insulating region is in contact with the shielding region, and there is also a second insulating region between part of the active region and the shielding region, the active region comprises a first region and a second region separated from each other, and a third region surrounding the first region and the second region; forming a gate electrode on the third region, and part of the gate electrode also extends onto the second insulating region; forming a source electrode in the first region; forming a drain electrode in the second region; implanting shielding ions in the shielding region to form a shielding structure.

[0012] Optionally, the method for forming the gate electrode, the source electrode, the drain electrode and the shielding structure comprises: forming the gate electrode; after forming the gate electrode, implanting doped ions in the first region and the second region to form the source electrode and the drain electrode; after forming the gate electrode, implanting the shielding ions in the shielding region to form the shielding structure.

[0013] Optionally, the process parameters of the implantation process include: the shielding ions include P-type conductive ions; the dopant amount of the conductive ions ranges from greater than or equal to 1E12 atom / cm 2 , and the implantation energy ranges from greater than or equal to 5 Kev.

[0014] Optionally, the method further includes: after forming the gate, forming a contact layer on the second insulating region, and the contact layer is located on the surface of the gate.

[0015] Optionally, the source and the drain are N-type, and the shielding ions are P-type conductive ions.

[0016] Optionally, the depth of the shielding structure ranges from 0 µm to 5 µm, and the width of the shielding structure ranges from 0.05 µm to 5 µm.

[0017] Optionally, the size of the second insulating region along the extension direction of the gate ranges from 0 µm to 5 µm.

[0018] Compared with the prior art, the technical scheme of the embodiment of the present application has the following beneficial effects:

[0019] In the semiconductor structure provided by the technical scheme, the active region includes a first region and a second region separated from each other, and a third region surrounding the first region and the second region, so that the gate surrounds the source and the drain, and the source and the drain are not in contact with the first insulating region and the second insulating region, thereby avoiding the leakage caused by radiation ionization in the transistor; at the same time, since the shielding region surrounds the active region, the shielding structure in the shielding region is used to shield the additional electric field introduced by the positive charges generated by radiation in the second insulating region, thereby reducing the induced charges generated in the active region of the adjacent transistor due to the additional electric field, and further reducing the leakage between the adjacent transistors; in addition, the second insulating region is located between part of the active region and the shielding region, and the second insulating region can be as small as possible to reduce the impact on the leakage, and at the same time, is used to meet the logic circuit design requirement of leading out the contact layer on the gate on the second insulating region, and the logic circuit design requirement means that the contact layer cannot be located above the active region.

[0020] The forming method of the semiconductor structure provided in the technical scheme comprises the following steps: forming a substrate, wherein the substrate comprises a base, a plurality of active regions and an isolation structure, the isolation structure is located between adjacent active regions; forming a gate on part of the substrate; and forming a source and a drain in the active regions on both sides of the gate. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a structural schematic diagram of a semiconductor structure;

[0022] Figure 2 is a structural schematic diagram of another semiconductor structure;

[0023] Figure 3 is a structural schematic diagram of still another semiconductor structure;

[0024] Figures 4 to 13 is a structural schematic diagram of each step of the forming method of the semiconductor structure of the embodiment of the present application. DETAILED DESCRIPTION

[0025] As described in the background, the image output quality of the CMOS image sensor in a high radiation environment needs to be improved. Now a semiconductor structure is described and analyzed.

[0026] It should be noted that the "surface", "upper" in the specification are used to describe the relative position relationship in space, and are not limited to whether they are in direct contact.

[0027] Figure 1 is a structural schematic diagram of a semiconductor structure.

[0028] Please refer to Figure 1 , the semiconductor structure comprises: a substrate, the substrate comprises a base 100, a plurality of active regions (not shown in the figure) and an isolation structure 101 located on the base 100, the isolation structure 101 is located between adjacent active regions; a gate 102 located on part of the substrate; a source 103 and a drain 104 in the active regions on both sides of the gate 102.

[0029] The above structure is a NMOS device. When the above transistor is in a radiation condition, the silicon oxide in the isolation structure 101 generates ionization, and generates electron-hole pairs. The electrons are quickly transmitted out because of the fast transmission speed in the isolation structure 101, and the interface between the isolation structure 101 and the active region is positively charged due to the accumulation of holes. These accumulated positive charges form a conductive channel, resulting in leakage of the transistor.

[0030] Figure 2 is a structural diagram of another semiconductor structure.

[0031] Please refer to Figure 2 , the semiconductor structure comprises: a substrate 200; a first device comprising a first gate 201 on part of the substrate 200, and a first source-drain region 202 in the substrate 200 on both sides of the first gate 201; a second device comprising a second gate 203 on part of the substrate 200, and a second source-drain region 204 in the substrate 200 on both sides of the second gate 203, and the substrate 200 between the first device and the second device has an isolation structure 205.

[0032] Similar to the previous embodiment, under a radiation condition, the interface between the isolation structure 205 between the adjacent first device and the second device and the substrate 200 and one side of the isolation structure 205 are positively charged due to the accumulation of holes, and these accumulated positive charges induce negative charges at the interface and on one side of the substrate 200. When there is a voltage difference between the first source-drain region 202 and the second source-drain region 204 on both sides of the isolation structure 205 (such as VDD and ground, respectively), the induced negative charges will cause the generation of leakage current.

[0033] In yet another embodiment, in order to reduce the leakage current caused by the positive charge of the SiO2 / Si interface due to the accumulation of holes under a radiation condition, please refer to Figure 3 .

[0034] Figure 3 is a structural diagram of another semiconductor structure.

[0035] Please refer to Figure 3 , the semiconductor structure comprises: a substrate (not shown in the figure), the substrate comprises a base (not shown in the figure), an active region on the base, and an isolation structure 301 surrounding the active region, the active region comprises a first region (not shown in the figure), a second region (not shown in the figure) surrounding the first region, and a third region (not shown in the figure) surrounding the second region; a gate 302 on the second region; a drain 303 on the first region; and a source 304 on the third region.

[0036] In the structure, the gate 302 is designed as a ring shape, avoiding the isolation structure under the gate, causing the leakage of the source and the drain of the transistor, and enhancing the anti-radiation performance. However, the source 304 is in contact with the isolation structure 301, and it is difficult to avoid the leakage between the source and the drain of the adjacent transistor.

[0037] To solve the above problems, the semiconductor structure and the forming method thereof provided by the application, the active region includes the first region and the second region separated from each other, and the third region surrounding the first region and the second region, the gate surrounds the source and the drain, and the source and the drain are not in contact with the first insulating region and the second insulating region, avoiding the leakage caused by the radiation ionization in the transistor; at the same time, the shielding region surrounds the active region, the shielding region is used for shielding the additional electric field introduced by the positive charge generated by the radiation in the second insulating region, reducing the induced charge generated in the active region between the adjacent transistors by the additional electric field, and further reducing the leakage between the adjacent transistors; in addition, the second insulating region is located between part of the active region and the shielding region, the second insulating region can be as small as possible to reduce the influence on the leakage, and at the same time, the second insulating region is used for meeting the logic circuit design requirement of leading out the contact layer on the gate on the second insulating region, the logic circuit design requirement refers to that the contact layer cannot be located above the active region.

[0038] In order to make the above-mentioned purpose, characteristics and beneficial effects of the application more obvious and easy to understand, the specific embodiments of the application will be described in detail below with reference to the drawings.

[0039] Figures 4 to 13 is the structure schematic diagram of each step of the forming method of the semiconductor structure of the embodiment of the application.

[0040] Please refer to Figures 4 to 6 , Figure 4 is the top view structure schematic diagram, Figure 5 is Figure 4 is the cross-sectional structure schematic diagram along the XX1 direction in the figure, Figure 6 is Figure 4 is the cross-sectional structure schematic diagram along the YY1 direction in the figure, the substrate is provided, the substrate includes the substrate 400, the active region located on the substrate 400, the shielding region P+ surrounding the active region, and the first insulating region 401 surrounding the shielding region P+, and the first insulating region 401 is in contact with the shielding region P+, the second insulating region 402 is further provided between part of the active region and the shielding region P+, the active region includes the first region I and the second region II separated from each other, and the third region III surrounding the first region I and the second region II.

[0041] In the embodiment, the forming method of the substrate comprises: providing an initial substrate (not shown in the figure); etching the initial substrate to form the substrate 400 and the active region on the substrate 400, the active region having a first recess (not shown in the figure) and a second recess (not shown in the figure) between adjacent active regions; forming the first insulating region 401 in the second recess; and forming the second insulating region 402 in the first recess.

[0042] The first insulating region 401 is used to form electrical insulation between different devices; and the second insulating region 402 is used to meet the design requirements of a logic circuit when a contact layer is subsequently led out from the gate.

[0043] In the embodiment, the material of the first insulating region 401 comprises silicon oxide; and the material of the second insulating region 402 comprises silicon oxide.

[0044] The width d1 of the second insulating region 402 ranges from 0 µm to 5 µm. The width d1 refers to the dimension of the second insulating region 402 in the direction along which the subsequently formed gate extends.

[0045] The width d2 of the shielding region P+ ranges from 0.05 µm to 5 µm. The shielding region P+ has a first side adjacent to the active region and a second side away from the active region, and the width d2 refers to the distance between the first side and the second side.

[0046] Subsequently, a gate is formed on the third region III, and part of the gate also extends onto the second insulating region D2; a source is formed in the first region I; a drain is formed in the second region II; and shielding ions are implanted in the shielding region P.

[0047] In the embodiment, the forming method of the gate, the source, the drain, and the shielding structure comprises referring to Figures 7 to 12 In other embodiments, the forming method of the gate, the source, the drain, and the shielding structure can not be limited to this.

[0048] Please refer to Figures 7 to 9 , Figure 7 is a schematic view of a top view structure, Figure 8 is Figure 7 is a schematic view of a cross-sectional structure along the XX1 direction in Figure 9 is Figure 7 is a schematic view of a cross-sectional structure along the YY1 direction in

[0049] In the embodiment, the material of the gate 403 is polysilicon.

[0050] Please refer to Figures 10 to 12 ,Figure 10 is a schematic diagram of a top view structure, Figure 11 is Figure 10 is a schematic diagram of a cross-sectional structure along the XX1 direction, Figure 12 is Figure 10 is a schematic diagram of a cross-sectional structure along the YY1 direction, after forming the gate 403, the source 404 and the drain 405 are formed by implanting doping ions in the first region I and the second region II; after forming the gate 403, the shielding structure 406 is formed by implanting the shielding ions in the shielding region P+.

[0051] So far, the gate 403 is arranged around the source 404 and the drain 405, and the source 404 and the drain 405 have no contact with the first insulating region 401 and the second insulating region 402, avoiding the leakage caused by radiation ionization in the transistor; at the same time, since the shielding region P+ is arranged around the active region, the shielding structure 406 in the shielding region P+ is used to shield the additional electric field introduced by the positive charge generated by radiation in the second insulating region 402, reducing the induced charge generated in the active region between adjacent transistors by the additional electric field, and further reducing the leakage between adjacent transistors.

[0052] In this embodiment, the source 404 and the drain 405 are N-type conductive.

[0053] In this embodiment, the doping ions are N-type conductive ions. Specifically, the doping ions are phosphorus.

[0054] In this embodiment, the shielding ions are P-type conductive ions.

[0055] In this embodiment, the process parameters of the implantation process include: the shielding ions include P-type conductive ions; the implantation dose of the conductive ions ranges from greater than or equal to 1E12 atom / cm 2 , and the implantation energy ranges from greater than or equal to 5Kev.

[0056] In this embodiment, the depth of the shielding structure 406 ranges from 0 µm to 5 µm; the width of the shielding structure 406 ranges from 0.05 µm to 5 µm. The width of the shielding structure 406 is the width of the shielding region P+.

[0057] Please refer to Figure 13 , Figure 13 is Figure 12 is a schematic diagram of a top view structure on the basis of the above, after forming the gate 403, a contact layer 407 is formed on the second insulating region 402, and the contact layer 407 is located on the surface of the gate 403.

[0058] The contact layer 407 is used to lead out electricity of the gate 403.

[0059] The second insulation region 402 can be as small as possible to reduce the influence on the leakage, and is used to meet the logic circuit design requirement of leading out the contact layer 407 on the gate 403 on the second insulation region 402, which means that the contact layer cannot be located above the active region.

[0060] Correspondingly, the embodiment of the present application also provides a semiconductor structure formed by the above method, which will be described below in detail Figures 10 to 13 The semiconductor structure comprises: a substrate, which comprises a substrate 400, an active region located on the substrate 400, a shielding region P+ surrounding the active region, a first insulation region 401 surrounding the shielding region P+, and the first insulation region 401 being in contact with the shielding region P+, and a second insulation region 402 between part of the active region and the shielding region P+, the active region comprising a first region I and a second region II separated from each other, and a third region III surrounding the first region I and the second region II; a source 404 located in the first region I; a drain 405 located in the second region II; a shielding structure in the shielding region P+, the shielding structure 406 having shielding ions; a gate 403 located on the third region III, and part of the gate 403 extending to the second insulation region 402.

[0061] The gate 403 surrounds the source 404 and the drain 405, and the source 404 and the drain 405 are not in contact with the first insulation region 401 and the second insulation region 402, thereby avoiding the leakage caused by radiation ionization in the transistor; meanwhile, the shielding region P+ surrounds the active region, and the shielding structure 406 in the shielding region P+ is used to shield the additional electric field introduced by the positive charges generated by radiation in the second insulation region 402, thereby reducing the induced charges generated in the active region between adjacent transistors due to the additional electric field, and further reducing the leakage between adjacent transistors.

[0062] In the embodiment, the semiconductor structure further comprises: a contact layer 407 located on the second insulation region 402, and the contact layer 407 is located on the surface of the gate 403.

[0063] The second insulation region 402 can be as small as possible to reduce the influence on the leakage, and is used to meet the logic circuit design requirement of leading out the contact layer 407 on the gate 403 on the second insulation region 402, which means that the contact layer cannot be located above the active region.

[0064] In the embodiment, the source 404 and the drain 405 are of N-type, and the shielding ions are of P-type.

[0065] In this embodiment, the shielding structure 406 has a depth ranging from 0 µm to 5 µm; and a width ranging from 0.05 µm to 5 µm.

[0066] In this embodiment, the second insulating region 402 has a dimension along the extension direction of the gate 403 ranging from 0 µm to 5 µm.

[0067] Although the present application has been disclosed with reference to the above embodiments, the present application is not limited to the above. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the present application. The scope of protection of the present application should be limited by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a base, an active region located on the base, a shielding region surrounding the active region, and a first insulating region surrounding the shielding region, wherein the first insulating region is in contact with the shielding region, and a second insulating region is also present between a portion of the active region and the shielding region. The active region includes a first region and a second region that are separated from each other, and a third region surrounding the first region and the second region. The source electrode is located within the first region; The drain electrode is located in the second region; A shielding structure located within the shielding area, wherein the shielding structure contains shielding ions; A gate located on the third region, and a portion of the gate also extends onto the second insulating region.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: A contact layer located on the second insulating region, and the contact layer is located on the gate surface.

3. The semiconductor structure as described in claim 1, characterized in that, The source and drain electrodes are of N-type conductivity; the shielding ions are of P-type conductivity.

4. The semiconductor structure as described in claim 3, characterized in that, The depth of the shielding structure ranges from 0 µm to 5 µm; the width of the shielding structure ranges from 0.05 µm to 5 µm.

5. The semiconductor structure as described in claim 1, characterized in that, The second insulating region has a dimension ranging from 0 µm to 5 µm along the extension direction of the gate.

6. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a base, an active region located on the base, a shielding region surrounding the active region, and a first insulating region surrounding the shielding region, wherein the first insulating region is in contact with the shielding region, and a second insulating region is further provided between a portion of the active region and the shielding region, the active region including a first region and a second region separated from each other, and a third region surrounding the first region and the second region; A gate is formed on the third region, and a portion of the gate also extends onto the second insulating region; A source electrode is formed within the first region; A drain electrode is formed in the second region; Shielding ions are injected into the shielding area to form a shielding structure.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The method for the gate, the source, the drain, and the shielding structure includes: forming the gate; after forming the gate, implanting dopant ions in a first region and a second region to form the source and the drain; and after forming the gate, implanting shielding ions in the shielding region to form the shielding structure.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The process parameters for implanting the shielding ions within the shielded region include: the shielding ions include P-type conductive ions; the doping dose of the conductive ions is greater than or equal to 1E12 atom / cm². 2 The injected energy range is greater than or equal to 5 KeV.

9. The method for forming a semiconductor structure as described in claim 6, characterized in that, Also includes: After the gate is formed, a contact layer is formed on the second insulating region, and the contact layer is located on the gate surface.

10. The method for forming a semiconductor structure as described in claim 6, characterized in that, The source and drain electrodes are of N-type conductivity; the shielding ions are of P-type conductivity.

11. The method for forming a semiconductor structure as described in claim 7, characterized in that, The depth of the shielding structure ranges from 0 µm to 5 µm; the width of the shielding structure ranges from 0.05 µm to 5 µm.

12. The method for forming a semiconductor structure as described in claim 6, characterized in that, The second insulating region has a dimension ranging from 0 µm to 5 µm along the extension direction of the gate.

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