A field-effect transistor, its fabrication method, switching circuit and circuit board

Abstract

This application provides a field-effect transistor (FET), its fabrication method, a switching circuit, and a circuit board. The fabrication method includes: providing a FET and irradiating it; applying a set current to the drain of the FET for a set duration, and applying the same set voltage to the gate and source of the FET; the set voltage is a ground voltage or a reverse voltage. This allows the FET to be in a reverse-biased off state, generating electron-hole pairs at the insulating oxide layer and the interface between the insulating oxide layer and the semiconductor substrate. These electron-hole pairs can recombine with trapped charges, thereby repairing the trapped charges generated during irradiation. Therefore, the drain current can be reduced, the uniformity of the drain current can be improved, and the convergence of the source and drain breakdown voltages can be enhanced. Furthermore, by applying the same set voltage to the gate and source of the FET, breakdown of the FET in the reverse-biased state can be prevented.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a field-effect transistor, its manufacturing method, switching circuit, and circuit board. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs), also known as field-effect transistors, MOS transistors, or MOS devices, are unipolar voltage-driven devices characterized by low conduction losses and high switching frequencies. They are widely used in applications such as switching circuits and communication equipment.

[0003] In some applications, MOS devices are frequently turned on and off. When a MOS device is turned on, it stores a large number of electrons and holes. When the device is turned off, these excess electrons and holes need to recombine or be removed as quickly as possible. To ensure the performance of the MOS device and meet application requirements, it is necessary to improve the reverse recovery performance of the parasitic body diode within the MOS device. This can be achieved by reducing the minority carrier lifetime in the MOS device, thereby accelerating the recombination of excess electron-hole pairs caused by the parasitic body diode's conduction and thus improving the reverse recovery performance of the parasitic body diode.

[0004] In MOS devices, minority carrier lifetime can be understood as the time from the generation of minority carriers in a semiconductor material to their disappearance. By using lifetime control technology, defect levels can be introduced into the semiconductor bandgap. These defect levels can form recombination centers, promoting the recombination of electrons in the conduction band and holes in the valence band, thereby accelerating minority carrier recombination, reducing minority carrier lifetime and reverse recovery charge, and thus improving the reverse recovery performance of parasitic diodes in MOS devices.

[0005] In related technologies, the commonly used lifetime control technology is the irradiation process. During the irradiation process, the MOS device is bombarded by high-energy particles, which will form unstable trap charges in the insulating oxide layer and at the interface between the insulating oxide layer and the semiconductor substrate. These trap charges are difficult to repair, which leads to a deterioration in the performance of the MOS device. For example, it will cause an increase in the leakage current of the drain in the MOS device and a decrease in the uniformity of the leakage current. It will also cause a decrease in the convergence of the source and drain breakdown voltage (which can be understood as the breakdown voltage) in the MOS device. Summary of the Invention

[0006] This application provides a field-effect transistor, its manufacturing method, a switching circuit, and a circuit board to reduce the leakage current of the drain, improve the uniformity of the leakage current, and improve the convergence of the source and drain breakdown voltages.

[0007] In a first aspect, embodiments of this application provide a method for fabricating a field-effect transistor (FET). The method may include: providing the FET and irradiating it; applying a set current to the drain of the FET for a set duration and applying the same set voltage to the gate and source of the FET; the set voltage being a ground voltage or a reverse voltage; wherein the ground voltage is a voltage that is 0 relative to ground, and the reverse voltage is a voltage that is opposite to the forward conduction voltage in terms of positive and negative values. For example, if the forward conduction voltage is positive, then the reverse conduction voltage is negative.

[0008] In this embodiment, irradiating the field-effect transistor (FET) can reduce its minority carrier lifetime, thereby improving the reverse recovery performance of the parasitic diode in the FET. However, during the irradiation process, the FET is bombarded by high-energy particles, forming unstable trap charges at the insulating oxide layer and the interface between the insulating oxide layer and the semiconductor substrate. These trap charges are difficult to repair, resulting in some FETs on the same semiconductor substrate (e.g., a wafer) having more unstable trap charges, some having fewer, and some even having no trap charges at all. This leads to poor performance uniformity among the multiple FETs on the same semiconductor substrate. In this embodiment, by applying a set current to the drain of a field-effect transistor (FET) for a set time period and applying the same set voltage to the gate and source, the FET can be put into a reverse-biased off state. The reverse-biased state refers to the state opposite to the forward-biased state. Taking an N-type FET as an example, applying a positive voltage to the gate allows the FET to conduct forward, while applying a negative voltage to the gate allows it to be reverse-biased. Furthermore, a certain number of electron-hole pairs can be generated at the insulating oxide layer and the interface between the insulating oxide layer and the semiconductor substrate. These electron-hole pairs can recombine with trapped charges, thereby repairing the unstable trapped charges generated by irradiation treatment. This ensures that the trapped charges in multiple FETs on the same semiconductor substrate are all in a stable state, reducing the performance differences between different FETs on the same semiconductor substrate and improving the performance uniformity of multiple FETs on the same semiconductor substrate. In other words, it can reduce the drain current, improve the uniformity of the drain current, and improve the convergence of the source and drain breakdown voltages, thus broadening the application range of FETs. In addition, by applying the same set voltage to the gate and source of the field-effect transistor, the gate and source can be kept at the same potential, preventing the field-effect transistor from being broken down in reverse bias.

[0009] In one possible implementation of this application, the aforementioned set current is in the range of 0.1uA to 100mA. In the embodiments of this application, applying a set current in the range of 0.1uA to 100mA to the drain of the field-effect transistor can prevent the field-effect transistor from burning out while ensuring the generation of sufficient electron-hole pairs.

[0010] In one possible implementation of this application, the aforementioned setting time is within the range of 1µs to 100s. In this embodiment, controlling the time for applying the setting current to the drain within the range of 1µs to 100s can prevent damage to the field-effect transistor while ensuring sufficient electron-hole pairs are generated. In specific implementations, the setting time for applying the current to the drain can be determined based on the magnitude of the setting current applied to the drain. For example, if the setting current applied to the drain is large, the time for applying the setting current to the drain can be shortened. This can be set according to actual needs; the magnitude of the setting current and the setting time are not limited here.

[0011] In one possible implementation of this application, the field-effect transistor is a P-type transistor, and the reverse voltage is a positive voltage. Alternatively, the field-effect transistor may be an N-type transistor, and the reverse voltage is a negative voltage. This allows the field-effect transistor to be kept in a reverse-biased state.

[0012] In one possible implementation of this application, the above-mentioned field-effect transistor is provided, and the field-effect transistor is subjected to irradiation treatment, including: forming the gate and source of a plurality of field-effect transistors on the surface of one side of a semiconductor substrate; irradiating the semiconductor substrate on which the gate and source are formed; and forming the drain of a plurality of field-effect transistors on the surface of the other side of the semiconductor substrate to obtain a plurality of field-effect transistors.

[0013] In this embodiment, after completing the front-side process of the field-effect transistor and before performing the back-side process, the semiconductor substrate forming the gate and source is irradiated. This allows the irradiation process to be fully compatible with the fabrication process of the field-effect transistor. Furthermore, after completing the front-side process of the field-effect transistor, the semiconductor substrate forming the gate and source can be directly placed in the irradiation equipment without repeatedly flipping the semiconductor substrate. This simplifies the process and facilitates mass production.

[0014] Of course, the field-effect transistor can also be irradiated after the back-side process of the field-effect transistor is completed. That is, the above-mentioned provision of the field-effect transistor and irradiation of the field-effect transistor can also include: forming the gate and source of a plurality of field-effect transistors on the surface of one side of the semiconductor substrate; forming the drain of a plurality of field-effect transistors on the surface of the other side of the semiconductor substrate to obtain the field-effect transistor; and irradiating the obtained field-effect transistor.

[0015] In one possible implementation of this application, the irradiation process may include electron irradiation, proton irradiation, or neutron irradiation. In specific implementation, the type of irradiation operation can be determined according to actual needs.

[0016] In one possible implementation of this application, after the above-mentioned irradiation treatment of the field-effect transistor (FET), an annealing operation may be performed on the FET. During the irradiation treatment, the FET is bombarded by high-energy particles, forming trapped charges at the insulating oxide layer and the interface between the insulating oxide layer and the semiconductor substrate. The annealing operation can repair some of the trapped charges, improving the leakage current and breakdown voltage performance of the FET. However, general annealing cannot completely repair the trapped charges. In this embodiment, after the irradiation treatment, a set current is applied to the drain of the FET, and the same set voltage is applied to the gate and source, putting the FET in a reverse-biased off state. A certain number of electron-hole pairs are generated at the interface between the insulating oxide layer and the semiconductor substrate. These electron-hole pairs can recombine with the trapped charges, thereby further repairing the trapped charges generated by the irradiation treatment, and further improving the leakage current and breakdown voltage performance of the FET.

[0017] In one possible implementation of this application, the method may further include: in a first testing phase, detecting the static parameters of multiple field-effect transistors (FETs) sharing the same semiconductor substrate after irradiation treatment, and comparing the static parameters with preset standard parameters to obtain multiple FETs after testing; dividing the multiple FETs obtained after the first testing phase to obtain multiple FET devices; and in a second testing phase following the first testing phase, detecting the static parameters of the multiple FET devices obtained, and comparing the static parameters with preset standard parameters to obtain multiple FET devices after testing. In this embodiment, in the first and / or second testing phases, a set current may be applied to the drain of the FET within a set duration. This makes the step of applying a set current to the drain of the FET compatible with the testing process, eliminating the need for additional processes, facilitating mass production, and saving production costs.

[0018] Secondly, embodiments of this application also provide a field-effect transistor (FET) that can be applied in integrated circuits. This FET is fabricated using any of the methods described above. In these fabrication methods, by applying a current within a certain range to the drain of the FET for a set time period and applying the same set voltage to the gate and source, the FET can be brought into a reverse-biased off state. This generates a certain number of electron-hole pairs at the insulating oxide layer and the interface between the insulating oxide layer and the semiconductor substrate. These electron-hole pairs can recombine with trapped charges, thereby repairing the trapped charges generated by irradiation treatment. Therefore, the FET obtained using the above fabrication method has a lower drain current, higher drain current uniformity, and better convergence of source and drain breakdown voltages.

[0019] Thirdly, this application also provides a switching circuit, which can be a switching circuit in an AC-DC conversion circuit, a high-voltage conversion circuit, or a half-bridge rectifier circuit. The switching circuit includes a motherboard and any of the aforementioned field-effect transistors provided in this application embodiment, with the field-effect transistor disposed on the motherboard. In this application embodiment, using any of the above-mentioned manufacturing methods can repair the trapped charge generated by irradiation treatment, resulting in a field-effect transistor with better performance, for example, better source and drain voltage withstand capabilities. Consequently, the switching circuit including the field-effect transistor also exhibits better performance. Since the principle by which this switching circuit solves the problem is similar to that of the aforementioned field-effect transistor, the implementation of this switching circuit can refer to the implementation of the aforementioned field-effect transistor, and repeated details will not be elaborated further.

[0020] Fourthly, embodiments of this application also provide a circuit board, which includes any of the aforementioned field-effect transistors or the aforementioned switching circuits. This circuit board can be a printed circuit board (PCB) or other types of circuit boards, and is not limited thereto. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of a field-effect transistor;

[0022] Figure 2 This is a schematic diagram of another structure of a different type of field-effect transistor;

[0023] Figure 3 A flowchart illustrating the fabrication method of a field-effect transistor provided in this application embodiment.

[0024] Figure label:

[0025] 101 - Semiconductor substrate; 102 - Insulating oxide layer; G - Gate; S - Source; D - Drain; I - Set current; U - Set voltage. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0027] This application provides a field-effect transistor, its fabrication method, a switching circuit, and a circuit board. The fabrication method can be used to fabricate various metal-oxide-semiconductor field-effect transistors, such as trench MOSFETs, shielded gate trench (SGT) transistors, or insulated gate bipolar transistors (IGBTs). Of course, the fabrication method in this application can also be used to fabricate other field-effect transistors, which will not be listed here.

[0028] It should be noted that in this specification, similar reference numerals and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0029] To more clearly describe the fabrication method of the embodiments of this application, the structure of the field-effect transistor will be described below in conjunction with the accompanying drawings.

[0030] Figure 1 This is a schematic diagram of the structure of a field-effect transistor, such as... Figure 1 As shown, the field-effect transistor may include: a semiconductor substrate 101, a source S, a drain D, a gate G, and an insulating oxide layer 102, wherein the source S and the drain D are located on opposite sides of the semiconductor substrate 101. Optionally, the semiconductor substrate 101 may be made of silicon, and the insulating oxide layer 102 may be made of silicon oxide.

[0031] Figure 1 In the field-effect transistor shown, the gate G and the source S are located on one side of the semiconductor substrate 101, and the drain D is located on the other side of the semiconductor substrate 101. In this way, when the field-effect transistor is turned on, the current flows from the drain D to the source S, that is, the current flows vertically in the semiconductor substrate 101, which can make full use of the area of ​​the semiconductor substrate 101.

[0032] Figure 2 This is a schematic diagram of another structure of a field-effect transistor, such as... Figure 2 As shown, the field-effect transistor is a shielded gate trench field-effect transistor. This field-effect transistor may include: a semiconductor substrate 101, a source S, a gate G, and an insulating oxide layer 102 located on one side of the semiconductor substrate 101, and a drain D located on the other side of the semiconductor substrate 101. Furthermore, the semiconductor substrate 101 also includes a trench T, within which the gate G, the source S, and the insulating oxide layer 102 are disposed. The insulating oxide layer 102 serves to insulate the gate G and the source S within the trench T. Optionally, the material of the semiconductor substrate 101 may include silicon, and the material of the insulating oxide layer 102 may include silicon oxide. Figure 2 The example shown is a shielded gate trench field-effect transistor with a left-right structure. Shielded gate trench field-effect transistors can also have a vertical structure, which is not limited here.

[0033] Continue to refer to Figure 2 The field-effect transistor may further include a contact hole 103 and a dielectric layer 104. The semiconductor substrate 101 has P-regions and N-regions around the trench T. The contact hole 103 is filled with a metallic material and connects the source S to the P-region of the semiconductor substrate 101. The dielectric layer 104 insulates the gate G from the source S and also serves a planarization function. The source S in this field-effect transistor is divided into two parts: one part is located above the dielectric layer 104, and the other part is located within the trench T. The portion of the source S above the dielectric layer 104 is interconnected with the portion of the source S located within the trench T. Similarly, the gate G in this field-effect transistor is also divided into two parts, with these two parts located on opposite sides of the source S within the trench T, and these two parts of the gate G are interconnected.

[0034] Figure 2 In the field-effect transistor shown, the gate G and source S are located on one side of the semiconductor substrate 101, and the drain D is located on the other side of the semiconductor substrate 101. Thus, when the field-effect transistor is turned on, the current flows from the drain D to the source S, meaning the current flows vertically within the semiconductor substrate 101, making full use of the area of ​​the semiconductor substrate 101. Furthermore, by providing a trench T in the semiconductor substrate 101, the direction of the electric field can be changed, resulting in better voltage withstand capability for the source S and drain D of the field-effect transistor.

[0035] Figure 3 This is a flowchart illustrating a method for fabricating a field-effect transistor (FET) according to an embodiment of this application. This method can be used to fabricate any FET, such as... Figure 1 and Figure 2 The two field-effect transistor structures shown can, of course, be used to fabricate other field-effect transistor structures, which are not limited herein. This application focuses on fabricating... Figure 2 The field-effect transistor shown is used as an example for illustration. Figure 3 As shown, the method for fabricating a field-effect transistor provided in this application embodiment may include:

[0036] S201, with Figure 2 Taking the structure shown as an example, a field-effect transistor is provided, and the field-effect transistor is subjected to irradiation treatment;

[0037] S202. Apply a set current I to the drain D of the field-effect transistor within a set time period, and apply the same set voltage U to the gate G and source S of the field-effect transistor; the set voltage U is a ground voltage or a reverse voltage; wherein, the ground voltage is a voltage that is 0 relative to the ground voltage; the reverse voltage is a voltage that is opposite to the forward conduction voltage in terms of positive and negative values. For example, if the forward conduction voltage is a positive voltage, then the reverse conduction voltage is a negative voltage.

[0038] In this embodiment, irradiating the field-effect transistor (FET) can reduce its minority carrier lifetime, thereby improving the reverse recovery performance of the parasitic diode in the FET. However, during the irradiation process, the FET is bombarded by high-energy particles, forming unstable trap charges at the insulating oxide layer and the interface between the insulating oxide layer and the semiconductor substrate. These trap charges are difficult to repair, resulting in some FETs on the same semiconductor substrate (e.g., a wafer) having more unstable trap charges, some having fewer, and some even having no trap charges at all. This leads to poor performance uniformity among the multiple FETs on the same semiconductor substrate. In this embodiment, by applying a set current to the drain of a field-effect transistor (FET) for a set time period and applying the same set voltage to the gate and source, the FET can be put into a reverse-biased off state. The reverse-biased state refers to the state opposite to the forward-biased state. Taking an N-type FET as an example, applying a positive voltage to the gate allows the FET to conduct forward, while applying a negative voltage to the gate allows it to be reverse-biased. Furthermore, a certain number of electron-hole pairs can be generated at the insulating oxide layer and the interface between the insulating oxide layer and the semiconductor substrate. These electron-hole pairs can recombine with trapped charges, thereby repairing the unstable trapped charges generated by irradiation treatment. This ensures that the trapped charges in multiple FETs on the same semiconductor substrate are all in a stable state, reducing the performance differences between different FETs on the same semiconductor substrate and improving the performance uniformity of multiple FETs on the same semiconductor substrate. In other words, it can reduce the drain current, improve the uniformity of the drain current, and improve the convergence of the source and drain breakdown voltages, thus broadening the application range of FETs. Experiments have verified that the fabrication method described in this application can improve the leakage current and withstand voltage performance of the field-effect transistor by more than 10%. Furthermore, by applying the same set voltage to the gate and source of the field-effect transistor, the gate and source can be kept at the same potential, preventing the field-effect transistor from breaking down under reverse bias.

[0039] It should be noted that, in the embodiments of this application, the following are used: Figure 2Taking the field-effect transistor shown as an example, the above fabrication method is explained. In specific implementations, the fabrication method in this application embodiment can also be used to fabricate other field-effect transistors, for example, it can be used to fabricate... Figure 1 The field-effect transistors shown are not illustrated here individually.

[0040] Continue to refer to Figure 2 In this embodiment, in step S202, the set current I is within the range of 0.1µA to 100mA, meaning a current within this range can be applied to the drain D of the field-effect transistor (FET). In practical applications, if the set current I applied to the drain D of the FET is greater than 100mA, i.e., the current applied to the drain D is too large, it can easily lead to the FET being burned out. If the set current I applied to the drain D of the FET is less than 0.1µA, i.e., the current applied to the drain D is too small, the effect on the FET is minimal, insufficient electron-hole pairs cannot be generated, and the duration of applying the set current I to the drain D is longer. Therefore, in this embodiment, applying a set current I within the range of 0.1µA to 100mA to the drain D of the FET can prevent the FET from being burned out while ensuring sufficient electron-hole pairs are generated.

[0041] Optionally, in step S202 above, the set duration is within the range of 1µs to 100s. For example, a set current can be continuously applied to the drain of the field-effect transistor (FET) within this set duration. In practical applications, if the time for applying the set current I to the drain D of the FET is greater than 100s, i.e., the time for applying current to the drain D is too long, it can easily lead to excessive heat in the FET, damaging it. Furthermore, the longer the time for applying current to the drain D, the higher the operating cost. If the time for applying the set current I to the drain D of the FET is less than 1µs, i.e., the time for applying current to the drain D is too short, the effect on the FET is minimal, and sufficient electron-hole pairs cannot be generated. Therefore, in this embodiment, the time for applying the set current I to the drain D is controlled within the range of 1µs to 100s, which can prevent damage to the FET while ensuring sufficient electron-hole pairs are generated. In practice, the set duration of applying current to drain D can be determined based on the magnitude of the set current I applied to drain D. For example, if the set current I applied to drain D is large, the time for applying the set current I to drain D can be shortened. It can be set according to actual needs. Here, the magnitude of the set current I and the set duration are not limited.

[0042] In some embodiments of this application, in step S202 above, while applying current to the drain of the field-effect transistor (FET), the same set voltage can be applied to the gate and source to keep the FET in a reverse-biased state. Furthermore, the gate and source can be kept at the same potential to prevent the FET from being damaged in the reverse-biased state. Optionally, the set voltage can be a ground voltage, that is, the gate and source are simultaneously grounded. Alternatively, the set voltage can also be a reverse voltage; if the FET is a P-type transistor, the reverse voltage is positive; if the FET is an N-type transistor, the reverse voltage is negative. This allows the FET to be kept in a reverse-biased state.

[0043] by Figure 2 Taking the field-effect transistor shown as an example, as Figure 2 As shown, step S201 above may include:

[0044] Front-side process of field-effect transistors: Gates G and sources S of multiple field-effect transistors are formed on the surface of one side of semiconductor substrate 101. Optionally, the semiconductor substrate 101 can be patterned to form a trench T on the surface of semiconductor substrate 101. Then, gates G and part of the sources S are formed in the trench T. Gates G and sources S are insulated from each other by an insulating oxide layer 102. After that, a dielectric layer 104 is formed on the trench T, and another part of the sources S is formed on the dielectric layer 104.

[0045] Irradiation process: The semiconductor substrate 101 forming the gate G and source S is subjected to irradiation treatment;

[0046] Backside process of field-effect transistors: Multiple drains D of field-effect transistors are formed on the surface of the semiconductor substrate 101 on the other side to obtain multiple field-effect transistors. Specifically, a thinning process and a metallization process can be performed on the surface of the semiconductor substrate 101 away from the source S to form drains D on the surface of the semiconductor substrate 101 on the other side.

[0047] In this embodiment, to improve manufacturing efficiency, multiple field-effect transistors (FETs) are formed on the same semiconductor substrate. After completing the front-side process of the FETs and before performing the back-side process, the semiconductor substrate 101 forming the gate G and source S is irradiated. This allows the irradiation process to be fully compatible with the FET manufacturing process. Furthermore, after completing the front-side process of the FETs, the semiconductor substrate 101 forming the gate G and source S can be directly placed in the irradiation equipment without repeatedly flipping the semiconductor substrate 101, simplifying the process flow and facilitating mass production.

[0048] Of course, in step S201 above, the field-effect transistor can also be irradiated after the back-side process of the field-effect transistor is completed. That is, step S201 above can include:

[0049] Front-side process of field-effect transistors: The gates (G) and sources (S) of multiple field-effect transistors are formed on the surface of one side of the semiconductor substrate 101;

[0050] Backside process of field-effect transistor: Multiple drains D of field-effect transistors are formed on the surface on the other side of semiconductor substrate 101 to obtain field-effect transistors;

[0051] Irradiation process: The obtained field-effect transistors are subjected to irradiation treatment.

[0052] In this embodiment of the application, after completing the front and back processes of the field-effect transistor, the field-effect transistor is then subjected to irradiation treatment, which can also make the irradiation treatment process compatible with the fabrication process of the field-effect transistor.

[0053] It should be noted that, in the embodiments of this application, the following are used: Figure 2 Taking the field-effect transistor shown as an example, the above fabrication method is explained. In specific implementations, the field-effect transistor can also have other structures. For example, the field-effect transistor can also be... Figure 1 The structure shown can be adapted to different process flows depending on the specific structure of the field-effect transistor (FET) in actual manufacturing processes; no specific limitations are imposed here.

[0054] Optionally, in the above-described manufacturing method provided in this application embodiment, in step S201, the field-effect transistor is subjected to irradiation treatment. In actual operation, the field-effect transistor can be placed in an irradiation device, and the field-effect transistor can be bombarded by high-energy particles to complete the irradiation operation. Specifically, the irradiation treatment may include electron irradiation, proton irradiation, or neutron irradiation. In specific implementation, the type of irradiation operation can be determined according to actual needs.

[0055] After step S201 above, the process may further include: annealing the field-effect transistor.

[0056] During irradiation, field-effect transistors (FETs) are bombarded by high-energy particles, forming trapped charges at the insulating oxide layer and the interface between the insulating oxide layer and the semiconductor substrate. Annealing can repair some of these trapped charges, improving the leakage current and breakdown voltage performance of the FET. However, conventional annealing cannot completely repair the trapped charges. In this embodiment, after irradiation, a set current is applied to the drain of the FET, and the same set voltage is applied to the gate and source, putting the FET in a reverse-biased off state. This generates a certain number of electron-hole pairs at the interface between the insulating oxide layer and the semiconductor substrate. These electron-hole pairs can recombine with the trapped charges, further repairing the trapped charges generated during irradiation and further improving the leakage current and breakdown voltage performance of the FET.

[0057] In some embodiments of this application, the above-described manufacturing method may further include:

[0058] In the first testing phase, the static parameters of multiple field-effect transistors (FETs) sharing the same semiconductor substrate after irradiation are detected, and these static parameters are compared with preset standard parameters to obtain the tested FETs. For example, these static parameters can be threshold voltage, drain current, drain current uniformity, and source and drain breakdown voltages, etc., or other parameters are not limited here. Each static parameter can correspond to a preset standard parameter; for example, the preset standard parameter for drain current uniformity can be 90%. During the testing process, if the detected static parameter reaches the corresponding standard parameter (e.g., drain current uniformity reaches 90%), the FET passes the test; if the detected static parameter does not reach the corresponding standard parameter (e.g., drain current uniformity does not reach 90%), the FET fails the test. Subsequent steps can be used to improve the FET, or FETs with significantly different static parameters from the preset standard parameters can be discarded.

[0059] The multiple field-effect transistors obtained after the first testing phase are divided to obtain multiple field-effect transistor devices;

[0060] In the second testing phase following the first testing phase, the static parameters of the obtained field-effect transistor (FET) are detected and compared with preset standard parameters to obtain the tested FET. The static parameters in the second testing phase can be threshold voltage, drain current, drain current uniformity, and source and drain breakdown voltages, or other parameters; no limitation is made here. Similar to the first testing phase, each static parameter in the second testing phase can also correspond to a preset standard parameter. The preset standard parameter in the second testing phase can be the same as or different from the preset standard parameter in the first phase. For example, the preset standard parameter corresponding to the drain current uniformity can be 95%. During the testing process, if the detected static parameter reaches the corresponding standard parameter (e.g., the drain current uniformity reaches 95%), the FET passes the test. If the detected static parameter does not reach the corresponding standard parameter (e.g., the drain current uniformity does not reach 95%), the FET fails the test. The FET can be improved through subsequent steps, or the FET with static parameters that differ significantly from the preset standard parameters can be discarded.

[0061] In the first test phase and / or the second test phase, perform the above step S202.

[0062] In actual manufacturing processes, to improve production efficiency, multiple field-effect transistors (FETs) can be fabricated on the same semiconductor substrate. After the FET fabrication process is completed, the semiconductor substrate can be diced to obtain multiple FET devices. Following the completion of the FET fabrication process, each FET can be tested in the first testing phase to detect its static parameters. After dicing the semiconductor substrate, the FETs can be packaged, and the packaged FET devices are tested in the second testing phase to detect their static parameters.

[0063] During the testing of the field-effect transistor (FET) in either the first or second testing phase, a test signal needs to be applied to the source, drain, or gate of the FET using a test device. Therefore, in this embodiment, step S202 is executed in the first and / or second testing phase. For example, after applying the test signal to the FET, the connection relationship or parameters between the test device and the FET can be simply adjusted to apply a set current to the drain of the FET and a set voltage to the gate and source of the FET. This makes step S202 compatible with the testing process, eliminating the need for additional processes, facilitating mass production, and saving production costs. Of course, in practical applications, step S202 can also be executed in other phases, such as during the testing process before the FET is put into use. This is not a limitation.

[0064] Based on the same technical concept, this application also provides a field-effect transistor (FET), which can be applied in integrated circuits. The FET can function as a switch, amplifier, or variable resistor. This FET is fabricated using any of the methods described above. In these fabrication methods, by applying a current within a certain range to the drain of the FET for a set time period and applying the same set voltage to the gate and source, the FET can be brought into a reverse-biased off state. This generates a certain number of electron-hole pairs at the insulating oxide layer and the interface between the insulating oxide layer and the semiconductor substrate. These electron-hole pairs can recombine with trapped charges, thereby repairing the trapped charges generated by irradiation treatment. Therefore, the FET obtained using the above fabrication method has a lower drain current, higher drain current uniformity, and better convergence of source and drain breakdown voltages.

[0065] Based on the same technical concept, embodiments of this application also provide a circuit board, which includes any of the aforementioned field-effect transistors. This circuit board can be a printed circuit board (PCB) or other types of circuit boards, and is not limited thereto.

[0066] Based on the same technical concept, this application also provides a switching circuit, which can be a switching circuit in an AC-DC conversion circuit, a high-voltage conversion circuit, or a half-bridge rectifier circuit. The switching circuit includes a motherboard and any of the aforementioned field-effect transistors provided in this application embodiment, with the field-effect transistor disposed on the motherboard. In this application embodiment, using any of the above-mentioned manufacturing methods can repair the trapped charges generated by irradiation treatment, resulting in a field-effect transistor with better performance, for example, better source and drain voltage withstand capabilities. Consequently, the switching circuit including the field-effect transistor also exhibits better performance. Since the principle by which this switching circuit solves the problem is similar to that of the aforementioned field-effect transistor, the implementation of this switching circuit can refer to the implementation of the aforementioned field-effect transistor, and repeated details will not be elaborated further.

[0067] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0068] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A method for fabricating a field-effect transistor, characterized in that, include: A field-effect transistor is provided, and one side of the field-effect transistor having a gate and a source is irradiated. The irradiation treatment includes: electron irradiation, proton irradiation, or neutron irradiation; A set current is applied to the drain of the field-effect transistor for a set duration, and the same set voltage is applied to the gate and source of the field-effect transistor; the set voltage is a ground voltage or a reverse voltage; wherein, the ground voltage is a voltage that is 0 relative to ground; and the reverse voltage is a voltage that is opposite in value to the forward conduction voltage.

2. The manufacturing method as described in claim 1, characterized in that, The set current is in the range of 0.1uA to 100mA.

3. The manufacturing method as described in claim 1, characterized in that, The set duration is in the range of 1µs to 100s.

4. The manufacturing method as described in claim 1, characterized in that, The field-effect transistor is a P-type transistor, and the reverse voltage is a positive voltage.

5. The manufacturing method as described in claim 1, characterized in that, The field-effect transistor is an N-type transistor, and the reverse voltage is a negative voltage.

6. The manufacturing method according to any one of claims 1 to 5, characterized in that, The provision of the field-effect transistor and the irradiation treatment of the field-effect transistor include: A plurality of the gates and sources of the field-effect transistors are formed on one side of the surface of the semiconductor substrate; The semiconductor substrate forming the gate and the source is subjected to irradiation treatment; The drains of a plurality of field-effect transistors are formed on the surface on the other side of the semiconductor substrate to obtain a plurality of field-effect transistors.

7. The manufacturing method as described in claim 6, characterized in that, Also includes: In the first testing phase, the static parameters of multiple field-effect transistors sharing the same semiconductor substrate after irradiation treatment are detected, and the static parameters are compared with preset standard parameters to obtain the multiple field-effect transistors after testing. The static parameters include: threshold voltage, leakage current of the drain, uniformity of the leakage current, or withstand voltage of the source and drain. The plurality of field-effect transistors obtained after the first testing phase are divided to obtain a plurality of field-effect transistor devices; In the second test phase following the first test phase, the static parameters of the multiple field-effect transistor devices are detected, and the static parameters are compared with preset standard parameters to obtain the multiple field-effect transistor devices after testing. Applying a set current to the drain of the field-effect transistor within a set time period includes: In the first test phase and / or the second test phase, a set current is applied to the drain of the field-effect transistor for a set duration.

8. The manufacturing method according to any one of claims 1 to 5, characterized in that, The provision of the field-effect transistor and the irradiation treatment of the field-effect transistor include: A plurality of the gates and sources of the field-effect transistors are formed on one side of the surface of the semiconductor substrate; A plurality of drains of the field-effect transistors are formed on the surface on the other side of the semiconductor substrate to obtain the field-effect transistors; The obtained field-effect transistor is subjected to irradiation treatment.

9. The manufacturing method as described in claim 8, characterized in that, Also includes: In the first testing phase, the static parameters of multiple field-effect transistors sharing the same semiconductor substrate after irradiation treatment are detected, and the static parameters are compared with preset standard parameters to obtain the multiple field-effect transistors after testing. The static parameters include: threshold voltage, leakage current of the drain, uniformity of the leakage current, or withstand voltage of the source and drain. The plurality of field-effect transistors obtained after the first testing phase are divided to obtain a plurality of field-effect transistor devices; In the second test phase following the first test phase, the static parameters of the multiple field-effect transistor devices are detected, and the static parameters are compared with preset standard parameters to obtain the multiple field-effect transistor devices after testing. Applying a set current to the drain of the field-effect transistor within a set time period includes: In the first test phase and / or the second test phase, a set current is applied to the drain of the field-effect transistor for a set duration.

10. The manufacturing method according to any one of claims 1 to 5, characterized in that, After irradiating the field-effect transistor, the process further includes: The field-effect transistor is annealed.

11. A field-effect transistor, characterized in that, The field-effect transistor is fabricated by the method described in any one of claims 1 to 10.

12. A switching circuit, characterized in that, include: The motherboard and the field-effect transistor as described in claim 11 disposed on the motherboard.

13. A circuit board, characterized in that, include: The field-effect transistor as claimed in claim 11 or the switching circuit as claimed in claim 12.

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