Three-dimensional pitch multiplication

Abstract

Memory devices and methods of manufacturing memory devices are provided. Devices and methods are described in which three-dimensional pitch multiplication decouples high aspect ratio etch width from cell width, resulting in small cell active area pitch to allow small DRAM die size.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the field of electronic devices and methods and apparatus for manufacturing electronic devices. More particularly, embodiments of the present disclosure provide 3D-DRAM memory cells and methods for forming 3D-DRAM memory cells. BACKGROUND

[0002] Semiconductor technology is rapidly advancing, and device sizes are shrinking with technological advances to provide faster processing and storage per unit of space. In DRAM devices, one of the main goals is to increase storage per unit of space, which leads to an increase in the vertical dimension or stack height of 3D DRAM devices.

[0003] In existing 3D DRAM memory, 160 nm wide slits and 80 nm holes with a pitch of 150 nm are the smallest features that can be etched into a 5-10 μιη deep oxide-nitride multi-layer film stack or 3-5 μιη of oxide-polysilicon. This etching is needed to access each layer in the stack for processing, but smaller pitch, especially in the word line direction, can allow higher memory density.

[0004] Accordingly, there is a need in the art for 3D-DRAM devices and methods for forming 3D-DRAM devices with improved smaller pitch and higher memory density. SUMMARY

[0005] One or more embodiments of the present disclosure relate to semiconductor memory devices. In one embodiment, a semiconductor memory device includes a first memory stack including alternating layers of a first material layer and a second material layer on a first portion of the device, the first memory stack including a first active region having a first width and a first pitch, a second memory stack on a second portion of the device, the second memory stack including alternating layers of the first material layer and the second material layer and including a second active region having a second width and a second pitch, a high aspect ratio opening separating the first portion from the second portion, and a dielectric layer separating the first material layer from the second material layer, wherein the pitch of the first active region and the second active region is in a range of about 50 nm to about 80 nm.

[0006] Additional embodiments of this disclosure relate to methods of forming electronic devices. In one embodiment, a method of forming an electronic device includes: forming a memory stack comprising alternating layers of a first material layer and a second material layer; forming an opening in the memory stack; recessing the second material layer to form a gap; growing a third material in the gap; and growing a fourth material adjacent to the third material in the gap to form active regions, wherein the spacing between the active regions is in the range of about 30 nm to about 50 nm.

[0007] Further embodiments of this disclosure relate to a non-transitory computer-readable medium including instructions that, when executed by a controller of a processing system, cause the processing system to: form a memory stack comprising alternating layers of a first material layer and a second material layer; form an opening in the memory stack; recess the second material layer to form a gap; grow a third material in the gap; and grow a fourth material adjacent to the third material in the gap to form active regions, wherein the spacing between the active regions is in the range of about 30 nm to about 50 nm. Attached Figure Description

[0008] To gain a more detailed understanding of the features of this disclosure, a more specific description of the disclosure, which has been briefly summarized above, can be obtained by referring to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments of this disclosure and should not be considered as limiting its scope, as other equivalent embodiments are permissible. The embodiments described herein are shown by way of example rather than limitation in the accompanying drawings, in which similar reference numerals indicate similar elements.

[0009] Figure 1 A cross-sectional view of a device according to the prior art is shown;

[0010] Figure 2 A cross-sectional view of a device according to one or more embodiments is shown;

[0011] Figure 3A A top view of a device according to one or more embodiments is shown;

[0012] Figure 3B The following are illustrated according to one or more embodiments: Figure 3A A cross-sectional view of the device;

[0013] Figure 4A A top view of a device according to one or more embodiments is shown;

[0014] Figure 4B The following are illustrated according to one or more embodiments: Figure 4A A cross-sectional view of the device;

[0015] Figure 5A a top view of a device according to one or more embodiments is shown;

[0016] Figure 5B a cross-sectional view of a device according to one or more embodiments is shown; Figure 5A

[0017] Figure 6A a top view of a device according to one or more embodiments is shown;

[0018] Figure 6B a cross-sectional view of a device according to one or more embodiments is shown; Figure 6A

[0019] Figure 7A a top view of a device according to one or more embodiments is shown;

[0020] Figure 7B a cross-sectional view of a device according to one or more embodiments is shown; Figure 7A

[0021] Figure 8A a cross-sectional view of a device according to one or more embodiments is shown;

[0022] Figure 8B a cross-sectional view of a device according to one or more embodiments is shown;

[0023] Figure 8C a cross-sectional view of a device according to one or more embodiments is shown;

[0024] Figure 8D a cross-sectional view of a device according to one or more embodiments is shown;

[0025] Figure 9A a cross-sectional view of a device according to one or more embodiments is shown;

[0026] Figure 9B a cross-sectional view of a device according to one or more embodiments is shown;

[0027] Figure 9C a cross-sectional view of a device according to one or more embodiments is shown;

[0028] Figure 9D a cross-sectional view of a device according to one or more embodiments is shown;

[0029] Figure 9E a cross-sectional view of a device according to one or more embodiments is shown;

[0030] Figure 9F a cross-sectional view of a device according to one or more embodiments is shown;​​​

[0031] Figure 9G a cross-sectional view of a device according to one or more embodiments is shown;

[0032] Figure 10A a cross-sectional view of a device according to one or more embodiments is shown;

[0033] Figure 10B a cross-sectional view of a device according to one or more embodiments is shown;

[0034] Figure 10C a cross-sectional view of a device according to one or more embodiments is shown;

[0035] Figure 11A a cross-sectional view of a device according to one or more embodiments is shown;

[0036] Figure 11B a cross-sectional view of a device according to one or more embodiments is shown;

[0037] Figure 11C a cross-sectional view of a device according to one or more embodiments is shown;

[0038] Figure 11D a cross-sectional view of a device according to one or more embodiments is shown;

[0039] Figure 11E a cross-sectional view of a device according to one or more embodiments is shown;

[0040] Figure 11F a cross-sectional view of a device according to one or more embodiments is shown;

[0041] Figure 11G a cross-sectional view of a device according to one or more embodiments is shown; and

[0042] Figure 12 a cluster tool according to one or more embodiments is shown. DETAILED DESCRIPTION

[0043] Before several illustrative embodiments of the present disclosure are described, it is to be understood that the present disclosure is not limited to the details of construction or processing steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or being carried out in various ways.

[0044] As used in this specification and the appended claims, the term "substrate" means a surface or a portion of a surface upon which processing is performed. Those skilled in the art will appreciate that references to a substrate can also mean only portions of a substrate, unless the context clearly indicates otherwise. Further, references to depositing on a substrate can mean both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0045] As used herein, "substrate" refers to any substrate or material surface formed on a substrate upon which film processing is performed during a fabrication process. For example, a substrate surface on which processing can be performed includes materials such as silicon, silicon dioxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxides, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, without limitation, semiconductor wafers. Substrates can be exposed to pre-processing treatments to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the film processing steps disclosed can also be performed on an underlayer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlayer as the context indicates. Thus, for example, in the case of depositing a film / layer or partial film / layer on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0046] As used herein, the term "dielectric layer" refers to a layer of material that is an electrical insulator that can be polarized in an electric field. In one or more embodiments, the dielectric layer comprises one or more of an oxide, a carbon-doped oxide, silicon dioxide (SiO2), porous silicon dioxide (SiO2), silicon dioxide (SiO2), silicon nitride (SiN), silicon dioxide / nitride, a carbide, an oxycarbide, a nitride, an oxynitride, an oxycarbonitride, a polymer, a phosphosilicate glass, a fluorosilicate (SiOF) glass, or an organosilicate glass (SiOCH). In one or more embodiments, the dielectric layer includes, but is not limited to, films deposited by furnace, CVD, PVD, ALD, and spin-on-coat (SoC). In one or more embodiments, the dielectric layer can be exposed to in-situ or ex-situ pretreatment and post-treatment processes to dope, implant, implant, heat, freeze, polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure, and / or bake the surface or the entire dielectric layer. In addition to film processing directly on the surface of the dielectric layer itself, in one or more embodiments, any of the film processing steps disclosed can also be performed on an underlayer formed on the dielectric layer, as disclosed in more detail below, and the term "dielectric surface" is intended to include such underlayers as indicated by the context. Thus, for example, in the case of depositing a film / layer or partial film / layer on a dielectric surface, the exposed surface of the newly deposited film / layer becomes the dielectric surface.

[0047] As used herein, the term "channel" refers to a layer of material that is an electrical conductor. In one or more embodiments, the channel comprises one or more of silicon, polysilicon, amorphous silicon, doped silicon, strained silicon, silicon on insulator (SOI), carbon-doped silicon dioxide, SiGe, germanium, gallium arsenide, GaN, InP, carbon nanotubes, and any other material such as Group III-IV, 2D TMD metals, metal oxides, metal nitrides, metal alloys, and other conductive materials, depending on the application. In one or more embodiments, the channel can be exposed to in-situ or ex-situ pretreatment and post-treatment processes to plate, fuse, freeze, heat, microwave, polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure, and / or bake the surface or the entire channel. In addition to film processing directly on the surface or the bulk structure of the channel itself, in one or more embodiments, any of the film processing steps disclosed can also be performed on an underlayer formed on the channel, as disclosed in more detail below, and the term "channel surface" is intended to include such underlayers as indicated by the context. Thus, for example, in the case of depositing a film / layer or partial film / layer on a channel surface, the exposed surface of the newly deposited film / layer becomes the channel surface.

[0048] As used herein, the term "bit line" or "source" refers to a layer of material that is an electrical conductor. In one or more embodiments, the channel comprises one or more of silicon, polysilicon, epitaxial silicon, amorphous silicon, doped silicon, strained silicon, silicon on insulator (SOI), carbon doped silicon dioxide, SiGe, germanium, Epi Ge, Epi SiGe, gallium arsenide, GaN, InP, carbon nanotubes, and any other material such as 2D TMD metals, metal oxides, metal nitrides, metal alloys, and other conductive materials, depending on the application. In one or more embodiments, the bit line includes, but is not limited to, grown silicon. The bit line can be exposed to in-situ or ex-situ pre- and post-treatment processes to fuse, freeze, heat, microwave, polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure, and / or bake the entire bit line or the surface of the bit line. In addition to film processing directly on the surface or bulk structure of the bit line itself, in the present disclosure, any of the film processing steps disclosed can also be performed on an underlying layer formed on the bit line, as disclosed in more detail below, and the term "bit line surface" is intended to include such underlying layers as indicated by the context. Thus, for example, in the case of depositing a film / layer or partial film / layer on the bit line surface, the exposed surface of the newly deposited film / layer becomes the bit line surface.

[0049] As used herein, the term "word line" or "gate" or "gate electrode" refers to a layer of material that is an electrical field generating material or a conductor material. In one or more embodiments, the word line comprises polysilicon, amorphous silicon, tungsten, ruthenium, cobalt, high dielectric constant dielectric layers, and any other material such as 2D TMD metals MoS, metal oxides, metal nitrides, metal alloys, and other conductive materials, depending on the application. The word line includes, but is not limited to, tungsten (W). The word line can be exposed to in-situ or ex-situ pre- and post-treatment processes to fuse, freeze, heat, microwave, polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure, and / or bake the metal surface and bulk. In addition to film processing directly on the surface or bulk structure of the word line itself, in the present disclosure, any of the film processing steps disclosed can also be performed on an underlying layer formed on the word line, as disclosed in more detail below, and the term "word line surface" is intended to include such underlying layers as indicated by the context. Thus, for example, in the case of depositing a film / layer or partial film / layer on the word line surface, the exposed surface of the newly deposited film / layer becomes the word line surface.

[0050] As used herein, the term "capacitor" or "memory" refers to a layer of material that acts as an electrical charge storage dam. In one or more embodiments, the capacitor includes one or more of metal, TiN, SN, Zr, ZrO, ZrAlO, AlO, Al, Nb, NgO, and any other material such as 2D TMD metal MoS, metal oxides, metal nitrides, metal alloys, and other conductive materials, depending on the application. The capacitor can be exposed to a pre-treatment process to fuse, freeze, heat, microwave, polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure, and / or bake the surface. In addition to film processing directly on the surface or bulk structure of the capacitor itself, in the present disclosure, any of the film processing steps disclosed can also be performed on an underlying layer formed on the capacitor, as disclosed in more detail below, and the term "capacitor surface" is intended to include such underlying layers as indicated by the context. Thus, for example, in the case of depositing a film / layer or partial film / layer on the capacitor surface, the exposed surface of the newly deposited film / layer becomes the capacitor surface.

[0051] As used herein, the term "active area" refers to a layer of material in which a channel, bit line, word line, or capacitor can be made. In one or more embodiments, the active area includes one or more of silicon or doped silicon. For example, in one or more embodiments, the channel material is selected from one or more of Si, molybdenum sulfide (MoS2), or IGZO (In-Ga-Zn oxide), and the cavity is replaced after the active area material is structured.

[0052] As used herein, the term "dynamic random access memory" or "DRAM" refers to a memory cell that stores a data bit by storing a packet of electrical charge on a capacitor (i.e., binary one) or not storing electrical charge (i.e., binary zero). The charge is gated onto the capacitor via an access transistor, and is sensed by turning on the same transistor and looking at the voltage perturbation created on an interconnect line by dumping the packet of charge onto the transistor output. Thus, a single DRAM cell consists of one transistor and one capacitor.

[0053] Existing 3D-NAND memory stacks with alternating layers of oxide and nitride require a replacement metal gate (RMG) process to establish word lines. As the stack height becomes larger and larger, high aspect ratio (HAR) memory hole etch / fill processes and stress control become more and more difficult. For example, in 3D-NAND memory, 160 nm wide slits and 80 nm holes with a pitch of 125 nm are the minimum features that can be etched into a 5-10 μιη deep oxide-nitride multilayer film stack or 3-5 μιη of oxide-polysilicon. This 160 nm slit etch is the spacing between active areas and is used to access each layer in the stack for processing, but smaller slits (especially in the word line direction) (e.g., 20-50 nm) can result in smaller pitches, such as 50-80 nm, which can allow for higher density memory. Etching these 20-50 nm wide slits several microns deep is extremely difficult.

[0054] Unlike creating one device or memory cell for each single memory hole or slit, one or more embodiments advantageously provide that many memory cells can be constructed with this pitch. For example, with the current 160 nm wide slits and 50 nm spacing, a single memory cell is made with a higher pitch, such as a 210 nm pitch. Using the method according to one or more embodiments, the same wide slit (e.g., 160 nm) can be created every 75 nm with a 1200 nm spacing and a 16 line space pitch. Thus, in this 160 + 1200 = 1360 nm spacing, there can advantageously be 16 memory cells with an effective pitch of 1360 / 16 = 85 nm. This is three times smaller than the memory cell size.

[0055] One or more embodiments advantageously provide that the minimum memory pitch is reduced from about 200 nm minimum pitch to less than or equal to 75 nm using existing processing technology, depending on the deposited film and recess uniformity. As a result, the memory cell density is increased by a factor of three and the die size is reduced by about 60%.

[0056] In one or more embodiments, sequential deposition is used to form many active area partitions. In one or more embodiments, alternating layers of deposited films (e.g., oxide-polysilicon, polysilicon-nitride, oxide-nitride, silicon-silicon germanium) are deposited. In a final structuring process, each set of repeated layers can form a memory cell in each layer.

[0057] In one or more embodiments, selective deposition of silicon germanium (SiGe) is used to form an oxide-polysilicon layer stack for a three-dimensional pitch multiplication film. In one or more embodiments, after etching high aspect ratio (e.g., about 160 nm wide x 1000 nm long) active area slits that are spaced from top to top (about 80 nm) and from side to side (about 1320 nm) through the layer stack, for example, the polysilicon layer in each layer is selectively etched back to remove almost all of the polysilicon between the slits, leaving only a small amount (e.g., about 50 nm) of polysilicon. High germanium (Ge) content silicon germanium (SiGe) is selectively grown to a thickness of about 20 nm, followed by an additional selective growth of a low germanium (Ge) content silicon germanium (SiGe) layer that is about 60 nm thick. In one or more embodiments, this process of alternating SiGe films is repeated eight times to form sixteen pairs of layers between each slit. In one or more embodiments, by performing a wide (e.g., about 160 nm) oxide-polysilicon slit etch, word line slits are formed perpendicular to and centered on the gap between the active area slits. In one or more embodiments, the high content Ge SiGe layer is selectively etched back in the direction of the word line slits to isolate the memory cells.

[0058] In other embodiments, non-selective deposition / recess etching of PSG / USG is used to form an oxide-nitride layer stack for a three-dimensional pitch multiplication film. In one or more embodiments, non-selective deposition and recess etching of PSG (phosphorus doped ALD oxide) and USG (undoped ALD oxide) is used to form an oxide-nitride layer stack.

[0059] As used herein, the term "three-dimensional pitch multiplication" refers to the concept of forming multiple independent active area partitions between each set of slits, segments, or holes in a layer stack.

[0060] As used herein, the term "high aspect ratio (HAR)" refers to the ratio of the depth of a feature to the width of the feature. In some embodiments, the aspect ratio of a slit or opening is greater than or equal to about 30: 1, 35: 1, 40: 1, 50: 1, 60: 1, 70: 1, or 80: 1.

[0061] Figure 1A cross-sectional view of a device 100 according to the prior art is shown. The cross-sectional view is across an active area slot, viewed from a word line slot etch sidewall. The prior art device 100 does not have pitch division. The device 120 includes alternating layers 104 and 106 on a substrate 102. There are five high aspect ratio (HAR) active area slots 108a, 108b, 108c, 108d, and 108e. Each high aspect ratio (HAR) active area slot 108 has an active area slot width 110 of about 120 nm width. The active area slot width 110 is equivalent to a cell spacing. The active area 112 has a width of about 30 nm. The horizontal pitch of a cell is the width plus the spacing, or in this case, 150 nm. The vertical pitch of a cell is the thickness of layer 106 plus 104, represented by 114, which is about 60 nm. In this document, when describing device pitch, it refers to horizontal pitch.

[0062] Figure 2 A cross-sectional view of a device 120 according to one or more embodiments is shown. The cross-sectional view is across an active area slot after three-dimensional pitch multiplication, viewed from a word line slot etch sidewall. In one or more embodiments, the device 120 has undergone three-dimensional pitch multiplication. The device 120 includes alternating layers 124 and 126 on a substrate 122. There are three high aspect ratio (HAR) active area slots 128a, 128b, and 128c. Each high aspect ratio (HAR) active area slot 128 has an active area slot width 130 in a range of about 100 nm to about 160 nm. In one or more embodiments, the width of the active area 132 is in a range of about 20 nm to about 40 nm, including about 30 nm, and the width of the active area spacing 134 is in a range of about 20 nm to about 40 nm, including about 30 nm. In one or more embodiments, three-dimensional pitch multiplication decouples the high aspect ratio (HAR) etch width from the cell width, resulting in a small cell active area pitch to allow for small DRAM die size. In one or more embodiments, the active area pitch is in a range of about 50 nm to about 80 nm. In one or more embodiments, dielectric layers 136 separate the first material layers 124 from one another.

[0063] The substrate 122 can be any suitable material known to one skilled in the art. As used in this specification and the appended claims, the term "substrate" refers to a surface or portion of a surface on which a process acts. One skilled in the art will also appreciate that reference to a substrate can refer to only a portion of a substrate, unless the context clearly indicates otherwise. Additionally, reference to depositing on a substrate can mean both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0064] In one or more embodiments, a semiconductor layer (not shown) is located on the substrate 122. In one or more embodiments, the semiconductor layer can also be referred to as a common source line. The semiconductor layer can be formed by any suitable technique known to those skilled in the art and can be made of any suitable material including, but not limited to, poly-Si. In some embodiments, the semiconductor layer is a common node made of a conductive or semiconductive material.

[0065] An optional sacrificial layer (not shown) can be formed on the semiconductor layer and can be made of any suitable material. In some embodiments, the sacrificial layer is removed and can be replaced in a subsequent process. In some embodiments, the sacrificial layer is not removed and remains within a portion of the electronic device, such as a memory device. In this case, the term "sacrificial" has an extended meaning to also include permanent layers.

[0066] In one or more embodiments, the first material layer 124 and the second material layer 126 independently include one or more of silicon (Si), silicon germanium (SiGe), silicon dioxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), poly-Si, and other materials compatible with subsequent standard semiconductor processing. In one or more embodiments, the first material layer 124 and the second material layer 126 are deposited by one or more of plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or epitaxial deposition. This processing can be used for deposition of any multilayer film stack on any substrate or semiconductor substrate, including but not limited to silicon (Si) or silicon germanium (SiGe), for example, including dielectric layers including but not limited to silicon dioxide (SiO2), silicon nitride (Si3N4) (e.g., Si / SiGe or silicon nitride / silicon dioxide).

[0067] In one or more embodiments, the dielectric layer 136 can comprise any suitable dielectric material, such as an electrical insulator known to those skilled in the art that can be polarized in an electric field. In some embodiments, the dielectric layer 136 comprises one or more of an oxide, a carbon-doped oxide, silicon dioxide (SiO), porous silicon dioxide (SiO2), silicon dioxide (SiO), silicon nitride (SiN), silicon dioxide / silicon nitride, a carbide, an oxycarbide, a nitride, an oxynitride, an oxycarbonitride, a polymer, a phosphosilicate glass, a fluorosilicate (SiOF) glass, or an organosilicate glass (SiOCH).

[0068] In one or more embodiments, a memory stack 140 is formed. The memory stack 140 in the illustrated embodiment includes a plurality of alternating stacks; such as a first material layer 124 and a second material layer 126. In a similar manner, three or more films deposited in some order can form each set of films to form each set of vertically oriented memory cells.

[0069] While Figure 2 The illustrated memory stack 140 has eight pairs of alternating first material layers 124 and second material layers 126, but one of skill in the art recognizes that this is for illustrative purposes only. The memory stack 140 can have any number of alternating first material layers 124 and second material layers 126. For example, in some embodiments, the memory stack 140 includes more than 50 pairs of alternating first material layers 124 and second material layers 126, or more than 100 pairs of alternating first material layers 124 and second material layers 126, or more than 200 pairs of alternating first material layers 124 and second material layers 126.

[0070] In one or more embodiments, a lateral laminate growth process is used for three- dimensional pitch multiplication. Figures 3A to 7B A lateral laminate growth process of one or more embodiments is illustrated. Figure 3A A top view of a device 150 according to one or more embodiments is shown. Figure 3B A cross-sectional view of the device 150 of Figure 3A In one or more embodiments, a slit etch is performed to form at least one opening 156 in the layer isolation layer 154. The silicon layer 152 can then be recessed using any suitable recessing technique known to those of skill in the art, including but not limited to a wet etch, a vapor phase etch, an isotropic plasma etch, or any other selective removal process (SRP).

[0071] Figure 4A A top view of a device 150 according to one or more embodiments is shown. Figure 4B A cross-sectional view of the device 150 of Figure 4Aa cross-sectional view of the device 150. In one or more embodiments, the first interlayer layer 160 and the second interlayer layer 158 are selectively grown in the at least one opening 156. In one or more embodiments, the first interlayer layer 160 and the second interlayer layer 158 can include any suitable material known to those skilled in the art. In one or more embodiments, the first interlayer layer 160 and the second interlayer layer 158 independently include one or more of silicon (Si), silicon germanium (SiGe), silicon dioxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON). In one or more embodiments, the first interlayer layer 160 and the second interlayer layer 158 are deposited by epitaxial deposition or some other selective deposition or reaction process. This process can be used for any multi-layer film stack deposition, such as forming nitride or oxynitride on Si, SiGe, or other materials.

[0072] Figure 5A a top view of the device 150 according to one or more embodiments is shown. Figure 5B a cross-sectional view of the device 150 according to one or more embodiments is shown. Figure 5A a cross-sectional view of the device 150. In one or more embodiments, the first interlayer layer 160 and the second interlayer layer 158 are selectively grown in the at least one opening 156 to fill the at least one opening 156.

[0073] In one or more embodiments, one side of the pitch multiplication structure is shown in 155. The memory stack 155 in the illustrated embodiment includes a plurality of alternating first interlayer layers 160 and second interlayer layers 158 formed on one side of the initial layer 152. In one or more embodiments, the second interlayer layer 158 includes silicon (Si). In one or more embodiments, the first interlayer layer 160 includes silicon germanium (SiGe). Thus, in some embodiments, the memory stack 155 includes alternating layers of silicon (Si) and silicon germanium (SiGe).

[0074] Although Figure 5AThe memory stack 155 shown in the middle has six pairs of alternating first interlayer gap layers 160 and second interlayer gap layers 158 on each side of 152, but one of skill in the art recognizes that this is for illustrative purposes only. The memory stack 155 can have any number of alternating first interlayer gap layers 160 and second interlayer gap layers 158. For example, in some embodiments, the memory stack 155 contains 1 pair of alternating first interlayer gap layers 160 and second interlayer gap layers 158. In other embodiments, the memory stack 155 contains 2 or more pairs of alternating first interlayer gap layers 160 and second interlayer gap layers 158 per side, or more than 4 pairs of alternating first interlayer gap layers 160 and second interlayer gap layers 158 per side, for a total of 8 pairs between the slits. More than 4 pairs becomes more difficult to handle, with diminishing returns, making 1 to 4 pairs a more desirable embodiment.

[0075] Figure 6A A top view of a device 150 is shown, according to one or more embodiments. Figure 6B A top view of a set of DRAM cells 150 is shown, according to one or more embodiments, that can be subsequently constructed with a common process. Figure 6A A cross-sectional view of the device 150 is shown. In one or more embodiments, the first interlayer gap layer 160 is removed to form a second opening 162. The layer spacing 164 is in the range of about 45 nm to about 80 nm. The layer separation 166 is in the range of about 25 nm to about 60 nm.

[0076] Figure 7A A top view of a set of DRAM cells 150 is shown, according to one or more embodiments, that can be subsequently constructed with a common process. Figure 7B A cross-sectional view of the device 150 is shown, according to one or more embodiments, as viewed from the word line slit gap etch 174. Figure 7A A cross-sectional view of the device 150 is shown. After one of the interlayer gap layers is removed, an isolation gap 162 can be formed, which can then be filled with a suitable dielectric material to isolate the device. Alternatively, one or the other of the removed interlayer gap layers can be replaced with material to form the active memory cells, while the other interlayer gap material remains in place or is also removed and replaced to form isolation between the memory cells. In one or more embodiments, the active interlayer gap layer 160 is replaced with material to form a DRAM capacitor 168, and another section of the active interlayer gap layer is used to form a transistor 170 for a DRAM memory cell. Common isolation materials between 168, 170, and 172 are SiO2 and Si3N4. In one or more embodiments, there is an opening 174 between the vertical bit line interconnects for DRAM memory cell operation.

[0077] In one or more embodiments, a selective growth method is used for three-dimensional pitch multiplication. Figures 8A to 8DFIG. 1 illustrates a cross-sectional view of a device 200 fabricated using a selective growth method of one or more embodiments. Reference is made to FIG. 1 throughout this disclosure. Figure 8A In one or more embodiments, a memory stack 205 is formed. The memory stack 205 in the illustrated embodiment includes a plurality of alternating first material layers 204 and second material layers 206 on a semiconductor layer 202 on a substrate 201.

[0078] In one or more embodiments, the semiconductor layer 202 is on the substrate 201. In one or more embodiments, the semiconductor layer 202 can also be referred to as a logic interface layer. The semiconductor layer 202 can be formed by any suitable technique known to those skilled in the art and can be made of any suitable material including, but not limited to, poly-Si. In some embodiments, the semiconductor layer 202 is a contact layer that contacts an underlying CMOS logic circuit.

[0079] An optional sacrificial layer (not shown) can be formed on the semiconductor layer 202 and can be made of any suitable material. In some embodiments, the sacrificial layer is removed and replaced in subsequent processing. In some embodiments, the sacrificial layer is not removed and remains within the electronic device, such as a memory device. In this case, the term "sacrificial" has an extended meaning to include a permanent layer and can be referred to as a conductive layer.

[0080] In one or more embodiments, the first material layers 204 and the second material layers 206 can include any suitable material known to those skilled in the art. In one or more embodiments, the first material layers 204 and the second material layers 206 independently include one or more of silicon (Si), silicon germanium (SiGe), silicon dioxide (Si02), silicon nitride (SiN), silicon oxynitride (SiON), and poly-Si. In one or more embodiments, the first material layers 204 and the second material layers 206 are deposited by one or more of plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or epitaxial deposition. This process can be used for any multi-layer film stack deposition on any substrate including dielectric layers including, but not limited to, silicon dioxide (Si02) and semiconductor substrates including, but not limited to, silicon (Si) or silicon germanium (SiGe) (e.g., Si / SiGe). In one or more embodiments, the first material layers include silicon dioxide (Si02) and the second material layers include poly-Si.

[0081] In one or more embodiments, the first material layers 204 and the second material layers 206 can have any suitable thickness. In particular embodiments, the thickness of the first material layers 204 is in a range from about 15 nm to about 25 nm, including about 20 nm. In particular embodiments, the thickness of the second material layers 206 is in a range from about 25 nm to about 45 nm, including about 30 nm or about 35 nm.

[0082] Although Figure 8A The memory stack 205 shown has three pairs of alternating first material layers 204 and second material layers 206, but one of skill in the art recognizes that this is for illustrative purposes only. The memory stack 205 can have any number of alternating first material layers 204 and second material layers 206. For example, in some embodiments, the memory stack 205 includes 192 pairs of alternating first material layers 204 and second material layers 206. In other embodiments, the memory stack 205 includes more than 100 pairs of alternating first material layers 204 and second material layers 206, or more than 200 pairs of alternating first material layers 204 and second material layers 206, or more than 300 pairs of alternating first material layers 204 and second material layers 206.

[0083] In one or more embodiments, a hard mask 208 is located on a top surface of the memory stack 205. In one or more embodiments, the hard mask layer 208 can be deposited using one or more mask layer deposition techniques known to those skilled in the microelectronics arts. In one or more embodiments, the hard mask layer 208 is deposited using one of deposition techniques such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other deposition techniques known to those skilled in the art. In one or more embodiments, the hard mask layer 208 includes a material selected from one or more of spin-on carbon, hard mask, or photoresist. One of skill in the art will appreciate that there can be multiple hard mask layers 208. In one or more embodiments, the hard mask layer 208 includes silicon nitride (SiN).

[0084] In one or more embodiments, the device 200 is patterned to form active region openings 210. The patterning can include any suitable patterning techniques known to those skilled in the art.

[0085] Referring to Figure 8B The device 200 undergoes a high aspect ratio (HAR) slit etch process to increase the depth of the openings 210 such that the openings 210 extend to the top surface of the semiconductor layer 202. In one or more embodiments, the width of the openings 210 is in a range from about 30 nm to about 160 nm. The second material layers 206 are subsequently recessed. In some embodiments, the second material layers 206 include polysilicon. In one or more embodiments, the polysilicon is recessed to a depth in a range from about 100 nm to about 400 nm.

[0086] Referring to Figure 8CThe third material 212 and the fourth material 214 are selectively grown. In one or more embodiments, the third material 212 and the fourth material 214 can include any suitable material known to those skilled in the art. In one or more embodiments, the third material 212 and the fourth material 214 independently include one or more of silicon (Si), silicon germanium (SiGe), or other selective deposition material groups. In one or more embodiments, the third material 212 and the fourth material 214 are deposited by selective reaction or epitaxial deposition. In one or more embodiments, the third material 212 includes silicon germanium (SiGe) and the fourth material 214 includes silicon (Si).

[0087] Referring to Figure 8D The process is repeated and the third material 212 and the fourth material 214 are selectively grown to form the fine pitch active region.

[0088] In one or more embodiments, a combination of non-selective and selective deposition methods are used for three-dimensional pitch multiplication. Figures 9A to 9G A cross-sectional view of a device 300 fabricated using a combination of non-selective and selective deposition methods of one or more embodiments is illustrated. Referring to Figure 9A In one or more embodiments, a memory stack 305 is formed. The memory stack 305 in the illustrated embodiment includes a plurality of alternating first material layers 304 and second material layers 306 on a semiconductor layer 302 on a substrate 301.

[0089] In one or more embodiments, the semiconductor layer 302 is on the substrate 301. In one or more embodiments, the semiconductor layer 302 can also be referred to as a logic interface layer. The semiconductor layer 302 can be formed by any suitable technique known to those skilled in the art.

[0090] An optional sacrificial layer (not shown) can be formed on the semiconductor layer 302 and can be made of any suitable material. In some embodiments, the sacrificial layer is removed and replaced in subsequent processing. In some embodiments, the sacrificial layer is not removed and remains within the electronic device, such as a memory device. In this case, the term "sacrificial" has an extended meaning to include a permanent layer and can be referred to as a conductive layer.

[0091] In one or more embodiments, the first material layers 304 and the second material layers 306 can include any suitable material known to those of skill in the art. In one or more embodiments, the first material layers 304 and the second material layers 306 independently include one or more of silicon (Si), silicon germanium (SiGe), silicon nitride (SiN), and polysilicon. In one or more embodiments, the first material layers 304 and the second material layers 306 are deposited by one or more of plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or epitaxial deposition. This process can be used for any multilayer film stack deposition on any substrate including dielectric layers including but not limited to silicon dioxide (SiO2) and semiconductor substrates including but not limited to silicon (Si) or silicon germanium (SiGe) (e.g., Si / SiGe). In one or more embodiments, the first material layers 304 include silicon (Si) and the second material layers 306 include silicon germanium (SiGe).

[0092] In one or more embodiments, the first material layers 304 and the second material layers 306 can have any suitable thickness. In particular embodiments, the first material layers 304 have a thickness in a range from about 15 nm to about 25 nm, including about 20 nm. In particular embodiments, the second material layers 306 have a thickness in a range from about 35 nm to about 45 nm, including about 40 nm.

[0093] While Figure 9A The memory stack 305 shown has three pairs of alternating first material layers 304 and second material layers 306, but one of skill in the art recognizes that this is for illustrative purposes only. The memory stack 305 can have any number of alternating first material layers 304 and second material layers 306. For example, in some embodiments, the memory stack 305 includes 192 pairs of alternating first material layers 304 and second material layers 306. In other embodiments, the memory stack 305 includes more than 50 pairs of alternating first material layers 304 and second material layers 306, or more than 100 pairs of alternating first material layers 304 and second material layers 306, or more than 300 pairs of alternating first material layers 304 and second material layers 306.

[0094] In one or more embodiments, a hard mask 308 is located on a top surface of the memory stack 305. In one or more embodiments, the hard mask layer 308 can be deposited using one or more mask layer deposition techniques known to those skilled in the art of microelectronic device fabrication. In one or more embodiments, the hard mask layer 308 is deposited using one of a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other deposition techniques known to those skilled in the art. In one or more embodiments, the hard mask layer 308 comprises a material selected from one or more of spin-on carbon, hard mask, or photoresist. Those skilled in the art will appreciate that there can be multiple hard mask layers 308. In one or more embodiments, the hard mask layer 308 comprises silicon nitride (SiN).

[0095] In one or more embodiments, the device 300 is patterned to form active region slit openings 310. The patterning can comprise any suitable patterning technique known to those skilled in the art.

[0096] Referring to Figure 9B The second material layer 306 is recessed through the openings 310. The method of recessing can be wet chemical or vapor etching or reactive vapor etching, as is common to those skilled in the art.

[0097] Referring to Figure 9C A chemical oxide layer 312 is grown around the first material layer 304 and the recessed second material layer 306. The oxide layer 312 can be chemically oxidized or formed by any suitable method known to those skilled in the art. In one or more embodiments, the chemical oxide layer 312 comprises silicon dioxide (SiOx). In one or more embodiments, the thickness of the chemical oxide layer 312 is in a range of about 1 nm to about 5 nm, including about 2 nm, about 3 nm, and about 4 nm. In one or more embodiments, the chemical oxide layer 312 is substantially conformal. As used herein, a "substantially conformal" layer refers to a layer having an overall thickness that is approximately the same. A substantially conformal layer varies in thickness by less than or equal to about 10%, 5%, 2%, or 0.5%.

[0098] Referring to Figure 9D An additional second material layer is deposited to fill the gaps in the layer, and subsequently recessed by wet etching, vapor etching, or reactive gas reaction, to leave a plug 314 of a desired horizontal dimension for memory cell structuring.

[0099] Referring to Figure 9EAn additional chemical oxide layer 312 is grown around the plug 314. The chemical oxide layer 312 can include any suitable material known to those skilled in the art. In one or more embodiments, the chemical oxide layer 312 includes silicon dioxide (SiO2). In one or more embodiments, the thickness of the chemical oxide layer 312 is in a range from about 1 nm to about 5 nm, including about 2 nm, about 3 nm, and about 4 nm. In one or more embodiments, the chemical oxide layer 312 is substantially conformal. As used herein, a "substantially conformal" layer refers to a layer having substantially the same overall thickness. A substantially conformal layer varies in thickness by less than or equal to about 10%, 5%, 2%, or 0.5%.

[0100] Referring to Figure 9F An additional second material layer is deposited to fill the layer, and then recessed to leave the plugs 314a and 314b. An additional chemical oxide layer 312 is grown around the plug 314b. The chemical oxide layer 312 can include any suitable material known to those skilled in the art. In one or more embodiments, the chemical oxide layer 312 includes silicon dioxide (SiOx). In one or more embodiments, the thickness of the chemical oxide layer 312 is in a range from about 1 nm to about 5 nm, including about 2 nm, about 3 nm, and about 4 nm. In one or more embodiments, the chemical oxide layer 312 is substantially conformal. As used herein, a "substantially conformal" layer refers to a layer having substantially the same overall thickness. A substantially conformal layer varies in thickness by less than or equal to about 10%, 5%, 2%, or 0.5%.

[0101] In one or more embodiments, the deposition of a second material layer (e.g., silicon germanium (SiGe)) and a chemical oxide layer 312 is repeated to form a fine pitch active region.

[0102] Referring to Figure 9G A fill material 316 is deposited to fill the opening 310. The fill material can include any suitable fill material known to those skilled in the art. In one or more embodiments, the fill material 316 includes silicon.

[0103] In one or more embodiments, a combined non-selective and selective deposition method is used for three-dimensional pitch multiplication. Figures 10A to 10C A cross-sectional view of a device 400 fabricated using a combined non-selective and selective deposition method of one or more embodiments is shown. Referring to Figure 10A In one or more embodiments, a memory stack 405 is formed. The memory stack 405 in the illustrated embodiment includes a plurality of alternating first material layers 404 and second material layers 406 on the semiconductor layer 402 on the substrate 401.

[0104] In one or more embodiments, the semiconductor layer 402 is located on the substrate 401. In one or more embodiments, the semiconductor layer 402 can also be referred to as a logic interface layer. The semiconductor layer 402 can be formed by any suitable technique known to those skilled in the art.

[0105] An optional sacrificial layer (not shown) can be formed on the semiconductor layer 402 and can be made of any suitable material. In some embodiments, the sacrificial layer is removed and replaced in subsequent processing. In some embodiments, the sacrificial layer is not removed and remains within the electronic device (e.g., memory device). In this case, the term "sacrificial" has an extended meaning to include a permanent layer and can be referred to as a conductive layer.

[0106] In one or more embodiments, the first material layer 404 and the second material layer 406 can include any suitable material known to those skilled in the art. In one or more embodiments, the first material layer 404 and the second material layer 406 independently include one or more of silicon (Si), silicon germanium (SiGe), silicon dioxide (Si02), silicon nitride (SiN), silicon oxynitride (SiON), and polysilicon. In one or more embodiments, the first material layer 404 and the second material layer 406 are deposited by one or more of plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or epitaxial deposition. This process can be used for any multilayer film stack deposition (e.g., Si / SiGe) on any substrate including dielectric layers including, but not limited to, silicon dioxide (Si02) and semiconductor substrates including, but not limited to, silicon (Si) or silicon germanium (SiGe). In one or more embodiments, the first material layer 404 includes silicon (Si) and the second material layer 406 includes silicon germanium (SiGe).

[0107] In one or more embodiments, the first material layer 404 and the second material layer 406 can have any suitable thickness. In particular embodiments, the thickness of the first material layer 404 is in a range from about 15 nm to about 25 nm, including about 20 nm. In particular embodiments, the thickness of the second material layer 406 is in a range from about 25 nm to about 45 nm, including about 30 nm and about 35 nm.

[0108] Although Figure 10AThe illustrated memory stack 405 has three pairs of alternating first material layers 404 and second material layers 406, but one of skill in the art recognizes that this is for illustrative purposes only. The memory stack 405 can have any number of alternating first material layers 404 and second material layers 406. For example, in some embodiments, the memory stack 405 includes 192 pairs of alternating first material layers 404 and second material layers 406. In other embodiments, the memory stack 405 includes more than 50 pairs of alternating first material layers 404 and second material layers 406, or more than 100 pairs of alternating first material layers 404 and second material layers 406, or more than 300 pairs of alternating first material layers 404 and second material layers 406.

[0109] In one or more embodiments, a hard mask 408 is located on a top surface of the memory stack 405. In one or more embodiments, the hard mask layer 408 can be deposited using one or more mask layer deposition techniques known to those skilled in the microelectronics arts. In one or more embodiments, the hard mask layer 408 is deposited using one of a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other deposition techniques known to those skilled in the art. In one or more embodiments, the hard mask layer 408 includes a material selected from one or more of spin-on carbon, hard mask, or photoresist. One of skill in the art will appreciate that there can be multiple hard mask layers 408. In one or more embodiments, the hard mask layer 408 includes silicon nitride (SiN).

[0110] In one or more embodiments, the device 400 is patterned to form active region openings 410. The patterning can include any suitable patterning technique known to those skilled in the art.

[0111] Referring to Figure 10B The second material layers 406 are recessed through the openings 410.

[0112] Referring to Figure 10C A chemical oxide layer 412 is grown around the first material layers 404 and the recessed second material layers 406. The chemical oxide layer 412 can include any suitable material known to those skilled in the art. In one or more embodiments, the chemical oxide layer 412 includes silicon dioxide (SiOx). In one or more embodiments, the chemical oxide layer 412 has a thickness in a range from about 1 nm to about 5 nm, including about 2 nm, about 3 nm, and about 4 nm. In one or more embodiments, the chemical oxide layer 412 is substantially conformal. As used herein, a "substantially conformal" layer refers to a layer having an overall thickness that is approximately the same. A substantially conformal layer varies in thickness by less than or equal to about 10%, 5%, 2%, or 0.5%.

[0113] In one or more embodiments, a non-selective deposition and recessing method is used for three-dimensional pitch multiplication. Figures 11A to 11G A cross-sectional view of a device 500 fabricated using a non-selective deposition and recessing method of one or more embodiments is shown. Reference is made to Figure 11A In one or more embodiments, a memory stack 505 is formed. The memory stack 505 in the illustrated embodiment includes a plurality of alternating first material layers 504 and second material layers 506 on a semiconductor layer 502 on a substrate 501.

[0114] In one or more embodiments, the semiconductor layer 502 is on a substrate 401. In one or more embodiments, the semiconductor layer 502 can also be referred to as a logic interface layer. The semiconductor layer 502 can be formed by any suitable technique known to those skilled in the art.

[0115] An optional sacrificial layer (not shown) can be formed on the semiconductor layer 502 and can be made of any suitable material. In some embodiments, the sacrificial layer is removed and replaced in subsequent processing. In some embodiments, the sacrificial layer is not removed and remains within the electronic device, such as a memory device. In this case, the term "sacrificial" has an extended meaning to include a permanent layer and can be referred to as a conductive layer.

[0116] In one or more embodiments, the first material layers 504 and the second material layers 506 can include any suitable material known to those skilled in the art. In one or more embodiments, the first material layers 504 and the second material layers 406 independently include one or more of silicon (Si), silicon germanium (SiGe), silicon dioxide (Si02), silicon nitride (SiN), silicon oxynitride (SiON), and polysilicon. In one or more embodiments, the first material layers 504 and the second material layers 506 are deposited by one or more of plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or epitaxial deposition. This process can be used for any multi-layer film stack deposition on any substrate including dielectric layers including but not limited to silicon dioxide (Si02) and semiconductor substrates including but not limited to silicon (Si) or silicon germanium (SiGe) (e.g., Si / SiGe). In one or more embodiments, the first material layers 504 include polysilicon and the second material layers 506 include silicon dioxide (Si02).

[0117] In one or more embodiments, the first material layers 504 and the second material layers 506 can have any suitable thickness. In particular embodiments, the thickness of the first material layers 504 is in a range from about 15 nm to about 25 nm, including about 20 nm. In particular embodiments, the thickness of the second material layers 506 is in a range from about 25 nm to about 35 nm, including about 30 nm.

[0118] While Figure 11A The memory stack 505 shown has two pairs of alternating first material layers 504 and second material layers 506, but one of skill in the art recognizes that this is for illustrative purposes only. The memory stack 505 can have any number of alternating first material layers 504 and second material layers 506. For example, in some embodiments, the memory stack 505 includes 192 pairs of alternating first material layers 504 and second material layers 506. In other embodiments, the memory stack 505 includes more than 50 pairs of alternating first material layers 504 and second material layers 506, or more than 100 pairs of alternating first material layers 404 and second material layers 506, or more than 300 pairs of alternating first material layers 404 and second material layers 506.

[0119] Referring to Figure 11B In one or more embodiments, the device 500 is patterned to form active region openings 510. The patterning can include any suitable patterning technique known to those of skill in the art.

[0120] Referring to Figure 11C The second material layers 506 are recessed through the openings 510. The silicon layers 506 can then be recessed using any suitable recessing technique known to those of skill in the art, including but not limited to wet etching, vapor phase etching, isotropic plasma etching, or any other selective removal process (SRP).

[0121] Referring to Figure 11D A fill material 512 is deposited into the openings 510 to fill the openings. The fill material 512 can include any suitable material known to those of skill in the art. In one or more embodiments, the fill material includes phospho silicate glass (PSG), which is 1-10% P2O5 doped silicon dioxide.

[0122] Referring to Figure 11E The fill material 512 is recessed, forming openings 520. As Figure 11F The undoped oxide 514 is deposited and recessed.

[0123] Referring to Figure 11G The fill material 512 and the undoped oxide 514 are alternately deposited and recessed. This can be done as few as 1 time or as many as 8 times or even more to achieve the desired number of alternating films to define the regions of each feature and the spacing between the features, respectively.

[0124] One or more embodiments of the present disclosure relate to semiconductor memory devices. In one embodiment, a semiconductor memory device includes a first memory stack on a first portion of the device including alternating first material layers and second material layers, the first memory stack including first active regions having a first width and a first spacing, a second memory stack on a second portion of the device, the second memory stack including alternating first material layers and second material layers and including second active regions having a second width and a second spacing, and a high aspect ratio opening separating the first portion from the second portion, and a dielectric layer separating the first material layers from the second material layers, repeated to fill recessed gaps, wherein a pitch of the first active regions and the second active regions is in a range from about 50 nm to about 80 nm.

[0125] Additional embodiments of the present disclosure relate to methods of forming electronic devices. In one embodiment, a method of forming an electronic device includes forming a memory stack including alternating layers of first material layers and second material layers, forming an opening in the memory stack, recessing the second material layers to form gaps, growing a third material on the second material in the gaps, conformally depositing a fourth material to fill the gaps and partially recessing the fourth material adjacent the third material to form active regions, repeating the steps to fill recessed gaps, wherein a pitch of the active regions is in a range from about 50 nm to about 100 nm.

[0126] Additional embodiments of the present disclosure relate to a processing tool 900 for forming the described memory devices and methods, as shown in Figure 12

[0127] The cluster tool 900 includes at least one central transfer station 921, 931 having a plurality of sides. Robots 925, 935 are positioned within the central transfer station 921, 931 and are configured to move robot blades and wafers to each of the plurality of sides.

[0128] The cluster tool 900 includes a plurality of processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918 connected to the central transfer station, also referred to as processing stations. Each processing chamber provides a separate processing area isolated from adjacent processing stations. The processing chambers can be any suitable chamber, including but not limited to, a pre-clean chamber, a buffer chamber, a transfer space(s), a wafer orienter / de-gas chamber, a low temperature cooling chamber, a deposition chamber, an anneal chamber, an etch chamber, and a crystallization agent removal chamber. The specific arrangement of processing chambers and components can vary depending on the cluster tool and should not be considered limiting to the scope of the present disclosure.

[0129] ​The deposition chambers of some embodiments include one or more of an atomic layer deposition chamber, a plasma-enhanced atomic layer deposition chamber, a chemical vapor deposition chamber, a plasma-enhanced chemical vapor deposition chamber, or a physical deposition chamber. In some embodiments, the cluster tool 900 includes a pre-clean chamber connected to the central transfer station.

[0130] In Figure 12 In the illustrated embodiment, the factory interface 950 is connected to the front end of the cluster tool 900. The factory interface 950 includes a load chamber 954 and an unload chamber 956 on the front end 951 of the factory interface 950. Although the load chamber 954 is shown on the left and the unload chamber 956 is shown on the right, one skilled in the art will appreciate that this represents only one possible configuration.

[0131] The size and shape of the load chamber 954 and the unload chamber 956 can vary depending, for example, on the substrates being processed in the cluster tool 900. In the illustrated embodiment, the load chamber 954 and the unload chamber 956 are sized to accommodate wafer boxes, with multiple wafers positioned within the boxes.

[0132] A robot 952 is located within the factory interface 950 and can move between the load chamber 954 and the unload chamber 956. The robot 952 is capable of transferring wafers from a box in the load chamber 954 to the load lock chamber 960 via the factory interface 950. The robot 952 is also capable of transferring wafers from the load lock chamber 962 to a box in the unload chamber 956 via the factory interface 950. As one skilled in the art will appreciate, the factory interface 950 can have more than one robot 952. For example, the factory interface 950 can have a first robot that transfers wafers between the load chamber 954 and the load lock chamber 960 and a second robot that transfers wafers between the load lock chamber 962 and the unload chamber 956.

[0133] The illustrated cluster tool 900 has a first portion 920 and a second portion 930. The first portion 920 is connected to the factory interface 950 via the load lock chambers 960, 962. The first portion 920 includes a first transfer chamber 921 in which at least one robot 925 is positioned. The robot 925 is also referred to as a robotic wafer transfer mechanism. The first transfer chamber 921 is centrally located with respect to the load lock chambers 960, 962, the process chambers 902, 904, 916, 918, and the buffer chambers 922, 924. The robot 925 of some embodiments is a multi-armed robot capable of moving more than one wafer independently at a time. In some embodiments, the first transfer chamber 921 contains more than one robotic wafer transfer mechanism. The robot 925 in the first transfer chamber 921 is configured to move wafers between chambers around the first transfer chamber 921. Individual wafers are carried on wafer transfer blades distal from the first robotic mechanism.

[0134] After processing the wafer in the first section 920, the wafer can be transferred to the second section 930 via a transfer chamber. For example, the chambers 922, 924 can be one-way or two-way transfer chambers. The transfer chambers 922, 924 can be used, for example, to cool the wafer down at low temperature before processing the wafer in the second section 930, or to allow for cooling or post processing before the wafer is moved back to the first section 920.

[0135] The system controller 990 is in communication with the first robot 925, the second robot 935, the first plurality of processing chambers 902, 904, 916, 918, and the second plurality of processing chambers 906, 908, 910, 912, 914. The system controller 990 can be any suitable component that can control the processing chambers and robots. For example, the system controller 990 can be a computer including a central processing unit, memory, suitable circuitry, and storage.

[0136] The processes can generally be stored as software routines in the memory of the system controller 990 that, when executed by the processor, cause the processing chambers to perform the processes of the present disclosure. The software routines can also be stored and / or executed by a second processor (not shown) that is located remotely from the hardware being controlled by the processor. Some or all of the methods of the present disclosure can also be performed in hardware. Accordingly, the processes can be implemented in software and executed using a computer system in the form of a hardware (e.g., as a special- purpose application-specific integrated circuit or other type of hardware implementation) or a combination of software and hardware. When executed by the processor, the software routines transform a general-purpose computer into a special-purpose computer (controller) that controls the operation of the chambers to perform processes.

[0137] In some embodiments, the system controller 990 has a configuration that controls the anneal chamber to anneal the wafer at a temperature in a range from about 300 °C to about 700 °C for a time in a range from about 0.1 to about 12 hours. In some embodiments, the controller 990 has a configuration that enables the pre-clean chamber to remove an oxide layer from the wafer.

[0138] As illustrated, spatially relative terms, such as "under", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. For example, if a element is illustrated below another element in the figures, it will be understood that the element can also be oriented above the other element (e.g., flipped over). Likewise, if an element is illustrated to the right of another element then the element can also be oriented to the left of the other element. Thus, the exemplary terms "below" or "under" can encompass both an orientation of above and below. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0139] The use of the terms "a" and "an" and "the" and similar referents in the context of describing the materials and methods discussed herein (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. Recitation of a numerical range using "between," "from," and "to" (e.g., between 1 and 10) should be understood to include the values explicitly recited in the range (e.g., 1, 2, 3, 4, 5, 6, 7, 8, 9, 10) as well as values that are implicitly

[0140] References to "one implementation", "certain implementations", "one or more implementations" or "an implementation" in the present disclosure means that a particular feature, structure, material or characteristic described in connection with the implementation is included in at least one implementation of the disclosure. Thus, the appearances of the phrases "in one or more implementations", "in certain implementations", "in one implementation" or "in an implementation" throughout the specification are not necessarily referring to the same implementation of the disclosure. Furthermore, the particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more implementations.

[0141] While the disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will thus be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatuses of the present disclosure without departing from the spirit and scope of the disclosure. It is therefore intended that the present disclosure include modifications and variations as come within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor memory device, comprising: A first memory stack includes alternating layers of a first material layer and a recessed second material layer on a first portion of the device, the first memory stack including a first active region having a first width and a first spacing; A second memory stack is located on a second portion of the device. The second memory stack includes alternating layers of the first material layer and the recessed second material layer, and includes a second active region having a second width and a second spacing. as well as A high aspect ratio opening that separates the first portion from the second portion; as well as A dielectric layer is formed between the recessed second material layer and an adjacent recessed second material layer, and separates the first material layer from the adjacent material layer. The distance between the first active region and the second active region is in the range of about 50 nm to about 80 nm.

2. The device according to claim 1, wherein the first material layer and the recessed second material layer independently comprise one or more of silicon (Si), silicon germanium (SiGe), silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and polycrystalline silicon.

3. The device of claim 1, wherein the first material layer comprises silicon (Si) and the recessed second material layer comprises silicon germanium (SiGe).

4. The device of claim 1, wherein the first material layer comprises silicon dioxide (SiO2) and the recessed second material layer comprises polycrystalline silicon.

5. The device of claim 1, wherein the dielectric layer comprises one or more of oxide, carbon-doped oxide, silicon nitride (SiN), silicon dioxide / silicon nitride, carbide, nitride, polymer, phosphosilicate glass, fluorosilicate (SiOF) glass or organosilicon glass (SiOCH).

6. The device of claim 5, wherein the oxide comprises silicon dioxide (SiO2) or porous silicon dioxide (SiO2).

7. The device of claim 5, wherein the carbide comprises an oxycarbide.

8. The device of claim 5, wherein the nitride comprises an oxynitride or an oxycarbonitride.

9. The device of claim 1, wherein the high aspect ratio opening has a width in the range of about 100 nm to about 160 nm.

10. The device of claim 1, wherein the first width and the second width are independently in the range of about 20 nm to about 40 nm.

11. The device of claim 1, wherein the first spacing and the second spacing are independently in the range of about 20 nm to about 40 nm.

12. A method of forming an electronic device, the method comprising the steps of: A memory stack comprising alternating layers of a first material layer and a second material layer is formed; An opening is formed in the memory stack; The second material layer is recessed to form a gap and a recessed second material layer; A third material is grown in the gap; A fourth material is grown adjacent to the third material in the gap, and The third material and the fourth material are repeatedly grown to form active regions comprising multiple pairs of the third and fourth materials in the gap, thereby forming an active region. The spacing of the active regions is in the range of about 50 nm to about 100 nm.

13. The method of claim 12, wherein the first material layer and the second material layer independently comprise one or more of silicon (Si), silicon germanium (SiGe), silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and polycrystalline silicon.

14. The method of claim 12, wherein the first material layer comprises silicon (Si) and the second material layer comprises silicon germanium (SiGe).

15. The method of claim 12, wherein the first material layer comprises silicon dioxide (SiO2) and the second material layer comprises polycrystalline silicon.

16. The method of claim 12, wherein the opening has a width in the range of about 100 nm to about 160 nm.

17. The method of claim 12, wherein the active region has a width in the range of about 20 nm to about 40 nm.

18. The method of claim 12, wherein the active regions have an interval in the range of about 20 nm to about 40 nm.

19. The method of claim 12, further comprising: depositing a conformal oxide layer on the recessed second material layer.

20. The method of claim 12, further comprising: depositing a filler material in the opening.

21. The method of claim 20, wherein the filler material comprises silicon.

22. A non-transitory computer-readable medium comprising instructions that, when executed by a controller of a processing system, cause the processing system to perform the following operations: A memory stack comprising alternating layers of a first material layer and a second material layer is formed; An opening is formed in the memory stack; The second material layer is recessed to form a gap and a recessed second material layer; A third material is grown in the gap; A fourth material is grown adjacent to the third material in the gap, and The third material and the fourth material are repeatedly grown to form active regions comprising multiple pairs of the third and fourth materials in the gap, thereby forming an active region. The spacing of the active regions is in the range of about 50 nm to about 100 nm.

23. The non-transitory computer-readable medium of claim 22, further comprising instructions that, when executed by a controller of the processing system, cause the processing system to perform the following operations: A conformal oxide layer is deposited on the recessed second material layer.

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