Power supply control device

Abstract

Regarding the N-channel FET (20) of the power supply control device (10), the drain of the input current and the source of the output current are configured in the current path of the current flowing from the DC power supply (11) to the load (12). When the first determination circuit (24) determines that the control voltage between the gate and the source of the FET (20) is above a first threshold and the second determination circuit (25) determines that the voltage between the drain and the source of the FET (20) is above a second threshold, the drive circuit (22) switches the FET (20) to off.

Description

Technical Field

[0001] This disclosure relates to power supply control devices.

[0002] This application claims priority based on Japanese Application No. 2020-084667, filed on May 13, 2020, and invokes all the contents of that Japanese application. Background Technology

[0003] Patent Document 1 describes a power supply control device for a vehicle that controls the supply of power from a DC power source to a load. In this power supply control device, the drain and source of an N-channel FET (Field Effect Transistor), which functions as a semiconductor switch, are arranged in the current path of the current flowing from the DC power source to the load. The drain is positioned upstream of the source in the current path. The supply of power from the DC power source to the load is controlled by switching the FET on or off.

[0004] When a FET is turned on, the voltage between its drain and source is represented by the product of the resistance between the drain and source and the current flowing through the FET. When the FET is turned on, if the voltage between its drain and source is above a specified voltage, the current flowing through the FET is large, causing the FET to switch off. This prevents overcurrent from flowing through the FET.

[0005] When a FET is switched from off to on, the voltage across the FET's gate, referenced to ground, increases. Consequently, the voltage between the gate and source increases, and the resistance between the drain and source decreases to a sufficiently small value. As a result, the FET switches on. During the transition from off to on, the resistance between the drain and source is high. Therefore, even though the current flowing through the FET is small during this transition, the voltage between the drain and source may still exceed a specified voltage. To prevent erroneous switching of the FET to off, the FET is not reverted to off during the transition from off to on, and the voltage between the gate and source continues to rise.

[0006] Prior art literature

[0007] Patent documents

[0008] Patent Document 1: Japanese Patent Application Publication No. 2006-229864 Summary of the Invention

[0009] One aspect of the power supply control device disclosed herein includes: an N-channel FET, wherein the drain is positioned upstream of the source in a current path from a DC power supply to a load; a first determination circuit that determines whether a control voltage between the gate and source of the FET is greater than or equal to a first threshold; a second determination circuit that determines whether a voltage across the drain and source of the FET is greater than or equal to a second threshold; and a switching circuit that switches the FET to off when the first determination circuit determines that the control voltage is greater than or equal to the first threshold and the second determination circuit determines that the voltage across the drain and source is greater than or equal to the second threshold. Attached Figure Description

[0010] Figure 1 This is a block diagram showing the main structural components of the power supply system in Implementation 1.

[0011] Figure 2 This is the first timeline showing the operation of the power supply control device.

[0012] Figure 3 This is the second example of a timeline showing the operation of a power supply control device.

[0013] Figure 4 This is the third example of a timeline showing the operation of a power supply control device.

[0014] Figure 5 This is the circuit diagram of the first decision circuit.

[0015] Figure 6 This is the circuit diagram of the second decision circuit.

[0016] Figure 7 This is a circuit diagram of the second determination circuit in Implementation Method 2. Detailed Implementation

[0017] [The problem this disclosure aims to solve]

[0018] During the transition period when the FET switches from off to on, current flows through the FET. In the power supply control device described in Patent Document 1, for example, when the FET switches from off to on with the load short-circuited, overcurrent continues to flow during the transition period. As a result, there is a possibility that the temperature of the FET will rise to an abnormal temperature and cause a failure in the FET.

[0019] Therefore, the objective is to provide a power supply control device that returns the FET to a de-energized state during the transition from switching the FET off to switching it on, provided that a large current flows through the FET.

[0020] [The Effects of This Disclosure]

[0021] According to this disclosure, during the transition period when the FET switches from off to on, if a large current flows through the FET, the FET is returned to off.

[0022] [Description of embodiments of this disclosure]

[0023] First, embodiments of this disclosure will be described. At least some of the embodiments described below may be combined arbitrarily.

[0024] (1) One aspect of the power supply control device disclosed herein includes: an N-channel FET, wherein the drain is disposed upstream of the source in a current path of current flowing from a DC power supply to a load; a first determination circuit that determines whether a control voltage between the gate and the source of the FET is greater than or equal to a first threshold; a second determination circuit that determines whether a voltage across the drain and the source of the FET is greater than or equal to a second threshold; and a switching circuit that switches the FET to off when the first determination circuit determines that the control voltage is greater than or equal to the first threshold and the second determination circuit determines that the voltage across the drain and the source is greater than or equal to the second threshold.

[0025] In the above configuration, the voltage between the gate and source of the FET is the control voltage. The voltage between the drain and source of the FET is the terminal voltage. When the FET is switched from off to on, the control voltage rises. In the absence of a fault, as the control voltage rises, the resistance between the drain and source of the FET decreases, thus causing the terminal voltage to decrease.

[0026] The first and second thresholds are set in a manner that satisfies the following conditions: In the absence of a fault, when the FET is off, the control voltage is less than the first threshold and the voltage across the terminals is greater than the second threshold. When the control voltage rises, while the control voltage is less than the first threshold, the voltage across the terminals drops to a level less than the second threshold. When the first and second thresholds are set in a manner that satisfies these conditions, a state where the control voltage is greater than the first threshold and the voltage across the terminals is greater than the second threshold will not exist unless a fault occurs.

[0027] During the transition from FET to FET, when a large current flows through the FET, it is possible to achieve a state where the control voltage is above a first threshold and the voltage across the terminals is above a second threshold, and the FET returns to FET.

[0028] (2) In one embodiment of the power supply control device of this disclosure, the first threshold exceeds the control voltage at the point in time when current begins to flow through the drain and source of the FET when the control voltage is increased, and the second threshold is greater than 0V and less than the voltage of the DC power supply.

[0029] In the above configuration, the control voltage between the gate and source of the FET is increased by increasing the voltage of the gate, which has a reference potential of, for example, ground. Assuming no fault occurs, in this case, current begins to flow through the drain and source of the FET. Then, before the voltage across the terminals drops from the DC power supply voltage to near 0V, the control voltage is maintained at the voltage at the point when current begins to flow. A first threshold exceeds the control voltage at the point when current begins to flow through the drain and source of the FET; therefore, in the absence of a fault, the voltage across the terminals reliably drops to a voltage below a second threshold while the control voltage is below the first threshold.

[0030] (3) In one embodiment of the power supply control device disclosed herein, the first determination circuit includes: an amplifier for amplifying the control voltage; and a comparator for comparing the voltage amplified by the amplifier with a predetermined voltage, wherein the predetermined voltage is set as the product of the first threshold and the amplification rate of the amplifier.

[0031] In the above configuration, an amplifier is used to generate a voltage proportional to the control voltage, and the generated voltage is compared with a predetermined voltage. This allows for a comparison between the control voltage and a first threshold voltage.

[0032] (4) In one embodiment of the power supply control device of this disclosure, the second determination circuit includes: a first resistor disposed in a second current path in which current flows, and one end of the upstream side of the first resistor is connected to the drain of the FET; an adjuster that adjusts the voltage at one end of the downstream side of the first resistor to the voltage of the source of the FET; a second resistor disposed in the second current path downstream of the first resistor; and a second comparator that compares the voltage between the two ends of the second resistor with a second predetermined voltage, the second predetermined voltage being a value obtained by dividing the product of the second threshold and the resistance value of the second resistor by the resistance value of the first resistor.

[0033] In the above configuration, since the voltage at one downstream end of the first resistor is adjusted to the source voltage of the FET, the voltage across the second resistor is proportional to the voltage between the drain and source of the FET. The voltage across the second resistor is then compared to a second predetermined voltage. This allows for a comparison between the voltage across the resistor and a second threshold.

[0034] (5) In one embodiment of the power supply control device disclosed herein, the second determination circuit includes: a second amplifier for amplifying the voltage at both ends; and a third comparator for comparing the voltage amplified by the second amplifier with a third predetermined voltage, wherein the third predetermined voltage is set as the product of the second threshold and the amplification rate of the second amplifier.

[0035] In the above configuration, a second amplifier is used to generate a voltage proportional to the voltage across the terminals, and the generated voltage is compared with a third predetermined voltage. This allows for a comparison between the voltage across the terminals and a second threshold.

[0036] [Details of the embodiments of this disclosure]

[0037] Hereinafter, specific examples of power supply systems according to embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that the present invention is not limited to these examples, but is disclosed in the claims and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0038] (Implementation Method 1)

[0039] <Structure of Power Supply System>

[0040] Figure 1 This is a block diagram showing the main structural components of the power system 1 in Embodiment 1. The power system 1 is suitable for installation in a vehicle and includes a power supply control device 10, a DC power supply 11, and a load 12. The power supply control device 10 has an N-channel FET 20 that functions as a semiconductor switch. A first capacitor C1 is connected between the drain and gate of the FET 20. A second capacitor C2 is connected between the source and gate of the FET 20. The first capacitor C1 and the second capacitor C2 are parasitic capacitances of the FET 20. The DC power supply 11 is, for example, a battery. The load 12 is an electrical device installed in the vehicle.

[0041] When FET20 is turned on, the resistance between the drain and source of FET20 is sufficiently small, and current may flow through the drain and source of FET20. When FET20 is turned off, the resistance between the drain and source of FET20 is sufficiently large, and current will not flow through FET20.

[0042] The drain and source of FET20 are connected to the positive terminal of DC power supply 11 and one end of load 12, respectively. The negative terminal of DC power supply 11 and the other end of load 12 are grounded. In the power supply control device 10, the power supply from DC power supply 11 to load 12 is controlled by switching FET20 on or off.

[0043] When FET20 is turned on, current flows from the positive terminal of DC power supply 11 to the load 12 via FET20. Thus, power is supplied from DC power supply 11 to load 12, and load 12 operates. When current flows through FET20, it flows in the order of drain and source. Therefore, the drain and source of FET20 are positioned in the current path of the current flowing from DC power supply 11 to load 12, with the drain positioned upstream of the source.

[0044] When FET20 is off, current will not flow through FET20. When FET20 switches from on to off, the power supply to load 12 stops, and load 12 stops operating.

[0045] <Structure of Power Supply Control Device 10>

[0046] In addition to FET 20, the power supply control device 10 also includes device resistor 21, drive circuit 22, microcomputer (hereinafter referred to as microcomputer) 23, first determination circuit 24, second determination circuit 25, and OR circuit 26. Drive circuit 22 has a first input terminal, a second input terminal, an output terminal, and a ground terminal. OR circuit 26 has a first input terminal, a second input terminal, and an output terminal.

[0047] The gate of FET 20 is also connected to one end of device resistor 21. The other end of device resistor 21 is connected to the output of drive circuit 22. The first input of drive circuit 22 is connected to microcomputer 23. The gate and source of FET 20 are respectively connected to first determination circuit 24. First determination circuit 24 is also connected to the first input of OR circuit 26. The drain and source of FET 20 are respectively connected to second determination circuit 25. Second determination circuit 25 is also connected to the second input of OR circuit 26. The output of OR circuit 26 is connected to the second input of drive circuit 22. The ground terminal of drive circuit 22 is grounded.

[0048] FET20 is an N-channel type; therefore, for FET20, as the voltage between the gate and source increases, the resistance between the drain and source decreases. Hereinafter, the voltage between the gate and source of FET20 will be described as the control voltage. When the control voltage is less than the turn-off voltage, FET20 is off. The turn-off voltage exceeds 0V. When the control voltage is greater than or equal to the turn-on voltage, FET20 is on. The turn-on voltage exceeds the turn-off voltage. When the control voltage is greater than the turn-off voltage but less than the turn-on voltage, current may flow through the drain and source of FET20. However, the resistance between the drain and source of FET20 is high.

[0049] The drive circuit 22 switches FET 20 on or off by adjusting the voltage at its output terminal, which has a reference potential of ground. When FET 20 is off, the drive circuit 22 adjusts the voltage at its output terminal to 0V. Therefore, the first capacitor C1 is charged by the DC power supply 11, and the voltage between the two terminals of the first capacitor C1 is the same as the voltage between the two terminals of the DC power supply 11. At this time, the voltage at the drain of the capacitor with a reference potential of ground exceeds the voltage at the gate of the capacitor with a reference potential of ground. Moreover, when FET 20 is off, the voltage between the two terminals of the second capacitor C2, i.e., the control voltage, is 0V.

[0050] It should be noted that the "consistency" between the voltage across the first capacitor C1 and the voltage across the DC power supply 11 does not refer to strict consistency. As long as substantial consistency can be achieved, there is no problem.

[0051] Hereinafter, the voltage between the two terminals of the DC power supply 11 will be recorded as the power supply voltage. The voltage of the gate, whose reference potential is ground, will be recorded as the gate voltage. The voltage of the drain, whose reference potential is ground, will be recorded as the drain voltage. The voltage of the source, whose reference potential is ground, will be recorded as the source voltage.

[0052] When the drive circuit 22 switches the FET 20 from off to on, it raises the output voltage to a target voltage. The target voltage is higher than the supply voltage. The difference between the target voltage and the supply voltage is greater than the on-state voltage. When the drive circuit 22 raises the output voltage, current flows from the output of the drive circuit 22 in sequence through the device resistor 21 and the second capacitor C2, charging the second capacitor C2. As a result, the voltage across the second capacitor C2, i.e., the control voltage, increases.

[0053] Furthermore, when the second capacitor C2 is charged, the gate voltage also rises. As the gate voltage rises, the voltage across the first capacitor C1 decreases. When the gate voltage exceeds the supply voltage, the first capacitor C1, in addition to the second capacitor C2, is also charged. At this time, the gate voltage exceeds the drain voltage. When the control voltage becomes a voltage above the turn-on voltage, FET20 switches to turn-on.

[0054] When the drive circuit 22 switches FET 20 off, the output voltage drops to 0V. As a result, current flows from the first capacitor C1 and the second capacitor C2 in the order of the device resistor 21 and the drive circuit 22, causing both capacitors to discharge. With the second capacitor C2 discharging, the voltage across it, i.e., the control voltage, decreases.

[0055] When the control voltage becomes lower than the off-voltage, FET20 switches off. Regarding the first capacitor C1, after discharge, current flows from the positive terminal of the DC power supply 11 in the order of the first capacitor C1, device resistor 21, and drive circuit 22, charging the first capacitor C1. Charging of the first capacitor C1 ends when the voltage across its terminals becomes the power supply voltage.

[0056] As described above, the drive circuit 22 switches FET 20 to be on or off.

[0057] The microprocessor 23 and / or circuit 26 output voltages to the drive circuit 22. The reference potential of the output voltage of each of the microprocessor 23 and / or circuit 26 is ground potential. The microprocessor 23 and / or circuit 26 switch the output voltage to a high-level voltage or a low-level voltage, respectively.

[0058] When the output voltage of OR circuit 26 is high, and microprocessor 23 switches the output voltage from low to high, drive circuit 22 turns FET 20 on. When microprocessor 23 switches the output voltage from high to low, drive circuit 22 turns FET 20 off, regardless of the output voltage of OR circuit 26. When OR circuit 26 switches the output voltage from high to low, drive circuit 22 turns FET 20 off, regardless of the output voltage of microprocessor 23. Then, drive circuit 22 maintains FET 20 off.

[0059] The first determination circuit 24 and the second determination circuit 25 each output voltage to the OR circuit 26. The reference potential of the output voltage of the first determination circuit 24 and the second determination circuit 25 is the ground potential. The output voltage of the first determination circuit 24 and the second determination circuit 25 is either a high-level voltage or a low-level voltage.

[0060] The first determination circuit 24 determines whether the voltage between the gate and source of the FET 20, i.e., whether the control voltage is above a certain first threshold. If the first determination circuit 24 determines that the control voltage is below the first threshold, it outputs a high-level voltage to the OR circuit 26. If the first determination circuit 24 determines that the control voltage is above the first threshold, it outputs a low-level voltage to the OR circuit 26. The second determination circuit 25 determines whether the voltage between the drain and source of the FET 20, i.e., whether the voltage across it is above a certain second threshold. If the second determination circuit 25 determines that the voltage across it is below the second threshold, it outputs a high-level voltage to the OR circuit 26. If the second determination circuit 25 determines that the voltage across it is above the second threshold, it outputs a low-level voltage to the OR circuit 26.

[0061] Alternatively, circuit 26 may output a high-level voltage if at least one of the output voltages of the first determination circuit 24 and the second determination circuit 25 is a high-level voltage. Or, circuit 26 may output a low-level voltage if both the output voltages of the first determination circuit 24 and the second determination circuit 25 are low-level voltages.

[0062] <First example of the operation of power supply control device 10>

[0063] Figure 2 This is a timing diagram showing the first example of the operation of the power supply control device 10. Figure 2The diagram illustrates the operation of the power supply control device 10 when no fault occurs in the power supply system 1. Vg, Vs, and Vd represent the gate voltage, source voltage, and drain voltage, respectively. Vb and Vp represent the power supply voltage and target voltage of the DC power supply 11, respectively. Vgs and Vds represent the control voltage and the voltage across the terminals, respectively. Vn and Vf represent the turn-on voltage and turn-off voltage, respectively. Vth1 and Vth2 represent the first threshold and the second threshold, respectively.

[0064] exist Figure 2 In the first section, the shifts in gate voltage Vg, source voltage Vs, and drain voltage Vd are represented by thick solid lines, thin solid lines, and thick dashed lines, respectively. The second section shows the shift in control voltage Vgs. The third section shows the shift in the voltage Vds across the terminals. The fourth section shows the shift in the output voltage of the first determination circuit 24. The fifth section shows the shift in the output voltage of the second determination circuit 25. The horizontal axis representing these shifts represents time.

[0065] The drain of FET20 is directly connected to the positive terminal of DC power supply 11, therefore the drain voltage Vd is fixed to the power supply voltage Vb. As mentioned earlier, the drive circuit 22 maintains the output voltage at 0V, thereby keeping FET20 off. When the output voltage of drive circuit 22 is 0V, the second capacitor C2 discharges. When the discharge of the second capacitor C2 is complete, the control voltage Vgs is 0V, and the gate voltage Vg and source voltage Vs are the same.

[0066] With the control voltage at 0V, FET20 is off, so no current flows through load 12. Therefore, the gate voltage Vg and source voltage Vs are both 0V. The drain voltage Vd is fixed at the supply voltage Vb, so the voltage across it remains at the supply voltage Vb while the source voltage Vs is 0V.

[0067] As previously described, when the drive circuit 22 switches FET 20 to the ON position, it causes the output voltage to rise. This charges the first capacitor C1 and the second capacitor C2. The gate voltage Vg rises along with the voltage across the second capacitor C2. While the gate voltage Vg is lower than the off-state voltage Vf, FET 20 is ON, and the source voltage Vs remains at 0V. Therefore, when the gate voltage Vg rises, the control voltage Vgs also rises.

[0068] When the control voltage Vgs becomes the off-state voltage Vf, current flows through FET20 and load 12. When the control voltage Vgs rises, the off-state voltage Vf is the control voltage Vgs at the point when current begins to flow through the drain and source of FET20. When current flows through FET20 and load 12, the source voltage Vs rises. Therefore, the control voltage Vgs becomes a voltage less than the off-state voltage Vf, and FET20 switches off. When FET20 switches off, the source voltage Vs drops to 0V, therefore, the control voltage Vgs again becomes a voltage greater than the off-state voltage Vf, and current flows through FET20. Thus, the flow of current through FET20 alternates with the switching of FET20 to off. The descriptions of the decrease in source voltage Vs to 0V and the increase in control voltage Vgs are described in... Figure 2 Omitted in .

[0069] During the alternation of current flow through FET20 and switching FET20 off, the gate voltage Vg continuously rises, and the control voltage Vgs at the time FET20 switches off rises over time. The higher the control voltage Vgs, the smaller the resistance between the drain and source of FET20, and the larger the current flowing through FET20 and load 12. Therefore, the source voltage Vs at the time FET20 switches off rises over time. As a result, the source voltage Vs rises with the increase of the gate voltage Vg until it becomes a voltage near the supply voltage Vb. During the period when the source voltage Vs becomes a voltage near the supply voltage Vb, the control voltage Vgs remains at the off voltage Vf. As mentioned earlier, the drain voltage Vd is fixed at the supply voltage Vb; therefore, as the source voltage Vs rises, the voltage Vds across FET20 decreases.

[0070] After the source voltage Vs becomes near the supply voltage Vb, the control voltage Vgs will not be less than the off-voltage Vf due to the current flowing through FET20 and load 12. Therefore, current continues to flow through FET20 and load 12. After the source voltage Vs becomes near the supply voltage Vb, the source voltage Vs varies according to the magnitude of the current flowing through FET20. However, because its variation is small, the source voltage Vs remains near the supply voltage Vb. The voltage Vds across the terminals also varies according to the magnitude of the current flowing through FET20. However, because its variation is also small, the voltage Vds across the terminals remains near 0V.

[0071] After the source voltage Vs becomes close to the power supply voltage Vb, the control voltage Vgs also rises as the gate voltage Vg rises. When the control voltage Vgs becomes higher than the turn-on voltage Vn, FET 20 switches on. Then, the gate voltage Vg rises to the target voltage Vp. Before the gate voltage Vg reaches the target voltage Vp, the control voltage Vgs also rises. After the gate voltage Vg reaches the target voltage Vp, the drive circuit 22 maintains the gate voltage Vg at the target voltage Vp. While the gate voltage Vg is at the target voltage Vp, the control voltage Vgs is also maintained at a constant voltage.

[0072] As previously described, when the drive circuit 22 switches FET 20 off, the output voltage drops to 0V. This causes the first capacitor C1 and the second capacitor C2 to discharge. As the voltage across the second capacitor C2 decreases, the gate voltage Vg decreases. Along with the decrease in gate voltage Vg, the control voltage Vgs also decreases. Even after the control voltage Vgs becomes lower than the turn-on voltage Vn, current continues to flow through FET 20.

[0073] When the control voltage Vgs becomes lower than the off-state voltage Vf, FET20 switches to off. Since the current flow through load 12 stops, the source voltage Vs drops to 0V. Consequently, the control voltage Vgs becomes higher than the off-state voltage Vf, and current flow through FET20 begins. When current flows through FET20, the source voltage Vs rises, and the control voltage Vgs again becomes lower than the off-state voltage Vf, stopping the current flow through FET20. Thus, the switching of FET20 to off and the current flow through FET20 alternate. The descriptions of the decrease in the source voltage Vs to 0V and the increase in the control voltage Vgs are described in... Figure 2 Omitted in .

[0074] During the alternation of switching FET20 to off and the flow of current through FET20, the gate voltage Vg continuously decreases, and the control voltage Vgs at the point when FET20 switches to off decreases over time. The lower the control voltage Vgs, the greater the resistance between the drain and source of FET20, and the smaller the current flowing through FET20 and load 12. Therefore, the source voltage Vs at the point when current flows through FET20 decreases over time. As a result, the source voltage Vs decreases as the gate voltage Vg decreases before reaching 0V. During the period until the source voltage Vs reaches 0V, the control voltage Vgs remains at the off voltage Vf. As mentioned earlier, the drain voltage Vd is fixed at the supply voltage Vb, so the voltage Vds across FET20 increases as the source voltage Vs decreases.

[0075] After the source voltage Vs reaches 0V, FET 20 remains off, and the control voltage Vgs decreases as the gate voltage Vg decreases. Then, the gate voltage Vg drops to 0V. After the source voltage Vs reaches 0V, it is fixed at 0V, so the control voltage Vgs decreases before the gate voltage Vg reaches 0V. After the gate voltage Vg reaches 0V, the drive circuit 22 maintains the gate voltage Vg at 0V. During the period when the gate voltage Vg is 0V, the control voltage Vgs also remains at 0V.

[0076] When the source voltage Vs becomes 0V, the voltage Vds across FET20 becomes the supply voltage Vb. Then, until the control voltage Vgs becomes a voltage higher than the off voltage Vf, the voltage Vds across FET20 remains at the supply voltage Vb.

[0077] The first threshold Vth1 exceeds the off-voltage Vf. The first threshold Vth1 is then below the control voltage Vgs when the gate voltage Vg is the target voltage Vp. Figure 2 The example described is one where the first threshold Vth1 is less than the turn-on voltage Vn. However, the first threshold Vth1 can also be greater than the turn-on voltage Vn.

[0078] The second threshold Vth2 is the voltage Vds across the gate when the gate voltage Vg is the target voltage Vp, which is greater than or equal to the power supply voltage Vb. The voltage Vds across the gate when the gate voltage Vg is the target voltage Vp is greater than or equal to 0V.

[0079] As described above, a first threshold Vth1 and a second threshold Vth2 are set. Therefore, in the absence of a fault in the power supply system 1, when FET 20 is off, the control voltage Vgs is less than the first threshold Vth1, and the voltage Vds across it is greater than the second threshold Vth2. When FET 20 is switched from off to on, during the period when the control voltage Vgs is less than the first threshold Vth1, the voltage Vds across it reliably drops from the power supply voltage Vb to a voltage less than the second threshold Vth2. When the voltage Vds across it is less than the second threshold Vth2, the control voltage Vgs becomes a voltage greater than the first threshold Vth1. As a result, during the transition period when FET 20 is switched from off to on, the state where the control voltage Vgs is less than the first threshold Vth1 and the voltage Vds across it is less than the second threshold Vth2 is not achieved.

[0080] Therefore, when FET20 is switched from off to on, while the output voltage of the first determination circuit 24 is at a high level, the second determination circuit 25 switches its output voltage from a low level to a high level. Conversely, when the output voltage of the second determination circuit 25 is at a high level, the first determination circuit 24 switches its output voltage from a high level to a low level. As a result, the state where the output voltages of both the first determination circuit 24 and the second determination circuit 25 are at a low level is not achieved.

[0081] Similarly, when FET20 is switched from on to off, after the control voltage Vgs becomes less than the first threshold Vth1, the voltage Vds across it changes from less than the second threshold Vth2 to more than the second threshold Vth2. As a result, during the transition from FET20 on to off, the state where the control voltage Vgs is less than the first threshold Vth1 and the voltage Vds across it is less than the second threshold Vth2 is not achieved.

[0082] Therefore, when FET20 is switched from off to on, after the first determination circuit 24 switches the output voltage from a low level to a high level, the second determination circuit 25 switches the output voltage from a high level to a low level. As a result, the state where the output voltages of the first determination circuit 24 and the second determination circuit 25 are both low-level is not achieved.

[0083] Based on the above, assuming no fault occurs in power supply system 1, at least one of the output voltages of the first determination circuit 24 and the second determination circuit 25 is a high-level voltage, therefore, circuit 26 continues to output a high-level voltage. When the microcomputer 23 switches the output voltage to a high-level voltage, drive circuit 22 switches FET 20 to the ON position. When the microcomputer 23 switches the output voltage to a low-level voltage, drive circuit 22 switches FET 20 to the OFF position.

[0084] <Second example of the operation of power supply control device 10>

[0085] Figure 3 This is a timing diagram representing the second example of the operation of the power supply control device 10. Figure 3 The diagram shows the operation of the power supply control device 10 when the two ends of the load 12 are short-circuited during the disconnection of FET20.

[0086] exist Figure 3In the first paragraph, the shifts in gate voltage Vg, source voltage Vs, and drain voltage Vd are represented by thick solid lines, thin solid lines, and thick dashed lines, respectively. The second paragraph shows the shift in control voltage Vgs. The third paragraph shows the shift in the voltage Vds across the terminals. The fourth paragraph shows the shift in the output voltage of the first determination circuit 24. The fifth paragraph shows the shift in the output voltage of the second determination circuit 25. The horizontal axis representing these shifts represents time.

[0087] As previously stated, the drain of FET20 is directly connected to the positive terminal of DC power supply 11, therefore the drain voltage Vd is fixed to the power supply voltage Vb. The drive circuit 22 keeps FET20 off by maintaining the output voltage at 0V. When the second capacitor C2 finishes discharging, the gate voltage Vg, source voltage Vs, and control voltage Vgs are all 0V. During the off-state of FET20, it is assumed that the load 12 is short-circuited. In this case, the current flowing through FET20 is large during the transition period from off to on.

[0088] Because the load 12 is short-circuited, the source voltage Vs is fixed at 0V. Therefore, the voltage between the drain and source of FET 20, i.e., the voltage Vds across its terminals, is fixed at the supply voltage Vb. As mentioned earlier, the second threshold Vth2 is less than the supply voltage Vb. Therefore, during the short circuit period across the load 12, the output voltage of the second determination circuit 25 is fixed at a low level and does not switch to a high level.

[0089] As previously described, when the drive circuit 22 switches FET 20 to the ON position, it causes the output voltage to rise. This charges the first capacitor C1 and the second capacitor C2. The gate voltage Vg rises along with the voltage across the second capacitor C2. Since the source voltage Vs is fixed at 0V, the shift in the control voltage Vgs coincides with the shift in the gate voltage Vg. When the control voltage Vgs becomes a voltage above the OFF voltage Vf, current flows through FET 20.

[0090] Because the load 12 is short-circuited, the current flowing through the FET 20 increases as the resistance between the drain and source of the FET 20 decreases, i.e., the control voltage Vgs increases. When the control voltage Vgs becomes higher than the first threshold voltage Vth1, and the second determination circuit 25 outputs a low-level voltage, the first determination circuit 24 switches the output voltage from a high-level voltage to a low-level voltage. Here, the first determination circuit 24 and the second determination circuit 25 detect a large current flowing through the FET 20.

[0091] When the second determination circuit 25 outputs a low-level voltage, and the first determination circuit 24 switches the output voltage from a high-level voltage to a low-level voltage, or the OR circuit 26 switches the output voltage from a high-level voltage to a low-level voltage. When the output voltage of the OR circuit 26 switches from a high-level voltage to a low-level voltage, as described above, the drive circuit 22 switches FET 20 to off independently of the output voltage of the microcomputer 23, maintaining FET 20 off. Specifically, the drive circuit 22 causes the output voltage to drop to 0V, maintaining the output voltage at 0V. The drive circuit 22 functions as a switching circuit.

[0092] Therefore, when the control voltage Vgs becomes a voltage above the first threshold Vth1, the drive circuit 22 causes the output voltage to drop to 0V, thus decreasing the gate voltage Vg and the control voltage Vgs. When the control voltage Vgs becomes a voltage below the first threshold Vth1, the first determination circuit 24 switches the output voltage from a low level to a high level, or the circuit 26 switches the output voltage from a low level to a high level. However, the drive circuit 22 continues to cause the output voltage to drop. When the control voltage Vgs becomes a voltage below the off-state voltage Vf, FET 20 switches off. Then, the gate voltage Vg and the control voltage Vgs drop to 0V and remain at 0V.

[0093] As described above, in the power supply control device 10, if a large current flows through the FET20 during the transition period when the FET20 switches from off to on, the drive circuit 22 causes the FET20 to return to off. This prevents overcurrent from flowing through the FET20.

[0094] <Third example of the operation of power supply control device 10>

[0095] Figure 4 This is a timing diagram representing the third example of the operation of the power supply control device 10. In Figure 4 The diagram shows the operation of the power supply control device 10 when the two ends of the load 12 are short-circuited during the period when the FET 20 is turned on.

[0096] exist Figure 4 In the first paragraph, the shifts in gate voltage Vg, source voltage Vs, and drain voltage Vd are represented by thick solid lines, thin solid lines, and thick dashed lines, respectively. The second paragraph shows the shift in control voltage Vgs. The third paragraph shows the shift in the voltage Vds across the terminals. The fourth paragraph shows the shift in the output voltage of the first determination circuit 24. The fifth paragraph shows the shift in the output voltage of the second determination circuit 25. The horizontal axis representing these shifts represents time.

[0097] When FET20 is turned on, as previously stated, the control voltage Vgs is above the first threshold Vth1, and the voltage Vds across it is less than the second threshold Vth2. During the period when FET20 is turned on, the load 12 is short-circuited, assuming that the current flowing through FET20 increases. In this case, the source voltage Vs drops from the voltage near the supply voltage Vb to 0V. As a result, the control voltage Vgs rises, and the voltage Vds across it rises to the supply voltage Vb. As previously stated, the second threshold Vth2 is less than the supply voltage Vb. Therefore, when the load 12 is short-circuited, with the control voltage Vgs above the first threshold Vth1, the voltage Vds across it becomes a voltage above the second threshold Vth2.

[0098] At this time, with the output voltage of the second determination circuit 25 at a low level, the output voltage of the first determination circuit 24 switches from a high level to a low level. Here, the first determination circuit 24 and the second determination circuit 25 detect a large current flowing through the FET 20. When the output voltage of the second determination circuit 25 is at a low level, and the output voltage of the first determination circuit 24 switches from a high level to a low level, the OR circuit 26 switches the output voltage from a high level to a low level. When the output voltage of the OR circuit 26 switches from a high level to a low level, as described above, the drive circuit 22 causes the output voltage to drop to 0V, maintaining the output voltage at 0V. As a result, the FET 20 switches off, maintaining the FET 20 off.

[0099] After the load 12 is short-circuited, the source voltage Vs is fixed at 0V, so the gate voltage Vg and the control voltage Vgs are the same. When the drive circuit 22 causes the output voltage to drop to 0V, the control voltage Vgs decreases. When the control voltage Vgs becomes less than the first threshold voltage Vth1, the first determination circuit 24 switches the output voltage from a low level to a high level, or the circuit 26 switches the output voltage from a low level to a high level. However, the drive circuit 22 causes the output voltage to continue to decrease. When the control voltage Vgs becomes less than the off-state voltage Vf, FET 20 switches off. Then, the gate voltage Vg and the control voltage Vgs drop to 0V and remain at 0V.

[0100] As described above, in the power supply control device 10, when a large current flows through FET20 during FET20's on-time, the drive circuit 22 switches FET20 to off-time. This prevents overcurrent from flowing through FET20.

[0101] It should be noted that during the transition period when FET20 switches from on to off, with a large current flowing through FET20, the drive circuit 22 switches FET20 off by causing the control voltage Vgs to continue to decrease.

[0102] <Structure of the first determination circuit 24>

[0103] Figure 5 This is a circuit diagram of the first determination circuit 24. Vr1 represents a certain first reference voltage, which is the ground potential. The first determination circuit 24 has a first differential amplifier 30 and a first comparator 31. The first differential amplifier 30 has circuit resistors 40, 41, 42, and 43 and a first operational amplifier 44. The first comparator 31 and the first operational amplifier 44 have a positive terminal, a negative terminal, and an output terminal, respectively.

[0104] The source of FET20 is also connected to one end of circuit resistor 40. The other end of circuit resistor 40 is connected to one end of circuit resistor 41 and the negative terminal of the first operational amplifier 44. The other end of circuit resistor 41 is connected to the output terminal of the first operational amplifier 44. The gate of FET20 is also connected to one end of circuit resistor 42. The other end of circuit resistor 42 is connected to one end of circuit resistor 43 and the positive terminal of the first operational amplifier 44. The other end of circuit resistor 43 is grounded.

[0105] The output of the first operational amplifier 44 is connected to the negative terminal of the first comparator 31. A first reference voltage Vr1 is applied to the positive terminal of the first comparator 31. The output of the first comparator 31 is connected to the first input terminal of the OR circuit 26. The first reference voltage Vr1 is generated, for example, by stepping down the power supply voltage Vb of the DC power supply 11 using a regulator (not shown).

[0106] The resistance values ​​of circuit resistors 40 and 42 are the same. The resistance values ​​of circuit resistors 41 and 43 are the same. Therefore, the first operational amplifier 44 amplifies the voltage between the gate and source of FET 20, i.e., the control voltage Vgs. The first operational amplifier 44 applies the amplified voltage to the negative terminal of the first comparator 31. The "consistency" of the resistance values ​​of circuit resistors 40 and 42, and the "consistency" of the resistance values ​​of circuit resistors 41 and 43, is not merely a strict consistency. As long as substantial consistency can be achieved, there is no problem.

[0107] exist Figure 5In this diagram, A represents the amplification of the first differential amplifier 30. The output voltage of the first operational amplifier 44 is represented by A·Vgs. "·" indicates a product. The amplification A is expressed as (resistance value of circuit resistor 41) / (resistance value of circuit resistor 40), which exceeds 0. Since the resistance values ​​of circuit resistors 40, 41, 42, and 43 are constant, the amplification A is also constant. When the resistance values ​​of circuit resistors 40, 41, 42, and 43 are identical, the amplification A is 1.

[0108] The first comparator 31 outputs a voltage to the OR circuit 26. The output voltage of the first comparator 31 is the output voltage of the aforementioned first determination circuit 24. The first comparator 31 compares the output voltage of the first operational amplifier 44 with the first reference voltage Vr1. The first comparator 31 functions as a comparator. The first reference voltage Vr1 corresponds to a specified voltage. Based on the comparison result, the first comparator 31 switches the output voltage to a high-level voltage or a low-level voltage.

[0109] The first comparator 31 switches the output voltage to a low level when the following equation (1) is satisfied.

[0110] A·Vgs≥Vr1…(1)

[0111] By expanding equation (1), we obtain equation (2) below.

[0112] Vgs≥Vr1 / A…(2)

[0113] Here, the first reference voltage Vr1 is set to A·Vth1. Therefore, the first comparator 31 switches the output voltage to a low level voltage when the following equation (3) is satisfied.

[0114] Vgs≥Vth1…(3)

[0115] Similarly, the first comparator 31 switches the output voltage to a high level voltage when the following equation (4) is satisfied.

[0116] A·Vgs <Vr1…(4)

[0117] As mentioned above, Vr1 is set to A·Vth1, so the first comparator 31 will switch the output voltage to a high level voltage if the following equation (5) is satisfied.

[0118] Vgs <Vth1…(5)

[0119] As described above, the first reference voltage Vr1 is set to A·Vth1, thus enabling the comparison between the control voltage Vgs and the first threshold Vth1. The first comparator 31 outputs a low-level voltage when the control voltage Vgs is above the first threshold Vth1, and outputs a high-level voltage when the control voltage Vgs is below the first threshold Vth1.

[0120] <Structure of the second determination circuit 25>

[0121] Figure 6 This is a circuit diagram of the second determination circuit 25. The second determination circuit 25 includes a first resistor 50, a second resistor 51, an adjuster 52, and a second comparator 53. The adjuster 52 includes a transistor 60 and a second operational amplifier 61. The transistor 60 is a PNP bipolar transistor that functions as a variable resistor. The second operational amplifier 61 has a positive terminal, a negative terminal, and an output terminal. Vr2 represents a certain second reference voltage with a reference potential equal to ground. R1 and R2 represent the resistance values ​​of the first resistor 50 and the second resistor 51, respectively.

[0122] One end of the first resistor 50 is connected to the drain of the FET 20. The other end of the first resistor 50 is connected to the emitter of the transistor 60. The collector of the transistor 60 is connected to one end of the second resistor 51. The other end of the second resistor 51 is grounded. The emitter and base of the transistor 60 are connected to the negative terminal and output terminal of the second operational amplifier 61, respectively. The positive terminal of the second operational amplifier 61 is connected to the source of the FET 20. The collector of the transistor 60 is also connected to the negative terminal of the second operational amplifier 61. A second reference voltage Vr2 is applied to the positive terminal of the second operational amplifier 61. The output terminal of the second operational amplifier 61 is connected to the second input terminal of the OR circuit 26. The second reference voltage Vr2 is generated, for example, by stepping down the power supply voltage Vb using a regulator (not shown).

[0123] Is represents the current flowing from the drain of FET20 towards the first resistor 50. The current Is flows in the order of the first resistor 50, transistor 60, and second resistor 51. The current path of current Is corresponds to the second current path. Therefore, the first resistor 50 is positioned in the current path of current Is, with one end of the first resistor 50 being the upstream end and the other end being the downstream end. In the current path of current Is, transistor 60 is positioned downstream of the first resistor 50, and the second resistor 51 is positioned downstream of the transistor 60. In transistor 60, the current Is flows in the order of the emitter and collector.

[0124] Regarding transistor 60, the resistance between the emitter and collector varies depending on the base voltage, which is the reference potential of the emitter. The lower the base voltage, which is the reference potential of the emitter, the smaller the resistance between the emitter and collector.

[0125] Hereinafter, the voltage of the base with the reference potential being ground will be referred to as the base voltage. When the base voltage decreases, the voltage of the base with the reference potential being the emitter potential decreases. When the base voltage increases, the voltage of the base with the reference potential being the emitter potential increases. The second operational amplifier 61 adjusts the resistance between the emitter and collector of the transistor 60 by adjusting the base voltage.

[0126] Hereinafter, the voltage at one downstream end of the first resistor 50 is recorded as the resistor voltage. The voltage at the source of FET 20 is recorded as the switching voltage. The reference potential for both the resistor voltage and the switching voltage is ground potential. The second operational amplifier 61 amplifies the differential voltage obtained by subtracting the resistor voltage from the switching voltage and applies the amplified voltage to the base of transistor 60. The output voltage of the second operational amplifier 61 is the base voltage. The second operational amplifier 61 adjusts the base voltage according to the differential voltage.

[0127] When the switching voltage drops below the resistor voltage, the second operational amplifier 61 causes the base voltage to decrease. This decreases the resistance between the emitter and collector of transistor 60. As a result, the current Is increases, and the resistor voltage decreases. When the switching voltage rises above the resistor voltage, the second operational amplifier 61 causes the base voltage to increase. This increases the resistance between the emitter and collector of transistor 60. As a result, the current Is decreases, and the resistor voltage increases. In this way, the second operational amplifier 61 adjusts the resistor voltage to match the switching voltage.

[0128] The second operational amplifier 61 adjusts the resistor voltage to the switching voltage, so the following equation (6) holds true.

[0129] Vb-Vds=Vb-R1·Is…(6)

[0130] Here, as mentioned above, Vb and Vds are the power supply voltage of DC power supply 11 and the voltage across FET 20, respectively. Equation (7) is obtained by expanding equation (6).

[0131] Is=Vds / R1…(7)

[0132] It should be noted that transistor 60 is fine as long as it functions as a variable resistor. Therefore, it is not limited to a PNP type bipolar transistor. Transistor 60 can also be, for example, a P-channel FET. In this case, the drain, source, and connector correspond to the collector, emitter, and base, respectively.

[0133] When the voltage between the two ends of the second resistor 51 is recorded as Vs, the following equation (8) holds.

[0134] Vs=R2·Is…(8)

[0135] Based on equations (7) and (8), by eliminating the current Is, we can obtain the following equation (9).

[0136] Vs=R2·Vds / R1…(9)

[0137] The second comparator 53 outputs a voltage to the OR circuit 26. The output voltage of the second comparator 53 is the output voltage of the aforementioned second determination circuit 25. The second comparator 53 compares the voltage across the second resistor 51 with the second reference voltage Vr2. The second comparator 53 functions as a second comparator. The second reference voltage Vr2 is equivalent to the second specified voltage. When the voltage across the second resistor 51 is greater than or equal to the second reference voltage Vr2, the output voltage is switched to a low level. Therefore, the second comparator 53 switches the output voltage to a low level when the following equation (10) is satisfied.

[0138] R2·Vds / R1≥Vr2…(10)

[0139] By expanding equation (10), we obtain equation (11) below.

[0140] Vds≥R1·Vr2 / R2…(11)

[0141] Here, the second reference voltage Vr2 is set to R2·Vth2 / R1. Therefore, the second comparator 53 switches the output voltage to a high level when the following equation (12) is satisfied. Vth2 is the second threshold as described above.

[0142] Vds≥Vth2…(12)

[0143] Similarly, when the voltage across the second resistor 51 is less than the second reference voltage Vr2, the second comparator 53 switches the output voltage to a high level. Therefore, the second comparator 53 switches the output voltage to a high level when the following equation (13) is satisfied.

[0144] R2·Vds / R1 <Vr2…(13)

[0145] As mentioned above, since Vr2 is set to R2·Vth2 / R1, the second comparator 53 will switch the output voltage to a high level voltage if the following equation (14) is satisfied.

[0146] Vds <Vth2…(14)

[0147] As described above, the second reference voltage Vr2 is set to R2·Vth2 / R1, thus enabling the comparison between the voltage Vds across the terminals and the second threshold Vth2. The second comparator 53 outputs a low-level voltage when the voltage Vds across the terminals is above the second threshold Vth2, and outputs a high-level voltage when the voltage Vds across the terminals is below the second threshold Vth2.

[0148] (Implementation Method 2)

[0149] In Embodiment 1, there is no problem as long as the second determination circuit 25 is a circuit that outputs a voltage corresponding to the comparison result of the voltage Vds across the FET 20 and the second threshold Vth2. Therefore, the structure of the second determination circuit 25 is not limited to a structure that uses the first resistor 50, the second resistor 51, the regulator 52, and the second comparator 53.

[0150] Hereinafter, regarding Embodiment 2, the differences from Embodiment 1 will be explained. Except for the structure described later, the structure is the same as in Embodiment 1. Therefore, for structural parts identical to those in Embodiment 1, the same reference numerals as in Embodiment 1 will be used, and their descriptions will be omitted.

[0151] <Structure of the second determination circuit 25>

[0152] Figure 7 This is a circuit diagram of the second determination circuit 25 in Embodiment 2. The structure of the second determination circuit 25 differs when comparing the power supply control device 10 in Embodiment 2 with that in Embodiment 1. The second determination circuit 25 includes a second differential amplifier 70 and a third comparator 71. The second differential amplifier 70 includes second circuit resistors 80, 81, 82, and 83, and a third operational amplifier 84. The third comparator 71 and the third operational amplifier 84 each have a positive terminal, a negative terminal, and an output terminal.

[0153] The second determination circuit 25 in embodiment 2 is configured similarly to the first determination circuit 24. The second circuit resistors 80, 81, 82, and 83 and the third operational amplifier 84 correspond to the circuit resistors 40, 41, 42, and 43 and the first operational amplifier 44, respectively. The negative terminal of the third operational amplifier 84 is connected to the source of the FET 20 via the second circuit resistor 80. The positive terminal of the third operational amplifier 84 is connected to the drain of the FET 20 via the second circuit resistor 82. The output terminal of the third comparator 71 is connected to the second input terminal of the OR circuit 26. A second reference voltage Vr2 is applied to the positive terminal of the third comparator 71.

[0154] The resistance values ​​of resistors 80 and 82 in the second circuit are the same. The resistance values ​​of resistors 81 and 83 in the second circuit are also the same. Therefore, the third operational amplifier 84 amplifies the voltage between the drain and source of FET 20, i.e., the voltage Vds across it. The third operational amplifier 84 applies the amplified voltage to the negative terminal of the third comparator 71. The "consistency" of the resistance values ​​of resistors 80 and 82 in the second circuit, and the "consistency" of the resistance values ​​of resistors 81 and 83 in the second circuit, are not merely strict consistency. As long as substantial consistency can be achieved, there is no problem.

[0155] exist Figure 7 In this diagram, B represents the amplification of the second differential amplifier 70. The output voltage of the third operational amplifier 84 is represented by B·Vds. The amplification B is expressed as (resistance value of the second circuit resistor 81) / (resistance value of the second circuit resistor 80), which exceeds 0. Since the resistance values ​​of the second circuit resistors 80, 81, 82, and 83 are constant, the amplification B is also constant. When the resistance values ​​of the second circuit resistors 80, 81, 82, and 83 are identical, the amplification B is 1.

[0156] The third comparator 71 outputs a voltage to the OR circuit 26. The output voltage of the third comparator 71 is the output voltage of the second determination circuit 25. The third comparator 71 compares the output voltage of the third operational amplifier 84 with the second reference voltage Vr2. The third comparator 71 functions as a third comparator. In Embodiment 2, the second reference voltage Vr2 is equivalent to the third specified voltage. Based on the comparison result, the third comparator 71 switches the output voltage to a high-level voltage or a low-level voltage.

[0157] The third comparator 71 switches the output voltage to a low level when the following equation (15) is satisfied.

[0158] B·Vds≥Vr2…(15)

[0159] By expanding equation (15), we obtain equation (16) below.

[0160] Vds≥Vr2 / B…(16)

[0161] In embodiment 2, the second reference voltage Vr2 is set to B·Vth2. Therefore, the third comparator 71 switches the output voltage to a low level when the following equation (17) is satisfied.

[0162] Vds≥Vth2…(17)

[0163] Similarly, the third comparator 71 switches the output voltage to a high level when the following equation (18) is satisfied.

[0164] B·Vds <Vr2…(18)

[0165] As mentioned above, Vr2 is set to B·Vth2, so the third comparator 71 will switch the output voltage to a high level voltage if the following equation (19) is satisfied.

[0166] Vds <Vth2…(19)

[0167] As described above, the second reference voltage Vr2 is set to B·Vth2, thus enabling the comparison between the voltage Vds across the terminals and the second threshold Vth2. The third comparator 71 outputs a low-level voltage when the voltage Vds across the terminals is above the second threshold Vth2, and outputs a high-level voltage when the voltage Vds across the terminals is below the second threshold Vth2.

[0168] The power supply control device 10 in Embodiment 2 also performs the same effect as the power supply control device 10 in Embodiment 1.

[0169] <Modifications of Implementation Methods 1 and 2>

[0170] In embodiments 1 and 2, there is no problem as long as FET 20 functions as a semiconductor switch. Therefore, a semiconductor switch different from the N-channel FET, such as IGBT (Insulated Gate Bipolar Transistor), can be used instead of FET 20. In this case, the collector and emitter of the IGBT correspond to the drain and source of FET 20, respectively. Moreover, in embodiments 1 and 2, there is no problem as long as the first determination circuit 24 is a circuit that outputs a voltage corresponding to the comparison result of the control voltage Vgs and the first threshold Vth1. Therefore, the structure of the first determination circuit 24 is not limited to a structure that uses the first differential amplifier 30 and the first comparator 31.

[0171] It should be considered that the disclosed embodiments 1 and 2 are illustrative in all respects and not restrictive. The scope of the invention is defined not by the foregoing but by the claims and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0172] Label Explanation

[0173] 1 Power System

[0174] 10 Power supply control device

[0175] 11 DC Power Supply

[0176] 12 Load

[0177] 20 FET

[0178] 21. Device resistance

[0179] 22. Drive circuit (switching circuit)

[0180] 23 Microcomputer

[0181] 24 First Decision Circuit

[0182] 25 Second Decision Circuit

[0183] 26 or circuit

[0184] 30. First Differential Amplifier (Amplifier)

[0185] 31 First comparator (comparator)

[0186] Circuit resistors 40, 41, 42, and 43

[0187] 44 First Operational Amplifier

[0188] 50 First resistor

[0189] 51 Second resistor

[0190] 52 Regulator

[0191] 53. Second Comparator

[0192] 60 transistors

[0193] 61 Second Operational Amplifier

[0194] 70 Second Differential Amplifier (Second Amplifier)

[0195] 71 Third Comparator

[0196] 80, 81, 82, 83 Second circuit resistors

[0197] 84 Third Operational Amplifier

[0198] C1 First capacitor

[0199] C2 is the second capacitor.

Claims

1. A power supply control device, comprising: In an N-channel FET, the drain is positioned upstream of the source in the current path of the current flowing from the DC power supply to the load. The first determination circuit determines whether the control voltage between the gate and source of the FET is above a first threshold. The second determination circuit determines whether the voltage between the drain and source of the FET is above a second threshold; and The switching circuit switches the FET to disconnect when the first determination circuit determines that the control voltage is above the first threshold and the second determination circuit determines that the voltage at both ends is above the second threshold.

2. The power supply control device according to claim 1, wherein, The first threshold exceeds the control voltage at the point in time when current begins to flow through the drain and source of the FET when the control voltage is increased. The second threshold is above 0V and less than the voltage of the DC power supply.

3. The power supply control device according to claim 1 or 2, wherein, The first determination circuit has: Amplifier, to amplify the control voltage; and The comparator compares the voltage amplified by the amplifier with a specified voltage. The specified voltage is set as the product of the first threshold and the amplification of the amplifier.

4. The power supply control device according to any one of claims 1 to 3, wherein, The second determination circuit has: A first resistor is configured in a second current path through which current flows, and one end of the first resistor is connected to the drain of the FET. The regulator adjusts the voltage at one end of the downstream side of the first resistor to the source voltage of the FET; The second resistor is disposed downstream of the first resistor in the second current path; and The second comparator compares the voltage across the second resistor with a second predetermined voltage. The second specified voltage is set to the value obtained by dividing the product of the second threshold and the resistance value of the second resistor by the resistance value of the first resistor.

5. The power supply control device according to any one of claims 1 to 3, wherein, The second determination circuit has: The second amplifier amplifies the voltage across the two terminals; and The third comparator compares the voltage amplified by the second amplifier with a third specified voltage. The third specified voltage is set as the product of the second threshold and the amplification of the second amplifier.

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