Mapping method, mapping device, many-core system, computer readable medium

Abstract

The present disclosure provides a mapping method, comprising: mapping a neural network to a plurality of core object clusters, each of the core object clusters comprising at least one core object, each of the core object clusters corresponding to a computing node in the neural network, each of the core objects describing configuration information of a processing core of a many-core system; and mapping the plurality of core object clusters to the many-core system. The present disclosure also provides a mapping apparatus, a many-core system, and a computer readable medium.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a mapping method, a mapping device, a many-core system, and a computer-readable medium. Background Technology

[0002] Neural network algorithms are a mainstream type of artificial intelligence algorithm, characterized by high computational complexity and high parallelism. These characteristics dictate new hardware requirements for running neural network programs.

[0003] In some related technologies, there is a lack of solutions that combine neural network programs with the hardware that runs them. Summary of the Invention

[0004] This disclosure provides a mapping method, a mapping apparatus, a many-core system, and a computer-readable medium.

[0005] In a first aspect, embodiments of this disclosure provide a mapping method, including:

[0006] The neural network is mapped to multiple core object clusters, each core object cluster includes at least one core object, each core object cluster corresponds to a computing node in the neural network, and each core object describes the configuration information of a processing core of the many-core system;

[0007] The multiple core object clusters are mapped to the many-core system.

[0008] In some embodiments, the step of mapping a neural network to multiple core object clusters includes:

[0009] A computation graph is generated based on the neural network, the computation graph including multiple computation subgraphs, each computation subgraph corresponding to a computation node;

[0010] Multiple core object clusters are generated based on the computation graph to complete the mapping of the neural network to the multiple core object clusters.

[0011] In some embodiments, the step of generating multiple core object clusters based on the computation graph includes:

[0012] Based on the computational subgraph corresponding to each core object cluster, a plurality of core objects constituting each core object cluster are generated;

[0013] The association relationships of multiple core object clusters are determined based on the computation graph.

[0014] In some embodiments, the computation graph includes multiple working phases, each computation subgraph corresponds to one working phase, and each computation subgraph includes multiple computation steps; for any one core object cluster, the step of generating multiple core object clusters according to the computation graph includes:

[0015] Based on the multiple calculation steps corresponding to the core object cluster, multiple core objects are generated, and each calculation step corresponds to at least one core object.

[0016] In some embodiments, the step of generating multiple core objects based on multiple computation steps corresponding to the core object cluster includes:

[0017] Based on the multiple calculation steps corresponding to the core object cluster, the configuration information of each core object in the core object cluster is determined, and the configuration information of the core object describes the configuration information of the processing core;

[0018] Instantiate each of the core object clusters and configure the configuration information of each of the core objects into the core objects.

[0019] In some embodiments, the configuration information of the core object includes timing information and synchronization information; the step of determining the configuration information of each core object in the core object cluster according to the plurality of calculation steps corresponding to the core object cluster includes:

[0020] Based on the correlation between the multiple calculation steps, the timing information and synchronization information of each core object are determined.

[0021] In some embodiments, the step of determining the configuration information of each core object in the core object cluster based on the plurality of calculation steps corresponding to the core object cluster further includes:

[0022] Based on the calculation steps corresponding to each core object, at least one of the memory information, computation primitives, and parameter information of each core object is determined.

[0023] In some embodiments, the association relationships among the multiple core object clusters include the connection relationships and temporal relationships among the multiple core object clusters; the step of determining the association relationships among the multiple core object clusters based on the computation graph includes:

[0024] The data flow relationships of the multiple core object clusters are determined based on the computation graph;

[0025] The connection relationship of the multiple core object clusters is determined based on the data flow relationship of the multiple core object clusters;

[0026] The temporal relationship of the multiple core object clusters is determined based on the data flow relationship of the multiple core object clusters.

[0027] In some embodiments, the step of determining the temporal relationship of the multiple core object clusters based on the data flow relationship of the multiple core object clusters includes:

[0028] A working phase diagram is generated based on the data flow relationships of multiple core object clusters, and the working phase diagram represents the temporal relationship of the multiple core object clusters.

[0029] In some embodiments, before the step of generating a plurality of core objects comprising each core object cluster based on the computational subgraph corresponding to each core object cluster, the step of generating a plurality of core object clusters based on the computational graph further includes:

[0030] Based on the processing kernel information of the neural network and the many-core system, multiple core resources are applied for from the core resource pool, and each core resource corresponds to a core object.

[0031] In some embodiments, the step of mapping multiple core object clusters to the many-core system includes:

[0032] Based on the topology of the many-core system, the correspondence between the core objects in each core object cluster and the processing cores in the many-core system is determined.

[0033] In some embodiments, the step of mapping multiple core object clusters to the many-core system further includes:

[0034] Determine the connection relationships among the multiple core objects;

[0035] Perform multicast detection to determine multicast configuration information;

[0036] A routing table is generated based on the connection relationships of the multiple core objects and the multicast configuration information.

[0037] In some embodiments, the step of mapping multiple core object clusters to the many-core system further includes:

[0038] Generate an executable file that the many-core system can execute.

[0039] In some embodiments, after the step of generating an executable file that the many-core system can execute, the step of mapping the plurality of core object clusters to the many-core system further includes:

[0040] Simulation is performed based on the executable file.

[0041] In some embodiments, the step of mapping the neural network to multiple core object clusters further includes:

[0042] The neural network is trained or fine-tuned based on the computation graph and multiple core object clusters to quantize and saturate the weights and activation values ​​of the neural network.

[0043] In some embodiments, after the step of mapping the neural network to multiple core object clusters, the mapping method further includes:

[0044] Determine the performance information of the neural network mapped to multiple core object clusters, wherein the performance information includes at least one of the number of core objects, storage resource utilization, and time-series resource utilization.

[0045] In some embodiments, after the step of mapping the neural network to multiple core object clusters, the mapping method further includes:

[0046] Perform bit-level precision simulation to determine execution efficiency information.

[0047] Secondly, embodiments of this disclosure provide a mapping apparatus, comprising:

[0048] One or more processors;

[0049] A memory having stored one or more programs that, when executed by one or more processors, cause the one or more processors to implement any of the mapping methods described in the first aspect of the present disclosure.

[0050] One or more I / O interfaces are connected between the processor and the memory and configured to enable information interaction between the processor and the memory.

[0051] Thirdly, embodiments of this disclosure provide a many-core system, including:

[0052] Multiple processing cores; and

[0053] The on-chip network is configured to interact with data between the multiple processing cores and external data;

[0054] One or more processing cores store one or more instructions, which are executed by one or more processing cores to enable the one or more processing cores to perform any of the mapping methods described in the first aspect of the present disclosure.

[0055] Fourthly, embodiments of this disclosure provide a computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any of the mapping methods described in the first aspect of this disclosure.

[0056] This disclosure provides a mapping method for mapping a neural network to a many-core system, a mapping apparatus capable of executing the mapping method, a many-core system capable of executing the mapping method, and a computer-readable medium storing a computer program capable of implementing the mapping method. In the mapping method, at the software level, core objects describing the processing cores of the many-core system are used to form core object clusters corresponding to each computing node of the neural network. A neural network program is built using these core object clusters. Then, the neural network program built using the core object clusters is mapped to the many-core system. Each core object in the core object cluster corresponds to a processing core in the many-core system, enabling the many-core system to run the neural network program, thereby realizing the mapping from the neural network to the many-core system.

[0057] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0058] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0059] Figure 1 This is a flowchart of a mapping method according to an embodiment of this disclosure;

[0060] Figure 2 This is a flowchart of some steps in another mapping method in this disclosure embodiment;

[0061] Figure 3 This is a flowchart of some steps in another mapping method according to an embodiment of the present disclosure;

[0062] Figure 4 This is a flowchart of some steps in another mapping method according to an embodiment of the present disclosure;

[0063] Figure 5 This is a flowchart of some steps in another mapping method according to an embodiment of the present disclosure;

[0064] Figure 6 This is a schematic diagram of the mapping from computing nodes to core object clusters in an embodiment of this disclosure;

[0065] Figure 7 This is a flowchart of some steps in another mapping method according to an embodiment of the present disclosure;

[0066] Figure 8This is a schematic diagram of an optional implementation of the working phase diagram in this disclosure;

[0067] Figure 9 This is a flowchart of some steps in another mapping method according to an embodiment of the present disclosure;

[0068] Figure 10 This is a flowchart of some steps in another mapping method according to an embodiment of the present disclosure;

[0069] Figure 11 This is a block diagram of a mapping device according to an embodiment of the present disclosure;

[0070] Figure 12 This is a block diagram of a many-core system according to an embodiment of the present disclosure. Detailed Implementation

[0071] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0072] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0073] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0074] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0075] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0076] Firstly, referring to Figure 1 This disclosure provides a mapping method, including:

[0077] In step S100, the neural network is mapped to multiple core object clusters, each core object cluster includes at least one core object, each core object cluster corresponds to a computing node in the neural network, and each core object describes the configuration information of a processing core of the many-core system;

[0078] In step S200, multiple core object clusters are mapped to the many-core system.

[0079] This disclosure does not impose any special limitations on many-core systems. For example, a many-core system can consist of a single chip; it can also be an array of multiple sub-chips, where each sub-chip has multiple computing units. The smallest computing unit in each sub-chip that can be independently scheduled and possesses complete computing capabilities is called a processing core. In a many-core system, multiple processing cores can work together, and each processing core can independently execute program instructions, utilizing parallel computing capabilities to accelerate program execution and provide multi-tasking capabilities.

[0080] In this embodiment of the disclosure, the processing cores in the many-core system are independent of each other and interconnected by routing. Each processing core has complete computing power and independent storage space. When a processing core runs program instructions, it interacts with the data stored locally on that processing core.

[0081] In the embodiments of this disclosure, the processing cores of a many-core system can be regarded as reconfigurable functional units. That is, each processing core has basic functions and can be configured as a functional core with specific functions. At least one processing core configured with a specific function can form a cluster of processing cores with specific functions.

[0082] The core object is instantiated from the processing core class. The core object is a software-level description of the processing core of the many-core system. The core object cluster, consisting of at least one core object, is a software-level description of the processing core cluster consisting of at least one processing core.

[0083] This disclosure does not impose any special limitations on the functional core class. For example, the functional core class includes a first functional core class, a second functional core class, and a third functional core class. The first functional core class, as a base class, defines the basic functions of the processing core in the many-core system. The second functional core class inherits from the first functional core class and defines the functions of functional cores with specific functions. The third functional core class inherits from the second functional core class and defines the functions of functional cores with more subdivided functions. Correspondingly, the core object can be instantiated from the first functional core class, the second functional core class, or the third functional core class.

[0084] It should be noted that in step S100, the neural network is mapped to multiple core object clusters, that is, the neural network program is built using multiple core object clusters, and each core object cluster corresponds to a computing node in the neural network; in step S200, the multiple core object clusters are mapped to a many-core system, and each core object in the core object cluster corresponds to a processing core in the many-core system. The processing core in the many-core system is configured as a functional core with corresponding functions according to the configuration information described by the core object, so that it can execute each computing node in the neural network, enabling the many-core system to run the neural network program, thus realizing the mapping of the neural network to the many-core system.

[0085] It should also be noted that the embodiments disclosed herein do not impose any special limitations on the neural network. For example, the neural network can be any of the following: Convolutional Neural Networks (CNN), Multilayer Perceptron (MLP), Long Short Term Memory (LSTM), Two-Dimensional Convolutional Network (CONV2D), Vector Product Network (MUL1D-1D), Vector Matrix Product Network (MUL1D-2D), or other user-defined networks.

[0086] This disclosure provides a mapping method for mapping a neural network to a many-core system. At the software level, core objects describing the processing cores of the many-core system are used to form core object clusters corresponding to each computing node of the neural network. The neural network program is built using the core object clusters, and then the neural network program built using the core object clusters is mapped to the many-core system. Each core object in the core object cluster corresponds to a processing core in the many-core system, enabling the many-core system to run the neural network program, thereby realizing the mapping from the neural network to the many-core system.

[0087] This disclosure does not impose any special limitations on how to decompose a neural network into multiple computing nodes. For example, the neural network can be decomposed according to the execution order of multiple computing steps in the neural network, with each computing node corresponding to at least one computing step; alternatively, multiple computing steps in the neural network can be mapped to multiple hardware execution stages, with each hardware execution stage being a working phase, and each computing node corresponding to at least one computing step in a working phase; alternatively, each computing node can be determined based on the neural network computing graph.

[0088] Accordingly, in some embodiments, reference is made to Figure 2 Step S100 includes:

[0089] In step S110, a computation graph is generated based on the neural network. The computation graph includes multiple computation subgraphs, and each computation subgraph corresponds to a computation node.

[0090] In step S120, multiple core object clusters are generated according to the computation graph to complete the mapping of the neural network to the multiple core object clusters.

[0091] In this embodiment of the disclosure, a computational subgraph in the computation graph corresponds to a computational node, and the connection relationship between multiple computational subgraphs represents the dependency relationship between the computations of each computational node. In this embodiment of the disclosure, when generating multiple core object clusters based on the computational graph, the association relationship between the multiple core object clusters is also determined based on the dependency relationship between the computations of each computational node.

[0092] Accordingly, in some embodiments, reference is made to Figure 3 Step S120 includes:

[0093] In step S121, multiple core objects constituting each core object cluster are generated based on the computational subgraph corresponding to each core object cluster.

[0094] In step S122, the association relationship of multiple core object clusters is determined according to the computation graph.

[0095] It should be noted that the embodiments disclosed herein do not impose any special limitations on the association relationships among multiple core object clusters. For example, the association relationships among multiple core object clusters include data flow relationships, temporal relationships, etc.

[0096] In this embodiment, generating multiple core object clusters through step S120 includes sequential decomposition and parallel decomposition. Sequential decomposition refers to generating multiple core object clusters corresponding to multiple working phases, with each core object cluster corresponding to one working phase. Multiple core object clusters corresponding to the same working phase can exist in parallel, or multiple core object clusters corresponding to different working phases can exist serially. This embodiment does not impose any special limitations on this. Parallel decomposition refers to determining multiple core objects constituting a core object cluster based on the degree of parallelism in each computational subgraph and each core object cluster. Within each core object cluster, one core object can correspond to one computational task; depending on fan-in / fan-out limitations or computational and storage efficiency limitations, multiple core objects can also correspond to one computational task. Each core object cluster can contain multiple parallel core objects or multiple serial core objects. This embodiment also does not impose any special limitations on this.

[0097] Accordingly, in some embodiments, the computation graph includes multiple working phases, each computation subgraph corresponds to one working phase, and each computation subgraph includes multiple computation steps; refer to Figure 4 For any one of the core object clusters, step S121 includes:

[0098] In step S1211, multiple core objects are generated according to the multiple calculation steps corresponding to the core object cluster, and each calculation step corresponds to at least one core object.

[0099] In this embodiment, the core object is a software-level description of the processing core of the many-core system, describing the configuration information of the processing core. The configuration information in the core object is determined based on its corresponding computational task. During the process of mapping the neural network to the many-core system, the processing core is encapsulated into a functional core capable of performing the computational task based on the configuration information described in the core object. This configuration information is configured into the core object when it is instantiated from the processing core class.

[0100] Accordingly, in some embodiments, reference is made to Figure 5 Step S1211 includes:

[0101] In step S1211a, configuration information of each core object in the core object cluster is determined according to the multiple calculation steps corresponding to the core object cluster, and the configuration information of the core object describes the configuration information of the processing core;

[0102] In step S1211b, each of the core object clusters is instantiated, and the configuration information of each core object is configured into the core object.

[0103] The embodiments disclosed herein do not impose special limitations on the configuration information of the core objects.

[0104] In this embodiment, multiple computational tasks obtained from the decomposition of the same computational subgraph also have dependencies. Based on these dependencies, the association relationships of the core objects corresponding to each computational task within the core object cluster can be determined. This embodiment does not impose special limitations on the association relationships of multiple core objects within the core object cluster. For example, the control logic of each core object can be determined based on the dependencies of multiple computational tasks. The control logic includes timing information and synchronization information. As an optional implementation, the timing information and synchronization information are configured as parameters of the core object.

[0105] Accordingly, in some embodiments, the configuration information of the core object includes timing information and synchronization information; the step of determining the configuration information of each core object in the core object cluster according to the multiple calculation steps corresponding to the core object cluster includes: determining the timing information and synchronization information of each core object according to the association relationship of the multiple calculation steps.

[0106] In some embodiments, the configuration information of the core object further includes at least one of memory information, computation primitives, and parameter information. The memory information describes the memory size of the processing cores in the many-core system, and the computation primitives are the instructions required to complete the computational tasks corresponding to the core object.

[0107] Accordingly, in some embodiments, the step of determining the configuration information of each core object in the core object cluster according to the multiple calculation steps corresponding to the core object cluster further includes: determining at least one of the memory information, calculation primitives, and parameter information of each core object according to the calculation steps corresponding to each core object.

[0108] In some embodiments, when core objects are used to form core object clusters and neural network programs are built using these core object clusters, the data flow relationships between various computation nodes in the computation graph can be mapped and expressed as the association relationships of the core object clusters. After mapping the core object clusters to a many-core system, the many-core system can achieve pipelined scheduling. In some embodiments, such as Figure 6As shown, Object D, Object E, and Object F each correspond to a computation node in the neural network. Through early compilation, Object D, Object E, and Object F are mapped to core object clusters Cluster D, Cluster E, and Cluster F, respectively. The relationships among Cluster D, Cluster E, and Cluster F are as follows: the computation result obtained by Cluster D can be transmitted to Cluster E for processing; the computation result obtained by Cluster E can be transmitted to Cluster F for processing. Simultaneously, after Cluster D transmits its computation result to Cluster E, it can continue processing the next computation task, and after Cluster E transmits its computation result to Cluster F, it can continue processing the next computation task, thereby improving parallelism. Through post-compilation, based on the topology of the neuromorphic many-core architecture, the corresponding processing cores of Cluster D, Cluster E, and Cluster F after mapping to the many-core system, as well as the relationships between Cluster D, Cluster E, and Cluster F, can be further determined. The correlation of F in many-core systems.

[0109] Accordingly, in some embodiments, the association relationship among the multiple core object clusters includes the connection relationship and temporal relationship among the multiple core object clusters; refer to Figure 7 Step S122 includes:

[0110] In step S1221, the data flow relationships of the multiple core object clusters are determined according to the computation graph;

[0111] In step S1222, the connection relationship of the multiple core object clusters is determined based on the data flow relationship of the multiple core object clusters;

[0112] In step S1223, the temporal relationship of the multiple core object clusters is determined based on the data flow relationship of the multiple core object clusters.

[0113] Optionally, in this embodiment, each core object cluster has an input interface and an output interface, and the connection relationship between each core object cluster is determined through the input interface / output interface.

[0114] This disclosure does not impose any special limitations on the form of the timing relationship between multiple core object clusters. As an optional implementation, a working phase diagram is used to represent the timing relationship between multiple core object clusters.

[0115] Accordingly, in some embodiments, the step of determining the temporal relationship of the multiple core object clusters based on the data flow relationship of the multiple core object clusters includes: generating a working phase diagram based on the data flow relationship of the multiple core object clusters, wherein the working phase diagram characterizes the temporal relationship of the multiple core object clusters.

[0116] Figure 8 This is a schematic diagram of an optional implementation of the working phase diagram in this disclosure. For example... Figure 8 The diagram shows a macro data event-driven mechanism based on data streams. Figure 8 Each first, second, third, fourth, and fifth data block in the process represents a macro data event. Multiple core object clusters are distinguished as layers 1, 2, 3, 4, and 5. Each core object cluster triggers computation based on the received macro data events. For example, layer 1 performs a computation once for each first data block received; layer 2 performs a computation once for each of the two second data blocks output from layer 1 received; layer 3 performs a computation once for each of the two third data blocks output from layer 2 received; layer 4 performs a computation once for each of the one fourth data block output from layer 3 received; and layer 5 performs a computation once for each of the two fifth data blocks output from layer 4 received.

[0117] It should be noted that, in this embodiment of the disclosure, after mapping multiple core object clusters to the many-core system in step S200, the processing cores in the many-core system perform calculations according to the macro data event-driven mechanism described in this embodiment. As an optional implementation, based on the determined temporal relationship of the multiple core object clusters, a macro data event satisfying the temporal relationship is triggered only upon receipt; when no macro data event satisfying the temporal relationship is received, the processing core can remain dormant.

[0118] In some embodiments, a core resource pool strategy is adopted, where the processing cores of the many-core system are treated as core resources with the same capabilities, and a core resource pool is designated through a resource allocator. When it is necessary to map a neural network to the many-core system, the corresponding core resources are first requested from the core resource pool.

[0119] Accordingly, in some embodiments, before the step of generating multiple core objects constituting each core object cluster according to the computation subgraph corresponding to each core object cluster, the step of generating multiple core object clusters according to the computation graph further includes: applying for multiple core resources from the core resource pool according to the processing core information of the neural network and the many-core system, wherein each core resource corresponds to one core object.

[0120] In some embodiments, refer to Figure 9 Step S200 includes:

[0121] In step S210, the correspondence between the core objects in each core object cluster and the processing cores in the many-core system is determined according to the topology of the many-core system.

[0122] This disclosure does not impose any particular limitation on how to characterize the topology of a many-core system. As an optional implementation, the topology of the many-core system is characterized using core planar graph information. For example, for a many-core system consisting of a single chip, the core planar graph information includes the number of processing cores in the chip and the number of processing cores in each row and column of the core array; for an array consisting of multiple sub-chips, the core planar graph information also includes the number of sub-chips in the chip array and the number of sub-chips in each row and column.

[0123] In some embodiments, when mapping core object clusters to many-core systems, it is necessary to optimize the layout of processing cores according to the topology of the many-core system to meet the routing transmission requirements; to avoid routing deadlock; to consider traffic overhead to obtain the minimum routing transmission time; and to perform multicast detection. The above information is reflected through configuring the routing table.

[0124] Accordingly, in some embodiments, reference is made to Figure 9 Step S200 further includes:

[0125] In step S220, the connection relationships of the multiple core objects are determined;

[0126] In step S230, multicast detection is performed to determine multicast configuration information;

[0127] In step S240, a routing table is generated based on the connection relationships of the multiple core objects and the multicast configuration information.

[0128] It should be noted that when multiple core objects in multiple core object clusters do not correspond to all the processing cores of the many-core system, that is, when the many-core system runs the neural network program, some processing cores are not used, it is necessary to configure the routing nodes corresponding to all processing cores in the many-core system.

[0129] In some embodiments, the step of mapping multiple core object clusters to the many-core system further includes: generating an executable file that the many-core system can execute.

[0130] As an optional implementation, the executable file includes a file header, chip-level data, and core-level data. Core-level data includes configuration parameters and weight / bias data. It should be noted that when multiple core objects in multiple core object clusters do not correspond to all the processing cores of the many-core system—that is, when the many-core system runs a neural network program, some processing cores are not used—only the processing cores used when the many-core system runs the neural network program have core-level data. Routing node configurations are contained in the chip-level data.

[0131] In some embodiments, after the step of generating an executable file that the many-core system can execute, the step of mapping the plurality of core object clusters to the many-core system further includes: performing simulation based on the executable file.

[0132] Simulation is used to verify the correctness of executable files. Simulation can also provide information such as the routing traffic information consumed in each stage and the utilization rate of the routing buffer in each clock cycle, which can be used to optimize the mapping of multiple core object clusters to many-core systems.

[0133] In some embodiments, refer to Figure 2 In addition to steps S110 and S120, step S100 also includes:

[0134] In step S130, the neural network is trained or fine-tuned according to the computation graph and the multiple core object clusters to quantize and saturate the weights and activation values ​​of the neural network.

[0135] It should be noted that quantizing and saturating the weights and activation values ​​of a neural network involves discretizing these values ​​using quantization and activation functions. For example, this maps a 32-bit floating-point number to an 8-bit integer; it transforms the multiplication and addition operations of a 32-bit floating-point number into 8-bit multiplication and low-precision addition operations. This reduces the computational load of the neural network, increases its operating speed, and ensures that the many-core system does not overflow when running the neural network.

[0136] As an optional implementation, step S130 specifically includes: based on the multiple core object clusters generated by the computation graph and mapping, the neural network is retrained by replacing the original convolution and addition functions in the front-end framework with quantized versions.

[0137] In some embodiments, after mapping the neural network to multiple core object clusters through step S100, early performance analysis and behavioral simulation can be invoked to analyze the algorithm performance of mapping the neural network to the core object clusters.

[0138] Accordingly, in some embodiments, reference is made to Figure 10 After step S100, the mapping method further includes:

[0139] In step S300, performance information of the neural network mapped to multiple core object clusters is determined, and the performance information includes at least one of the number of core objects, storage resource utilization, and time-series resource utilization.

[0140] It should be noted that in step S300, the impact of the many-core system's topology on the performance of the neural network mapping to multiple core object clusters is not considered, nor is the impact of the routing relationships between multiple processing cores in the many-core system considered. That is, the algorithm performance of the neural network mapping to core object clusters is evaluated under routing-independent mapping.

[0141] Accordingly, in some embodiments, reference is made to Figure 10 After step S100, the mapping method further includes:

[0142] In step S400, bit-level precision simulation is performed to determine execution efficiency information.

[0143] Secondly, referring to Figure 11 This disclosure provides a mapping apparatus, including:

[0144] One or more processors 101;

[0145] The memory 102 stores one or more programs, which, when executed by one or more processors, cause the one or more processors to implement any of the mapping methods described in the first aspect of the embodiments of this disclosure.

[0146] One or more I / O interfaces 103 are connected between the processor and the memory and configured to enable information exchange between the processor and the memory.

[0147] The processor 101 is a device with data processing capabilities, including but not limited to a central processing unit (CPU); the memory 102 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH); the I / O interface (read / write interface) 103 is connected between the processor 101 and the memory 102, enabling information exchange between the processor 101 and the memory 102, including but not limited to a data bus (Bus).

[0148] In some embodiments, the processor 101, memory 102, and I / O interface 103 are interconnected via bus 104, and thus connected to other components of the computing device.

[0149] Thirdly, referring to Figure 12 This disclosure provides a many-core system, including:

[0150] It includes multiple processing cores 201 and an on-chip network 202, wherein the multiple processing cores 201 are all connected to the on-chip network 202, and the on-chip network 202 is used to exchange data between the multiple processing cores and external data.

[0151] One or more processing cores 201 store one or more instructions, which are executed by one or more processing cores 201 to enable one or more processing cores 201 to perform any of the mapping methods described in the first aspect of the present disclosure.

[0152] Fourthly, embodiments of this disclosure provide a computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any of the mapping methods described in the first aspect of this disclosure.

[0153] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0154] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A mapping method, comprising: The neural network is mapped to multiple core object clusters, each core object cluster includes at least one core object, each core object cluster corresponds to a computing node in the neural network, and each core object describes the configuration information of a processing core of the many-core system; The core object is instantiated based on the processing core class, and the core object cluster is used to characterize the software-level description of a processing core cluster consisting of at least one processing core. The configuration information is used to configure the processing core in the many-core system as a functional core with corresponding functions; The multiple core object clusters are mapped to the many-core system.

2. The mapping method according to claim 1, wherein, The steps involved in mapping a neural network to multiple core object clusters include: A computation graph is generated based on the neural network, the computation graph including multiple computation subgraphs, each computation subgraph corresponding to a computation node; Multiple core object clusters are generated based on the computation graph to complete the mapping of the neural network to the multiple core object clusters.

3. The mapping method according to claim 2, wherein, The steps for generating multiple core object clusters based on the computation graph include: Based on the computational subgraph corresponding to each core object cluster, a plurality of core objects constituting each core object cluster are generated; The association relationships of multiple core object clusters are determined based on the computation graph.

4. The mapping method according to claim 3, wherein, The computation graph includes multiple working phases, and each computation subgraph corresponds to one working phase. Each computation subgraph includes multiple computation steps. For any one of the core object clusters, the step of generating multiple core object clusters based on the computation graph includes: Based on the multiple calculation steps corresponding to the core object cluster, multiple core objects are generated, and each calculation step corresponds to at least one core object.

5. The mapping method according to claim 4, wherein, The steps for generating multiple core objects based on the multiple computation steps corresponding to the core object cluster include: Based on the multiple calculation steps corresponding to the core object cluster, the configuration information of each core object in the core object cluster is determined, and the configuration information of the core object describes the configuration information of the processing core; Instantiate each of the core object clusters and configure the configuration information of each of the core objects into the core objects.

6. The mapping method according to claim 5, wherein, The configuration information of the core object includes timing information and synchronization information; The steps for determining the configuration information of each core object in the core object cluster based on the multiple calculation steps corresponding to the core object cluster include: Based on the correlation between the multiple calculation steps, the timing information and synchronization information of each core object are determined.

7. The mapping method according to claim 6, wherein, The step of determining the configuration information of each core object in the core object cluster based on the multiple calculation steps corresponding to the core object cluster further includes: Based on the calculation steps corresponding to each core object, at least one of the memory information, computation primitives, and parameter information of each core object is determined.

8. The mapping method according to any one of claims 3 to 7, wherein, The association relationships among the multiple core object clusters include the connection relationships and temporal relationships among the multiple core object clusters; The steps for determining the association relationships among multiple core object clusters based on the computation graph include: The data flow relationships of the multiple core object clusters are determined based on the computation graph; The connection relationship of the multiple core object clusters is determined based on the data flow relationship of the multiple core object clusters; The temporal relationship of the multiple core object clusters is determined based on the data flow relationship of the multiple core object clusters.

9. The mapping method according to claim 8, wherein, The steps for determining the temporal relationship of multiple core object clusters based on their data flow relationships include: A working phase diagram is generated based on the data flow relationships of multiple core object clusters, and the working phase diagram represents the temporal relationship of the multiple core object clusters.

10. The mapping method according to any one of claims 3 to 7, wherein, Before the step of generating multiple core objects constituting each core object cluster based on the computational subgraph corresponding to each core object cluster, the step of generating multiple core object clusters based on the computational graph further includes: Based on the processing kernel information of the neural network and the many-core system, multiple core resources are applied for from the core resource pool, and each core resource corresponds to a core object.

11. The mapping method according to claim 1, wherein, The step of mapping multiple core object clusters to the many-core system includes: Based on the topology of the many-core system, the correspondence between the core objects in each core object cluster and the processing cores in the many-core system is determined.

12. The mapping method according to claim 11, wherein, The step of mapping multiple core object clusters to the many-core system further includes: Determine the connection relationships among the multiple core objects; Perform multicast detection to determine multicast configuration information; A routing table is generated based on the connection relationships of the multiple core objects and the multicast configuration information.

13. The mapping method according to claim 11 or 12, wherein, The step of mapping multiple core object clusters to the many-core system further includes: Generate an executable file that the many-core system can execute.

14. The mapping method according to claim 13, wherein, After the step of generating an executable file that the many-core system can execute, the step of mapping the multiple core object clusters to the many-core system further includes: Simulation is performed based on the executable file.

15. The mapping method according to any one of claims 2 to 7, wherein, The steps of mapping a neural network to multiple core object clusters also include: The neural network is trained or fine-tuned based on the computation graph and multiple core object clusters to quantize and saturate the weights and activation values ​​of the neural network.

16. The mapping method according to any one of claims 1 to 7, 11, and 12, wherein, Following the step of mapping the neural network to multiple core object clusters, the mapping method further includes: Determine the performance information of the neural network mapped to multiple core object clusters, wherein the performance information includes at least one of the number of core objects, storage resource utilization, and time-series resource utilization.

17. The mapping method according to any one of claims 1 to 7, 11, and 12, wherein, Following the step of mapping the neural network to multiple core object clusters, the mapping method further includes: Perform bit-level precision simulation to determine execution efficiency information.

18. A mapping apparatus, comprising: One or more processors; A memory having stored one or more programs that, when executed by one or more processors, cause the one or more processors to implement the mapping method according to any one of claims 1 to 17; One or more I / O interfaces are connected between the processor and the memory and configured to enable information interaction between the processor and the memory.

19. A many-core system, comprising: Multiple processing cores; as well as The on-chip network is configured to interact with data between the multiple processing cores and external data; One or more processing cores store one or more instructions, which are executed by one or more processing cores to enable the one or more processing cores to perform the mapping method according to any one of claims 1 to 17.

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