Graphics processing method, apparatus and system, computing device, and storage medium

Abstract

The present disclosure provides a graphics processing method, apparatus and system, a computing device, and a storage medium. The method is executed by a topology splitting module in a target graphics processing core, and comprises: acquiring a graphics drawing command, the graphics drawing command indicating that a graphic having a specified topology type is to be drawn; on the basis of the graphics drawing command, acquiring vertex index data required for drawing the graphic; on the basis of the specified topology type, dividing the vertex index data into primitive packets according to index order, to determine a primitive packet to be processed by the target graphics processing core, and inserting a corresponding synchronization marker; transmitting the primitive packet to be processed by the target graphics processing core and the corresponding synchronization marker to a geometry processing pipeline module in the target graphics processing core for processing, to obtain a geometry processing result having the synchronization marker, wherein the geometry processing result having the synchronization marker is processed by a pixel processing pipeline module in the target graphics processing core to obtain a visual graphic.

Description

Graphics processing methods, apparatus and systems, computing devices and storage media

[0001] This application claims priority to Chinese Patent Application No. 202411887669.7, filed on December 19, 2024, entitled "Graphics Processing Method, Apparatus and System, Computing Device and Storage Medium", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of computer technology, and in particular to graphics processing methods, apparatus and systems, computing devices and storage media, and computer program products. Background Technology

[0003] In the field of computer science, graphics processing units (GPUs) are used to process various types of graphics data. The rendering pipeline is a key concept in computer graphics processing; it's a stage within the GPU responsible for processing and transforming graphics data. The main task of the rendering pipeline is to convert the geometric primitives (such as points, lines, and triangles) included in the input graphics data into pixels visible on the screen, thereby achieving the rendering of the graphics. Summary of the Invention

[0004] In view of this, the present disclosure provides graphics processing methods, apparatus and systems, computing devices and storage media, and computer program products.

[0005] According to a first aspect of this disclosure, a graphics processing method is provided, the method being executed by a topology splitting module in a target graphics processing core, the target graphics processing core being one of at least two enabled graphics processing cores included in a graphics processing system, each of the at least two enabled graphics processing cores including a topology splitting module, a geometry processing pipeline module, and a pixel processing pipeline module. The method includes: acquiring a graphics drawing command, the graphics drawing command indicating that a graphics with a specified topology type should be drawn; acquiring vertex index data required for drawing the graphics based on the graphics drawing command, the vertex index data including the indexes of the vertices of the graphics to be drawn; dividing the vertex index data into primitive packets according to the specified topology type in index order to determine the primitive packets to be processed by the target graphics processing core and inserting corresponding synchronization markers, wherein the synchronization markers are used to mark complete primitive packets, and each primitive packet divided by the topology splitting modules included in the at least two enabled graphics processing cores includes the same predetermined number of indexes of vertices of geometric primitives, the predetermined number of indexes of vertices of geometric primitives including a portion of the vertex index data; transmitting the primitive packets to be processed by the target graphics processing core and the corresponding synchronization markers to a geometry pipeline module in the target graphics processing core for processing to obtain a geometry processing result with synchronization markers, wherein the geometry processing result with synchronization markers is processed by a pixel processing pipeline module in the target graphics processing core to obtain a visualized graphics.

[0006] In some embodiments, obtaining vertex index data required for drawing the graphics based on the graphics drawing command includes: obtaining vertex index data required for drawing the graphics from an index buffer based on the graphics drawing command; or generating vertex index data required for drawing the graphics based on the graphics drawing command.

[0007] In some embodiments, the graphics drawing command includes indication information indicating that the graphics to be drawn do not have a reset point and includes source information related to the source of index data acquisition. Furthermore, based on the graphics drawing command, acquiring vertex index data required for drawing the graphics includes: in response to the source information indicating that the source of the index data is an index buffer, acquiring the vertex index data required for drawing the graphics from the index buffer, wherein the vertex index data in the index buffer is pre-generated by the application that issued the graphics drawing command; in response to the source information indicating that the index data will be automatically generated, generating the vertex index data required for drawing the graphics; wherein the reset point indicates that there are no common vertices between the geometric primitive containing the vertex preceding the reset point and the geometric primitive containing the vertex following the reset point.

[0008] In some embodiments, the graphics drawing command includes indication information indicating that the graphics to be drawn have a reset point, and, based on the graphics drawing command, obtaining vertex index data required for drawing the graphics includes: obtaining vertex index data required for drawing the graphics from an index buffer, wherein the vertex index data in the index buffer is pre-generated by the application that issued the graphics drawing command; wherein the reset point indicates that there are no common vertices between the geometric primitive containing the vertex preceding the reset point and the geometric primitive containing the vertex following the reset point.

[0009] In some embodiments, according to the specified topology type, the vertex index data is divided into primitive packets according to the index order to determine the primitive packets to be processed by the target graphics processing core and insert corresponding synchronization markers. This includes: numbering the divided primitive packets according to the order in which the vertex index data is divided, and determining the sequence number of the target graphics processing core among the at least two enabled graphics processing cores in this graphics processing process; in response to the remainder obtained by dividing the number of the divided primitive packets by the number of the at least two enabled graphics processing cores being the same as the sequence number of the target graphics processing core, the divided primitive packets are determined as the primitive packets to be processed by the target graphics processing core, and corresponding synchronization markers are inserted.

[0010] In some embodiments, transmitting the primitive package to be processed by the target graphics processing core and the corresponding synchronization mark to the geometry pipeline module in the target graphics processing core for processing to obtain a geometry processing result with synchronization mark includes: in response to an inconsistency in the winding order of geometric primitives in the graphics having a specified topology, transmitting the primitive package to be processed by the target graphics processing core and the corresponding synchronization mark to the geometry pipeline module in the target graphics processing core, so that the geometry pipeline module obtains a geometry processing result with synchronization mark based on the primitive package to be processed by the target graphics processing core, the corresponding synchronization mark, and the winding order of the initial geometric primitives of the primitive package to be processed by the target graphics processing core; wherein the winding order of the geometric primitives in the graphics indicates the connection order of the vertices of the geometric primitives when forming the geometric primitive, and the connection order includes one of clockwise and counterclockwise.

[0011] In some embodiments, transmitting the primitive package to be processed by the target graphics processing core and the corresponding synchronization mark to the geometry pipeline module in the target graphics processing core for processing to obtain a geometry processing result with synchronization mark includes: in response to the inconsistency of the winding order of geometric primitives in the graphics having a specified topology, transmitting the primitive package to be processed by the target graphics processing core and the corresponding synchronization mark to the geometry pipeline module in the target graphics processing core, so that the geometry pipeline module obtains a geometry processing result with synchronization mark based on the primitive package to be processed by the target graphics processing core, the corresponding synchronization mark, and the winding order of the initial geometric primitives of the primitive package to be processed by the target graphics processing core, and storing the geometry processing result with synchronization mark in a geometry processing result memory; wherein the geometry processing result with synchronization mark is obtained from the geometry processing result memory and processed by the pixel processing pipeline module in the target graphics processing core to obtain a visual graphic, and wherein the winding order of the geometric primitives in the graphic indicates the connection order of the vertices of the geometric primitives when forming the geometric primitive, the connection order including one of clockwise and counterclockwise.

[0012] In some embodiments, the winding order of the initial geometric primitives of the primitive package processed by the target graphics processing core is determined as follows: in response to a reset point in the graph having a specified topology type, the winding order of the initial geometric primitives of the primitive package processed by the target graphics processing core is determined based on the previous reset point adjacent to the primitive package and a pre-configured initial winding order, wherein the pre-configured initial winding order indicates the winding order of the initial primitives of the primitive package in which the vertex index data is first divided.

[0013] In some embodiments, the winding order of the initial geometric primitives of the primitive package processed by the target graphics processing core is determined as follows: in response to the absence of a reset point in the graphics having a specified topology, and when the number of geometric primitives in each primitive package is configured to be even, the winding order of the initial geometric primitives of the primitive package processed by the target graphics processing core is determined to be a pre-configured initial winding order, wherein the pre-configured initial winding order indicates the winding order of the initial primitives of the primitive package in which the vertex index data is first divided.

[0014] In some embodiments, the winding order of the initial geometric primitives of the primitive package processed by the target graphics processing core is determined by the following steps, the steps including: determining the number of the primitive package processed by the target graphics processing core in response to the absence of a reset point in the graphics having a specified topology, and in the case that the number of geometric primitives in each primitive package is configured to be odd; determining the winding order of the initial geometric primitives of the primitive package as a pre-configured initial winding order in response to an even number of the primitive package processed by the target graphics processing core; and determining that the winding order of the initial geometric primitives of the primitive package is flipped relative to the pre-configured initial winding order in response to an odd number of the primitive package processed by the target graphics processing core; wherein the pre-configured initial winding order indicates the winding order of the initial primitives of the primitive package in which the vertex index data is first divided.

[0015] In some embodiments, the winding order of the initial geometric primitives of the primitive package processed by the target graphics processing core is determined as follows. In response to the fact that the graphics having a specified topology type does not have a reset point and the primitive package processed by the target graphics processing core is the initial primitive package to be processed by the target graphics processing core, the following steps are performed: If the product of the number of geometric primitives in each divided primitive package and the sequence number of the target graphics processing core in this graphics processing process is even, it is determined that the winding order of the initial geometric primitives of the initial primitive package processed by the target graphics processing core is the same as a pre-configured initial winding order, wherein the pre-configured initial winding order indicates the winding order of the initial primitives of the primitive package in which the vertex index data is first divided; if the product of the number of geometric primitives in each divided primitive package and the sequence number of the target graphics processing core in this graphics processing process is odd, it is determined that the winding order of the initial geometric primitives of the initial primitive package processed by the target graphics processing core is flipped relative to the pre-configured initial winding order. In response to the fact that the graph with the specified topology does not have a reset point and the primitive package processed by the target graphics processing core is a subsequent primitive package numbered after the initial primitive package, the following steps are performed: if the product of the number of geometric primitives in each partitioned primitive package and the number of enabled graphics processing cores is even, it is determined that the winding order of the initial geometric primitives of the subsequent primitive package remains unchanged compared to the winding order of the initial geometric primitives of the previous primitive package processed by the target graphics processing core; if the product of the number of geometric primitives in each partitioned primitive package and the number of enabled graphics processing cores is odd, it is determined that the winding order of the initial geometric primitives of the subsequent primitive package is reversed compared to the winding order of the initial geometric primitives of the previous primitive package processed by the target graphics processing core.

[0016] In some embodiments, the method further includes: obtaining configuration information, the configuration information including the number of geometric primitives in each primitive package, information indicating at least two enabled graphics processing cores among the plurality of graphics processing cores included in the graphics processing system, and the sequence number of the at least two enabled graphics processing cores during the current graphics processing.

[0017] According to a second aspect of this disclosure, a graphics processing apparatus is provided, wherein the processing is performed by a topology splitting module in a target graphics processing core, the target graphics processing core being one of at least two enabled graphics processing cores in a graphics processing system, each of the at least two enabled graphics processing cores including a topology splitting module, a geometry processing pipeline module, and a pixel processing pipeline module. The processing apparatus includes: a first acquisition module configured to acquire a graphics drawing command, the graphics drawing command indicating that a graphics having a specified topology type should be drawn; a second acquisition module configured to acquire vertex index data required for drawing the graphics based on the graphics drawing command, the vertex index data being indexes of the vertices of the graphics to be drawn; and a primitive packet determination module configured to divide the vertex index data into primitive packets according to the specified topology type, in index order, to determine the primitive packets to be processed by the target graphics processing core and insert corresponding synchronization markers, wherein the synchronization markers are used to mark the division order of complete primitive packets, and wherein... Each primitive packet, divided by the topology splitting module of at least two enabled graphics processing cores, includes the same predetermined number of vertex indices of geometric primitives, the predetermined number of vertex indices of geometric primitives including a portion of the vertex index data; a transmission module is configured to transmit the primitive packet to be processed by the target graphics processing core and the corresponding synchronization mark to the geometry pipeline module in the target graphics processing core for processing to obtain a geometry processing result with synchronization mark, wherein the geometry processing result with synchronization mark is processed by the pixel processing pipeline module in the target graphics processing core to obtain a visualization graphic.

[0018] According to a third aspect of this disclosure, a graphics processing system is provided, the graphics processing system comprising at least two enabled graphics processing cores, and each of the at least two enabled graphics processing cores comprising: a topology splitting module configured to perform the method as described in the first aspect of this disclosure as a topology splitting module in a target graphics processing core; a geometry processing pipeline module configured to obtain a geometry processing result based at least on the primitive packet to be processed by the target graphics processing core and the corresponding synchronization tag; and a pixel processing pipeline module configured to process the geometry processing result to obtain a visualization graphic.

[0019] According to a fourth aspect of this disclosure, a computing device is provided, including a processor; and a memory configured to store computer-executable instructions thereon, which, when executed by the processor, perform any of the methods described above.

[0020] According to a fifth aspect of this disclosure, a computer-readable storage medium is provided that stores computer-executable instructions that, when executed, perform any of the methods described above.

[0021] According to a sixth aspect of this disclosure, a computer program product is provided, including computer-readable code or a non-volatile computer-readable storage medium carrying the computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs any of the methods described above.

[0022] The graphics processing methods, apparatus, and systems claimed in this disclosure employ decentralized parallel geometry processing pipelines. Each geometry processing pipeline does not need to communicate with each other to exchange processing information for reset points during processing, effectively improving the throughput of the graphics processing system for handling graphics tasks, increasing the processing speed of the graphics processing system, achieving high-quality and high-resolution rendering in real time, and possessing good scalability. Users can easily add or remove (or dynamically configure as needed) the corresponding GPU units (e.g., enabled graphics processing cores) according to the usage scenario to meet the performance and power consumption requirements of different scenarios.

[0023] These and other advantages of this disclosure will become clear from the embodiments described below, and will be illustrated with reference to the embodiments described below. Attached Figure Description

[0024] Embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings, in which:

[0025] Figure 1 illustrates an exemplary architecture diagram of a graphics processing system according to an embodiment of the present disclosure;

[0026] Figure 2 shows an exemplary flowchart of a graphics processing method according to an embodiment of the present disclosure;

[0027] Figure 3 illustrates an exemplary flowchart of a method for partitioning vertex index data into primitive packets according to a specified topology type based on an embodiment of the present disclosure.

[0028] Figure 4 illustrates an exemplary process of partitioning primitive packets according to an embodiment of the present disclosure;

[0029] Figure 5 illustrates an exemplary flowchart of a method for determining the winding order of the initial geometric primitives of a primitive package for target graphics processing core processing according to an embodiment of the present disclosure;

[0030] Figure 6 illustrates an exemplary structural block diagram of a graphics processing apparatus 600 according to an embodiment of the present disclosure;

[0031] Figure 7 illustrates an example system, which includes an example computing device representing one or more systems and / or devices that can implement the various technologies described herein. Detailed Implementation

[0032] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0033] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0034] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0035] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0036] It should be understood that while the terms first, second, third, etc., may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. Therefore, the first component discussed below may be referred to as the second component without departing from the teachings of this disclosure. As used herein, the terms "and / or" and similar terms include all combinations of any, multiple, and all of the associated listed items.

[0037] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of exemplary embodiments, and the modules or processes in the drawings are not necessarily necessary for implementing this disclosure, and therefore cannot be used to limit the scope of protection of this disclosure.

[0038] Before detailing the embodiments of this disclosure, some related concepts will be explained for clarity.

[0039] Geometric primitives, also known as graphic primitives, refer to the basic geometric shapes that make up a graphic, including points, lines, triangles, etc. For example, a graphic drawn by an application can be represented in a computer by a large number of triangles. After breaking down graphic data into corresponding basic geometric shapes, the geometry processing pipeline can use these basic geometric shapes to determine the pixels of the drawn graphic.

[0040] Topology types: also known as primitive topology types, typically include point lists, line lists, triangle lists, line bands, triangle bands, line lists with adjacency information, triangle lists with adjacency information, line bands with adjacency information, triangle bands with adjacency information, loop lines, etc. The definitions of these topologies are the same as those in Microsoft DirectX 11.3.

[0041] As mentioned earlier, the GPU rendering pipeline is a key concept in computer graphics. It's a stage within the graphics processing unit (GPU) responsible for processing and transforming graphics data for rendering. The primary task of the rendering pipeline is to convert input geometric primitives (such as points, lines, triangles, etc.) into pixels visible on the screen. The goal of the rendering pipeline is to process graphics efficiently and generate the final image. Through parallel processing and specialized hardware support, the GPU can perform these calculations rapidly to achieve real-time graphics rendering.

[0042] In related technologies, the rendering pipeline can generally be divided into two parts: the geometry processing part (also known as the geometry pipeline) and the pixel processing part (also known as the fragment pipeline).

[0043] The geometry processing section includes the vertex input stage, vertex shading stage, primitive assembly stage, geometry shading stage, clipping stage, and screen mapping stage. The geometry pipeline primarily focuses on the processing and transformation of geometric data. It receives input geometric primitives (such as points, lines, triangles, etc.) and, after a series of stages, transforms them into geometric processing results mapped to pixel coordinates in screen space. The geometry processing section is responsible for performing geometric calculations such as model transformation, view transformation, and projection transformation, as well as generating new geometric primitives and changing their shape, size, and position.

[0044] The pixel processing section generally includes the rasterization stage, the fragment shading stage, and the pixel manipulation stage. The fragment pipeline focuses on pixel-level processing. It receives the pixels on the screen generated by the rasterization stage and processes each pixel through a series of stages. The pixel processing section is responsible for performing pixel-level lighting calculations, texture sampling, depth testing, and other operations to determine the final color and attributes of each pixel.

[0045] Specifically, the vertex input phase passes vertex data from the application to the geometry pipeline. Vertex data includes attributes such as position, color, and normals. In the vertex shading phase, the vertex shader calculates for each input vertex and can perform various transformations and operations, such as model transformations, view transformations, and projection transformations. It can also calculate vertex lighting and texture coordinates. In the primitive assembly phase, the primitive assembler converts vertices into complete geometric primitives, such as points, line segments, and triangles. In the geometry shading phase, the geometry shader can manipulate and generate geometric primitives. It can create new primitives and change their shape, size, and position. In the clipping phase, the clipper compares primitives to the screen boundary and discards portions outside the view volume. The screen mapping phase maps the clipped primitives to pixel coordinates in screen space. The rasterization phase converts the transformed geometry into pixels on the screen and determines the position, color, and other attributes of each pixel. In the fragment shading phase, the fragment shader calculates for each rasterized pixel, performing pixel-level lighting calculations, texture sampling, depth testing, and other operations. Pixel operations are used to perform final pixel processing, such as blending, dithering, and anti-aliasing.

[0046] It should be noted that these two pipelines are consecutive stages in the rendering pipeline; they are interdependent and work closely together to ultimately generate a visualized image. The geometry pipeline transforms geometric data into geometric processing results corresponding to pixel coordinates, while the fragment pipeline performs final processing and computation on the geometric processing results and the corresponding pixel data. Through parallel processing and dedicated hardware support, the GPU can efficiently execute these pipeline stages to achieve real-time graphics rendering.

[0047] With the development of GPUs, there is an urgent need to improve GPU throughput to increase processing speed and achieve high-quality, high-resolution rendering in real time. However, this poses a significant challenge to the data processing capabilities of current conventional GPUs. This disclosure proposes a decentralized graphics processing method, apparatus, and system that significantly expands the data processing throughput at the geometry stage, thereby improving GPU speed. The implementation of this graphics processing method and apparatus will be explained in detail below with reference to several embodiments.

[0048] Figure 1 illustrates an exemplary architecture diagram of a graphics processing system 100 according to an embodiment of the present disclosure. As shown in Figure 1, the graphics processing system includes multiple graphics processing cores, of which three are shown: 110, 120, and 130. Two or more of the multiple graphics processing cores can be enabled as needed; for example, graphics processing cores 110 and 120 can be enabled while 130 is disabled. Here, "enable" means "to enable" or "to activate." Each graphics processing core may include a topology splitting module, a geometry processing pipeline module, and a pixel processing pipeline module. As shown in Figure 1, graphics processing core 110 includes a topology splitting module 111, a geometry processing pipeline module 112, and a pixel processing pipeline module 113. Graphics processing core 120 includes a topology splitting module 121, a geometry processing pipeline module 122, and a pixel processing pipeline module 123. Graphics processing core 130 includes a topology splitting module 131, a geometry processing pipeline module 132, and a pixel processing pipeline module 133.

[0049] For each enabled graphics processing core, taking graphics processing core 110 as an example, its topology splitting module 111 can obtain a graphics drawing command, which indicates that a graphic with a specified topology type should be drawn; then, based on the graphics drawing command, it obtains vertex index data required to draw the graphic, the vertex index data including the indexes of the vertices of the graphic to be drawn; and according to the specified topology type, it divides the vertex index data into primitive packets according to the index order to determine the primitive packets to be processed by the target graphics processing core and inserts corresponding synchronization markers, wherein the synchronization markers are used to mark complete primitive packets, and each primitive packet divided by the topology splitting module of the at least two enabled graphics processing cores includes the same predetermined number of indexes of vertices of geometric primitives, the predetermined number of indexes of vertices of geometric primitives including a portion of the vertex index data; finally, the primitive packets to be processed by the target graphics processing core and the corresponding synchronization markers are transmitted to the geometry pipeline module in the target graphics processing core for processing. The geometry processing pipeline module 112 can obtain geometry processing results based at least on the primitive package to be processed by the target graphics processing core and the corresponding synchronization marker. The geometry processing pipeline module primarily obtains geometry processing results by executing the various stages of the geometry processing portion of the rendering pipeline as described above. The pixel processing pipeline module 113 can be configured to process the geometry processing results to obtain visualization graphics. The pixel processing pipeline module primarily obtains visualization graphics by executing the various stages of the pixel processing portion of the rendering pipeline as described above. These stages are similar to those described in related technologies and will not be described in detail here.

[0050] In this way, the individual geometry processing pipelines do not need to communicate with each other to exchange processing information such as reset points during the processing, thus realizing a decentralized and parallel geometry processing pipeline.

[0051] Optionally, the graphics processing system 100 may further include a system configuration module 140, which can be configured to generate configuration information and send the configuration information to the topology splitting module of each graphics processing core for configuration. The configuration information may include the number of geometric primitives in each primitive package, information indicating at least two enabled graphics processing cores among the multiple graphics processing cores included in the graphics processing system, and the sequence numbers of the at least two enabled graphics processing cores in the current graphics processing process.

[0052] Optionally, the graphics processing system 100 may further include a system bus 150 and a storage unit 160. The graphics processing core can obtain the required data from the storage unit via the system bus, or store the generated data into the storage unit via the system bus. The system bus can be an on-chip bus or an on-chip bus. The storage unit can be SRAM (Static Random-Access Memory), DRAM (Dynamic Random-Access Memory), etc., and is not limited here. In some embodiments, the system bus 150 and the storage unit 160 may not be included in the graphics processing system and exist as independent components outside the graphics processing system.

[0053] In embodiments of this disclosure, the graphics processing system 100 can be implemented as a complete GPU system (i.e., GPU) as a chip module. Each graphics processing core can be implemented as a smaller module or chip unit as a GPU unit. A GPU system may have only one GPU unit, suitable for applications with low performance and low power consumption requirements, such as PDAs (Personal Digital Assistants) and automotive chips. A GPU system may also include multiple GPU units to provide solutions for high-performance applications. This disclosure does not limit the number of GPU units.

[0054] Chip modules are a novel integrated circuit design approach that breaks down a complex chip into multiple smaller modules or chip units, which are then combined to form a complete system-on-a-chip (SoC). Each smaller module typically contains a specific function or subsystem and can be designed, tested, and manufactured independently. These modules can be implemented using different manufacturing processes, technologies, or suppliers. Finally, these modules can be assembled in a single package to form a fully functional SoC.

[0055] As can be seen from the above, the graphics processing system disclosed herein adopts a decentralized parallel geometry processing pipeline. Each geometry processing pipeline does not need to communicate with each other to exchange processing information of reset points during the processing process, which effectively improves the throughput of the graphics processing system in processing graphics tasks, increases the processing speed of the graphics processing system, realizes high-quality and high-resolution rendering in real time, and has good scalability. Users can easily add or reduce (or dynamically configure as needed) the corresponding GPU units (e.g., enabled graphics processing cores) according to the usage scenario to meet the performance and power consumption requirements of different scenarios.

[0056] Figure 2 shows an exemplary flowchart of a graphics processing method 200 according to an embodiment of the present disclosure. The method 200 can be executed by a topology splitting module in a target graphics processing core, which is one of at least two enabled graphics processing cores included in a graphics processing system. Each of the at least two enabled graphics processing cores includes a topology splitting module, a geometry processing pipeline module, and a pixel processing pipeline module. The target graphics processing core can be, for example, an enabled graphics processing core 110 as described with reference to Figure 1. The method 200 may include the following steps.

[0057] In step 210, a drawing command is obtained, which indicates that a graphic with a specified topology type should be drawn. The drawing command may be received from a graphics drawing application or may be a drawing command specified by a driver. The topology type may be one of the following: a point list, a line list, a triangle list, a line strip, a triangle strip, a line list with adjacency information, a triangle list with adjacency information, a line strip with adjacency information, a triangle strip with adjacency information, a loop line, etc.

[0058] In step 220, based on the graphics drawing command, vertex index data required for drawing the graphics is obtained. The vertex index data includes the indices of the vertices of the graphics to be drawn. The vertex index data can be in the form of numbers or letters, for example, without limitation. Numerical indices include, for example, 0, 1, 2, etc., and letter indices include, for example, A, B, C, etc. In some embodiments, the vertex index data required for drawing the graphics can be obtained from an index buffer memory, or it can be automatically generated.

[0059] The graphic to be drawn may or may not have a reset point, which can be explicitly specified in the drawing command. A reset point is a point where there are no common vertices between the geometric primitive containing the vertex before the reset point and the geometric primitive containing the vertex after the reset point. For example, in the vertex index data A, B, C, (CT), D, E, F of a triangle band, ABC constitutes the first triangle primitive, and DEF constitutes the second triangle primitive. CT represents a reset point, indicating that there are no common vertices between the first and second triangle primitives, that is, A, B, C, D, E, F are divided into two primitives, while B, C, and D do not constitute a triangle primitive.

[0060] In some embodiments, the graphics drawing command includes indication information indicating that the graphics to be drawn do not have a reset point and includes source information related to the source of the index data acquisition. In this case, if the source information indicates that the source of the index data acquisition is an index buffer, the vertex index data required for drawing the graphics is obtained from the index buffer, wherein the vertex index data in the index buffer is pre-generated by the application that issued the graphics drawing command. The application that issues the graphics drawing command is, for example, the graphics drawing application described above. If the source information indicates that the index data will be generated automatically, the vertex index data required for drawing the graphics is automatically generated. That is, when the graphics drawing command includes indication information indicating that the graphics to be drawn do not have a reset point, the vertex index data required for drawing the graphics can be obtained from the index buffer, or the vertex index data required for drawing the graphics can be generated directly. The index buffer can be, for example, the storage component 160 or a portion thereof described with reference to FIG1, but this is not limiting.

[0061] In some embodiments, the graphics drawing command includes indication information indicating that the graphic to be drawn has a reset point. In this case, the vertex index data required for drawing the graphic is obtained from the index buffer, rather than being directly generated because the location of the reset point cannot be accurately determined. The vertex index data in the index buffer is pre-generated by the application that issued the graphics drawing command.

[0062] In step 230, according to the specified topology type, the vertex index data is divided into primitive packets according to index order to determine the primitive packets to be processed by the target graphics processing core and insert corresponding synchronization markers. The synchronization markers are used to mark complete primitive packets. Each primitive packet divided by the topology splitting modules of the at least two enabled graphics processing cores includes the same predetermined number of vertex indices of geometric primitives, where the predetermined number of vertex indices of geometric primitives includes a portion of the vertex index data. Since primitive packets lose boundary information after being processed by the geometry pipeline module, i.e., adjacent primitive packets cannot be distinguished, inserting corresponding synchronization markers into each primitive packet here can clearly indicate the boundaries of each primitive packet, helping subsequent pixel processing pipeline modules to correctly recover these primitive packets and their order.

[0063] In some embodiments, when determining the primitive packet to be processed by the target graphics processing core and inserting the corresponding synchronization marker, the primitive packets can first be numbered according to the order in which the vertex index data was divided, and the sequence number of the target graphics processing core among the at least two enabled graphics processing cores in this graphics processing process can be determined. Then, if the remainder obtained by dividing the number of the primitive packet by the number of the at least two enabled graphics processing cores is the same as the sequence number of the target graphics processing core, the primitive packet is determined as the primitive packet to be processed by the target graphics processing core, and the corresponding synchronization marker is inserted.

[0064] As an example, primitive pack numbers can start from 0, for instance, they can be divided into primitive packs 0, 1, 2, etc., according to the order in which vertex index data is divided. The serial number of the graphics processing core is different from its physical number. The physical number is usually assigned to the graphics processing core at the physical level and is fixed, while the serial number is variable and can be dynamically assigned each time it is used. For example, the physical numbers of the two enabled graphics processing cores 110 and 120 described with reference to FIG1 are fixed at 0 and 1, respectively, while the physical number of the disabled graphics processing core 130 is fixed at 3. However, the serial numbers of graphics processing cores 110 and 120 can be 0 and 1, or 1 and 0, respectively, while the disabled graphics processing core 130 may not be assigned a serial number or may not have one (representing NULL), which enhances the flexibility of primitive processing. For graphics processing systems that already have multiple graphics processing cores, users (applications or drivers, or operating systems) can dynamically adjust the number of enabled graphics processing cores as needed to meet the performance requirements and power consumption limitations of different application scenarios. Meanwhile, for graphics processing systems with multiple graphics processing cores, if some graphics processing cores are defective and unusable during the tape-out process, these defective graphics processing cores can be disabled, for example, through the configuration of the system configuration module, so that the partially defective chip can still be used, reducing the losses caused by the impact of yield. Moreover, this mechanism is also applicable to supporting virtualization scenarios.

[0065] As an example, assuming the serial number of the target graphics processing core is 0, if the number of the partitioned primitive package is 2, then the remainder obtained by dividing it by the number of the at least two enabled graphics processing cores is 0, which is the same as the serial number of the target graphics processing core. In this case, the partitioned primitive package 2 is determined as the primitive package to be processed by the target graphics processing core, and the corresponding synchronization tag is inserted.

[0066] As described with reference to FIG1, the number of geometric primitives in each primitive package, information indicating at least two enabled graphics processing cores among the multiple graphics processing cores included in the graphics processing system (e.g., the number of enabled graphics processing cores), and the sequence numbers of the at least two enabled graphics processing cores in this graphics processing process can be configured by the system configuration module into the topology splitting module of each graphics processing core when the graphics processing system starts. The synchronization flag here is used to mark a complete primitive package, indicating that a complete primitive package has been formed. Additionally, the synchronization flag can also be used to mark the partitioning order of complete primitive packages, which may include information about the primitive package numbers, providing further assurance that multiple small graphics processing cores process primitives in the correct order.

[0067] In step 240, the primitive package to be processed by the target graphics processing core and the corresponding synchronization mark are transmitted to the geometry pipeline module in the target graphics processing core for processing to obtain a geometry processing result with synchronization marks. This geometry processing result with synchronization marks is then processed by the pixel processing pipeline module in the target graphics processing core to obtain a visualized graphic. As described above, using the synchronization mark, the primitive package can be rearranged according to the synchronization mark during processing in the geometry processing pipeline module, ensuring that the boundary information between the geometry processing results of different primitive packages remains clear after processing. This ensures that all primitives maintain the same order as their original order during the pixel processing stage, thereby improving the accuracy of graphic rendering and preventing incorrect rendering situations such as occlusion and transparency blending. The geometry processing result with synchronization marks is then processed by the pixel processing pipeline module in the target graphics processing core to obtain a visualized graphic.

[0068] In some topological types of graphics (such as triangle strip types), the winding order of geometric primitives is inconsistent. Here, the winding order of geometric primitives refers to the connection order of the vertices of a geometric primitive when forming the primitive, which can be either clockwise or counterclockwise. For example, in a triangle strip type graphic represented by vertex index data A, B, C, D, there are two triangles: a first triangle formed by vertices A, B, and C, and a second triangle formed by vertices B, C, and D. The first triangle has a clockwise winding order, and the second triangle has a counterclockwise winding order. To correctly process geometric primitives in the rendering pipeline for proper rendering, the winding order of each geometric primitive needs to be considered during graphics processing.

[0069] In some embodiments, when the winding order of geometric primitives in a graph with a specified topology is inconsistent, the primitive package to be processed by the target graphics processing core and the corresponding synchronization marker can be transmitted to the geometry pipeline module in the target graphics processing core. This allows the geometry pipeline module to obtain a geometry processing result with the synchronization marker based on the primitive package to be processed by the target graphics processing core, the corresponding synchronization marker, and the winding order of the initial geometric primitives in the primitive package. The initial geometric primitive of the primitive package is the first primitive formed by the vertex index data in the primitive package. For example, in a primitive package consisting of vertex index data A, B, C, D, E representing a topology-type triangle, the initial geometric primitive is the first triangle geometric primitive formed by vertices A, B, and C. In this case, the primitive package can be rearranged according to the inserted synchronization marker, ensuring that the boundary information between the geometry processing results of different primitive packages remains clear after processing by the geometry pipeline module. This ensures that all primitives are processed in the same order as their original order during the pixel processing stage, thereby improving the accuracy of graphic rendering and preventing incorrect rendering issues such as occlusion or transparency blending.

[0070] In some embodiments, when the winding order of geometric primitives in a graphic with a specified topology is inconsistent, the primitive package to be processed by the target graphics processing core and the corresponding synchronization marker can be transmitted to the geometry pipeline module in the target graphics processing core. This allows the geometry pipeline module to obtain a geometry processing result with synchronization markers based on the primitive package to be processed by the target graphics processing core, the corresponding synchronization markers, and the initial winding order of the geometric primitives in the primitive package to be processed by the target graphics processing core, and store the geometry processing result with synchronization markers in a geometry processing result memory. The geometry processing result with synchronization markers is then retrieved from the geometry processing result memory and processed by the pixel processing pipeline module in the target graphics processing core to obtain a visualized graphic. Since the geometry processing results have a storage order in the geometry processing result memory, and this storage order is consistent with the primitive package order, this further ensures that the order of all primitives in the pixel processing stage is consistent with their original order, thereby improving the accuracy of graphic rendering and preventing incorrect rendering situations such as occlusion and transparency blending. The geometry processing result memory can, for example, be a part of a storage component 160.

[0071] The winding order of the initial geometric primitives of the primitive package processed by the target graphics processing core can be determined in various ways. In some embodiments, when there is a reset point in the graphics having a specified topology, the winding order of the initial geometric primitives of the primitive package processed by the target graphics processing core can be determined based on the previous reset point adjacent to the primitive package and a pre-configured initial winding order. The pre-configured initial winding order indicates the winding order of the initial primitives of the primitive package where the vertex index data is first divided.

[0072] For example, in a triangle-band type topology with reset points, suppose there is vertex index data: A, B, C, D, (CT), E, ​​F, G, H, I, (CT), J, K, L, M, N, O, and suppose the pre-configured initial winding order is clockwise. The initial primitives of the first primitive packet divided in the above vertex index data are triangles A, B, and C, and their winding order is the pre-configured initial winding order, i.e., clockwise.

[0073] The triangular primitives corresponding to the above vertex index data should be: A, B, C; B, C, D; E, F, G; F, G, H; G, H, I; J, K, L; K, L, M; L, M, N; M, N, O. With each primitive pack containing 3 primitives, the first primitive pack can be divided into: A, B, C, D, (CT), E, ​​F, G; the second primitive pack into: F, G, H, I, (CT), J, K, L; and the third primitive pack into: K, L, M, N, O.

[0074] If the primitive package processed by the target graphics processing core is the second primitive package, then based on its previous reset point (i.e., the reset point between D and E) and the pre-configured initial winding order, the winding order of primitives E, F, and G is determined to be clockwise (starting again with the pre-configured initial winding order after the reset point). Furthermore, the winding order of primitives F, G, and H is determined to be counterclockwise. Thus, the winding order of the initial geometric primitives of the primitive package processed by the target graphics processing core is determined to be counterclockwise.

[0075] Similarly, the winding order of all triangle primitives corresponding to the vertex index data can be determined as follows: A,B,C (CW); B,C,D (CCW); E,F,G (CW); F,G,H (CCW); G,H,I (CW); J,K,L (CW); K,L,M (CCW); L,M,N (CW); M,N,O (CCW). The symbols in parentheses indicate the winding order of the primitives, with CW representing clockwise and CCW representing counterclockwise. The initial geometric primitive winding order of the first primitive packet is CW; the initial geometric primitive winding order of the second primitive packet is CCW; and the initial geometric primitive winding order of the third primitive packet is CCW.

[0076] In some embodiments, where there is no reset point in the graph with the specified topology type, the winding order of the initial geometric primitives of the primitive package processed by the target graphics processing core can be determined in several ways. As an example, when the number of geometric primitives in each partitioned primitive package is configured to be even (e.g., this can be configured by the system configuration module), the winding order of the initial geometric primitives of the primitive package processed by the target graphics processing core can be determined to be a pre-configured initial winding order. The pre-configured initial winding order indicates the winding order of the initial primitives of the primitive package where the vertex index data is first partitioned. For example, if the pre-configured initial winding order is clockwise, since the winding order of the initial geometric primitives in each primitive package is clockwise, the winding order of the initial geometric primitives of the primitive package processed by the target graphics processing core can be determined to be clockwise.

[0077] As another example, when the number of geometric primitives in each partitioned primitive package is configured to be odd, the primitive package number processed by the target graphics processing core is determined, and the initial winding order of the geometric primitives in the primitive package is determined based on the primitive package number processed by the target graphics processing core. If the primitive package number processed by the target graphics processing core is even, the initial winding order of the geometric primitives in the primitive package is determined to be a pre-configured initial winding order. If the primitive package number processed by the target graphics processing core is odd, the initial winding order of the geometric primitives in the primitive package is determined to be reversed relative to the pre-configured initial winding order. For example, if the pre-configured initial winding order is clockwise, the winding order reversed relative to it is counterclockwise.

[0078] This provides an efficient and quick way to determine the winding order of primitive packets, although it is not a newly devised method. It should be noted that the winding order of the initial geometric primitives of the primitive packet processed by the target graphics processing core described here can be determined by either the topology splitting module or the geometry processing pipeline module; this is not limited to either.

[0079] In the graphics processing method of this disclosure embodiment, a decentralized parallel geometry processing pipeline is adopted. Each geometry processing pipeline does not need to communicate with each other to exchange processing information such as reset points during the processing, which effectively improves the throughput of graphics processing tasks, increases the speed of graphics processing, achieves high-quality and high-resolution rendering, and has good scalability. Users can easily add or reduce (or dynamically configure as needed) the corresponding GPU units according to the usage scenario to meet the performance and power consumption requirements of different scenarios.

[0080] Figure 3 illustrates an exemplary flowchart of a method 300 for partitioning vertex index data into primitive packets according to a specified topology type based on an embodiment of the present disclosure. The method 300 includes the following steps.

[0081] In step 310, the current primitive package number i is reset to 0.

[0082] In step 320, the vertex index data is divided into primitive packets according to the index order based on the specified topology type, and the current primitive packet number i is assigned to the divided primitive packet.

[0083] In step 330, it is determined whether the remainder obtained by dividing the number i by the number of at least two enabled graphics processing cores is the same as the serial number of the target graphics processing core. If they are different, in step 340, it is determined that the partitioned primitive packet is not a primitive packet to be processed by the target graphics processing core, and it is discarded directly. If they are the same, in step 350, it is determined that the partitioned primitive packet is a primitive packet to be processed by the target graphics processing core, and it is sent to the geometry processing pipeline module. In step 360, a corresponding synchronization tag is inserted into the partitioned primitive packet.

[0084] In step 370, it is determined whether the primitive packet partitioning has ended. If it has ended, the execution of this method is terminated. If it has not ended, in step 380, the value of the number i is incremented by one and assigned to the current primitive packet number i, and the process returns to step 320 to continue execution.

[0085] The embodiments of this disclosure provide an efficient and simple method for partitioning vertex index data into primitive packets according to index order, which can quickly determine the primitive packets to be processed by the target graphics processing core.

[0086] As an example, Figure 4 illustrates an exemplary process of partitioning primitive packets according to an embodiment of this disclosure, specifically showing the partitioning of primitive packets by the topology splitting module in the first graphics processing core (serial number 0) when three graphics processing cores are enabled. Taking graphics processing core 110 in Figure 1 as an example, as shown in Figure 4, the first partitioned primitive packet is numbered 0, the second partitioned primitive packet is numbered 1, and so on. According to the method described in Figure 3, primitive packets 0 and 3 can be determined as the primitive packets to be processed by the first graphics processing core, and corresponding synchronization markers are inserted, while primitive packets 1, 2, 4, and 5 are not the primitive packets to be processed by the first graphics processing core and should therefore be discarded.

[0087] Figure 5 illustrates an exemplary flowchart of a method 500 for determining the winding order of initial geometric primitives of a primitive package for target graphics processing core processing according to an embodiment of the present disclosure, applicable to cases where there are no reset points in a graphics with a specified topology type. As shown in Figure 5, the method 500 includes the following steps.

[0088] In step 510, it is determined whether the number of geometric primitives in each divided primitive packet is set to an even number. If the number of geometric primitives in each divided primitive packet is set to an even number, it can be directly determined at 550 that the winding order of the initial geometric primitives of the initial primitive packet processed by the target graphics processing core is the same as the pre-configured initial winding order, wherein the pre-configured initial winding order indicates the winding order of the initial primitives of the primitive packet in which the vertex index data is first divided, and the winding order of the initial geometric primitives of the subsequent primitive packets processed by the target graphics processing core after the initial primitive packet remains unchanged (i.e., the same) as the winding order of the initial geometric primitives of the subsequent primitive packets processed by the target graphics processing core. Taking Figure 4 as an example, if the initial primitive packet is primitive packet 0, then primitive packets 3, 6, and 9 are all subsequent primitive packets processed by the target graphics processing core after the initial primitive packet 0, and the previous primitive packet of primitive packet 6 processed by the target graphics processing core is primitive packet 3. That is, the previous primitive packet here refers to the directly adjacent primitive packet.

[0089] If the number of geometric primitives in each primitive package is set to an odd number, then in step 520 it is determined whether the number of enabled graphics processing cores is even. If the number of enabled graphics processing cores is even, then in step 530 it is determined whether the sequence number of the target graphics processing core is even.

[0090] If it is determined in step 530 that the sequence number of the target graphics processing core is even, then in step 550 it can be determined that the winding order of the initial geometric primitives of the initial primitive package processed by the target graphics processing core is the same as the pre-configured initial winding order, and the winding order of the initial geometric primitives of the subsequent primitive packages processed by the target graphics processing core after the initial primitive package remains unchanged from the winding order of the initial geometric primitives of the previous primitive package of the subsequent primitive package processed by the target graphics processing core.

[0091] If it is determined in step 530 that the sequence number of the target graphics processing core is odd, it can be determined in step 560 that the winding order of the initial geometric primitives of the initial primitive package processed by the target graphics processing core is reversed relative to the pre-configured initial winding order, and the winding order of the initial geometric primitives of the subsequent primitive packages processed by the target graphics processing core after the initial primitive package remains unchanged from the winding order of the initial geometric primitives of the previous primitive package of the subsequent primitive package processed by the target graphics processing core.

[0092] If it is determined at step 520 that the number of enabled graphics processing cores is odd, then at step 540 it is determined whether the serial number of the target graphics processing core is even.

[0093] If it is determined in step 540 that the sequence number of the target graphics processing core is even, then in step 570 it can be determined that the winding order of the initial geometric primitives of the initial primitive package processed by the target graphics processing core is the same as the pre-configured initial winding order, and the winding order of the initial geometric primitives of the subsequent primitive packages processed by the target graphics processing core after the initial primitive package is reversed compared to the winding order of the initial geometric primitives of the previous primitive package of the subsequent primitive package processed by the target graphics processing core.

[0094] If it is determined in step 540 that the sequence number of the target graphics processing core is odd, it can be determined in step 580 that the winding order of the initial geometric primitives of the initial primitive package processed by the target graphics processing core is reversed relative to the pre-configured initial winding order, and the winding order of the initial geometric primitives of the subsequent primitive package processed by the target graphics processing core after the initial primitive package is reversed relative to the winding order of the initial geometric primitives of the previous primitive package of the subsequent primitive package processed by the target graphics processing core.

[0095] The method 500 provides an efficient and universal mechanism for determining the winding order of the initial geometric primitives of the primitive package processed by the target graphics processing core.

[0096] As an example, the following table shows the specific winding order of the initial geometric primitives in the primitive packets under the four scenarios mentioned in steps 550-580. In the table below, CW indicates that the winding order of the initial geometric primitives is clockwise, and CCW indicates that the winding order of the initial geometric primitives is counterclockwise. The pre-configured initial winding order is CW, and the primitive packets 1-4 are all primitive packets processed by the target graphics processing core.

[0097] As can be seen from the above, the winding order of the initial geometric primitives of the primitive package processed by the target graphics processing core depends on the number of geometric primitives M in each primitive package (which is preset), the number of enabled graphics processing cores N, and the sequence number I of the target graphics processing core in this graphics processing process, where M is a positive integer, N is a positive integer less than 2, and I is greater than or equal to 0 and less than or equal to N-1.

[0098] In some embodiments, if the primitive package processed by the target graphics processing core is the initial primitive package to be processed by the target graphics processing core, the following steps are performed: if the product of the number M of geometric primitives in each primitive package and the sequence number I of the target graphics processing core in this graphics processing process (i.e., M*I) is even, it is determined that the winding order of the initial geometric primitives of the initial primitive package processed by the target graphics processing core is the same as the pre-configured initial winding order, wherein the pre-configured initial winding order indicates the winding order of the initial primitives of the primitive package in which the vertex index data is first divided; if the product of the number M of geometric primitives in each primitive package and the sequence number I of the target graphics processing core in this graphics processing process (i.e., M*I) is odd, it is determined that the winding order of the initial geometric primitives of the initial primitive package processed by the target graphics processing core is flipped relative to the pre-configured initial winding order.

[0099] If the primitive package processed by the target graphics processing core is a subsequent primitive package numbered after the initial primitive package, then the following steps are performed: If the product of the number of geometric primitives M and the number of enabled graphics processing cores N (i.e., M*N) in each primitive package is even, then the winding order of the initial geometric primitives in the subsequent primitive package remains unchanged compared to the winding order of the initial geometric primitives in the previous primitive package processed by the target graphics processing core; if the product of the number of geometric primitives M and the number of enabled graphics processing cores N (i.e., M*N) in each primitive package is odd, then the winding order of the initial geometric primitives in the subsequent primitive package is reversed compared to the winding order of the initial geometric primitives in the previous primitive package processed by the target graphics processing core.

[0100] As an example, in a triangle-band type topology where the graph does not have a reset point, assume vertex index data exists: A, B, C, D, E, F, G, H, I, J, K, and assume the pre-configured initial winding order is clockwise. This pre-configured initial winding order indicates the winding order of the initial primitives in the primitive packet where the vertex index data is first divided. This vertex index data can be generated automatically by the topology splitting module driven by the graph drawing command, or retrieved from the index buffer. With the number of geometric primitives M in each divided primitive packet set to 3, the first primitive packet (numbered 0) is A, B, C, D, E; the second primitive packet (numbered 1) is F, E, F, G, H; and the third primitive packet (numbered 2) is I, H, I, J, K.

[0101] In the example above, each primitive packet contains 3 geometric primitives. Assuming a graphics processing system includes 2 (even) enabled graphics processing cores, for all even-numbered graphics processing cores, i.e., graphics processing core 0, the situation corresponds to step 550 in Figure 5. That is, the winding order of the initial geometric primitives in the initial primitive packet is the same as the pre-configured initial winding order, always CW, and the winding order of the initial geometric primitives in subsequent primitive packets remains unchanged from the winding order of the initial geometric primitives in the preceding primitive packet, also being CW. Corresponding to this example, the first and third primitive packets are assigned to graphics processing core 0, and the winding order of their initial geometric primitives is CW. For graphics processing cores with odd sequence numbers, corresponding to step 560 of Figure 5, the winding order of the initial geometric primitives of the initial primitive packet is reversed relative to the pre-configured initial winding order, which is CCW, and the winding order of the initial geometric primitives of subsequent primitive packets remains unchanged from the winding order of the initial geometric primitives of the preceding primitive packet, which is also CCW. In this example, the second primitive packet is assigned to graphics processing core 1, and its initial geometric primitive winding order is CCW. If there is a fourth primitive packet (4), its initial geometric primitive winding order is also CCW, and it is assigned to graphics processing core 1.

[0102] Assuming a graphics processing system includes 3 (odd) enabled graphics processing cores, for all even-numbered graphics processing cores, namely graphics processing cores 0 and 2, corresponding to step 570 of Figure 5, the initial geometric primitive winding order of the initial primitive packet is the same as the pre-configured initial winding order, always CW, and the winding order of the initial geometric primitives of subsequent primitive packets is reversed relative to the winding order of the initial geometric primitives of the preceding primitive packet. For example, the first primitive packet is assigned to graphics processing core 0, and its initial geometric primitive winding order is CW. If there is a fourth primitive packet, it needs to be assigned to graphics processing core 0, and its initial geometric primitive winding order is reversed compared to the winding order of the first primitive packet, becoming CCW. If there is a seventh primitive packet, it is also assigned to graphics processing core 0, and its initial geometric primitive winding order is reversed compared to the winding order of the fourth primitive packet, becoming CW. For a graphics processing core with an odd-numbered sequence number, namely graphics processing core 1, corresponding to step 580 of Figure 5, the winding order of the initial geometric primitives of the initial primitive packet is reversed relative to the pre-configured initial winding order, and the winding order of the initial geometric primitives of subsequent primitive packets is reversed relative to the winding order of the initial geometric primitives of the preceding primitive packet. For example, a second primitive packet is assigned to graphics processing core 1, and its initial geometric primitive winding order is CCW. If a fifth primitive packet is assigned to graphics processing core 1, its initial geometric primitive winding order is reversed compared to the second primitive packet, becoming CW. If an eighth primitive packet is assigned to graphics processing core 1, its initial geometric primitive winding order is reversed compared to the fifth primitive packet, becoming CCW.

[0103] The above disclosure primarily describes the graphics processing method from the perspective of the topology splitting module. Correspondingly, the geometry processing pipeline module in the target graphics processing core can also execute the corresponding graphics processing method. For example, this method can be applied to a graphics processing system, which may include at least one target graphics processing core. Each target graphics processing core may include a topology splitting module, a geometry processing pipeline module, and a pixel processing pipeline module. The topology splitting module is used to divide vertex index data into multiple primitive packets according to a specified topology type, determine the primitive packets to be processed by the target graphics processing core from among the multiple primitive packets, and send them to the geometry processing pipeline module. The geometry processing pipeline module is used to process the received primitive packets to obtain geometric processing results and store the results. The pixel processing pipeline module is used to further process the geometric processing results to obtain a visualized graphic. In this way, different target graphics processing cores of the graphics processing system can process only a portion of the primitive packets. The geometry pipeline modules of different target graphics processing cores are independent of each other and do not need to communicate. The geometry pipeline modules of different target graphics processing cores can be located inside the same chip or on different small chips within the chip.

[0104] The vertex index data can be obtained from the index cache or generated by the topology splitting module. The specific methods used by the topology splitting module to divide the vertex index data into multiple primitive packets according to a specified topology type, to determine the orientation of the initial primitive when a reset point is available, and to determine the orientation of the initial primitive when no reset point is available, are as described above and will not be repeated here.

[0105] Similarly, the winding order of the initial geometric primitives of the primitive package processed by the target graphics processing core can be determined by the topology splitting module or the geometry pipeline module in the target graphics processing core.

[0106] Similarly, in some embodiments, in response to a reset point in the graph having a specified topology type, the winding order of the initial geometric primitives of the primitive package processed by the target graphics processing core is determined based on the previous reset point adjacent to the primitive package and a pre-configured initial winding order, wherein the pre-configured initial winding order indicates the winding order of the initial primitives of the primitive package where the vertex index data is first divided, and wherein the reset point indicates that there are no common vertices between the geometric primitive containing the vertex preceding the reset point and the geometric primitive containing the vertex following the reset point.

[0107] Similarly, in some embodiments, in response to the absence of a reset point in the graph having a specified topology type, and when the number of geometric primitives in each partitioned primitive package is configured to be even, the initial geometric primitive winding order of the primitive package processed by the target graphics processing core is determined to be a pre-configured initial winding order, wherein the pre-configured initial winding order indicates the initial primitive winding order of the primitive package in which the vertex index data is first partitioned, and wherein the reset point indicates that there are no common vertices between the geometric primitive containing the vertex preceding the reset point and the geometric primitive containing the vertex following the reset point.

[0108] Similarly, in some embodiments, in response to the absence of a reset point in the graph having a specified topology, and when the number of geometric primitives in each partitioned primitive package is configured to be odd, the number of the primitive package processed by the target graphics processing core is determined; in response to the determined primitive package number of the target graphics processing core being even, the winding order of the initial geometric primitives of the primitive package is determined to be a pre-configured initial winding order; in response to the determined primitive package number of the target graphics processing core being odd, the winding order of the initial geometric primitives of the primitive package is determined to be flipped relative to the pre-configured initial winding order; wherein the pre-configured initial winding order indicates the winding order of the initial primitives of the primitive package in which the vertex index data is first partitioned, and wherein the reset point indicates that there are no common vertices between the geometric primitive containing the vertex preceding the reset point and the geometric primitive containing the vertex following the reset point.

[0109] Similarly, in some embodiments, in response to the fact that the graph having a specified topology type does not have a reset point and the primitive package processed by the target graphics processing core is the initial primitive package to be processed by the target graphics processing core, the following steps are performed: if the product of the number of geometric primitives in each divided primitive package and the sequence number of the target graphics processing core in this graphics processing process is even, it is determined that the winding order of the initial geometric primitives of the initial primitive package processed by the target graphics processing core is the same as the pre-configured initial winding order, wherein the pre-configured initial winding order indicates the winding order of the initial primitives of the primitive package in which the vertex index data is first divided; if the product of the number of geometric primitives in each divided primitive package and the sequence number of the target graphics processing core in this graphics processing process is odd, it is determined that the winding order of the initial geometric primitives of the initial primitive package processed by the target graphics processing core is flipped relative to the pre-configured initial winding order. In response to the fact that the graph with the specified topology does not have a reset point and the primitive package processed by the target graphics processing core is a subsequent primitive package numbered after the initial primitive package, the following steps are performed: if the product of the number of geometric primitives in each partitioned primitive package and the number of enabled graphics processing cores is even, it is determined that the winding order of the initial geometric primitives of the subsequent primitive package remains unchanged compared to the winding order of the initial geometric primitives of the preceding primitive package processed by the target graphics processing core; if the product of the number of geometric primitives in each partitioned primitive package and the number of enabled graphics processing cores is odd, it is determined that the winding order of the initial geometric primitives of the subsequent primitive package is reversed compared to the winding order of the initial geometric primitives of the preceding primitive package processed by the target graphics processing core; wherein the reset point indicates that there are no common vertices between the geometric primitive containing the vertex preceding the reset point and the geometric primitive containing the vertex following the reset point.

[0110] The topology splitting module identifies the primitive packets to be processed by the target graphics processing core and determines the corresponding synchronization markers. It then sends the primitive packets and synchronization markers to the geometry pipeline module. Furthermore, the synchronization markers inserted by the topology splitting module for each primitive packet are stored along with the geometry processing results. This allows the pixel processing pipeline module to restore the order of the primitive packets based on the synchronization markers and generate the visualization graphics.

[0111] For example, the graphics processing method may first obtain the primitive package to be processed by the target graphics processing core and the corresponding synchronization marker, wherein the synchronization marker is used to mark the complete primitive package, and wherein the primitive package is obtained by the topology splitting module in the target graphics processing core dividing the vertex index data required to draw a graphic with a specified topology type according to the index order, wherein the vertex index data includes the index of the vertices of the graphic to be drawn, and wherein each primitive package divided by the topology splitting module included in the at least two enabled graphics processing cores includes the index of the vertices of the same predetermined number of geometric primitives, wherein the index of the vertices of the predetermined number of geometric primitives includes a portion of the vertex index data. Then, in response to the inconsistency in the winding order of geometric primitives in the graph having a specified topology, the graphics processing method can obtain a geometric processing result with a synchronization mark based on the primitive package to be processed by the target graphics processing core, the corresponding synchronization mark, and the initial winding order of the geometric primitives in the primitive package to be processed by the target graphics processing core. The geometric processing result with the synchronization mark is processed by the pixel processing pipeline module in the target graphics processing core to obtain a visual graph. The winding order of the geometric primitives in the graph indicates the connection order of the vertices of the geometric primitives when forming the geometric primitives, and the connection order includes one of clockwise and counterclockwise.

[0112] In some embodiments, when the winding order of geometric primitives in the graphic having a specified topology is inconsistent, when obtaining a geometric processing result with a synchronization mark based on the primitive package to be processed by the target graphics processing core, the corresponding synchronization mark, and the initial winding order of the geometric primitives in the primitive package to be processed by the target graphics processing core, the winding order of the predetermined number of geometric primitives in the primitive package to be processed by the target graphics processing core can be determined based on the initial winding order of the geometric primitives in the primitive package to be processed by the target graphics processing core, in response to the inconsistent winding order of geometric primitives in the graphic having a specified topology. If the winding order of any geometric primitive in the predetermined number of geometric primitives differs from the pre-configured initial winding order, the order of the vertex indices in that geometric primitive is adjusted to obtain an adjusted geometric primitive, such that the winding order of the adjusted geometric primitive is the same as the pre-configured initial winding order, wherein the pre-configured initial winding order indicates the initial winding order of the primitive package in which the vertex index data is first divided; based on the adjusted geometric primitive, the geometric primitives in the primitive package to be processed by the target graphics processing core whose winding order is the same as the pre-configured initial winding order, and the corresponding synchronization marker, a geometric processing result with synchronization marker is obtained.

[0113] As an example, when splitting primitives, the resulting primitives must all have the same orientation. This orientation is, for example, uniformly defined as clockwise. Given vertex indices of 0, 1, 2, 3, 4, 5, 6, 7, 8, 9…2n, 2n+1, 2n+2, 2n+3 and a triangle strip topology, triangle 0 / 1 / 2 is inherently clockwise, while triangle 1 / 2 / 3 is counter-clockwise. Therefore, triangle 1 / 3 / 2 needs to be adjusted to become clockwise. The reason for maintaining the same orientation for the split primitives is that only when the primitives have consistent orientations can the rendering process determine whether a primitive is facing the screen. Primitives facing away from the screen can be deleted without rendering.

[0114] In some embodiments, in response to inconsistencies in the winding order of geometric primitives in a graph with a specified topology, a geometric processing result with a synchronization mark is obtained based on the primitive package to be processed by the target graphics processing core, the corresponding synchronization mark, and the initial winding order of the geometric primitives in the primitive package to be processed by the target graphics processing core, and the geometric processing result with the synchronization mark is stored in a geometric processing result memory; wherein the geometric processing result with the synchronization mark is retrieved from the geometric processing result memory and processed by the pixel processing pipeline module in the target graphics processing core to obtain a visual graph.

[0115] Without violating logic, different embodiments of this application can be combined with each other. The descriptions of different embodiments have different focuses, and the parts not described in a particular focus can be referred to the descriptions of other embodiments.

[0116] In some embodiments of this disclosure, the functions or modules of the apparatus provided in the embodiments of this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation and technical effects can be referred to the description of the above method embodiments. For the sake of brevity, they will not be repeated here.

[0117] Figure 6 illustrates an exemplary structural block diagram of a graphics processing apparatus 600 according to an embodiment of the present disclosure. As shown in Figure 6, the graphics processing apparatus 600 includes a first acquisition module 610, a second acquisition module 620, a primitive packet determination module 630, and a transmission module 640.

[0118] The first acquisition module 610 is configured to acquire a graphics drawing command, which indicates that a graphic with a specified topology type should be drawn.

[0119] The second acquisition module 620 is configured to acquire vertex index data required for drawing the graphic based on the graphic drawing command, wherein the vertex index data is the index of the vertices of the graphic to be drawn.

[0120] The primitive package determination module 630 is configured to divide the vertex index data into primitive packages according to the specified topology type, in order of index, to determine the primitive packages to be processed by the target graphics processing core and insert corresponding synchronization markers, wherein the synchronization markers are used to mark the division order of the complete primitive packages, and wherein each primitive package divided by the topology splitting module of the at least two enabled graphics processing cores includes the same predetermined number of vertex indices of geometric primitives, the predetermined number of vertex indices of geometric primitives including a portion of the vertex index data.

[0121] The transmission module 640 is configured to transmit the primitive packet to be processed by the target graphics processing core and the corresponding synchronization mark to the geometry pipeline module in the target graphics processing core for processing, so as to obtain a geometry processing result with synchronization mark, wherein the geometry processing result with synchronization mark is processed by the pixel processing pipeline module in the target graphics processing core to obtain a visualization graphic.

[0122] Similarly, the graphics processing apparatus can also be implemented by a geometry processing pipeline module in the target graphics processing core. This graphics processing apparatus may include a primitive packet acquisition module and a geometry processing result determination module. The primitive packet acquisition module is configured to acquire the primitive packets to be processed by the target graphics processing core and the corresponding synchronization markers. The synchronization markers are used to mark complete primitive packets. The primitive packets are obtained by the topology splitting module in the target graphics processing core by dividing the vertex index data required to draw a graph with a specified topology type according to the index order. The vertex index data includes the indexes of the vertices of the graph to be drawn. Each primitive packet divided by the topology splitting modules of the at least two enabled graphics processing cores includes the indexes of the vertices of the same predetermined number of geometric primitives. The indexes of the vertices of the predetermined number of geometric primitives include a portion of the vertex index data. The geometry processing result determination module is configured to, in response to inconsistencies in the winding order of geometric primitives in a graph having a specified topology, obtain a geometry processing result with a synchronization mark based on the primitive package to be processed by the target graphics processing core, the corresponding synchronization mark, and the initial winding order of the geometric primitives in the primitive package to be processed by the target graphics processing core. The geometry processing result with the synchronization mark is then processed by the pixel processing pipeline module in the target graphics processing core to obtain a visual graph. The winding order of the geometric primitives in the graph indicates the connection order of the vertices of the geometric primitives when forming the geometric primitive, and the connection order includes either clockwise or counterclockwise.

[0123] Similarly, the graphics processing system may include at least two enabled graphics processing cores, and each of the at least two enabled graphics processing cores includes a topology splitting module, a geometry processing pipeline module, and a pixel processing pipeline module. The topology splitting module of the target graphics processing core is configured to divide the vertex index data required to draw a graph with a specified topology type according to index order to determine the primitive package to be processed by the target graphics processing core and insert corresponding synchronization markers. The synchronization markers are used to mark complete primitive packages. The vertex index data includes indexes of the vertices of the graph to be drawn, and each primitive package divided by the topology splitting module of the at least two enabled graphics processing cores includes the indexes of vertices of the same predetermined number of geometric primitives. The indexes of the vertices of the predetermined number of geometric primitives include a portion of the vertex index data. The geometry processing pipeline module of the target graphics processing core is configured to perform: obtaining the graph to be processed by the target graphics processing core. The graph includes a primitive packet and a corresponding synchronization marker; and, in response to an inconsistency in the winding order of geometric primitives in the graph having a specified topology, a geometric processing result with a synchronization marker is obtained based on the primitive packet to be processed by the target graphics processing core, the corresponding synchronization marker, and the initial winding order of the geometric primitives in the primitive packet to be processed by the target graphics processing core. The geometric processing result with the synchronization marker is then processed by a pixel processing pipeline module in the target graphics processing core to obtain a visual graph. The winding order of the geometric primitives in the graph indicates the connection order of the vertices of the geometric primitives when forming the geometric primitive, the connection order including clockwise and counterclockwise. The pixel processing pipeline module of the target graphics processing core is configured to process the geometric processing result to obtain a visual graph.

[0124] Figure 7 illustrates an example system 700, which includes an example computing device 710 representing one or more systems and / or devices that can implement the various technologies described herein. The computing device 710 may be, for example, a server of a service provider, a device associated with a server, a system-on-a-chip, and / or any other suitable computing device or computing system. The graphics processing apparatus 600 described above with reference to Figure 6 may take the form of computing device 710. Alternatively, the graphics processing apparatus 600 may be implemented as a computer program in the form of application 716.

[0125] The example computing device 710 shown includes a processing system 711 communicatively coupled to each other, one or more computer-readable media 712, and one or more I / O interfaces 713. Although not shown, the computing device 710 may also include a system bus or other data and command transfer system that couples the various components to each other. The system bus may include any or a combination of different bus architectures, such as a memory bus or memory controller, a peripheral bus, a universal serial bus, and / or a processor or local bus utilizing any of the various bus architectures. Various other examples, such as control and data lines, are also conceived.

[0126] Processing system 711 represents the functionality of performing one or more operations using hardware. Therefore, processing system 711 is illustrated as including hardware elements 714 that can be configured as processors, function blocks, etc. This may include application-specific integrated circuits (ASICs) or other logic devices formed using one or more semiconductors in the hardware. Hardware element 714 is not limited by the materials in which it is formed or the processing mechanism employed therein. For example, a processor may consist of semiconductors and / or transistors (e.g., integrated circuits (ICs)). In such a context, processor-executable instructions may be electronically executable instructions.

[0127] Computer-readable medium 712 is illustrated as including memory / storage device 715. Memory / storage device 715 represents a memory / storage capacity associated with one or more computer-readable media. Memory / storage device 715 may include volatile media (such as random access memory (RAM)) and / or non-volatile media (such as read-only memory (ROM), flash memory, optical disk, magnetic disk, etc.). Memory / storage device 715 may include fixed media (e.g., RAM, ROM, fixed hard disk drive, etc.) and removable media (e.g., flash memory, removable hard disk drive, optical disk, etc.). Computer-readable medium 712 may be configured in various other ways as further described below.

[0128] One or more I / O interfaces 713 represent the functionality to allow users to input commands and information to computing device 710 using various input devices and optionally also to present information to the user and / or other components or devices using various output devices. Examples of input devices include keyboards, cursor control devices (e.g., mice), microphones (e.g., for voice input), scanners, touch functionality (e.g., capacitive or other sensors configured to detect physical touch), cameras (e.g., capable of detecting non-touch-related motion as gestures using visible or invisible wavelengths (such as infrared frequencies), etc. Examples of output devices include display devices (e.g., monitors or projectors), speakers, printers, network interface cards, haptic-responsive devices, etc. Therefore, computing device 710 can be configured in various ways, as further described below, to support user interaction.

[0129] The computing device 710 also includes an application 716. The application 716 may be, for example, a software instance of the graphics processing device 600, and implements the techniques described herein in combination with other elements in the computing device 710.

[0130] This document describes various technologies within the general context of software and hardware components or program modules. Generally, these modules include routines, programs, objects, elements, components, data structures, etc., that perform specific tasks or implement specific abstract data types. As used herein, the terms "module," "function," and "component" generally refer to software, firmware, hardware, or a combination thereof. The technologies described herein are characterized as platform-independent, meaning that these technologies can be implemented on a variety of computing platforms with various processors.

[0131] Implementations of the described modules and technologies may be stored on or transmitted across some form of computer-readable medium. The computer-readable medium may include a variety of media accessible by the computing device 710. By way of example and not limitation, the computer-readable medium may include "computer-readable storage media" and "computer-readable signal media".

[0132] In contrast to simple signal transmission, carrier waves, or signals themselves, a "computer-readable storage medium" refers to a medium and / or device capable of persistently storing information, and / or a tangible storage device. Therefore, a computer-readable storage medium refers to a non-signal-bearing medium. Computer-readable storage media include hardware such as volatile and non-volatile, removable and non-removable media and / or storage devices implemented using methods or techniques suitable for storing information (such as computer-readable instructions, data structures, program modules, logic elements / circuits, or other data). Examples of computer-readable storage media may include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, DVD or other optical storage devices, hard disks, magnetic tape cassettes, magnetic tapes, disk storage devices or other magnetic storage devices, or other storage devices, tangible media, or articles of art suitable for storing desired information and accessible by a computer.

[0133] "Computer-readable signal medium" refers to a signal-bearing medium configured to transmit instructions, such as via a network, to computing device 710. A signal medium typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal, such as a carrier wave, data signal, or other transmission mechanism. Signal media also include any information transmission medium. The term "modulated data signal" refers to a signal in which one or more of its characteristics are set or altered to encode information. By way of example and not limitation, communication media include wired media such as wired networks or direct connections, and wireless media such as acoustic, RF, infrared, and other wireless media.

[0134] As previously described, hardware element 714 and computer-readable medium 712 represent instructions, modules, programmable device logic, and / or fixed device logic implemented in hardware, which in some embodiments can be used to implement at least some aspects of the techniques described herein. Hardware elements may include components of integrated circuits or systems-on-a-chip, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and other implementations or other hardware devices in silicon. In this context, hardware elements can serve as processing devices for executing program tasks defined by instructions, modules, and / or logic embodied by the hardware element, and as hardware devices for storing instructions for execution, such as the previously described computer-readable storage medium.

[0135] The foregoing combinations can also be used to implement the various techniques and modules described herein. Therefore, software, hardware, or program modules and other program modules can be implemented as one or more instructions and / or logic embodied on some form of computer-readable storage medium and / or by one or more hardware elements 714. The computing device 710 can be configured to implement specific instructions and / or functions corresponding to the software and / or hardware modules. Thus, for example, by using the computer-readable storage medium and / or hardware elements 714 of a processing system, modules can be implemented at least partially in hardware as modules executable as software by the computing device 710. Instructions and / or functions can be executable / operable by one or more articles of art (e.g., one or more computing devices 710 and / or processing systems 711) to implement the techniques, modules, and examples described herein.

[0136] In various embodiments, the computing device 710 can be configured in various ways. For example, the computing device 710 can be implemented as a computer-type device, including personal computers, desktop computers, multi-screen computers, laptop computers, netbooks, etc. The computing device 710 can also be implemented as a mobile device, including mobile devices such as mobile phones, portable music players, portable gaming devices, tablet computers, multi-screen computers, etc. The computing device 710 can also be implemented as a television-type device, including devices with or connected to a generally large screen in a leisure viewing environment. These devices include televisions, set-top boxes, game consoles, etc.

[0137] The techniques described herein can be supported by these various configurations of computing device 710, and are not limited to specific examples of the techniques described herein. Functionality can also be implemented, wholly or partially, on the “cloud” 720 using distributed systems, such as through platform 722 as described below.

[0138] Cloud 720 includes and / or represents platform 722 for resource 724. Platform 722 abstracts the underlying functionality of the hardware (e.g., server) and software resources of cloud 720. Resource 724 may include applications and / or data that can be used when performing computer processing on a server located remotely from computing device 710. Resource 724 may also include services provided via the Internet and / or via subscriber networks such as cellular or Wi-Fi networks.

[0139] Platform 722 can abstract resources and functions to connect computing device 710 to other computing devices. Platform 722 can also be used to abstract resource hierarchy to provide a corresponding level of hierarchy for any encountered needs for resource 724 implemented via platform 722. Therefore, in interconnect device embodiments, the implementation of the functions described herein can be distributed throughout system 700. For example, functions can be implemented partly on computing device 710 and partly through platform 722, which abstracts the functions of cloud 720.

[0140] This disclosure provides a computer-readable storage medium having computer-readable instructions stored thereon, which, when executed, implement any of the methods described above.

[0141] This disclosure provides a computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computing device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computing device to perform any of the methods provided in the various alternative implementations described above.

[0142] It should be understood that, for clarity, embodiments of this disclosure have been described with reference to different functional units. However, it will be apparent that, without departing from this disclosure, the functionality of each functional unit may be implemented in a single unit, in multiple units, or as part of other functional units. For example, functionality described as being performed by a single unit may be performed by multiple different units. Therefore, references to a particular functional unit are considered merely as references to the appropriate unit used to provide the described functionality, and not as indicating a strict logical or physical structure or organization. Thus, this disclosure may be implemented in a single unit, or may be physically and functionally distributed among different units and circuits.

[0143] It will be understood that although the terms first, second, third, etc., may be used herein to describe various devices, elements, components, or parts, these devices, elements, components, or parts should not be limited by these terms. These terms are used only to distinguish one device, element, component, or part from another device, element, component, or part.

[0144] Although this disclosure has been described in conjunction with some embodiments, it is not intended to be limited to the specific forms set forth herein. Rather, the scope of this disclosure is limited only by the appended claims. Additionally, although individual features may be included in different claims, these may be advantageously combined, and inclusion in different claims does not imply that such a combination of features is not feasible and / or advantageous. The order of features in the claims does not imply that the features must be in any particular order of their operation. Furthermore, in the claims, the word "comprising" does not exclude other elements, and the terms "a" or "an" do not exclude a plurality. Reference numerals in the claims are provided only by way of explicit example and should not be construed as limiting the scope of the claims in any way.

Claims

A graphics processing method, the method being executed by a topology splitting module in a target graphics processing core, the target graphics processing core being one of at least two enabled graphics processing cores in a graphics processing system, each of the at least two enabled graphics processing cores including a topology splitting module, a geometry processing pipeline module, and a pixel processing pipeline module, and the method comprising: Obtain a graphics drawing command, which indicates that a graph with a specified topology type should be drawn; Based on the graphics drawing command, obtain the vertex index data required to draw the graphics, the vertex index data including the indexes of the vertices of the graphics to be drawn; According to the specified topology type, the vertex index data is divided into primitive packets according to index order to determine the primitive packets to be processed by the target graphics processing core and insert corresponding synchronization markers, wherein the synchronization markers are used to mark complete primitive packets, and each primitive packet divided by the topology splitting module included in the at least two enabled graphics processing cores includes the same predetermined number of indexes of vertices of geometric primitives, wherein the indexes of vertices of the predetermined number of geometric primitives include a portion of the vertex index data; The primitive packet to be processed by the target graphics processing core and the corresponding synchronization mark are transmitted to the geometry pipeline module in the target graphics processing core for processing to obtain a geometry processing result with synchronization mark. The geometry processing result with synchronization mark is then processed by the pixel processing pipeline module in the target graphics processing core to obtain a visualization graphic. The method of claim 1, wherein, Based on the graphics drawing command, obtain the vertex index data required for drawing the graphics, including: Based on the graphics drawing command, retrieve the vertex index data required for drawing the graphics from the index buffer; or Based on the graphics drawing command, the vertex index data required to draw the graphics is generated. The method according to claim 1 or 2, wherein The graphics drawing command includes indication information indicating that the graphics to be drawn do not have reset points and source information related to the source of the index data acquisition. Furthermore, based on the graphics drawing command, the vertex index data required for drawing the graphics is obtained, including: In response to the source information indicating that the source of the index data is an index buffer, the vertex index data required for drawing the graphics is obtained from the index buffer, wherein the vertex index data in the index buffer is pre-generated by the application that issued the graphics drawing command; In response to the source information indicating that the index data will be generated automatically, vertex index data required for drawing the graphics is generated; The reset point indicates that there are no common vertices between the geometric primitive containing the vertex preceding the reset point and the geometric primitive containing the vertex following the reset point. The method according to claim 1 or 2, wherein The graphics drawing command includes indication information indicating that the graphics to be drawn have reset points, and, based on the graphics drawing command, obtains the vertex index data required to draw the graphics, including: Retrieve the vertex index data required for drawing the graphics from the index buffer, wherein the vertex index data in the index buffer is pre-generated by the application that issued the graphics drawing command; The reset point indicates that there are no common vertices between the geometric primitive containing the vertex preceding the reset point and the geometric primitive containing the vertex following the reset point. The method of any one of claims 1 to 4, wherein, Based on the specified topology type, the vertex index data is divided into primitive packets according to index order to determine the primitive packets to be processed by the target graphics processing core and insert corresponding synchronization markers, including: The primitive packets are numbered according to the order in which the vertex index data is divided, and the sequence number of the target graphics processing core among the at least two enabled graphics processing cores is determined during this graphics processing. If the remainder obtained by dividing the number of the partitioned primitive packet by the number of the at least two enabled graphics processing cores is the same as the serial number of the target graphics processing core, then the partitioned primitive packet is determined as the primitive packet to be processed by the target graphics processing core, and a corresponding synchronization tag is inserted. The method of any one of claims 1 to 5, wherein, The primitive packet to be processed by the target graphics processing core and the corresponding synchronization tag are transmitted to the geometry pipeline module in the target graphics processing core for processing to obtain a geometry processing result with synchronization tags, including: In response to the inconsistency in the winding order of geometric primitives in the graph with a specified topology, the primitive packet to be processed by the target graphics processing core and the corresponding synchronization mark are transmitted to the geometry pipeline module in the target graphics processing core, so that the geometry pipeline module obtains a geometry processing result with synchronization mark based on the primitive packet to be processed by the target graphics processing core, the corresponding synchronization mark, and the initial winding order of the geometric primitives of the primitive packet to be processed by the target graphics processing core; The winding order of the geometric primitives in the graphic indicates the connection order of the vertices of the geometric primitives when forming the geometric primitives, and the connection order includes one of clockwise and counterclockwise. The method of any one of claims 1 to 5, wherein, The primitive packet to be processed by the target graphics processing core and the corresponding synchronization tag are transmitted to the geometry pipeline module in the target graphics processing core for processing to obtain a geometry processing result with synchronization tags, including: In response to the inconsistency in the winding order of geometric primitives in the graph with a specified topology, the primitive package to be processed by the target graphics processing core and the corresponding synchronization mark are transmitted to the geometry pipeline module in the target graphics processing core. The geometry pipeline module obtains a geometry processing result with synchronization mark based on the primitive package to be processed by the target graphics processing core, the corresponding synchronization mark, and the initial winding order of the geometric primitives in the primitive package to be processed by the target graphics processing core, and stores the geometry processing result with synchronization mark in the geometry processing result memory. The geometric processing results with synchronization markers are retrieved from the geometric processing result memory and processed by the pixel processing pipeline module in the target graphics processing core to obtain a visual graphic. The winding order of the geometric primitives in the graphic indicates the connection order of the vertices of the geometric primitives when forming the geometric primitives, and the connection order includes one of clockwise and counterclockwise. The method according to claim 6 or 7, wherein The winding order of the initial geometric primitives of the primitive package processed by the target graphics processing core is determined in the following way: In response to a reset point in the graph having a specified topology type, the winding order of the initial geometric primitives of the primitive package processed by the target graph processing core is determined based on the previous reset point adjacent to the primitive package and a pre-configured initial winding order, wherein the pre-configured initial winding order indicates the winding order of the initial primitives of the primitive package where the vertex index data is first divided. The method according to claim 6 or 7, wherein The winding order of the initial geometric primitives of the primitive package processed by the target graphics processing core is determined in the following way: In response to the absence of a reset point in the graph having a specified topology type, and with the number of geometric primitives in each partitioned primitive package being configured to be even, the initial geometric primitive winding order of the primitive package processed by the target graph processing core is determined to be a pre-configured initial winding order, wherein the pre-configured initial winding order indicates the initial primitive winding order of the primitive package in which the vertex index data is first partitioned. The method according to claim 6 or 7, wherein The winding order of the initial geometric primitives of the primitive package processed by the target graphics processing core is determined by the following steps, which include: In response to the absence of a reset point in the graph with the specified topology type, and in the case where the number of geometric primitives in each partitioned primitive package is configured to be odd, the number of the primitive package processed by the target graph processing core is determined. In response to the fact that the primitive package number processed by the target graphics processing core is even, the winding order of the initial geometric primitives of the primitive package is determined to be a pre-configured initial winding order. In response to the fact that the primitive package number processed by the target graphics processing core is odd, the winding order of the initial geometric primitives of the primitive package is determined to be flipped relative to the pre-configured initial winding order. The pre-configured initial winding order indicates the initial winding order of primitives in the primitive packet where the vertex index data is first divided. The method according to claim 6 or 7, wherein The winding order of the initial geometric primitives of the primitive package processed by the target graphics processing core is determined by the following steps, which include: If the graph with the specified topology does not have a reset point and the primitive package processed by the target graph processing core is the initial primitive package to be processed by the target graph processing core, then the following steps are performed: If the product of the number of geometric primitives in each primitive package and the sequence number of the target graphics processing core in this graphics processing process is even, it is determined that the winding order of the initial geometric primitives in the initial primitive package processed by the target graphics processing core is the same as the pre-configured initial winding order, wherein the pre-configured initial winding order indicates the winding order of the initial primitives in the primitive package where the vertex index data is first divided. If the product of the number of geometric primitives in each primitive package and the sequence number of the target graphics processing core in this graphics processing process is odd, the winding order of the initial geometric primitives in the initial primitive package processed by the target graphics processing core is determined to be reversed relative to the pre-configured initial winding order. In response to the fact that the graph with the specified topology does not have a reset point and the primitive package processed by the target graph processing core is a subsequent primitive package numbered after the initial primitive package, the following steps are performed: If the product of the number of geometric primitives in each primitive packet and the number of enabled graphics processing cores is even, it is determined that the winding order of the initial geometric primitives of the subsequent primitive packet remains unchanged compared to the winding order of the initial geometric primitives of the previous primitive packet processed by the target graphics processing core. If the product of the number of geometric primitives in each primitive packet and the number of enabled graphics processing cores is odd, the winding order of the initial geometric primitives in the subsequent primitive packet is determined to be reversed compared to the winding order of the initial geometric primitives in the previous primitive packet processed by the target graphics processing core. The method of any one of claims 1 to 11, wherein, The method further includes: Obtain configuration information, which includes the number of geometric primitives in each primitive package, information indicating at least two enabled graphics processing cores among the multiple graphics processing cores included in the graphics processing system, and the sequence number of the at least two enabled graphics processing cores during this graphics processing. A graphics processing apparatus is implemented by a topology splitting module in a target graphics processing core, the target graphics processing core being one of at least two enabled graphics processing cores in a graphics processing system, each of the at least two enabled graphics processing cores including a topology splitting module, a geometry processing pipeline module, and a pixel processing pipeline module; and the graphics processing apparatus includes: The first acquisition module is configured to acquire a graphics drawing command, which indicates that a graphic with a specified topology type should be drawn. The second acquisition module is configured to acquire vertex index data required for drawing the graphic based on the graphic drawing command, wherein the vertex index data is the index of the vertices of the graphic to be drawn; The primitive package determination module is configured to divide the vertex index data into primitive packages according to the specified topology type, in order of index, to determine the primitive packages to be processed by the target graphics processing core and insert corresponding synchronization markers. The synchronization markers are used to mark the division order of the complete primitive packages, and each primitive package divided by the topology splitting module of the at least two enabled graphics processing cores includes the same predetermined number of indexes of vertices of geometric primitives. The indexes of vertices of the predetermined number of geometric primitives include a portion of the vertex index data. The transmission module is configured to transmit the primitive packet to be processed by the target graphics processing core and the corresponding synchronization mark to the geometry pipeline module in the target graphics processing core for processing, so as to obtain a geometry processing result with synchronization mark, wherein the geometry processing result with synchronization mark is processed by the pixel processing pipeline module in the target graphics processing core to obtain a visualization graphic. A graphics processing system includes at least two enabled graphics processing cores, and each of the at least two enabled graphics processing cores includes a topology splitting module, a geometry processing pipeline module, and a pixel processing pipeline module; wherein, The topology splitting module of the target graphics processing core in the at least two enabled graphics processing cores is configured to execute: Obtain a graphics drawing command, which indicates that a graph with a specified topology type should be drawn; Based on the graphics drawing command, obtain the vertex index data required to draw the graphics, the vertex index data including the indexes of the vertices of the graphics to be drawn; According to the specified topology type, the vertex index data is divided into primitive packets according to index order to determine the primitive packets to be processed by the target graphics processing core and insert corresponding synchronization markers, wherein the synchronization markers are used to mark complete primitive packets, and each primitive packet divided by the topology splitting module included in the at least two enabled graphics processing cores includes the same predetermined number of indexes of vertices of geometric primitives, wherein the indexes of vertices of the predetermined number of geometric primitives include a portion of the vertex index data; The primitive packet to be processed by the target graphics processing core and the corresponding synchronization mark are transmitted to the geometry pipeline module in the target graphics processing core for processing to obtain a geometry processing result with synchronization mark. The geometry processing result with synchronization mark is processed by the pixel processing pipeline module in the target graphics processing core to obtain a visualization graphic. The geometry processing pipeline module of the target graphics processing core is configured to obtain geometry processing results based at least on the primitive package to be processed by the target graphics processing core and the corresponding synchronization marker; The pixel processing pipeline module of the target graphics processing core is configured to process the geometric processing results to obtain a visual graphic. A computing device, the computing device comprising: Memory, which is configured to store computer-executable instructions; A processor configured to perform the method as described in any one of claims 1-12 when the computer-executable instructions are executed by the processor. A computer-readable storage medium storing computer-executable instructions that, when executed, perform the method as described in any one of claims 1-12. A computer program product comprising computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is executed in a processor of an electronic device, the processor in the electronic device performs the method for implementing any one of claims 1-12.

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