An SRAM in-memory calculation circuit that uses redundant row quantization of bit line voltage differences
By using a redundant row quantization bit line voltage difference SRAM in-memory calculation circuit, the problems of voltage gradient variation affecting calculation results and excessive area consumption in the prior art are solved, achieving efficient quantization and determination of calculation results.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-09-15
- Publication Date
- 2026-03-10
AI Technical Summary
Existing SRAM in-memory computing technologies lack effective quantization schemes, which cannot effectively reduce the impact of voltage gradient changes caused by factors such as word line pulse width distortion in the array on the calculation results, and also have the problem of excessive area consumption.
The SRAM in-memory calculation circuit employs redundant row quantization bit line voltage difference. Through a row decoding module, a precharge circuit, a timing control circuit, a word line data control module, a redundant row control circuit, and a quantization result statistics circuit, the calculation result is determined by using the redundant row control circuit and the quantization result statistics circuit, thereby reducing the impact of voltage gradient changes in the array and reducing area consumption.
It effectively reduces the impact of voltage gradient changes caused by factors such as word line pulse width distortion on the calculation results, reduces area consumption, and improves quantization accuracy and calculation efficiency.
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Figure CN115472197B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of integrated circuits, and in particular to an SRAM in-memory computing circuit for quantifying bit line voltage difference through redundant rows. BACKGROUND
[0002] With the rapid development of science and technology, the rapid development of application fields such as machine learning, image recognition and edge computing, a large amount of data needs to be transmitted between the memory and the processor, but in the traditional von Neumann architecture, the processor computing unit and the memory are separated, which cannot meet the frequent access demand. Due to the rapid development of Moore's law, the running speed of the memory is out of sync with the speed of the processor, and the access speed of the memory lags far behind the computing speed of the processor, and the memory performance has become an important bottleneck of the overall computer performance, and this bottleneck is particularly obvious in the field of machine learning and image recognition, such as convolutional neural network. The birth of in-memory computing (CIM) technology breaks through the von Neumann bottleneck and breaks the "memory wall" in the traditional computing architecture. In-memory computing does not need to transfer data to the processor, but directly performs operations in the memory, greatly reducing the energy consumption of the access in the computing process, and improving the computing speed and energy efficiency, so it has revolutionary significance for the "computing power era".
[0003] Because the static random access memory (SRAM) has fast data reading speed and good compatibility with advanced logic process, the in-memory computing technology based on SRAM has attracted attention from domestic and foreign scholars. The existing in-memory technology can realize Boolean logic operation, multiplication operation and addition operation and other algorithms in the internal unit of SRAM, and the operation results are mostly obtained by quantizing the bit line discharge amount through ADC. In the current SRAM in-memory computing quantization technology, whether it is Flash ADC / successive approximation ADC or digital circuit assisted ADC, the bit line operation result is quantized, and a compromise is made among area, power consumption and precision, and there is a lack of effective solution for in-memory computing. SUMMARY
[0004] The purpose of the present application is to provide an SRAM in-memory computing circuit for quantizing bit line voltage difference through redundant rows, which can realize quantization of bit line voltage difference and determination of calculation result in SRAM, effectively reduce the influence of voltage gradient change caused by word line pulse width distortion and other factors in the array on the calculation result, and reduce the area consumption.
[0005] The purpose of the present application is realized by the following technical scheme:
[0006] An SRAM in-memory computing circuit for quantizing bit line voltage difference of redundant rows, the circuit comprising a row decoding module, a pre-charge circuit, a timing control circuit, a word line data control module, a redundant row control circuit and a quantization result statistics circuit, and an SRAM memory array, wherein:
[0007] The timing control circuit is connected with the row decoding module, the word line data control module, the pre-charge circuit, and the redundant row control circuit and the quantization result statistics circuit, respectively;
[0008] The timing control circuit is used to generate clock signals required by each functional module;
[0009] The row decoding module is connected with the word line data control module, and is used to decode input signals, whose output signals in turn control the word line data control module;
[0010] The word line data control module is used to control the opening or closing of word lines in the SRAM memory array;
[0011] The pre-charge circuit is used to pre-charge bit lines BL and BLB, i.e. to charge the bit lines BL and BLB to a power supply voltage before computing;
[0012] The redundant row control circuit and the quantization result statistics circuit are used to control the opening or closing of redundant rows and to count quantization results;
[0013] The SRAM memory array is connected with the word line data control module, the pre-charge circuit, and the redundant row control circuit and the quantization result statistics circuit;
[0014] The SRAM memory array is an N*N row 6T SRAM memory unit, specifically comprising two redundant rows and a plurality of computing rows, and each of the redundant rows and the computing rows comprises a plurality of 6T SRAM memory units; a bit line BL in each column is connected with the left end of the 6T SRAM memory unit and the redundant row unit, connected with the pre-charge circuit at the upper end, and connected with a sensitive amplifier SA at the left port at the lower end; a bit line BLB in each column is connected with the right end of the 6T SRAM memory unit and the redundant row unit, connected with the pre-charge circuit at the upper end, and connected with the sensitive amplifier SA at the right port at the lower end;
[0015] Before computing, the timing control circuit and the pre-charge circuit pre-charge the two bit lines BL and BLB to a high level; after the word line is opened, in the 64 6T SRAM memory units controlled by the word line WL, if Q=0 and QB=1, the bit line BL discharges the 6T SRAM memory unit; otherwise, if Q=1 and QB=0, the bit line BLB discharges the 6T SRAM memory unit; wherein Q and QB are values stored in the 6T unit in the SRAM memory array;
[0016] After the discharge, the high and low of the voltages of the two bit lines BL and BLB are compared by the sense amplifier SA at the bottom of the bit line, and the output result of the sense amplifier SA is controlled by the redundant row control circuit and the quantization result statistical circuit to control the redundant row to discharge the bit line with higher voltage until the output result of the sense amplifier SA is reversed, which means that the quantization of the voltage difference of the bit line by the redundant row is completed, and then the calculation result is obtained by the redundant row control circuit and the quantization result statistical circuit.
[0017] As can be seen from the technical solutions provided by the above-mentioned application, the above-mentioned circuit can realize the quantization of the voltage difference of the bit line and determine the calculation result in the SRAM, effectively reducing the influence of the voltage gradient change caused by the word line pulse width distortion and other factors in the array on the calculation result, and reducing the area consumption. BRIEF DESCRIPTION OF DRAWINGS
[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0019] Figure 1 The structure schematic diagram of the SRAM in-memory calculation circuit for quantizing the voltage difference of the bit line by the redundant row is provided for the embodiments of the present application;
[0020] Figure 2 The structure schematic diagram of each row of the SRAM memory array is provided for the embodiments of the present application;
[0021] Figure 3 The quantization process schematic diagram is provided for the embodiments of the present application, taking the storage unit of 4*1 and two redundant row units as an example;
[0022] Figure 4 The function test simulation diagram is provided for the embodiments of the present application. DETAILED DESCRIPTION
[0023] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all the embodiments, which do not constitute a limitation to the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.
[0024] As Figure 1The diagram shows a schematic of an SRAM in-memory calculation circuit structure for quantizing bit line voltage differences using redundant rows, as provided in an embodiment of the present invention. The circuit includes a row decoding module, a pre-charge circuit, a timing control circuit, a word line data control module, a redundant row control circuit and a quantization result statistics circuit, and an SRAM memory array (including a sensitive amplifier connected to the bottom of the bit lines).
[0025] The timing control circuit is connected to the row decoding module, the word line data control module, the precharge circuit, the redundant row control circuit, and the quantization result statistics circuit, respectively.
[0026] The timing control circuit is used to generate the clock signals required by each functional module.
[0027] The row decoding module is connected to the word line data control module. The row decoding module is used to decode the input signal, and its output signal controls the word line data control module.
[0028] The word line data control module is used to control the opening or closing of word lines in the SRAM storage array.
[0029] The pre-charging circuit is used to pre-charge the bit lines BL and BLB, that is, to charge the bit lines BL and BLB to the power supply voltage before performing calculations.
[0030] The redundant row control circuit and the quantization result statistics circuit are used to control the opening or closing of the redundant rows and to perform statistics on the quantization results.
[0031] The SRAM storage array is connected to the word line data control module, the precharge circuit, the redundant row control circuit, and the quantization result statistics circuit.
[0032] The SRAM storage array is an N*N row 6T SRAM storage unit, specifically containing two redundant rows and several calculation rows (such as...). Figure 1 The array is a 64*64 array, with redundant rows and computation rows each containing multiple 6T SRAM memory cells. One of the two redundant rows stores all "1"s (Q=1, QB=0), and the other row stores all "0"s (Q=0, QB=1). All word lines in the redundant rows are turned off during computation. The bit line BL in each column is connected to the left end of the 6T SRAM memory cell and the redundant row cell, with its upper end connected to the pre-charge circuit and its lower end connected to the left port of the sensitive amplifier SA. The bit line BLB in each column is connected to the right end of the 6T SRAM memory cell and the redundant row cell, with its upper end connected to the pre-charge circuit and its lower end connected to the right port of the sensitive amplifier SA.
[0033] by Figure 1For example, in the middle left first column, before the calculation, the timing control circuit and the pre-charge circuit first pre-charge the two bit lines BL and BLB to a high level; after the word line is opened, in the 64 6T SRAM memory units controlled by the word line WL, if Q=0, QB=1 (for example, as shown in the 6T unit in the middle, Q and QB are the values stored in the 6T unit in the storage array), the bit line BL discharges the 6T SRAM memory unit; otherwise, if Q=1, QB=0, the bit line BLB discharges the 6T SRAM memory unit; Figure 2
[0034] After the discharge is completed, the sensitive amplifier SA at the bottom of the bit line compares the high and low of the voltages of the two bit lines BL and BLB, and the redundant row control circuit and the quantization result statistical circuit control the redundant row to discharge the bit line with a higher voltage according to the output result of the sensitive amplifier SA until the output result of the sensitive amplifier SA flips, which means that the quantization of the voltage difference of the bit line by the redundant row is completed, and then the calculation result is obtained through the redundant row control circuit and the quantization result statistical circuit.
[0035] As shown in FIG. 1, the structure of the SRAM storage array of the embodiment of the present application is shown, and each column of the SRAM storage array includes 64 6T SRAM memory units as a calculation row, two 6T SRAM memory units as a redundant row, and a sensitive amplifier SA, wherein: Figure 2
[0036] The left side of all the 6T SRAM memory units is connected by the bit line BL, and the right side is connected by the bit line BLB;
[0037] The calculation row is connected with the word line WL<63>, WL<62>…WL<0> respectively;
[0038] The redundant row is connected with the word line W0, W1 respectively;
[0039] The left end of the sensitive amplifier SA is connected with the bit line BL, and the right end is connected with the bit line BLB.
[0040] The structure of a single 6T SRAM memory unit is shown in FIG. 2, and as shown by the dashed box on the right side, the single 6T SRAM memory unit includes two cross-coupled inverters I0 and I1 and two NMOS transistors N0 and N1; Figure 2
[0041] The inverters I0 and I1 are composed of four transistors, wherein the inverters I0 and I1 are each composed of an NMOS transistor and a PMOS transistor, and wherein:
[0042] The gate of the NMOS transistor N0 and the gate of the NMOS transistor N1 are connected with the word line signal WL;
[0043] The source of the NMOS transistor N0 is connected with the bit line signal BL, and the drain of the NMOS transistor N0 is connected with the input terminal point Q of the inverter I0;
[0044] The source of the NMOS transistor N1 is connected with the bit line signal BLB, and the drain of the NMOS transistor N1 is connected with the input terminal point QB of the inverter I1;
[0045] The output terminal of the inverter I0 is connected with the input terminal point QB of the inverter I1, and the output terminal of the inverter I1 is connected with the input terminal point Q of the inverter I0.
[0046] Based on the circuit structure, for example, the figure is a 64*64 array, and two redundant rows are additionally added below the traditional 6T array; one row stores all "1" (Q=1, QB=0), such as H0, H1…H63 in the figure; the other row stores all "0" (Q=0, QB=1), such as L0, L1…L63 in the figure, and the redundant row word lines are all closed in the calculation process. Figure 1 Figure 1 Figure 1
[0047] Before the calculation, the two bit lines BL and BLB are pre-charged to a high level (Vdd), and after the word line is opened, if Q=0, QB=1, the bit line BL discharges the storage unit; if Q=1, QB=0, the bit line BLB discharges the storage unit. That is, if there are n word lines opened, there are n storage units discharged, and the total discharge amount is bΔV.
[0048] In the calculation process, it is assumed that there are n word lines opened in the calculation process, the discharge amount of the bit line BL is Vdd-VBL, the discharge amount of the bit line BLB is Vdd-VBLB, and Vdd is pre-charged to a high level, then:
[0049]
[0050] Wherein, n is the number of opened word lines WL; m is the quantized bit line voltage difference; ΔV is the discharge amount;
[0051] The positive and negative of the absolute value in formula ② is determined by the first comparison result of the sensitive amplifier SA, specifically:
[0052] If VBL<VBLB, the output result of the sensitive amplifier SA is SA_out=0, formula ② is positive, then:
[0053]
[0054] If VBL>VBLB, the output result of the sensitive amplifier SA is SA_out=1, formula ② is negative, then:
[0055]
[0056] Therefore, the final calculated result, i.e., the bit line discharge amount, can be quantified as or Since n is known, as long as the sense amplifier SA is used to compare and discharge the bit line with a higher voltage using redundant rows simultaneously, and the bit line voltage difference mΔV is quantified, the calculated result (the discharge amount of bit lines BL / BLB) can be obtained.
[0057] In addition, assuming the calculation is completed and the word line WL is turned off, the bit lines BL and BLB are partially discharged respectively. Through the first comparison by SA, if VBL < VBLB, then SA_out = 0. At this time, open Figure 1 the redundant row H0 in the first column to make the bit line BLB discharge a ΔV to its storage cell; if still VBL < VBLB, then SA_out = 0, and repeat the above operation until VBL > VBLB and SA_out = 1, and the output of SA has a flip point, which means the quantization is completed. Counting the number of SA_out = 0 is the required m. For the case of VBL > VBLB, it is the opposite, and the principle is the same; it should be noted that the pulse width of the redundant row opening should be slightly wider than the pulse width of the word line WL to meet the condition for the final flip of SA_out.
[0058] Compared with the traditional ADC quantization, this method of quantifying the bit line voltage difference through redundant rows reduces the quantization complexity on the one hand. When the difference in the number of "1" and "0" in the storage array is not particularly large, only a small part of the discharge amount needs to be quantified to obtain the final calculated result; on the other hand, the quantization result is determined by the number of "0" or "1" output by SA, and the subsequent circuit can be completely implemented by a counter to count the quantization result, and the quantization accuracy will be greatly improved; more importantly, the redundant row can better follow the discharge amount of the cells in the storage array under different bit line voltages, can generate an adaptive ΔV, and compared with the traditional ADC quantization, it can effectively reduce the influence of the voltage gradient change caused by factors such as word line pulse width distortion in the array on the calculated result and reduce the area consumption.
[0059] As Figure 3 shown is a schematic diagram of the quantization process taking a 4*1 storage cell and two redundant row cells provided by an embodiment of the present invention as an example (where, Q3Q2Q1Q0 = 0100, QB3QB2QB1QB0 = 1011). According to Figure 3 the principle of quantifying the bit line voltage difference by redundant rows is described as follows:
[0060] (1) The two bit lines are pre-charged to high level by prec, the word line WL[3:0] is opened, and BL and BLB are discharged at the same time. The discharge amount of BL is Vdd-VBL=3ΔV, and the discharge amount of BLB is Vdd-VBLB=1ΔV. The voltage difference between the two bit lines is VBLB-VBL=2ΔV. Therefore, the first comparison result of SA is SA_out=0, which means that the absolute value of formula ② is positive.
[0061] (2) SA_out=0 means that the voltage of bit line VBLB is relatively high. The redundant row W1 is opened (W1=1), and BLB is discharged by 1ΔV. At this time, the discharge amount of BLB is Vdd-VBLB=2ΔV, and the voltage difference between the two bit lines is VBLB-VBL=1ΔV. The second comparison result of SA is SA_out=0.
[0062] (3) Similarly, SA_out=0, the redundant row W1 is opened (W1=1), and BLB is discharged by 1ΔV. At this time, the discharge amount of BLB is Vdd-VBLB=3ΔV, and the voltage difference between the two bit lines is VBLB-VBL<0 (in fact, since the pulse width of W1 we set is slightly wider than the pulse width of the word line, the discharge amount will be slightly larger than 3ΔV). The third comparison result of SA is SA_out=1.
[0063] (4) SA_out=1, the output of SA reaches the flip point, which means that the quantization of the voltage difference between the two bit lines is completed. The timing waveform diagram is as follows: Figure 3 At this time, as long as the number of SA_out=0 is counted, the value of m can be obtained. Obviously, in this example, m=2, and the discharge amount of bit line BL can be quantized as
[0064] It is worth noting that the above process is carried out under the condition that the number of "0" and "1" in the storage array is different. Obviously, another case will occur, that is, when the same column has the same number of "0" and "1" when the even row word line is opened, the discharge amount of BL and BLB is consistent, and the output result of SA has uncertainty, which can be 0 or 1, but this can be solved, because the sum of two integers is even, and the difference is also even. Take 4 as an example, it can be split into these integer combinations: 4+0, 3+1 and 2+2. When the 4 row word line is opened and the storage cells therein store 2 "1"s and 2 "0"s respectively, the first comparison result of SA will output 0 or 1, at this time the redundant row W1 or W0 will be opened to discharge the bit line, no matter which bit line is discharged, the output result SA_out of the second comparison of SA will reach the flip point, that is, only one redundant row is opened to discharge; and for the number of "1" and "0" stored in the unit is different (4+0 or 3+1), it is obvious that at least two redundant rows need to be opened to discharge the bit line to get the quantization result. The judgment of these two cases can be easily determined from the number of opened word lines n and the number of opened redundant rows (or the flip time of SA_out).
[0065] In order to more clearly show the technical solutions provided by the present application and the technical effects produced, the above examples are simulated and verified, as shown in the following table: Figure 4 The figure shows the functional test simulation diagram provided by the embodiment of the present application:
[0066] At the same time, 4 row word lines (WL<63:60>) are opened, and the data stored in the storage unit is Q63Q62Q61Q60=0100, QB63QB62QB61QB60=1011. The word line (WL<63:60>) voltage is set to 600mv, and the opening time is 100ps; the redundant row word line (W1) voltage is set to 600mv, and the opening time is 103ps.
[0067] First, the two bit lines are pre-charged to high level by preck, the word line WL[63:60] is opened, and the bit lines BL and BLB are discharged at the same time. The discharge amount of BL is Vdd-VBL=3ΔV, the discharge amount of BLB is Vdd-VBLB=1ΔV, the bit line voltage difference VBLB-VBL=2ΔV, the enable signal SAEN of the sensitive amplifier SA is opened for the first time, and since VBLB>VBL, the output result DOUT of the sensitive amplifier SA is 0 (DOUT_BAR=1). At this time, the redundant row W1 is opened to discharge the bit line BLB by 1ΔV. At this time, the discharge amount of BL is Vdd-VBL=3ΔV, the discharge amount of BLB is Vdd-VBLB=2ΔV, the bit line voltage difference VBLB-VBL=ΔV, the enable signal SAEN of the sensitive amplifier SA is opened for the second time, and since VBLB>VBL, the output result DOUT of the sensitive amplifier SA is 0 (DOUT_BAR=1). At this time, the redundant row W1 is opened to discharge the bit line BLB by 1ΔV. At this time, the discharge amount of BLB is Vdd-VBLB=3ΔV, and the bit line voltage difference VBLB-VBL<0 (actually, since the pulse width (103ps) of W1 is slightly wider than the pulse width (100ps) of the word line, the discharge amount is slightly greater than 3ΔV). The enable signal SAEN of the sensitive amplifier SA is opened for the third time, and the output result DOUT of the sensitive amplifier SA is 1 (DOUT_BAR=0). The output result of the sensitive amplifier SA is flipped to represent that the redundant row quantifies the bit line voltage difference, and the number of results of DOUT=0 is 2, that is, the bit line voltage difference is 2ΔV, so the discharge amount of the bit line BL can be quantified as
[0068] It is to be noted that the contents not described in detail in the embodiments of the present application belong to the prior art known to the person skilled in the art.
[0069] The above description is only the preferred embodiment of the present application, but the protection scope of the present application is not limited to this. Any change or replacement within the technical range disclosed in the present application can be easily thought by the person skilled in the art, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be limited by the protection scope of the claims. The information disclosed in the background section of the present application is only intended to deepen the understanding of the general background of the present application, and should not be regarded as acknowledging or implying in any form that the information constitutes the prior art known to the person skilled in the art.
Claims
1. An SRAM in-memory calculation circuit that uses redundant row quantization of bit line voltage differences, characterized in that, The circuit comprises a row decoding module, a pre-charge circuit, a timing control circuit, a word line data control module, a redundant row control circuit and a quantization result statistics circuit, and an SRAM storage array, wherein: The timing control circuit is connected with the row decoding module, the word line data control module, the pre-charge circuit and the redundant row control circuit and the quantization result statistics circuit respectively; The timing control circuit is used to generate clock signals required by each functional module; The row decoding module is connected with the word line data control module, and is used to decode input signals, and the output signals of the row decoding module further control the word line data control module; The word line data control module is used to control the opening or closing of word lines in the SRAM storage array; The pre-charge circuit is used to pre-charge bit lines BL and BLB, i.e. to charge the bit lines BL and BLB to a power supply voltage before calculation; The redundant row control circuit and the quantization result statistics circuit are used to control the opening or closing of redundant rows and to count quantization results; The SRAM storage array is connected with the word line data control module, the pre-charge circuit and the redundant row control circuit and the quantization result statistics circuit; The SRAM storage array is an N*N row 6T SRAM storage unit, specifically comprising two redundant rows and a plurality of calculation rows, and each of the redundant rows and the calculation rows comprises a plurality of 6T SRAM storage units; a bit line BL in each column is connected with the left end of the 6T SRAM storage unit and the redundant row unit, connected with the pre-charge circuit at the upper end, and connected with a sensitive amplifier SA at the lower end; a bit line BLB in each column is connected with the right end of the 6T SRAM storage unit and the redundant row unit, connected with the pre-charge circuit at the upper end, and connected with the sensitive amplifier SA at the lower end; Before calculation, the timing control circuit and the pre-charge circuit pre-charge the two bit lines BL and BLB to a high level; after the word line is opened, in the 64 6T SRAM storage units controlled by the word line WL, if Q=0 and QB=1, the bit line BL discharges the 6T SRAM storage unit; otherwise, if Q=1 and QB=0, the bit line BLB discharges the 6T SRAM storage unit; wherein Q and QB are values stored in the 6T unit in the SRAM storage array; After the discharge is completed, the sensitive amplifier SA at the bottom of the bit line compares the high and low of the voltages of the two bit lines BL and BLB, and the redundant row control circuit and the quantization result statistics circuit control the redundant row to discharge the bit line with a higher voltage according to the output result of the sensitive amplifier SA until the output result of the sensitive amplifier SA flips, which means that the redundant row completes the quantization of the voltage difference of the bit line, and then the calculation result is obtained through the redundant row control circuit and the quantization result statistics circuit.
2. The SRAM in-memory computing circuit that quantifies the bit line voltage difference by redundancy rows of claim 1, wherein, Each column of the SRAM storage array comprises 64 6T SRAM storage units as calculation rows, two 6T SRAM storage units as redundant rows, and one sensitive amplifier SA, wherein: The left side of all the 6T SRAM storage units is connected with the bit line BL, and the right side is connected with the bit line BLB; The computing rows are connected with word lines WL<63>, WL<62>…WL<0> respectively; The redundant rows are connected with word lines W0, W1 respectively; The left end of the sensitive amplifier SA is connected with the bit line BL, and the right end is connected with the bit line BLB.
3. The SRAM in-memory computing circuit that quantifies the bit line voltage difference by redundancy rows of claim 1, wherein, The single 6T SRAM memory cell includes two cross-coupled inverters I0 and I1, and two NMOS transistors N0 and N1; The inverters I0 and I1 are composed of 4 transistors, wherein the inverters I0, I1 are each composed of an NMOS transistor and a PMOS transistor, wherein: The gate of the NMOS transistor N0 and the gate of the NMOS transistor N1 are connected with the word line signal WL; The source of the NMOS transistor N0 is connected with the bit line signal BL, and the drain of the NMOS transistor N0 is connected with the input end point Q of the inverter I0; The source of the NMOS transistor N1 is connected with the bit line signal BLB, and the drain of the NMOS transistor N1 is connected with the input end point QB of the inverter I1; The output end of the inverter I0 is connected with the input end point QB of the inverter I1, and the output end of the inverter I1 is connected with the input end point Q of the inverter I0.
4. The SRAM in-memory computing circuit that quantifies the bit line voltage difference by redundancy rows of claim 1, wherein, Based on the circuit structure, in the calculation process, assuming that there are n word lines opened in the calculation process, the discharge amount of the bit line BL is Vdd-VBL, the discharge amount of the bit line BLB is Vdd-VBLB, and Vdd is the pre-charged high level, then: Wherein, n is the number of opened word lines; m is the quantized bit line voltage difference; ΔV is the discharge amount; The positive and negative of the absolute value in formula ② is determined by the first comparison result of the sensitive amplifier SA, specifically: If VBL<VBLB, then the output result of the sensitive amplifier SA is SA_out=0, formula ② is positive, then: If VBL>VBLB, then the output result of the sensitive amplifier SA is SA_out=1, formula ② is negative, then: If VBL<VBLB, then the output result of the sensitive amplifier SA is SA_out=0, formula ② is positive, then: If VBL>VBLB, then the output result of the sensitive amplifier SA is SA_out=1, formula ② is negative, then: Therefore, the final calculation result, i.e., the discharge amount of the bit line, can be quantified as or Since n is known, the calculation result can be obtained by comparing the voltages of the bit lines using the redundant row pair through the sensitive amplifier SA and discharging the bit line with a higher voltage, and quantifying the bit line voltage difference mΔV.