Oxide semiconductor semi-floating gate transistor memory and methods of programming, erasing and reading thereof

Abstract

The application belongs to the technical field of semiconductor integrated circuits, and particularly relates to an oxide semiconductor semi-floating gate transistor memory and a programming, erasing and reading method thereof. The memory unit is embedded with an n-type oxide semiconductor thin film in a gate dielectric layer of a p-type floating gate transistor (p-FGT), the oxide semiconductor thin film is connected with a drain of the p-FGT, simultaneously connects a floating gate of the p-FGT, and forms an n-type oxide semiconductor thin film transistor (n-OSTFT) embedded in the gate dielectric of the p-FGT through a shared gate and part of the gate dielectric of the p-FGT. The memory has non-volatility. The memory unit can be used to construct a memory chip in a NOR architecture circuit or a NAND architecture circuit, and the erasing, writing and reading operations can be realized in both architectures. The disclosed memory has good compatibility with the process and architecture of existing commercial memories, fast erasing and writing speed, long storage time, and has a practical and broad application prospect.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit technology, specifically relating to an oxide semiconductor semi-floating gate transistor memory and its programming, erasing and reading methods. Background Technology

[0002] Floating-gate transistor memory (Floating-gate transistor memory) retains the charge stored in its floating gate for years after power loss without requiring refresh, making it a type of non-volatile memory. These memory cells can be connected in parallel or series to construct memory chips, namely NOR Flash or NAND Flash. The former offers faster operation speeds, while the latter boasts higher storage density. Currently, Floating-gate transistor memory is widely used in solid-state drives (SSDs) and USB flash drives. However, Floating-gate transistor memory typically relies on Fowler-Nordheim (FN) tunneling for programming and erasing, requiring write / erase voltages exceeding 10V and programming / erase times on the order of 1ms, resulting in slow data processing speeds and high power consumption. With the advent of the big data era, there is an urgent need to develop a non-volatile memory with low write / erase voltages and fast write / erase speeds.

[0003] The design, which connects another transistor to the floating gate in the floating-gate transistor memory, allows charge injection and removal from the floating gate to be based on the charging and discharging of the capacitance formed by the floating gate and the gate, rather than on the FN tunneling mechanism, when the other transistor is turned on. This design promises to significantly improve the erase and write speeds of the memory, but it also introduces new problems: first, the leakage current of the other transistor must be extremely low; otherwise, the stored charge in the floating gate will rapidly leak out through the channel of that transistor, significantly reducing the memory's retention time; second, the structure of the memory cell must be sufficiently optimized to be compatible with current memory circuit architectures, especially NAND architectures, otherwise the density of the memory chip will be sacrificed. In recent years, significant progress has been made in oxide semiconductor research, with recently reported leakage currents of oxide semiconductor transistors (OSTFTs) below 10 ohms. -22 A / μm, switching current ratio exceeding 10 17 Furthermore, it can maintain excellent performance even with a channel length of only 7nm, which provides an opportunity to solve the aforementioned problems of floating gate transistor memory. Summary of the Invention

[0004] The purpose of this invention is to provide a non-volatile oxide semiconductor semi-floating gate transistor memory that is compatible with the existing commercial NAND Flash fabrication process and circuit architecture, has a fast programming and erasing speed and does not require refreshing, and a programming, erasing and reading method thereof.

[0005] The present invention provides an oxide semiconductor semi-floating gate transistor memory. The memory cell embeds an n-type oxide semiconductor thin film in the gate dielectric layer of a p-type floating gate transistor (p-FGT). This oxide semiconductor thin film is connected to the drain of the p-FGT and also to the floating gate of the p-FGT. By sharing the gate and part of the gate dielectric of the p-FGT, an n-type oxide semiconductor thin film transistor (n-OSTFT) embedded in the gate dielectric of the p-FGT is formed. Specifically, the memory cell includes a p-FGT and an n-OSTFT embedded in the gate dielectric of the p-FGT. The p-FGT includes a gate, a first gate dielectric layer, a floating gate, a second gate dielectric layer, source and drain electrodes, and a channel. The channel of the n-OSTFT is located between the first and second gate dielectric layers of the p-FGT, and connects the floating gate and drain of the p-FGT. Furthermore, the n-OSTFT shares the gate and part of the gate dielectric of the p-FGT.

[0006] The oxide semiconductor semi-floating gate transistor memory designed in this invention features a fast write / erase speed. Applying a positive voltage to the gate turns on the n-OSTFT, allowing for programming or erasure operations by injecting charge into or removing charge from the floating gate through the connected p-FGT drain. Applying a negative voltage to the gate turns off the n-OSTFT, enabling the memory's storage state to be read by measuring the current or voltage difference across the p-FGT source and drain electrodes, a non-destructive read operation. When no gate voltage is applied (power off), the n-OSTFT turns off, and the charge programmed into the p-FGT floating gate is retained long-term, thus the memory is non-volatile. This memory cell can be constructed using either NOR or NAND architecture circuitry, and write / erase operations can be performed in both architectures. The memory disclosed in this invention exhibits good compatibility with existing commercial memory processes and architectures, fast write / erase speeds, and long storage times, demonstrating practical and broad application prospects.

[0007] In this invention, the memory cell may employ a top-gate structure, a bottom-gate structure, or a ring-gate structure; wherein:

[0008] The top gate structure, from bottom to top, consists of a channel substrate, a source and a drain, a first gate dielectric layer, a floating gate and an oxide semiconductor, a second gate dielectric layer, and a gate electrode, wherein the oxide semiconductor is connected to the floating gate and the drain electrode respectively.

[0009] The bottom gate structure, from bottom to top, consists of a substrate, a gate, a first gate dielectric layer, a floating gate and an oxide semiconductor, a second gate dielectric layer, a source and a drain, and a channel, wherein the oxide semiconductor is connected to the floating gate and the drain, respectively.

[0010] The ring gate structure, from the outside to the inside, consists of a gate, a first gate dielectric layer, a floating gate and an oxide semiconductor, a second gate dielectric layer, a channel and source / drain electrodes, wherein the oxide semiconductor is connected to the floating gate, and one end is connected to the drain or the channel; or any other suitable device structure.

[0011] Furthermore:

[0012] The top gate device includes:

[0013] Substrate trench;

[0014] Source and drain electrodes are formed on the substrate channel separately, according to a design pattern;

[0015] The first gate dielectric layer is formed on the source and part of the drain, and also on the substrate channel at a location not covered by the source and drain electrodes. This layer is not formed on part of the drain.

[0016] An oxide semiconductor semi-floating gate is formed on the first layer of gate dielectric according to a set pattern, located within the channel position range defined by the lower source and drain electrodes, and also formed on the position where the drain electrode is not covered by the first layer of gate dielectric, and connected to the drain electrode;

[0017] The floating gate can be a thin film structure or a discontinuous nanostructure: the floating gate thin film is formed on the first gate dielectric layer according to a set pattern, located within the channel position range defined by the lower source and drain electrodes, and connected to the oxide semiconductor semi-floating gate; the nano-floating gate is formed on the oxide semiconductor semi-floating gate according to a set pattern.

[0018] The second gate dielectric is formed on the floating gate and the oxide semiconductor semi-floating gate, and is also formed on the first gate dielectric at a location not covered by the floating gate and the oxide semiconductor semi-floating gate.

[0019] The gate is formed on the second gate dielectric according to a set pattern, corresponding to the channel position defined by the lower source and drain electrodes, and covering the position range of the lower floating gate and oxide semiconductor semi-floating gate.

[0020] The bottom gate device includes:

[0021] Substrate;

[0022] The gate is formed on the substrate according to a predetermined pattern;

[0023] A first gate dielectric layer is formed on the gate and also on the substrate at a location not covered by the gate.

[0024] An oxide semiconductor semi-floating gate is formed on the first gate dielectric layer according to a set pattern and is located within the area covered by the lower gate.

[0025] The floating gate can be a thin film structure or a discontinuous nanostructure: the floating gate thin film is formed on the first gate dielectric layer according to a set pattern, located within the position covered by the lower gate, and connected to the oxide semiconductor semi-floating gate; the nano-floating gate is formed on the oxide semiconductor semi-floating gate according to a set pattern.

[0026] The second gate dielectric layer is formed on the floating gate and part of the oxide semiconductor semi-floating gate, and is also formed on the first gate dielectric layer at a location not covered by the floating gate and oxide semiconductor semi-floating gate. In addition, this layer is not formed above part of the oxide semiconductor semi-floating gate.

[0027] Source and drain electrodes are formed on the second gate dielectric layer separately according to the design pattern. The drain electrode is also formed on the oxide semiconductor thin film at a position not covered by the second gate dielectric layer and is connected to the oxide semiconductor thin film.

[0028] The channel is formed on the source and drain electrodes according to the design pattern, and also on the second gate dielectric layer at a location not covered by the source and drain electrodes, corresponding to the position of the gate below.

[0029] The ring-gate device comprises the following structure from the outside in: gate, first gate dielectric, oxide semiconductor, floating gate, second gate dielectric, channel and source / drain electrodes, wherein the oxide semiconductor is connected to the floating gate, and one end is connected to the drain or channel.

[0030] In this invention, the p-FGT channel employs an elemental semiconductor, alloy semiconductor, compound semiconductor, two-dimensional semiconductor, oxide semiconductor, or organic semiconductor, or a combination of several thereof; wherein:

[0031] The elemental semiconductor includes Si or Ge with single crystal, polycrystalline, or amorphous structures;

[0032] The alloy semiconductor includes SiGe, AlGaAs, AlInAs, GaAsP, GaInP, GaInAs, and GaInAsP;

[0033] The compound semiconductors include SiC, GaN, GaAs, GaP, InP, InAs, and InTe;

[0034] The two-dimensional semiconductor includes two-dimensional molybdenum sulfide, two-dimensional tungsten sulfide, two-dimensional tungsten selenide, and two-dimensional black phosphorus.

[0035] In this invention, the drain, source, and gate may be metals, including Mg, Al, Sc, Ti, V, Cr, Mn, Ni, Cu, Zn, Ga, Zr, Nb, Mo, Pd, Ag, Cd, In, Sn, La, Hf, Ta, W, Ir, Pt, Au, Bi, Co, Ru; binary or multi-element alloys of the above metals; and oxides or nitrides of the above metal units or units.

[0036] In this invention, the first and second gate dielectrics may be stacks of one or more of SiO2, Si3N4, Al2O3, HfO2, ZrO2, Ta2O5, and Y2O3; or binary or multi-component oxides or nitrides composed of two or more of the elements Si, Al, Hf, Zr, Ba, Ti, Ta, and Y.

[0037] In this invention, the floating gate may be an elemental semiconductor, alloy semiconductor, compound semiconductor, two-dimensional semiconductor, oxide semiconductor, or organic semiconductor, or a combination of several thereof; wherein:

[0038] The elemental semiconductor includes Si or Ge with single crystal, polycrystalline, or amorphous structures;

[0039] The alloy semiconductor includes SiGe, AlGaAs, AlInAs, GaAsP, GaInP, GaInAs, and GaInAsP;

[0040] The compound semiconductors include SiC, GaN, GaAs, GaP, InP, InAs, and InTe;

[0041] The two-dimensional semiconductor includes two-dimensional molybdenum sulfide, two-dimensional tungsten sulfide, two-dimensional tungsten selenide, and two-dimensional black phosphorus.

[0042] Metals, including Mg, Al, Sc, Ti, V, Cr, Mn, Ni, Cu, Zn, Ga, Zr, Nb, Mo, Pd, Ag, Cd, In, Sn, La, Hf, Ta, W, Ir, Pt, Au, Bi, Co, Ru; binary or multi-element alloys of the above metals; oxides or nitrides of the above metal units or components.

[0043] In this invention, the n-type oxide semiconductor semi-floating gate can be made of a mono-oxide semiconductor material, specifically selected from ZnO. x GaO x InO x SnO x NiO x CuO x WO x VO xBinary or multi-element oxides composed of two or more elements selected from Al, Zn, Ga, In, Sn, Ni, Cu, W, Er, La, V, Ti, Ta, Bi, and Y.

[0044] This invention also provides the above-mentioned memory cell and its programming, erasing, and reading methods in NAND architecture circuits; wherein:

[0045] The programming method for the memory cell is to apply a first voltage to the gate of the memory, apply a second voltage to the drain, and ground the source, wherein the first voltage is a positive voltage and is greater than the second voltage;

[0046] The method for erasing a memory cell is to apply the first voltage to the gate of the memory, apply the third voltage to the drain, and ground the source, wherein the third voltage is not greater than the first voltage, but is greater than the second voltage;

[0047] The method for reading a memory cell is to apply a negative voltage to the gate of the memory, ground the source, apply a read voltage to the drain, and measure the voltage difference or current across the source and drain.

[0048] The programming method for memory in NAND architecture circuits is as follows: a first voltage is applied to the word line of the selected memory cell, and a sufficiently high negative voltage is applied to the word lines of other memory cells in the same bit line to fully turn on the p-FGT. At the same time, the bit line at the source end of the selected memory cell is grounded, and a second voltage is applied to the bit line at the drain end of the selected memory cell. The first voltage is a positive voltage and is greater than the second voltage.

[0049] The memory erasure method in the NAND architecture circuit is as follows: apply the first voltage to the word line of the selected memory cell, and apply a sufficiently high negative voltage to the word lines of other memory cells in the same bit line to fully turn on the p-FGT therein. At the same time, ground the bit line at the source end of the selected memory cell, and apply a third voltage to the bit line at the drain end of the selected memory cell, wherein the third voltage is not greater than the first voltage, but is greater than the second voltage.

[0050] The method for reading memory in NAND architecture circuits is as follows: apply a negative voltage to the word line of the selected memory cell, and apply a sufficiently high negative voltage to the word lines of other memory cells in the same bit line to fully turn on the p-FGT. At the same time, ground the bit line at the source terminal of the selected memory cell, apply a read voltage to the bit line at the drain terminal of the selected memory cell, and measure the voltage difference or current across the bit line.

[0051] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0052] (1) Programming and erasing of the memory can be achieved by charging and discharging the floating gate of the floating gate transistor through the OSTFT, which can significantly improve the memory's write and erase speed. At the same time, the ultra-low off-state current of the OSTFT allows the charge stored in the floating gate to be maintained for a long time, avoiding sacrificing the memory's retention time.

[0053] (2) By embedding the n-OSTFT into the gate dielectric of the p-FGT, the memory containing two transistors requires only three control electrodes. The two transistors are controlled to turn on and off by applying positive and negative voltages to the gate, thus enabling programming, erasing, and reading operations on the memory cell and its NAND architecture circuitry. This allows the memory cell provided by this invention to have excellent architectural compatibility with existing commercial NAND Flash memory, achieving higher storage density.

[0054] (3) Oxide semiconductors can be uniformly prepared over a large area at a lower temperature using atomic layer deposition technology. The prepared thin film has excellent step coverage. Therefore, the fabrication process of the memory can be compatible with both CMOS standard process and 3D-NAND fabrication process.

[0055] (4) The performance of the OSTFT can be controlled within a wide range of parameters such as constituent elements, defect concentration, and film thickness, making the memory provided by this invention a potential universal memory device structure. When the OSTFT has an ultra-low off-state current, the memory can be applied to non-volatile memory scenarios, improving its programming and erasing speed; when the OSTFT has a high on-state current, the memory can be applied to DRAM scenarios, improving its retention time and storage density. When the OSTFT has both an ultra-low off-state current and a high on-state current, the memory is expected to combine the programming and erasing speed of DRAM with the retention time and storage density of non-volatile memory. Attached Figure Description

[0056] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention.

[0057] Figure 1 This is an equivalent circuit diagram of the oxide semiconductor semi-floating gate transistor memory of the present invention.

[0058] Figures 2-4 Here are several device structure embodiments of the oxide semiconductor semi-floating gate transistor memory of the present invention, wherein:

[0059] Figure 2 This is a schematic diagram of a top-gate oxide semiconductor semi-floating gate transistor memory structure with a silicon substrate as the channel and a thin-film floating gate.

[0060] Figure 3 This is a schematic diagram of a top-gate oxide semiconductor semi-floating gate transistor memory structure with a silicon substrate as the channel and a nano-floating gate.

[0061] Figure 4 This is a schematic diagram of a thin-film floating gate bottom gate structure oxide semiconductor semi-floating gate transistor memory structure.

[0062] Figures 5-7 The following are schematic diagrams illustrating the programming, erasing, and reading methods of the oxide semiconductor semi-floating gate transistor memory cell of the present invention.

[0063] Figures 8-10 The following are schematic diagrams illustrating the programming, erasing, and reading methods of the oxide semiconductor semi-floating gate transistor memory in a NAND architecture circuit according to the present invention. Detailed Implementation

[0064] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the invention.

[0065] The oxide semiconductor semi-floating gate transistor memory provided by this invention, such as Figure 1 As shown, the memory embeds an n-OSTFT in the gate dielectric of the p-FGT. The oxide semiconductor channel of the n-OSTFT is connected to the drain of the p-FGT and also to the floating gate of the p-FGT. Furthermore, the n-OSTFT shares the gate and part of the gate dielectric of the p-FGT.

[0066] In a preferred embodiment, a silicon substrate is used as the channel of the oxide semiconductor semi-floating gate transistor memory. In this case, the memory has a top-gate structure, where the p-type transistor is a p-MOSFET, such as... Figure 2 As shown. The channel of the memory is n-type lightly doped silicon (1), and the silicon is p-type heavily doped (2) at the contact between the channel and the source / drain electrodes; (3) and (4) are the drain and source of the memory, respectively; (5) is the first gate dielectric of the memory; (6) is the floating gate film of the memory; (7) is the n-oxide semiconductor semi-floating gate of the memory, which is connected to the drain (3) and the floating gate (6) of the memory; (8) and (9) are the second gate dielectric and the gate of the memory, respectively.

[0067] In a preferred embodiment, the oxide semiconductor semi-floating gate transistor memory can also employ a dispersed nanostructured floating gate (6), such as... Figure 3 As shown.

[0068] Preferably, the oxide semiconductor semi-floating gate transistor memory can also employ a bottom gate structure, such as... Figure 4As shown. (1) is the substrate of the memory, which can be any substrate well-known to those skilled in the art for carrying semiconductor integrated circuit components; (2) and (3) are the gate and the first gate dielectric of the memory respectively; (4) and (5) are the floating gate and the oxide semiconductor semi-floating gate of the memory respectively, which are interconnected; (6) is the second gate dielectric of the memory, and this layer is not formed above a part of the oxide semiconductor semi-floating gate (5); (7) is the source of the memory; (8) is the drain of the memory, which is connected to the oxide semiconductor semi-floating gate; (9) is the channel of the memory.

[0069] Figure 5 A method for programming the oxide semiconductor semi-floating gate transistor memory cell is shown. Apply a first voltage (V1) to the gate of the memory, a second voltage (V2) to the drain, and ground the source. Where V1 > 0 and V2 < V1. At this time, the p-FGT in the memory is turned off and the n-OSTFT is turned on. There is a potential difference across the capacitor formed by the gate and the floating gate, and electrons can be injected into the floating gate through the n-OSTFT to achieve programming of the memory.

[0070] Figure 6 A method for erasing the oxide semiconductor semi-floating gate transistor memory cell is shown. Apply the first voltage (V1) to the gate of the memory, a third voltage (V3) to the drain, and ground the source. Where V1 > 0 and V2 < V3 ≤ V1. At this time, the p-FGT in the memory is turned off and the n-OSTFT is turned on. The potential difference across the capacitor formed by the gate and the floating gate is smaller than that during programming, and electrons in the floating gate can be removed through the n-OSTFT to achieve erasing of the memory.

[0071] Figure 7 A method for reading the oxide semiconductor semi-floating gate transistor memory cell is shown. Apply a first read voltage (V read ) to the gate of the memory, ground the source, and at the same time apply a second read voltage (V d ) to the drain. Where V read < 0. At this time, the n-OSTFT in the memory is turned off and the p-FGT is turned on. Reading of the memory can be achieved by measuring the voltage difference or current between the source and the drain.

[0072] The oxide semiconductor semi-floating gate transistor memory cell can be used to construct a memory circuit in either a NOR architecture or a NAND architecture. Programming, erasing, and reading operations can be implemented in both architectures. Among them, for programming, erasing, and reading of the memory in the NOR architecture, the same methods as those for programming, erasing, and reading of the memory cell can be used; the methods for programming, erasing, and reading of the memory in the NAND architecture are as Figure 4 shown in a-4c.

[0073] Figure 8 Fig. shows a method for programming the memory in the NAND architecture circuit. A first voltage (V1) is applied to the word line of the selected memory cell, and a pass voltage (V pass ) is applied to the word lines of other memory cells in the same bit line. At the same time, the bit line at the source end of the selected memory cell is grounded, and a second voltage (V2) is applied to the bit line at the drain end of the selected memory cell. Among them, V pass < 0, V1 > 0 and V2 < V1. At this time, the p-FGT of the memory cells in the same bit line as the selected memory cell is fully turned on, the n-OSTFT is turned off, and the memory state is not affected; the p-FGT in the selected memory cell is turned off, the n-OSTFT is turned on, and there is a potential difference across the capacitor formed by the gate and the floating gate in the selected memory cell. Electrons can be injected into the floating gate through the n-OSTFT, realizing the programming of the selected memory cell. According to this method, a scanning operation can be performed to achieve the programming of all memory cells in the circuit.

[0074] Figure 9 Fig. shows a method for erasing the memory in the NAND architecture circuit. The first voltage (V1) is applied to the word line of the selected memory cell, and a pass voltage (V pass ) is applied to the word lines of other memory cells in the same bit line. At the same time, the bit line at the source end of the selected memory cell is grounded, and a third voltage (V3) is applied to the bit line at the drain end of the selected memory cell. Among them, V pass < 0, V1 > 0 and V2 < V3 ≤ V1. At this time, the p-FGT of the memory cells in the same bit line as the selected memory cell is fully turned on, the n-OSTFT is turned off, and the memory state is not affected; the p-FGT in the selected memory is turned off, the n-OSTFT is turned on, and the potential difference across the capacitor formed by the gate and the floating gate is smaller than that during programming. Electrons in the floating gate can be removed through the n-OSTFT, realizing the erasing of the selected memory cell. According to this method, a scanning operation can be performed to achieve the erasing of all memory cells in the circuit.

[0075] Figure 10 A method for reading memory in a NAND architecture circuit is illustrated. A first read voltage (V) is applied to the word line of the selected memory cell. read ), and apply a pass voltage (V) to the word line of other memory cells in the same bit line. pass Simultaneously, the bit line at the source terminal of the selected memory cell is grounded, and a second read voltage (V) is applied to the bit line at the drain terminal of the selected memory cell. d ), where V pass 0 and V read When the value is less than 0, the p-FGT of the memory cell on the same bit line as the selected memory cell is fully turned on, the n-OSTFT is turned off, and the memory state is unaffected. In the selected memory cell, the n-OSTFT is turned off, and the p-FGT is turned on. The selected memory cell can be read by measuring the voltage difference or current across the bit line. By performing a scan operation using this method, all memory cells in the circuit can be read.

Claims

1. An oxide semiconductor semi-floating gate transistor memory, characterized in that, The memory cell includes a p-type floating gate transistor (p-FGT) and an n-type oxide semiconductor thin-film transistor (n-OSTFT) embedded in the gate dielectric of the p-FGT; the p-FGT includes a gate, a first gate dielectric layer, a floating gate, a second gate dielectric layer, source and drain electrodes, and a channel; the channel of the n-OSTFT is located between the first and second gate dielectric layers of the p-FGT, and connects the floating gate and drain of the p-FGT; furthermore, the n-OSTFT shares the gate and part of the gate dielectric of the p-FGT. Top grid structure, bottom grid structure, or ring grid structure are adopted; among which: The top gate structure, from bottom to top, consists of a channel substrate, a source and a drain, a first gate dielectric layer, a floating gate and an oxide semiconductor, a second gate dielectric layer, and a gate electrode, wherein the oxide semiconductor is connected to the floating gate and the drain electrode respectively. The bottom gate structure, from bottom to top, consists of a substrate, a gate, a first gate dielectric layer, a floating gate and an oxide semiconductor, a second gate dielectric layer, a source and a drain, and a channel, wherein the oxide semiconductor is connected to the floating gate and the drain, respectively. The ring gate structure, from the outside to the inside, consists of a gate, a first gate dielectric layer, a floating gate and an oxide semiconductor, a second gate dielectric layer, a channel and source / drain electrodes, wherein the oxide semiconductor is connected to the floating gate, and one end is connected to the drain or the channel; or any other suitable device structure.

2. The memory according to claim 1, characterized in that, The p-FGT channel employs elemental semiconductors, alloy semiconductors, compound semiconductors, two-dimensional semiconductors, oxide semiconductors, or organic semiconductors, or a combination of several of these; wherein: The semiconductor element is selected from Si or Ge, which have single-crystal, polycrystalline, or amorphous structures. The alloy semiconductor is selected from SiGe, AlGaAs, AlInAs, GaAsP, GaInP, GaInAs, and GaInAsP; The compound semiconductor is selected from SiC, GaN, GaAs, GaP, InP, InAs, and InTe; The two-dimensional semiconductor is selected from two-dimensional molybdenum sulfide, two-dimensional tungsten sulfide, two-dimensional tungsten selenide, and two-dimensional black phosphorus.

3. The memory according to claim 2, characterized in that, The source, drain, and gate are made of one of the following metals: Mg, Al, Sc, Ti, V, Cr, Mn, Ni, Cu, Zn, Ga, Zr, Nb, Mo, Pd, Ag, Cd, In, Sn, La, Hf, Ta, W, Ir, Pt, Au, Bi, Co, Ru; or binary or multi-element alloys of these metals, or oxides or nitrides of these metal units or units.

4. The memory according to claim 3, characterized in that, The gate dielectric is a stack of one or more of SiO2, Si3N4, Al2O3, HfO2, ZrO2, Ta2O5, and Y2O3; or a binary or multi-component oxide or nitride composed of two or more of the elements Si, Al, Hf, Zr, Ba, Ti, Ta, and Y.

5. The memory according to claim 1, characterized in that, The floating gate of the p-FGT adopts a continuous thin film structure or a dispersed nanostructure; the floating gate adopts an elemental semiconductor, alloy semiconductor, compound semiconductor, two-dimensional semiconductor, oxide semiconductor, or organic semiconductor, or a combination of several thereof; wherein: The semiconductor element is selected from Si or Ge, which have single-crystal, polycrystalline, or amorphous structures. The alloy semiconductor is selected from SiGe, AlGaAs, AlInAs, GaAsP, GaInP, GaInAs, and GaInAsP; The compound semiconductor is selected from SiC, GaN, GaAs, GaP, InP, InAs, and InTe; The two-dimensional semiconductor is selected from two-dimensional molybdenum sulfide, two-dimensional tungsten sulfide, two-dimensional tungsten selenide, and two-dimensional black phosphorus. The metal used is one of the following: Mg, Al, Sc, Ti, V, Cr, Mn, Ni, Cu, Zn, Ga, Zr, Nb, Mo, Pd, Ag, Cd, In, Sn, La, Hf, Ta, W, Ir, Pt, Au, Bi, Co, Ru; or a binary or multi-element alloy of these metals, or an oxide or nitride of these metal units or units.

6. The memory according to claim 1, characterized in that, The n-type oxide semiconductor uses a mono-oxide semiconductor material, specifically selected from ZnO. x GaO x InO x SnO x NiO x CuO x WO x VO x Binary or multi-element oxides composed of two or more elements selected from Al, Zn, Ga, In, Sn, Ni, Cu, W, Er, La, V, Ti, Ta, Bi, and Y.

7. A method for programming, erasing, and reading an oxide semiconductor semi-floating gate transistor memory according to any one of claims 1-6, characterized in that: Programming: Apply a first voltage to the gate of the memory, apply a second voltage to the drain, and ground the source, wherein the first voltage is a positive voltage and is greater than the second voltage; Erasure: Apply the first voltage to the gate of the memory, apply the third voltage to the drain, and ground the source, wherein the third voltage is not greater than the first voltage, but is greater than the second voltage; Read / store: Apply a negative voltage to the gate of the memory, ground the source, and simultaneously apply a read voltage to the drain, measuring the voltage difference or current across the source and drain.

8. A method for programming, erasing, and reading a NAND architecture memory circuit of an oxide semiconductor semi-floating gate transistor memory as described in any one of claims 1-6, characterized in that: Programming the memory in the NAND architecture circuit: A first voltage is applied to the word line of the selected memory cell, and a sufficiently high negative voltage is applied to the word lines of other memory cells in the same bit line to fully turn on the p-FGT therein. At the same time, the bit line at the source end of the selected memory cell is grounded, and a second voltage is applied to the bit line at the drain end of the selected memory cell, wherein the first voltage is a positive voltage and is greater than the second voltage. Erasing memory in NAND architecture circuitry: Apply the first voltage to the word line of the selected memory cell, and apply a sufficiently high negative voltage to the word lines of other memory cells in the same bit line to fully enable the p-FGT therein. At the same time, ground the bit line at the source end of the selected memory cell, and apply a third voltage to the bit line at the drain end of the selected memory cell, wherein the third voltage is not greater than the first voltage, but is greater than the second voltage. Memory read operation in NAND architecture circuitry: Apply a negative voltage to the word line of the selected memory cell, and apply a sufficiently high negative voltage to the word lines of other memory cells in the same bit line to fully enable the p-FGT. At the same time, ground the bit line at the source terminal of the selected memory cell, apply a read voltage to the bit line at the drain terminal of the selected memory cell, and measure the voltage difference or current across the bit line.

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