Multilayer Ceramic Capacitors

By stacking nickel plating on the outer electrodes of the multi-layer ceramic capacitor, the problem of poor bonding strength between the electrode and the metal plating layer of the low-profile capacitor is solved, and higher bonding strength and capacitance value are achieved.

CN115472432BActive Publication Date: 2025-05-06SAMSUNG ELECTRO MECHANICS CO LTD
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Patent Information

Application Number
CN202211326225.7
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2019-08-02
Filing Date
2020-05-11
Publication Date
2025-05-06
Estimated Expiration
2040-05-11

AI Technical Summary

Technical Problem

In the lower electrode applied to low profile capacitors with very small thickness, the bond strength difference between the lower electrode and the metal plating layer.

Method used

A sintered electrode containing nickel is employed, and a first and second plating layer are sequentially stacked thereon, the first and second plating layers extend to and formed on the third and fourth surfaces of the body, respectively, thereby improving the bond strength between the outer electrode and the body.

Benefits of technology

By improving the adhesive strength between the outer electrode and the main body, the installation reliability and moisture resistance of the multi-layer ceramic capacitor are enhanced, while a significant increase in the capacitor is achieved.

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Abstract

The present invention provides a multilayer ceramic capacitor, which includes: a main body, including a dielectric layer and a first inner electrode and a second inner electrode, and the dielectric layer is interposed between the first inner electrode and the second inner electrode; a first through-electrode, passing through the main body and connected to the first inner electrode; a second through-electrode, passing through the main body and connected to the second inner electrode; a first external electrode and a second external electrode, formed on the first surface and the second surface of the main body and connected to the first through-electrode; and a third external electrode and a fourth external electrode, spaced apart from the first external electrode and the second external electrode and connected to the second through-electrode, wherein the first external electrode, the second external electrode, the third external electrode and the fourth external electrode include sintered electrodes containing nickel, and each includes a first plating layer and a second plating layer sequentially stacked on the sintered electrode.
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Description

[0001] This application is a divisional application of the invention patent application "Multilayer Ceramic Capacitor" with an application date of May 11, 2020 and application number 202010393550.X. Technical Field

[0002] The present disclosure relates to a multilayer ceramic capacitor. Background Art

[0003] Recently, the use of electronic devices using multilayer ceramic capacitors (MLCCs) has increased rapidly. Specifically, as the fifth generation (5G) era has arrived, smartphones require capacitors with a larger number and higher capacitance. On the other hand, due to the miniaturization technology of group products, the installation area of ​​passive components (such as MLCCs and inductors) has been reduced, and therefore, miniaturization and slimming of passive components are also required. Therefore, a method is proposed in which multilayer ceramic capacitors and inductors are packaged together with an integrated circuit (IC) and an application processor (AP), embedded in a substrate, or mounted on the lower end of the AP in a land-side capacitor (LSC) type manner to increase the degree of freedom of installation.

[0004] In this case, not only a reduction in mounting area but also a reduction in equivalent series inductance (ESL) generated in the substrate can be achieved. Therefore, the demand for multilayer ceramic capacitor products having a small thickness increases.

[0005] However, in a lower electrode applied to a low-profile capacitor having a very small thickness, such as an embedded capacitor and a surface mount capacitor, the adhesive strength between the lower electrode and the metal plating layer is poor. Summary of the invention

[0006] An aspect of the present disclosure is to provide a multilayer ceramic capacitor having improved adhesive strength when mounted on or embedded in a substrate.

[0007] Another aspect of the present disclosure is to provide a multilayer ceramic capacitor capable of miniaturization and slimming and having improved reliability.

[0008] According to one aspect of the present disclosure, a multilayer ceramic capacitor includes: a body including a dielectric layer and a first inner electrode and a second inner electrode, and the dielectric layer is interposed between the first inner electrode and the second inner electrode, and the body includes a fifth surface and a sixth surface opposite to each other in a first direction, a third surface and a fourth surface opposite to each other in a second direction, and a first surface and a second surface opposite to each other in a third direction; a first through electrode passing through the body and connected to the first inner electrode; a second through electrode passing through the body and connected to the second inner electrode; a first external electrode and a second external electrode formed on the first surface and the second surface and connected to the first through electrode; and a third external electrode and a fourth external electrode spaced apart from the first external electrode and the second external electrode and connected to the second through electrode, wherein the first external electrode, the second external electrode, the third external electrode and the fourth external electrode include sintered electrodes containing nickel, and each includes a first plating layer and a second plating layer sequentially stacked on the sintered electrodes, wherein the first plating layer and the second plating layer extend to and are formed on the third surface and the fourth surface of the body, respectively.

[0009] According to one aspect of the present disclosure, a multilayer ceramic capacitor includes: a main body, including a dielectric layer and a first inner electrode and a second inner electrode, and the dielectric layer is interposed between the first inner electrode and the second inner electrode, and the first inner electrode and the second inner electrode are point-symmetrical to each other; a pair of first outer electrodes, arranged on a first pair of opposite surfaces of the main body; a pair of second outer electrodes, arranged on the first pair of opposite surfaces of the main body and spaced apart from the pair of first outer electrodes; a first connecting electrode, connected to the pair of first outer electrodes, passing through a first via hole in the second inner electrode and electrically insulated from the second inner electrode; a second connecting electrode, connected to the pair of second outer electrodes, passing through a second via hole in the first inner electrode and electrically insulated from the first inner electrode, wherein the first inner electrode is connected to the first outer electrode through the first connecting electrode, and the second inner electrode is connected to the second outer electrode through the second connecting electrode.

[0010] According to an aspect of the present disclosure, a substrate in which the multilayer ceramic capacitor as described above is embedded may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a schematic perspective view of a multilayer ceramic capacitor according to an embodiment of the present disclosure.

[0013] Figure 2When viewed in the X direction Figure 1 Side view of.

[0014] Figure 3 It is along Figure 1 A cross-sectional view taken along line II'.

[0015] Figure 4A and Figure 4B yes Figure 1 A cross-sectional view in the X direction and the Y direction, and Figure 4A is a cross-sectional view in which the first inner electrode is visible, Figure 4B is a cross-sectional view in which the second inner electrode is visible.

[0016] Figure 5 is a schematic perspective view of a multilayer ceramic capacitor according to another embodiment of the present disclosure.

[0017] Figure 6 When viewed in the X direction Figure 5 Side view of.

[0018] Figure 7 It is along Figure 5 A cross-sectional view taken along line II-II'.

[0019] Fig. 8A and Figure 8B yes Figure 5 A cross-sectional view in the X direction and the Y direction, and Fig. 8A is a cross-sectional view in which the first inner electrode is visible, Figure 8B is a cross-sectional view in which the second inner electrode is visible.

[0020] Fig.9A and Fig. 9B yes Figure 5 , which is a cross-sectional view in the X direction and the Y direction, and shows a multilayer ceramic capacitor according to another embodiment of the present disclosure, Fig.9A is a cross-sectional view in which the first inner electrode is visible, Fig. 9B is a cross-sectional view in which the second inner electrode is visible.

[0021] Fig. 10A and Fig. 10B yes Figure 5 , which is a cross-sectional view in the X direction and the Y direction, and shows a multilayer ceramic capacitor according to another embodiment of the present disclosure, Fig. 10A is a cross-sectional view in which the first inner electrode is visible, Fig. 10B is a cross-sectional view in which the second inner electrode is visible.

[0022] Fig.11 When viewed in the Z direction Figure 5 Side view of. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. However, the present disclosure may be illustrated in many different forms and should not be construed as being limited to the specific embodiments set forth herein. In addition, embodiments of the present disclosure may be provided to make the description of the present disclosure more complete for those skilled in the art. Therefore, for clarity of description, the shapes and sizes of the elements in the accompanying drawings may be exaggerated, and the elements represented by the same reference numerals in the accompanying drawings may be the same elements.

[0024] In order to clearly illustrate the present disclosure, parts irrelevant to the description are omitted, and the thickness is magnified to clearly indicate the layers and regions, and the same parts with the same functions in the same scope are indicated by the same reference numerals throughout the specification. Throughout the specification, unless otherwise explicitly stated, when an element is referred to as "comprising", it means that it may also include other elements without excluding other elements.

[0025] In the drawings, the X direction may be defined as a first direction, L direction or length direction, the Y direction may be defined as a second direction, W direction or width direction, and the Z direction may be defined as a third direction, T direction or thickness direction.

[0026] In the following, reference will be made to Figures 1 to 3 A multilayer ceramic capacitor according to an example embodiment of the present disclosure is described in detail.

[0027] A multilayer ceramic capacitor 100 according to an embodiment of the present disclosure may include: a body 110 including a dielectric layer 111 and first and second internal electrodes 121 and 122, and the dielectric layer 111 is interposed between the first and second internal electrodes 121 and 122, and the body 110 includes a fifth surface S5 and a sixth surface S6 opposite to each other in a first direction (X direction), a third surface S3 and a fourth surface S4 opposite to each other in a second direction (Y direction), and a first surface S1 and a second surface S2 opposite to each other in a third direction (Z direction); a first through electrode 131 passing through the body 110 and connected to the first internal electrode 121; a second through electrode 132 passing through the body 110 and connected to the second internal electrode 122; a first external electrode 141 and a second external electrode 144 formed on the second surface and the first surface and connected to the first through electrode 131; and a third external electrode 142 and a fourth external electrode 143 spaced apart from the first and second external electrodes 141 and 144 and connected to the second through electrode 132.

[0028] In this case, the first external electrode 141, the second external electrode 144, the third external electrode 142, and the fourth external electrode 143 may include a sintered electrode including nickel. In addition, the first external electrode 141, the second external electrode 144, the third external electrode 142, and the fourth external electrode 143 may also each include first plating layers 141b, 144b, 142b, and 143b and second plating layers 141c, 144c, 142c, and 143c sequentially stacked on the sintered electrodes 141a, 144a, 142a, and 143a, wherein the first plating layers 141b, 144b, 142b, and 143b and the second plating layers 141c, 144c, 142c, and 143c may extend to and be formed on the third and fourth surfaces of the body, respectively.

[0029] In the body 110, the dielectric layer 111 and the internal electrodes 121 and 122 may be alternately stacked. The specific shape of the body 110 is not limited, for example, the body 110 may have a hexahedral shape as shown in the drawings or a shape approximate to a hexahedral shape. The body 110 may have a substantially hexahedral shape (although it is not a perfect hexahedral shape due to shrinkage of ceramic powder particles included in the body 110 during the sintering process).

[0030] The body 110 may have a first surface S1 and a second surface S2 opposite to each other in the thickness direction (Z direction), a third surface S3 and a fourth surface S4 connected to the first surface S1 and the second surface S2 and opposite to each other in the width direction (Y direction), and a fifth surface S5 and a sixth surface S6 connected to the first surface S1 and the second surface S2, connected to the third surface S3 and the fourth surface S4 and opposite to each other in the length direction (X direction). In this case, a surface selected from the first surface S1, the second surface S2, the third surface S3, and the fourth surface S4 may be a mounting surface.

[0031] The plurality of dielectric layers 111 constituting the body 110 may be in a sintered state, and adjacent dielectric layers 111 may be integrated with each other so that a boundary therebetween is not apparent without using a scanning electron microscope (SEM).

[0032] According to example embodiments, the raw material used to form the dielectric layer 111 is not limited as long as sufficient capacitance can be obtained therefrom. For example, the raw material used to form the dielectric layer 111 may be a barium titanate-based material, a lead composite perovskite-based material, a strontium titanate-based material, etc. The barium titanate-based material may include BaTiO 3 The ceramic powder particles can be, for example, BaTiO2 by partially dissolving calcium (Ca), zirconium (Zr), etc. 3 Prepared in (Ba 1-x Ca x )TiO 3、Ba(Ti 1-y Ca y ) 3 、(Ba 1- x Ca x )(Ti 1-y Zr y ) 3 、Ba(Ti 1-y Zr y ) 3 As an example of a raw material for forming the dielectric layer 111, various ceramic additives, organic solvents, plasticizers, binders, dispersants, etc. may be added to the dielectric material such as barium titanate (BaTiO 3 ) and other powder particles.

[0033] The first cover 112 and the second cover 113 each having a predetermined thickness may be respectively disposed below the lowermost internal electrode and above the uppermost internal electrode of the body 110. In this case, the first cover 112 and the second cover 113 may have the same composition as that of the dielectric layer 111 and may be formed by stacking at least one dielectric layer not including an internal electrode above the uppermost internal electrode and below the lowermost internal electrode of the body 110.

[0034] The internal electrodes 121 and 122 may include first and second internal electrodes 121 and 122 that are alternately arranged to be opposite to each other with the dielectric layer 111 interposed therebetween.

[0035] In this case, the first and second internal electrodes 121 and 122 may include a first insulating portion 122a and a second insulating portion 121a, respectively (see Figure 4A and Figure 4B ). The first insulating portion 122a and the second insulating portion 121a refer to regions where the first and second internal electrodes 121 and 122 are not formed, respectively. The first insulating portion 122a and the second insulating portion 121a may be used to connect the first and second internal electrodes 121 and 122 only to corresponding external electrodes having opposite polarities. For example, the first through electrode 131 may be spaced apart from the second internal electrode 122 by the second insulating portion 121a, and the second through electrode 132 may be spaced apart from the first internal electrode 121 by the first insulating portion 122a.

[0036] The first internal electrode 121 may be connected to the first external electrode 141 and the second external electrode 144 through the first through electrode 131, and the second internal electrode 122 may be connected to the third external electrode 142 and the fourth external electrode 143 through the second through electrode 132, thereby significantly increasing the region (area) in which the first internal electrode 121 and the second internal electrode 122 overlap each other with the dielectric layer 111 interposed therebetween. Therefore, the capacitance of the multilayer ceramic capacitor 100 may be significantly increased.

[0037] The first internal electrode 121 and the second internal electrode 122 may contain nickel (Ni) at a maximum content, but are not limited thereto. For example, the first internal electrode 121 and the second internal electrode 122 may be formed using a conductive paste containing one or more materials of silver (Ag), palladium (Pd), gold (Au), platinum (Pt), nickel (Ni), tin (Sn), copper (Cu), tungsten (W), titanium (Ti), and alloys thereof. The conductive paste may be printed by screen printing, gravure printing, etc., but the present disclosure is not limited thereto.

[0038] The through electrodes 131 and 132 may contain nickel (Ni) at a maximum content, but are not limited thereto. For example, the through electrodes 131 and 132 may be formed using a conductive paste containing one or more materials of silver (Ag), palladium (Pd), gold (Au), platinum (Pt), nickel (Ni), tin (Sn), copper (Cu), tungsten (W), titanium (Ti) and their alloys. The method of forming the through electrodes 131 and 132 is not limited. For example, the through electrodes 131 and 132 may be formed by forming a stacked body in which the first inner electrode 121 and the second inner electrode 122 are stacked, penetrating the body 110 in a third direction (Z direction) using laser drilling, mechanical pin punching, etc., and filling the above-mentioned conductive paste.

[0039] In an example, the inner electrodes 121 and 122 and the through electrodes 131 and 132 may include the same metal material. The same metal material may be nickel (Ni), but is not limited thereto. For example, the same metal material may be one or more of silver (Ag), palladium (Pd), gold (Au), platinum (Pt), nickel (Ni), tin (Sn), copper (Cu), tungsten (W), titanium (Ti), and alloys thereof. In the case where the inner electrodes 121 and 122 and the through electrodes 131 and 132 of the multilayer ceramic capacitor include the same metal material, the sintering start temperature and / or the sintering shrinkage ratio may be matched to prevent cracks, delamination (peeling), etc.

[0040] In the present specification, each of the through electrodes 131 and 132 is shown to have a circular shape. Each of the through electrodes 131 and 132 may have a hexagonal shape, a square shape, a triangular shape, or an arbitrary convex polygonal shape, and their shapes are not limited thereto. The through electrodes 131 and 132 may be formed to occupy 5% to 65% in the width direction (Y direction) of the body, but the present disclosure is not limited thereto.

[0041] In an example, the body 110 may have a thickness of less than or equal to 100 μm. The thickness of the body 110 may be a vertical distance between the first surface and the second surface, and its lower limit is not limited, but may be, for example, greater than or equal to 5 μm. Since the body 110 may have a thickness of less than or equal to 100 μm, the multilayer ceramic capacitor according to the present disclosure may be applied to a multilayer ceramic capacitor embedded in a substrate and / or a capacitor mounted on the lower end of an AP in an LSC type.

[0042] According to an embodiment of the present disclosure, the first external electrode 141, the second external electrode 144, the third external electrode 142, and the fourth external electrode 143 may be formed on both surfaces of the body 110. The first external electrode 141 and the second external electrode 144 may be disposed on the second surface S2 and the first surface S1 of the body 110, respectively, and may be connected to each other through the first through electrode 131 described herein. The third external electrode 142 and the fourth external electrode 143 may be spaced apart from the first external electrode 141 and the second external electrode 144, may be disposed on the second surface S2 and the first surface S1 of the body 110, respectively, and may be connected to each other through the second through electrode 132 described herein.

[0043] In the multilayer ceramic capacitor 100 having the above structure, the edge portion connecting the upper surface and the lower surface of the body 110 to each other can be reduced, thereby increasing the area where the first internal electrode 121 and the second internal electrode 122 are formed. Therefore, the capacitance of the multilayer ceramic capacitor 100 can be significantly increased. For example, since the multilayer ceramic capacitor 100 according to an embodiment of the present disclosure has an electrode structure in which no external electrode is provided on the side surface (e.g., the fifth surface S5 and the sixth surface S6) and the internal electrode is connected to the external electrode through the through electrode passing through the body, the capacitance of the multilayer ceramic capacitor can be significantly increased.

[0044] In the following, reference will be made to Figure 2 The structure of the first external electrode 141 is described. The description of the structure of the first external electrode 141 may be applied to the second, third, and fourth external electrodes 144, 142, and 143 in the same manner.

[0045] Reference Figure 2, the first external electrode 141 may include a first sintered electrode 141a and a first plating layer 141b and a second plating layer 141c. The first sintered electrode 141a may include one or more materials of silver (Ag), palladium (Pd), gold (Au), platinum (Pt), nickel (Ni), tin (Sn), copper (Cu), tungsten (W), titanium (Ti) and alloys thereof. For example, the first sintered electrode 141a may be a sintered electrode formed by sintering a conductive paste containing nickel (Ni). Similar to the first sintered electrode 141a, when the external electrode is formed as a sintered electrode, there is an advantage in that the external electrode can be sintered simultaneously with the body and the internal electrode, and the bonding strength between the through electrode and the external electrode can be further improved.

[0046] According to an example of the present disclosure, the length (T 2 ) and the thickness of the main body (T 1 ) 2 / T 1 ) may be in the range of 1 / 3 to 2 / 5. The length (T 2 ) may refer to the shortest distance from the end of the body to the end of the plating in the Z direction, or may refer to the sum of the extended lengths of the plating of the first external electrode 141 and the second external electrode 144 or the sum of the extended lengths of the plating of the third external electrode 142 and the fourth external electrode 143. The sum of the extended lengths of the plating of the first external electrode 141 and the second external electrode 144 or the sum of the extended lengths of the plating of the third external electrode 142 and the fourth external electrode 143 may be the average value of five randomly selected distances. Figure 2 , when the extension length of the plating layer of the first external electrode 141 is referred to as T b And the extension length of the plating layer of the second external electrode 144 is referred to as T a When the first plating layer or the second plating layer extends to the third surface and the fourth surface of the main body (T 2 ) can refer to T a and T b The sum (T a +T b ).

[0047] When installed, by extending the first plating layer or the second plating layer to the length (T 2 ) and the thickness of the main body (T 1 ) 2 / T 1 ) is kept within the above range (ie, 1 / 3 to 2 / 5), excellent bonding strength can be ensured. In addition, when the above ratio is satisfied, the portion exposed at the boundary between the sintered electrode and the dielectric layer can be reduced, thereby improving moisture resistance reliability.

[0048] In an example, the centerline average roughness (Ra) of the surface of the sintered electrodes 141a, 142a, 143a, and 144a of the present disclosure may be in the range of 1 nm to 100 nm. In this specification, "centerline average roughness (Ra)" may refer to the average value of the distance to the virtual center line. An external electrode having a centerline average roughness (Ra) in the range of 1 nm to 100 nm may refer to an external electrode having a surface roughness in the above range, and may refer to an external electrode having a surface roughness artificially formed to meet the above range.

[0049] The center line average roughness (Ra) is a value calculated by the following steps: drawing a virtual center line of roughness on the surfaces of the sintered electrodes 141a, 142a, 143a, and 144a; measuring corresponding distances (e.g., r1, r2, r3, . . . , and rn) based on the virtual center line of roughness; and obtaining an average value given by Formula 1. And the center line average roughness (Ra) of the dielectric layer can be calculated.

[0050] Formula 1:

[0051]

[0052] The sintered electrode having a center line average roughness (Ra) satisfying the above range can be formed by surface modification using a physical method or a chemical method. The surface modification method is not limited as long as the above roughness can be provided. For example, the surface modification method may be surface treatment using an acidic solution or an alkaline solution, physical polishing using an abrasive, etc.

[0053] Generally, during the sintering process, an oxide layer is formed on the surface of a sintered electrode containing nickel or the like. Therefore, it may be difficult to form a plating layer, and the plating layer may be easily peeled off. When the sintered electrode according to an embodiment of the present disclosure is surface-modified to satisfy the center line average roughness (Ra) in the above range, the oxide layer may be removed or a surface having a predetermined roughness may be formed. Therefore, the bonding strength between the sintered electrode and the plating layer may be enhanced, and the plating layer may be prevented from peeling off.

[0054] The first plating layer 141b according to an embodiment of the present disclosure may be a plating layer including nickel, and the second plating layer 141c may be a plating layer including copper or tin. The first plating layer 141b may include nickel to improve adhesion with the first sintered electrode 141a. In addition, the second plating layer 141c may include copper or tin to form an external electrode with improved conductivity, plating adhesion, and solderability.

[0055] In the embodiment of the present disclosure, when the thickness of the portion of the first plating layer extending to the third surface and the fourth surface of the body 110 is t 2The thickness of the portion of the first plating layer disposed on the sintered electrode is t 1 When the multilayer ceramic capacitor can satisfy the relationship t 2 ≥t 1 . Figure 2 Schematic diagram showing the structure of the sintered electrode and the plating layer of this embodiment. Figure 2 , the first plating layer 144b and the second plating layer 144c may be sequentially stacked on the second sintered electrode 144a, and the first plating layer 144b and the second plating layer 144c may extend to and be formed on the third surface of the body 110. In this case, the thickness (t 1 ) may be less than or equal to the thickness (t 2 When the thickness of the portion of the first plating layer 144b extending to the third surface of the body 110 (t 2 ) and the thickness (t 1 ) when the above relationship between them is achieved, moisture resistance reliability and excellent solderability can be improved.

[0056] In another embodiment of the present disclosure, when the thickness of the portion of the second plating layer extending to the third surface and the fourth surface of the body 110 is t 4 The thickness of the second coating layer disposed on the first coating layer and above the sintered electrode is t 3 When the multilayer ceramic capacitor can satisfy the relationship t 4 ≥t 3 . Figure 2 Schematic diagram showing the structure of the first plating layer 144b and the second plating layer 144c of this embodiment. Figure 2 , the second plating layer 144c may be stacked on the first plating layer 144b, and the first plating layer 144b and the second plating layer 144c may extend to and be formed on the third surface of the body 110. In this case, the thickness (t 3 ) may be less than or equal to the thickness (t 4 When the thickness (t 4 ) and the thickness (t 3 ) when the above relationship between them is achieved, moisture resistance reliability and excellent solderability can be improved.

[0057] In an example, each of the first external electrode 141, the second external electrode 144, the third external electrode 142, and the fourth external electrode 143 may have a thickness in the range of 1 μm to 30 μm. The thickness of each of the first external electrode 141, the second external electrode 144, the third external electrode 142, and the fourth external electrode 143 may refer to the total thickness of the sintered electrode, the first plating layer, and the second plating layer stack, and may refer to the vertical distance from the body to the corresponding surface of the external electrode. The thickness of the external electrode may be adjusted within the above range to obtain improved mountability, and does not occupy a large space when used for surface mounting or substrate embedding.

[0058] Figures 5 to 7 A multilayer ceramic capacitor according to another embodiment of the present disclosure is shown. Figures 5 to 7 A multilayer ceramic capacitor according to another embodiment of the present disclosure is described in detail.

[0059] A multilayer ceramic capacitor 200 according to another embodiment of the present disclosure may include a body 210 in which a first internal electrode 221, a dielectric layer 211, and a second internal electrode 222 are stacked; a first connection electrode 231, a second connection electrode 232, a third connection electrode 233, and a fourth connection electrode 234; and a first external electrode 241, a second external electrode 244, a third external electrode 242, and a fourth external electrode 243. The materials and configurations of the dielectric layer 211, the first internal electrode 221, the second internal electrode 222, and the first external electrode 241, the second external electrode 244, the third external electrode 242, and the fourth external electrode 243 are the same as those described above, and thus description thereof will be omitted.

[0060] The multilayer ceramic capacitor 200 may include a first connection electrode 231, a second connection electrode 232, a third connection electrode 233, and a fourth connection electrode 234, the first connection electrode 231 and the fourth connection electrode 234 may be connected to the first external electrode 241 and the second external electrode 244, and the second connection electrode 232 and the third connection electrode 233 may be connected to the third external electrode 242 and the fourth external electrode 243. As described above, since a plurality of connection electrodes may be provided for connecting the first external electrode and the second external electrode and for connecting the third external electrode and the fourth external electrode, the adhesive strength between the external electrode and the body may be further enhanced.

[0061] Fig. 8A and Figure 8B 2 is a cross-sectional view showing the shapes of the first internal electrode 221 and the second internal electrode 222. Fig. 8A and Figure 8B, the first inner electrode 221 and the second inner electrode 222 may be T-shaped and point-symmetrical to each other. The first inner electrode 221 may have a T-shaped electrode pattern. The non-setting region 222a where the electrode pattern is not formed may be an insulating region. The second inner electrode 222 may have a T-shaped electrode pattern. The non-setting region 221a where the electrode pattern is not formed may be an insulating region.

[0062] In the multilayer ceramic capacitor having the electrode pattern, the first connection electrode 231 and the fourth connection electrode 234 may be connected to the first internal electrode 221 and may pass through the non-disposition region 221a of the second internal electrode 222. The second connection electrode 232 and the third connection electrode 233 may be connected to the second internal electrode 222 and may pass through the non-disposition region 222a of the first internal electrode 221. By forming a via hole in the internal electrode and the connection electrode passing through the non-disposition region of the internal electrode, the multilayer ceramic capacitor according to the present disclosure may cancel out the mutual inductance to improve the equivalent series inductance (ESL), and may increase the capacitance.

[0063] In an example, the non-disposition regions 322a and 321a of the first and second internal electrodes 321 and 322 may be rounded. Fig.9A and Fig. 9B , the first internal electrode 321 may have a T-shaped electrode pattern, and a non-disposition region 322a in which the internal electrode is not disposed may be formed to have a rounded shape. The second internal electrode 322 may have a T-shaped electrode pattern, and a non-disposition region 321a in which the internal electrode is not disposed may be formed to have a rounded shape. As described above, when the concave portion of the internal electrode pattern is formed in a rounded shape, the capacitance of the multilayer ceramic capacitor may be further increased.

[0064] In the above, the case where the non-setting area of ​​the inner electrode has a square shape and a rounded shape has been described as an example, but the shape of the inner electrode pattern is not limited thereto. For example, the inner electrode may have various shapes such as a triangular shape, a polygonal shape, etc., which all belong to the scope of the present disclosure.

[0065] Fig. 10A , Fig. 10B and Fig.11 2 is a cross-sectional view showing another embodiment of the present disclosure. Fig. 10A , Fig. 10B and Fig.11, the first inner electrode 421 and the second inner electrode 422 may be point-symmetrical to each other, and each of the first inner electrode 421 and the second inner electrode 422 may have a rectangular shape. The first inner electrode 421 may have a second via hole and a third via hole, and the second inner electrode 422 may have a first via hole and a fourth via hole. In this case, the first connection electrode 431 and the fourth connection electrode 434 may be connected to the first inner electrode 421, and may pass through the first via hole and the fourth via hole of the second inner electrode 422. The second connection electrode 432 and the third connection electrode 433 may be connected to the second inner electrode 422, and may pass through the second via hole and the third via hole of the first inner electrode 421. The first connection electrode 431 and the fourth connection electrode 434 may be disposed to pass through the first via hole and the fourth via hole of the second inner electrode 422, so that the first connection electrode 431 and the fourth connection electrode 434 may be electrically insulated from the second inner electrode 422. The second and third connection electrodes 432 and 433 may be disposed through the second and third via holes of the first internal electrode 421 , so that the second and third connection electrodes 432 and 433 may be electrically insulated from the first internal electrode 421 .

[0066] Fig.11 The distance (D1) between the first connection electrode 431 and the fourth connection electrode 434 or the distance (D1) between the second connection electrode 432 and the third connection electrode 433 is shown, and the diameter (D2) of each of the first connection electrode 431, the second connection electrode 432, the third connection electrode 433 and the fourth connection electrode 434 (or the diameter (D2) in the case of a non-circular shape connection electrode) Fig.11 ), and the distance (D3) between the first via hole and the second via hole or the distance (D3) between the third via hole and the fourth via hole.

[0067] Reference Fig.11In the present embodiment, a ratio (D1 / D3) of a distance (D1) between the first connection electrode 431 and the fourth connection electrode 434 or a distance (D1) between the second connection electrode 432 and the third connection electrode 433 to a distance (D3) between the first via hole and the second via hole may be in a range of 2.08 to 4.7. The ratio (D1 / D3) may be greater than or equal to 2.08, greater than or equal to 2.20, greater than or equal to 2.30, greater than or equal to 2.40, greater than or equal to 2.50, greater than or equal to 2.60, greater than or equal to 2.70, greater than or equal to 2.80, greater than or equal to 2.90, greater than or equal to 3.00, greater than or equal to 3.05, greater than or equal to 3.10, or greater than or equal to 3.15, and may be less than or equal to 4.700, less than or equal to 4.695, less than or equal to 4.690, or less than or equal to 4.688, but is not limited thereto. When the ratio (D1 / D3) of the distance (D1) between the first connection electrode and the fourth connection electrode or the distance (D1) between the second connection electrode and the third connection electrode to the distance (D3) between the first via hole and the second via hole satisfies the above range, the equivalent series inductance (ESL) can be reduced. In detail, when the ratio is greater than or equal to 3.125, the ESL reduction effect is significantly improved.

[0068] In another embodiment of the present disclosure, a ratio (D2 / D3) of a diameter (D2) of the first connection electrode or the second connection electrode to a distance (D3) between the first via hole and the second via hole may be in a range of 0.375 to 0.52. A ratio (D2 / D3) of a diameter (D2) of the first connection electrode or the second connection electrode to a distance (D3) between the first via hole and the second via hole may be greater than or equal to 0.375, greater than or equal to 0.380, greater than or equal to 0.385, greater than or equal to 0.390, greater than or equal to 0.395, greater than or equal to 0.400, greater than or equal to 0.405, or greater than or equal to 0.410, and may be less than or equal to 0.52. When a ratio (D2 / D3) of a diameter (D2) of the first connection electrode or the second connection electrode to a distance (D3) between the first via hole and the second via hole satisfies the above range, an equivalent series inductance (ESL) may be reduced. In detail, when the ratio (D2 / D3) is greater than or equal to 0.41, the ESL reduction effect can be significantly improved. When the ratio (D2 / D3) is greater than or equal to 0.52, the capacitance of the capacitor may decrease.

[0069] Hereinafter, a method for manufacturing a multilayer ceramic capacitor according to the present disclosure will be described. Through the description of the method, the structure of the multilayer ceramic capacitor described above can be more clearly explained.

[0070] First, a body including a dielectric layer, a first internal electrode, and a second internal electrode with the dielectric layer interposed between the first internal electrode and the second internal electrode can be prepared by stacking sheets on which a paste containing a conductive metal is printed, the sheets being ceramic green sheets for forming a dielectric layer of a predetermined thickness. The first covering portion and the second covering portion can be formed by stacking dielectric layers neither including an internal electrode on an upper portion and a lower portion of the body.

[0071] After forming the cover, through holes may be formed in the body using laser drilling, mechanical pin punching, etc. Then, first and second through electrodes may be formed by applying conductive paste to the through holes or filling conductive material using plating or the like.

[0072] Then, first, second, third, and fourth external electrodes may be formed on one surface of the body to be connected to the first and second through electrodes.

[0073] Specifically, the formation of the first external electrode, the second external electrode, the third external electrode and the fourth external electrode can be achieved by an operation including the following steps: forming a first sintered electrode, a second sintered electrode, a third sintered electrode and a fourth sintered electrode each containing nickel on the main body; forming a first plating layer on each of the first sintered electrode, the second sintered electrode, the third sintered electrode and the fourth sintered electrode; and forming a second plating layer on each of the first plating layers.

[0074] The sintered electrode may be formed by coating a conductive paste containing nickel and sintering the conductive paste. The first plating layer may contain tin and may be formed by an electroplating method or a chemical plating method. The second plating layer may contain copper or tin and may be formed by an electroplating method or a chemical plating method.

[0075] After forming the sintered electrode, sintering and plasticization are performed to form the first plating layer and the second plating layer. As a result, the Figure 1 and Figure 5 The multilayer ceramic capacitor shown in .

[0076] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the above embodiments and drawings, and is intended to be limited by the appended claims. Therefore, without departing from the technical spirit of the present disclosure described in the claims, those skilled in the art may make various forms of replacement, modification and change, which may also be within the scope of the present disclosure.

[0077] According to an embodiment of the present disclosure, by applying a sintered electrode including nickel to an external electrode connected to a through electrode penetrating a body, the adhesive strength of a multilayer ceramic capacitor may be improved.

[0078] According to another embodiment of the present disclosure, a plating layer may be provided on a side surface of a body to increase a bonding area with solder during mounting, and moisture resistance reliability may be improved.

[0079] According to another embodiment of the present disclosure, a surface of the external electrode may have a predetermined centerline average roughness (Ra) to form a nickel plating layer on the external electrode.

[0080] According to another embodiment of the present disclosure, a multilayer ceramic capacitor having improved adhesion to a substrate while having a low profile may be provided.

[0081] According to another embodiment of the present disclosure, the occurrence of cracks due to mismatching, etc. in a sintering process may be prevented, thereby improving the reliability of a product.

[0082] However, various advantageous advantages and effects of the present disclosure are not limited to the above description and will be more easily understood in the course of describing specific embodiments of the present disclosure.

[0083] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A multilayer ceramic capacitor comprising: a body including a dielectric layer and first and second internal electrodes, wherein the dielectric layer is interposed between the first and second internal electrodes, and the body including a fifth surface and a sixth surface opposite to each other in a first direction, a third surface and a fourth surface opposite to each other in a second direction, and a first surface and a second surface opposite to each other in a third direction; a first external electrode disposed on the first surface of the body; a second external electrode disposed on the second surface of the body; a third external electrode disposed on the first surface of the body and spaced apart from the first external electrode; a fourth external electrode disposed on the second surface of the body and spaced apart from the second external electrode; a first through electrode passing through the body and connected to the first internal electrode, and located between the first external electrode and the second external electrode; and a second through electrode, passing through the body and connected to the second inner electrode, and located between the third outer electrode and the fourth outer electrode, wherein a portion of each of the first external electrode and the second external electrode is disposed on the third surface of the body, and a first gap is formed between the first external electrode and the second external electrode, wherein a portion of each of the third external electrode and the fourth external electrode is disposed on the fourth surface of the body, and a second gap is formed between the third external electrode and the fourth external electrode, wherein each of the first external electrode, the second external electrode, the third external electrode and the fourth external electrode comprises: at least one plating layer; and a sintered electrode disposed between the body and the at least one plating layer, and The at least one plating layer is disposed on the third surface and the fourth surface of the main body, and is closer to the center of the third surface or the fourth surface in the third direction than the sintered electrode.

2. The multilayer ceramic capacitor according to claim 1, wherein The first internal electrode and the first through-electrode include the same metal material, and the second internal electrode and the second through-electrode include the same metal material.

3. The multilayer ceramic capacitor according to claim 1, wherein Each of the first external electrode, the second external electrode, the third external electrode, and the fourth external electrode has a thickness in the range of 1 μm to 30 μm.

4. The multilayer ceramic capacitor according to claim 1, wherein The at least one plating layer is in contact with the third surface or the fourth surface of the body, and The sintered electrode is in contact with the first surface or the second surface of the body.

5. The multilayer ceramic capacitor according to claim 1, wherein The body has a thickness greater than or equal to 5 μm and less than or equal to 100 μm.

6. The multilayer ceramic capacitor according to claim 1, wherein Portions of the third surface and the fourth surface overlapping the first through electrode and the second through electrode in the second direction are not completely covered by the first, second, third, and fourth external electrodes.

7. The multilayer ceramic capacitor according to claim 1, wherein: Each of the first external electrode, the second external electrode, the third external electrode, and the fourth external electrode is L-shaped when viewed from the first direction.

8. The multilayer ceramic capacitor according to claim 1, wherein The ratio T2 / T1 is in the range of 1 / 3 to 2 / 5, wherein T1 is the thickness of the body, and T2 is the sum of the lengths of at least one plating layer of the first external electrode and the second external electrode disposed on the third surface of the body or the sum of the lengths of at least one plating layer of the third external electrode and the fourth external electrode disposed on the fourth surface of the body.

9. The multilayer ceramic capacitor according to claim 1, wherein: The center line average roughness Ra of the sintered electrode is in the range of 1 nm to 100 nm.

10. The multilayer ceramic capacitor according to claim 1, wherein The sintered electrode includes nickel.

11. The multilayer ceramic capacitor according to claim 10, wherein: The at least one plating layer includes a first plating layer including nickel and a second plating layer including copper or tin, and The first plating layer is disposed between the second plating layer and the sintered electrode.

12. The multilayer ceramic capacitor according to claim 11, wherein When the thickness of the portion of the first plating layer extending to the third and fourth surfaces of the body is t2 and the thickness of the portion of the first plating layer disposed on the sintered electrode is t1, the multilayer ceramic capacitor satisfies a relationship of t2 ≥ t1.

13. The multilayer ceramic capacitor according to claim 11, wherein When the thickness of the portion of the second plating layer extending to the third and fourth surfaces of the body is t4 and the thickness of the portion of the second plating layer disposed on the sintered electrode is t3, the multilayer ceramic capacitor satisfies a relationship of t4 ≥ t3.

14. The multilayer ceramic capacitor according to claim 10, wherein: The first internal electrode and the second internal electrode include nickel.

15. The multilayer ceramic capacitor according to claim 10, wherein: The first through-electrode and the second through-electrode include nickel.

16. The multilayer ceramic capacitor according to claim 1, wherein The first through electrode includes a first connection electrode and a fourth connection electrode connected to the first external electrode and the second external electrode, and The second through electrode includes a second connection electrode and a third connection electrode connected to the third external electrode and the fourth external electrode.

17. The multilayer ceramic capacitor according to claim 16, wherein: The first inner electrode and the second inner electrode are T-shaped and point-symmetrical to each other. The first connection electrode and the fourth connection electrode pass through a region where the second inner electrode is not provided, and The second connection electrode and the third connection electrode pass through a region where the first internal electrode is not disposed.

18. The multilayer ceramic capacitor according to claim 16, wherein: The first inner electrode and the second inner electrode are rectangular and point symmetrical to each other. The first inner electrode includes a second via hole and a third via hole, The second inner electrode includes a first via hole and a fourth via hole, The first connection electrode and the fourth connection electrode pass through the first via hole and the fourth via hole of the second inner electrode, and The second connection electrode and the third connection electrode pass through the second via hole and the third via hole of the first internal electrode.

19. A multilayer ceramic capacitor comprising: a body including a dielectric layer and first and second internal electrodes, wherein the dielectric layer is interposed between the first and second internal electrodes, and the body including a fifth surface and a sixth surface opposite to each other in a first direction, a third surface and a fourth surface opposite to each other in a second direction, and a first surface and a second surface opposite to each other in a third direction; a first external electrode disposed on the first surface of the body; a second external electrode disposed on the second surface of the body; a third external electrode disposed on the first surface of the body and spaced apart from the first external electrode; a fourth external electrode disposed on the second surface of the body and spaced apart from the second external electrode; a first through electrode passing through the body and connected to the first internal electrode, and located between the first external electrode and the second external electrode; and a second through electrode, passing through the body and connected to the second inner electrode, and located between the third outer electrode and the fourth outer electrode, wherein a portion of each of the first external electrode and the second external electrode is disposed on the third surface of the body, and a first gap is formed between the first external electrode and the second external electrode, wherein a portion of each of the third external electrode and the fourth external electrode is disposed on the fourth surface of the body, and a second gap is formed between the third external electrode and the fourth external electrode, The first through electrode includes a first connecting electrode and a fourth connecting electrode connected to the first external electrode and the second external electrode. The second through electrode includes a second connection electrode and a third connection electrode connected to the third external electrode and the fourth external electrode. The first inner electrode and the second inner electrode are rectangular and point symmetrical to each other. The first inner electrode includes a second via hole and a third via hole, The second inner electrode includes a first via hole and a fourth via hole, The first connection electrode and the fourth connection electrode pass through the first via hole and the fourth via hole of the second inner electrode, The second connection electrode and the third connection electrode pass through the second via hole and the third via hole of the first inner electrode, and A ratio D1 / D3 of a distance D1 between the first connection electrode and the fourth connection electrode or a distance D1 between the second connection electrode and the third connection electrode to a distance D3 between the first via hole and the second via hole is in a range of 2.08 to 4.

7.

20. A multilayer ceramic capacitor comprising: a body including a dielectric layer and first and second internal electrodes, wherein the dielectric layer is interposed between the first and second internal electrodes, and the body including a fifth surface and a sixth surface opposite to each other in a first direction, a third surface and a fourth surface opposite to each other in a second direction, and a first surface and a second surface opposite to each other in a third direction; a first external electrode disposed on the first surface of the body; a second external electrode disposed on the second surface of the body; a third external electrode disposed on the first surface of the body and spaced apart from the first external electrode; a fourth external electrode disposed on the second surface of the body and spaced apart from the second external electrode; a first through electrode passing through the body and connected to the first internal electrode, and located between the first external electrode and the second external electrode; and a second through electrode, passing through the body and connected to the second inner electrode, and located between the third outer electrode and the fourth outer electrode, wherein a portion of each of the first external electrode and the second external electrode is disposed on the third surface of the body, and a first gap is formed between the first external electrode and the second external electrode, wherein a portion of each of the third external electrode and the fourth external electrode is disposed on the fourth surface of the body, and a second gap is formed between the third external electrode and the fourth external electrode, The first through electrode includes a first connection electrode and a fourth connection electrode connected to the first external electrode and the second external electrode. The second through electrode includes a second connection electrode and a third connection electrode connected to the third external electrode and the fourth external electrode. The first inner electrode and the second inner electrode are rectangular and point symmetrical to each other. The first inner electrode includes a second via hole and a third via hole, The second inner electrode includes a first via hole and a fourth via hole, The first connection electrode and the fourth connection electrode pass through the first via hole and the fourth via hole of the second inner electrode, The second connection electrode and the third connection electrode pass through the second via hole and the third via hole of the first inner electrode, and A ratio D2 / D3 of a diameter D2 of the first connection electrode or the second connection electrode to a distance D3 between the first via hole and the second via hole is in a range of 0.375 to 0.

52.

21. A multilayer ceramic capacitor comprising: a body including a dielectric layer and first and second internal electrodes, wherein the dielectric layer is interposed between the first and second internal electrodes, and the body including a fifth surface and a sixth surface opposite to each other in a first direction, a third surface and a fourth surface opposite to each other in a second direction, and a first surface and a second surface opposite to each other in a third direction; a first external electrode disposed on the first surface of the body; a second external electrode disposed on the second surface of the body; a third external electrode disposed on the first surface of the body and spaced apart from the first external electrode; a fourth external electrode disposed on the second surface of the body and spaced apart from the second external electrode; a first through electrode passing through the body and connected to the first internal electrode, and located between the first external electrode and the second external electrode; and a second through electrode, passing through the body and connected to the second inner electrode, and located between the third outer electrode and the fourth outer electrode, wherein a portion of each of the first external electrode and the second external electrode is disposed on the third surface of the body, and a first gap is formed between the first external electrode and the second external electrode, wherein a portion of each of the third external electrode and the fourth external electrode is disposed on the fourth surface of the body, and a second gap is formed between the third external electrode and the fourth external electrode, wherein each of the first external electrode, the second external electrode, the third external electrode and the fourth external electrode comprises at least one plating layer, and wherein the ratio T2 / T1 is in the range of 1 / 3 to 2 / 5, wherein T1 is the thickness of the body, and T2 is the sum of the lengths of at least one plating layer of the first external electrode and the second external electrode disposed on the third surface of the body or the sum of the lengths of at least one plating layer of the third external electrode and the fourth external electrode disposed on the fourth surface of the body.

Citation Information

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