Semiconductor device with identification structure, method of manufacturing the same and method of tracing production information thereof

Abstract

A semiconductor device with identification structure is provided. The semiconductor device has a substrate and a metallization structure above the substrate. The metallization structure includes an interconnect region with a plurality of metal layers and an identification region isolated from the interconnect region. The identification region has an identification structure at the same level as one of the metal layers. The identification structure has at least one exposed recess and at least one exposed fuse. A method of manufacturing a semiconductor device with an identification structure and a method of tracing production information of a semiconductor device are also provided.

Description

Technical Field

[0001] The present invention discloses a semiconductor device, a method for manufacturing the same, and a method for tracing its production information. In particular, the identification structure formed in the semiconductor device of the present invention can be visually identified. Since passive components cannot be identified electronically, the identification structure disclosed in the present invention can be applied to identify passive components. Background Technology

[0002] Manufacturing information for semiconductor integrated circuits (ICs) can be an identification number representing the manufacturing history or an IC chip number assigned by the manufacturer. In some examples, the manufacturing information of a semiconductor IC is written to its built-in memory or external memory before it begins normal operation. With this configuration, the processor can immediately read the manufacturing information stored in memory after normal operation begins, allowing the processor to appropriately control the semiconductor IC.

[0003] In other examples, production information such as the manufacturing history and manufacturer's identification number of a semiconductor IC is stored in a production information reference register within the semiconductor IC. This stored production information can be read by an external processor and used for various purposes. Summary of the Invention

[0004] In one exemplary embodiment, the present invention provides a semiconductor device. The semiconductor device includes a substrate and a metallization structure located above the substrate. The metallization structure includes an interconnect region having a plurality of metal layers and an identification region isolated from the interconnect region. The identification region has an identification structure at the same level as one of the metal layers. The identification structure has at least one exposed groove and at least one exposed fuse.

[0005] In another exemplary embodiment of the present invention, a method for manufacturing a semiconductor device having an identification structure is provided, the method comprising the following operations: receiving a substrate; forming a metallization structure on the substrate, wherein the metallization structure includes an identification region, the identification region including a plurality of grooves arranged in at least one row, and each groove being filled with a fuse; removing a portion of the fuses from the grooves to form an identification structure.

[0006] In yet another exemplary embodiment of the present invention, a method is provided for tracing production information of a semiconductor device having an identification structure as described above, the method comprising the following operations: identifying the distribution of at least one exposed groove and at least one exposed fuse to obtain distribution information; and obtaining production information of the semiconductor device by using the distribution information.

[0007] Simple Explanation of the Diagram

[0008] By reading the following embodiments and accompanying drawings, one can best understand the various embodiments disclosed in this invention. It should be noted that, in accordance with standard practice in the art, the various features in the figures are not drawn to scale. In fact, the dimensions of some features may be intentionally enlarged or reduced for clarity of description.

[0009] Figure 1A A top view of a semiconductor device according to some embodiments disclosed in the present invention is shown.

[0010] Figure 1B A cross-sectional view of a semiconductor device according to some embodiments disclosed in the present invention is shown.

[0011] Figure 2 A list of conversions of production information in binary representation is illustrated according to some embodiments of the content disclosed in this invention.

[0012] Figure 3A A top view illustrating an identification structure according to some embodiments of the present invention is shown.

[0013] Figure 3B A cross-sectional view illustrating an identification structure according to some embodiments of the content disclosed in this invention is shown.

[0014] Figure 4 A top view illustrating adjacent grooves and grooves filled with fusible wires according to some embodiments of the present invention is shown.

[0015] Figures 5A to 5D Cross-sectional views of a semiconductor device having an identifiable structure are illustrated in some embodiments of the invention disclosed herein.

[0016] Figures 6A to 6C Cross-sectional views of a semiconductor device having an identifiable structure are illustrated in some embodiments of the invention disclosed herein.

[0017] Figure 7A and Figure 7B Cross-sectional views of a semiconductor device having an identifiable structure are illustrated in some embodiments of the invention disclosed herein. Detailed Implementation

[0018] This application claims priority to U.S. Provisional Application No. 63 / 209,934, filed on June 11, 2021, the entire contents of which are incorporated herein by reference.

[0019] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and configurations are described below to simplify the invention. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the first member being formed above or on the second member may include embodiments where the first and second members are in direct contact, and may also include embodiments where an additional member is formed between the first and second members, so that the first and second members are not in direct contact. Furthermore, element symbols and / or letters may be repeated in various instances of the invention disclosure. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, for ease of description, spatial relative terms such as "below," "under," "down," "above," "above," and similar terms may be used herein to describe the relationship of one element or component to another element or component(s), as illustrated in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and these can also be used accordingly to explain the spatial relative descriptors used herein.

[0021] As used herein, terms such as "first," "second," and "third" describe various elements, components, regions, layers, and / or sections, and these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms may only be used to distinguish one element, component, region, layer, or section from another. When terms such as "first," "second," and "third" are used in the text, it does not imply order or sequence unless explicitly indicated by the context.

[0022] If the semiconductor device is an active element, its identification can be achieved through electronic identification formed within it. An active element is a device containing analog electronic filters that amplifies signals or generates power gain. Typical active elements can be oscillators, transistors, or integrated circuits. Because active elements have logic circuits (e.g., register circuits) that can be programmed to read element information such as production information, they can be accessed electrically.

[0023] Compared to active components, the aforementioned electronic identification cannot be implemented in passive components because passive components cannot introduce net energy into the circuit. Passive components include two-terminal components such as resistors, capacitors, inductors, and transformers. These passive components do not rely on a power source other than the AC circuit to which they are connected. Therefore, even if a passive component can increase voltage or current, it cannot amplify the signal (increase the signal power).

[0024] Therefore, this invention provides a non-electronic identification method for identifying semiconductor devices, particularly passive components that were previously unidentifiable. In some embodiments of this invention, the non-electronic identification method is a visual identification method, and by utilizing structural features embedded in the semiconductor device, production information of the semiconductor device can be accurately recorded and read via the visual identification method. Accordingly, traceability of semiconductor devices, such as fault analysis and tracing, can be traced back to the manufacturing stage, thereby revealing the cause of failure. This is of great help for product manufacturing research and development and for optimizing quality control.

[0025] In some embodiments of the present invention, a semiconductor device having an identification structure or identification tag is disclosed. (See reference...) Figure 1A and Figure 1B The semiconductor device 10 may include a substrate 100 and a metallization structure 102 located above the substrate 100. The substrate 100 may be a semiconductor substrate comprising semiconductor materials such as silicon, germanium, or diamond. In some alternative embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, or combinations thereof may also be used. In other embodiments, the substrate 100 is made of glass. In embodiments where the semiconductor device is a passive element, the substrate 100 may not have an electrical structure.

[0026] Metallization structure 102 is formed above a top surface of substrate 100. In some embodiments, a dielectric layer 104 is provided between metallization structure 102 and substrate 100. Dielectric layer 104 may be part of a mid-stage process (MOL / MEOL) structure, i.e., a portion formed before the formation of the first metal layer (M1) of metallization structure 102. Metallization structure 102 includes an interconnect region 118 and an identification region 114 isolated outside the interconnect region 118. The interconnect region 118 of metallization structure 102 may include at least one metal layer, for example, the interconnect region 118 may have a plurality of stacked metal layers and a plurality of second dielectric layers, and these metal layers may be electrically connected via a plurality of conductive vias. In some embodiments, metallization structure 102 may be part of a back-end process (BEOL) structure. In some embodiments, some structures of passive components may be formed in the MEOL structure.

[0027] refer to Figure 1B , it is along Figure 1AThe cross-sectional view of the semiconductor device shown by line segment AB in some embodiments shows that the metallization structure 102 includes a metal layer 106 and an identification structure 108 located at the same level as the metal layer 106. The metal layer 106 is made of a conductive material such as aluminum or copper. The metal layer 106 is part of the circuit structure, and therefore the metal layer 106 is in contact with a conductive via (not shown) on a top surface of the metal structure of the metal layer 106. In contrast, in the identification region 114, where the identification structure 108 is configured for identification purposes, the identification structure 108 is electrically isolated from and disconnected from the metal layer 106. In some embodiments, the identification structure 108 is completely disconnected from any conductive structure in the semiconductor device.

[0028] The identification structure 108 may include at least one exposed groove and at least one exposed fuse for visual identification. In some embodiments, such as in Figure 1A As shown, the identification structure 108 may include a plurality of grooves 110 arranged in at least one row from a top view angle, and a plurality of fuses 112 distributed in the plurality of grooves 110. These fuses 112 are distributed in at least a portion of the grooves 110. In other words, in some embodiments of the invention, the identification structure 108 is an array of empty grooves 110 and grooves 110 filled with fuses 112, or an arrangement of one or more rows. The fuses 112 filling the grooves 110 may be conductive metal wires or conductors suspended in the surrounding dielectric material, and from a top view angle, the outline of each groove 110 substantially corresponds to the outline of the fuse 112. Each fuse 112 is electrically disconnected from the metal layer 106. Additionally, in some embodiments, the fuse 112 may be melted by a laser beam or laser energy, and a portion of the dielectric material (if any) covering the fuse 112 is thus vaporized, forming (exposed) grooves 110. These grooves are typically used as high-resistance cuts for electrical purposes; however, in this invention, these grooves 110 are used for visual identification purposes by comparison with a fuse 112 that has not been melted by a laser. Details regarding the formation of the grooves 110 and the distribution of the grooves 110 and the fuse 112 will be discussed in later paragraphs.

[0029] Since the fuse 112 can be formed simultaneously with the metal layer, the material of the fuse 112 is the same as that of the metal layer (such as aluminum or copper). The groove 110 without the fuse 112 can be configured to represent a "first code" or "first number", while the groove 110 with the fuse 112 therein can be configured to represent a "second code" or "second number". This means that the identification structure 108 in some embodiments of the present invention is a binary representation system.

[0030] Since the identification structure 108 in some embodiments of the present invention is electrically isolated and disconnected from the metal layer 106, the function of the identification structure 108 must be implemented visually rather than electrically. According to the schematic diagram, i.e. Figure 1A As shown, the brightness of a groove 110 without a fuse 112 and a groove 110 with a fuse 112 are visually distinguishable. For example, when a groove 110 is filled with a fuse 112, the groove 110 (with the fuse 112) is bright (marked by a diagonal line in the diagram), and it is significantly brighter than a groove 110 not filled with a fuse 112. Meanwhile, multiple grooves 110 not filled with a fuse 112 can be classified as dark. Therefore, these grooves 110 can be divided into bright or dark depending on whether they are filled with a metallic material such as a fuse 112.

[0031] By using these light and dark patterns, the identification structure 108 can record production information in binary representation. In some embodiments, fuses 112 can be arranged or programmed to represent production information of a semiconductor device. For example, a recess 110 without fuses 112 (i.e., fuses 112 are not arranged to occupy recess 110) can be configured as the number "1", while a recess 110 with fuses 112 (i.e., fuses 112 are arranged to occupy recess 110) can be configured as the number "0". Accordingly, the recess 110 has a difference (i.e., light and dark contrast) between having and not having fuses 112, which can therefore be used as binary numbers and further translated into different letters, numbers, or other characters that can be represented by bit strings of the same length.

[0032] In some embodiments, the identification structure 108 may include dozens of recesses 110 arranged in one or more rows. For example, the identification structure 108 may include 40 recesses 110 for illustrating manufacturing information of the semiconductor device. These recesses 110 may be physically arranged in an array of multiple rows. The physical arrangement of the recesses 110 is to conform to the structure of the semiconductor device; that is, the identification region 114 is typically located in a peripheral region of the semiconductor device, and the dielectric layer of the metallization structure 102 within the identification region 114 may include a rectangular opening window to expose the identification structure 108. This rectangular opening window may have a cross-sectional area of ​​about tens of micrometers in length and tens of micrometers in width, for example, about 70 micrometers * about 20 micrometers.

[0033] In some embodiments, the production information of a semiconductor device, such as a semiconductor die, may correspond to information about the location of the semiconductor die before it is diced from the wafer. This information is helpful in tracing the manufacturing status of the wafer if the semiconductor die fails during testing or if there is customer feedback. In these embodiments, the identification structure 108 can provide production serial numbers, particularly production information such as the batch number of the wafer and the coordinates of the semiconductor die on the wafer.

[0034] refer to Figure 2 In the embodiment described above regarding the identification structure 108 providing production information, the wafer batch number (i.e., batch ID) may include the wafer batch number and the wafer's number within that batch, while the semiconductor die coordinates may include X and Y coordinates. Figure 2 In the example shown, the batch number can be a three-bit information, requiring 10 notches 110 and some necessary fuses 112 to record the information in binary. Since each batch of wafers typically contains 25 wafers, the wafer number can therefore be a two-bit information, requiring 5 notches 110 and some necessary fuses 112 to record the information in binary. Each X and Y coordinate can also be a three-bit information, thus requiring a total of 20 notches 110 and some necessary fuses 112 to record the information in binary. Accordingly, in order to record the production information of the semiconductor device, a total of 35 notches 110 and some necessary fuses 112 are required in the above example. In some embodiments, a total of 40 or more notches 110 and some necessary fuses 112 are used, because 5 or more additional notches 110 can be prepared as reserved bits. Reserved bits can be used to record test results, for example, a simple result about whether the semiconductor die has been tested as a good die or a bad die. In some embodiments, the number of recesses 110 may be between about 20 and about 50. Generally speaking, the more information to be recorded in the identification structure 108, the more recesses 110 need to be formed within the rectangular opening window, which also means that the identification structure 108 needs to occupy more area in the metallized structure 102.

[0035] In some embodiments, the identification structure 108 may be used solely to record the production serial number of a semiconductor device. In other embodiments, the identification structure 108 may be further used to record the test results of the semiconductor device, meaning that the identification structure 108 needs to be formed after testing to provide more specific performance information for each semiconductor device. For example, semiconductor devices such as memory chips may be tested and classified into different grades based on their performance. These graded semiconductor devices may be used in different electronic products for different purposes, such as general use or for overclocking. By utilizing the identification structure 108, the test results of the semiconductor device (e.g., chip grading) can be easily visually identified.

[0036] In some embodiments, the production information can be very detailed. For example, the wafer fabrication equipment used in the semiconductor device manufacturing process, the production date, the testing date, and the coordinates of the semiconductor device on the wafer can be directly traced based on the identification structure 108.

[0037] The identification structure 108 can provide significant benefits in fault analysis and tracing. Fault analysis can include aspects such as wafer fault location, wafer pattern correlation, and wafer acceptance testing. For example, in some semiconductor industry applications, a wafer may be sold by an upstream manufacturer to a downstream manufacturer. This wafer has been tested, and there may be several defective dies marked for the downstream manufacturer. If the semiconductor dies are passive components, traditionally, these dies cannot be traced after the wafer is cut, and therefore the downstream manufacturer may misuse defective dies in its products. At this point, it is impossible to determine whether the presence of defective dies in the product is due to the downstream manufacturer's misuse or damage caused during the shipping process. However, based on the identification structure 108 formed on each die, even if these dies are passive components that cannot be electronically identified, they can still be visually identified. Therefore, at this point it is possible to determine whether there are specific problems in the manufacturing process (such as defective parameters of the wafer fabrication equipment), whether the good product testing performed by the upstream manufacturer is correct, and whether the downstream manufacturer has correctly selected the good dies cut from the wafer.

[0038] Furthermore, as mentioned earlier, since electronic (identification) methods cannot be implemented in passive components, visual identification methods are suitable for passive components. However, visual identification methods can also be applied to active components as an alternative for product traceability. For example, considering that the register circuit of an active component may malfunction and fail to be read correctly, the aforementioned visual identification method can serve as a backup option for product traceability.

[0039] In some embodiments, the identification structure 108 is located at the same horizontal level as the first metal layer 106 of the metallization structure 102. The thickness of one of the plurality of metal layers (e.g., the first metal layer 106) is the same as the thickness of the fuse 112, and the width of each fuse 112 is substantially the same as the diameter of the spot size of a laser beam used to melt the fuse 112. Therefore, during the writing of production information, the fuse 112 can be selectively removed from the groove 110 by passing through the laser. In some embodiments, the identification structure 108 is located at the same horizontal level as the thinnest metal layer in the metallization structure 102. The vertical position of the identification structure 108 is related to its manufacturing process, which will be explained in later paragraphs.

[0040] To visually distinguish between recesses 110 with and without fuses 112, a portion of the fuses 112 are removed from the recesses 110 by a laser. In some embodiments, the fuses 112 may not be completely removed from the recesses 110. For example, such as Figure 3A and Figure 3B As shown, where Figure 3B It is along Figure 3A The cross-sectional view of the identification device for line segment CD, as indicated, shows that after the fuse 112 is removed by laser (which can be described as laser melting, trimming, or cutting), some residue may remain in the groove 110, and thus a corner of the groove 110 may be covered by residual metal 112A. In other words, the fuse 112 may only be partially removed rather than completely removed. In the case of partial removal, the laser-cut fuse 112 may have a substantially recessed contour on its top surface. That is, these grooves 110 may not be filled by the fuse 112, but the bottom of each of these grooves 110 is covered by metal with a recessed contour on its top surface. Even though these grooves 110 do not contain completely undamaged fuses or metal particles, the residual metal is not as bright as a complete fuse 112. Therefore, grooves 110 with complete fuses 112 and grooves 110 without complete fuses 112 can still be visually distinguished by a microscope or the naked eye.

[0041] refer to Figure 4In some embodiments, each groove 110 and the fuse 112 therein may have a rectangular outline from a top viewing angle. In some embodiments, adjacent grooves 110 are spaced about 2.7x (x is a constant value), and the width of each groove 110 is about 0.8x. In some embodiments, the length of each groove 110 is about 1.8x. There are no strict limitations on the spacing and aspect ratio, but each groove 110 and the fuse 112 therein should be visually distinguishable, and the fuse 112 should be laser-cut. Similarly, the outline of the groove 110 and the fuse 112 therein is not limited to the rectangle in the above examples, and other shapes of outlines are still within the scope of the invention.

[0042] In some embodiments, the identification structure 108 is completed during the waferout stage of the semiconductor manufacturing process. Specifically, the formation of the identification structure 108 can be divided into two stages, the first stage being the formation of recesses 110 and the filling of fuses 112 in each recess. Therefore, each recess 110 is filled with metal (i.e., fuses 112), and each of the neatly arranged recesses 110 is visually completely bright. Parts of the fuses 112 will be melted, trimmed, or cut through a laser programming process to form (empty) recesses 110, thereby programming the recesses 110 and the remaining fuses 112 into an information structure.

[0043] Manufacturing such as Figure 1B The process of the semiconductor device with identification structure 108 shown can be referred to Figures 5A to 5D .like Figure 5A As shown, in some embodiments, a substrate 100 is first received, wherein the substrate 100 is typically a semiconductor wafer on which a plurality of semiconductor devices are formed, and the identification structure 108 is formed at the wafer level, rather than after the wafer dicing operation. In some embodiments, a dielectric layer 104 may be formed on the substrate 100 before the metallization structure 102 is formed on the substrate 100, and therefore the subsequently formed metallization structure 102 is formed on the dielectric layer 104.

[0044] Next, refer to Figure 5BA metallization structure 102 may be formed over a substrate 100. The metallization structure 102 includes an identification region 114 reserved for forming an identification structure 108, and one or more metal layers are formed within an interconnect region 118 of the metallization structure 102. One or more interlayer dielectrics (ILDs) 126 may be used to cover and / or surround the metal layers in the metallization structure 102. In some embodiments, a pattern of one of the metal layers (e.g., metal layer 106) and a fuse 112 may be formed simultaneously, wherein the metal layer is formed for electrical connection, and the fuse 112 is completely isolated from any conductive structure. The contour of the material (e.g., dielectric material) surrounding each fuse 112 can be considered as a groove 110, which is not yet exposed at this stage. In some embodiments, metal layer 106 is the thinnest metal layer in the metallization structure 102. The selection of the vertical position of the fuse 112 is related to the laser parameters used to cut the fuse 112. That is, in some embodiments, the fuse 112 is at the same level as the thinnest metal layer in the metallization structure 102, which is usually the first metal layer (M1), because this cleaning operation, or trimming operation or cutting operation, is more easily performed on the first metal layer in the metallization structure 102.

[0045] When the fuse 112 is relatively thick, for example, when the fuse 112 is formed simultaneously with layers that are thicker than the first metal layer, such as a second metal layer or other upper metal layers, the thickness of the fuse 112 may make it more difficult to remove. The thickness of the metal layer is substantially the same as the thickness of the fuse 112 located at the same level. On the other hand, once the laser power is increased to remove these thicker fuses 112, not only may the increased laser power damage the surrounding structure, but the additional debris generated by the removed fuse 112 may also sputter into the surrounding area, causing contamination. As mentioned above, in some embodiments, some structures of the passive element may be formed within the MEOL structure, and if these passive element structures are formed below the identification structure 108, the increased laser power may damage these passive elements. Therefore, the preferred option in current practice is to make the thickness of the fuse 112 as thin as the first metal layer, but the scope of the invention is not limited to these practical experiences.

[0046] refer to Figure 5C and 5DIn some embodiments, a portion of the fuses 112 are removed from the plurality of recesses 110. Before removing these portion of the fuses 112, since the fuses 112 are covered by a thick dielectric material (e.g., several ILD layers 126), an opening window 116 can be formed in the ILD layer 126 in the identification region 114 to pre-expose the fuses 112. In some embodiments, the opening window 116 can be formed by photomask and etching operations. The removal of the fuses 112, which may be referred to as cleaning, trimming, or cutting, is performed based on a laser profile provided by the semiconductor device manufacturer. The laser profile is a guide indicating which fuses 112 should be removed from the recesses 110, thereby programming the array of recesses 110 as visual labels. Generally, the removal step can be performed based on laser repair techniques. Laser repair is widely used in the semiconductor industry, such as memory manufacturing. This technology uses a laser beam to cut circuit fuses to decode the circuit, thereby replacing defective memory cells with spare circuitry to improve manufacturing yield. In this invention, since the targets to be cut are almost identical, the two technologies should be technically compatible, making it relatively easy to use these well-tuned laser parameters to cut the fuses 112 in the grooves 110. However, the thickness of the metal layer of the metallization structure 102 in different semiconductor devices can vary significantly due to different design rules. Therefore, the laser power and other corresponding parameters required to remove a portion of the fuses 112 from multiple grooves 110 should still be readjusted according to the specific circumstances.

[0047] The laser profiles provided by the semiconductor device manufacturer may contain production information for the semiconductor device. Since each semiconductor device (e.g., a semiconductor die) should have once been located at a specific coordinate position on a specific wafer, each semiconductor device should have a unique identification structure that differs from each other. In other words, the identification structure 108 in this invention is customized for each semiconductor device, and therefore this identification structure 108 is not the kind of manufacturer's trademark that is typically patterned in the corner of a semiconductor device.

[0048] The laser file is used to provide production information. As mentioned earlier, the production information may include information that can be used to trace the manufacturing process, including the wafer fabrication equipment used in the manufacturing process of the semiconductor device, the production date, the testing date, and the coordinates of the semiconductor device on the wafer. In addition, if the semiconductor device has been tested, the laser file may further include the test results to add more information to the identification structure 108.

[0049] By removing a portion of the fuses 112 from the plurality of grooves 110, the arrangement of grooves 110 in the identification structure 108 can thus include a plurality of dark units (i.e., grooves 110 in which no fuses 112 are located) and a plurality of bright units (i.e., grooves 110 in which fuses 112 are located), and these visually distinguishable units can be used to represent the numbers 0 and 1 (or 1 and 0) in binary.

[0050] refer to Figures 6A to 6C In some embodiments, the identification structure 108 is at the same horizontal level as a metal layer in the metallization structure 102 located above the first metal layer. In other words, in some embodiments, the identification structure 108 is not formed at the same height as the thinnest metal layer in the metallization structure 102. However, regardless of whether the fuse 112 used as the identification structure 108 is... Figure 5B The (first) metal layer (M1) 106 shown is located at the same height and is with Figure 6A The second metal layer (M2) 120 or the third metal layer (M3) 122 shown are located at the same height, as... Figure 6B As shown, before removing a portion of the fuses 112, the opening windows 116 can be formed in the ILD layer 126 within the identification region 114 to provide sufficient depth to expose the fuses 112 used for the identification structure 108.

[0051] refer to Figure 7A and 7B In some embodiments, the dielectric material on the identification structure 108 is not completely removed during the formation of the opening window 116. That is, a thin dielectric layer 124 may be retained above the fuses 112 of the identification structure 108. The thickness of the thin dielectric layer 124 is less than that of each other dielectric layer (i.e., ILD layer 126) in the interconnect region 118 of the metallization structure 102. By removing a portion of the fuses 112 using a laser, the thin dielectric layer 124 may thus include a plurality of openings exposing the recesses 110 not filled by the fuses 112. On the other hand, the top surface of each fuse 112 is in contact with the thin dielectric layer 124.

[0052] In some embodiments, the thin dielectric layer 124 is made of aluminum oxide (AlOx), which is advantageous for focusing laser energy during the cutting of the fuse 112. Additionally, the thin dielectric layer 124 retained on and in contact with the fuse 112 serves to prevent oxidation of the fuse 112 in the identification structure 108. Although these fuses 112 are configured for visual identification rather than electrical connection purposes, the unoxidized metal provides better contrast compared to grooves 110 without fuses 112 located therein.

[0053] After removing a portion of the fuses 112 from the plurality of recesses 110, the wafer with the semiconductor device can then undergo subsequent manufacturing operations according to typical manufacturing processes, such as bumping, packaging, dicing, testing (testing operations may precede the removal of some fuses using a laser), and shipping. In some embodiments, the opening 116 for exposing the identification structure 108 is covered or at least partially surrounded by molding material during the packaging operation. Accordingly, once the semiconductor device is returned to the manufacturer, the manufacturer can remove the molding material on the identification structure 108 before using the identification structure 108 to trace the production information of the semiconductor device. The manufacturer can then identify the distribution of the plurality of fuses 112 within the identification structure 108 to obtain distribution information, and then use this distribution information to obtain the production information of the semiconductor device. In some embodiments of the present invention, production information of a semiconductor device can thus be obtained by means of the contrast between light and dark between at least one exposed groove and at least one exposed fuse in the identification structure, for example, by means of the contrast between light and dark between a plurality of grooves 110 and a plurality of fuses 112 in the identification structure 108.

[0054] In detail, the aforementioned identification structure 108 enables semiconductor devices (especially passive components) to possess a unique ID and thus become traceable. Therefore, upon receiving feedback from the customer, the production information of the semiconductor device can be traced based on the identification structure 108. Generally, once a faulty semiconductor device is received, a visual inspection of the identification structure 108 can be performed using a microscope or the naked eye. The mixture of bright and dark cells in the identification structure 108 can be easily, quickly, and accurately decoded into production information to identify production parameters. This allows semiconductor device manufacturers to perform fault testing operations, thereby improving and optimizing product quality and yield.

[0055] In summary, according to the above embodiments, this invention discloses an identification structure for identifying semiconductor devices, enabling visual identification of semiconductor devices. In particular, the identification structure disclosed in this invention overcomes the problem that passive components lack register circuitry, making it impossible to trace production information. By utilizing fuse, groove, and laser repair techniques, the identification structure can be formed synchronously with a general BEOL structure and is easily programmed according to the unique manufacturing information of each semiconductor device. In this way, fault analysis of each semiconductor device can be traced back to very detailed production information, thereby comprehensively improving after-sales service and technical support for semiconductor devices.

[0056] The foregoing description briefly outlines some features of embodiments of this application, enabling those skilled in the art to more fully understand the various embodiments of this application. Those skilled in the art will readily recognize that this application can serve as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should understand that these equivalent embodiments remain within the spirit and scope of this application, and various changes, substitutions, and modifications can be made without departing from the spirit and scope of this application.

[0057] [Symbol Explanation]

[0058] 10: Semiconductor devices

[0059] 100: Substrate

[0060] 102: Metallized Structure

[0061] 104: Dielectric layer

[0062] 106: Metal layer

[0063] 108: Identifying Structure

[0064] 110: Groove

[0065] 112: Fuse

[0066] 112A: Residual Metals

[0067] 114: Identify the region

[0068] 116: Open window

[0069] 118: Interconnection Area

[0070] 120: Second metal layer

[0071] 122: Third metal layer

[0072] 124: Thin dielectric layer

[0073] 126: Interlayer Dielectric (ILD) Layer

[0074] AB: Line segment

[0075] CD: Line segment

Claims

1. A semiconductor device comprising: A substrate; and A metallization structure is located above the substrate, the metallization structure comprising: An interconnect region having a plurality of metal layers; and An identification region, isolated from the interconnect region, has an identification structure at the same level as one of the metal layers. This identification structure has a plurality of grooves, a plurality of fuses, and a plurality of residual metals. The fuses are made of the same material as the residual metals. The grooves are arranged in at least one row in the top view, with the fuses located in a portion of the grooves and the residual metals located in another portion of the grooves. The thickness of one of the metal layers is the same as the thickness of each of the fuses, and the top surface of the residual metal has a recessed profile.

2. The semiconductor device of claim 1, wherein an arrangement of the fuses is configured via a laser beam to represent production information of the semiconductor device, and each of the fuses is electrically disconnected from the metal layers.

3. The semiconductor device of claim 1, wherein the semiconductor device is a passive element.

4. The semiconductor device of claim 2, wherein the production information is a batch number corresponding to a wafer, the wafer number, a coordinate of the semiconductor device on the wafer, a production date, a manufacturing machine number, a test date, or a test result.

5. The semiconductor device of claim 1, wherein the metallization structure further comprises a dielectric layer having an opening window exposing the identification structure.

6. The semiconductor device of claim 1, wherein the metallization structure further includes a thin dielectric layer covering the identification structure, wherein the thickness of the thin dielectric layer is less than the thickness of each plurality of dielectric layers of the interconnect region of the metallization structure.

7. The semiconductor device of claim 6, wherein the thin dielectric layer includes a plurality of openings exposing the grooves not filled by the said fuses.

8. The semiconductor device of claim 6, wherein a top surface of each of the fuses in a portion of the said grooves is in contact with the thin dielectric layer.

9. The semiconductor device of claim 1, wherein the bottom of each of the other portion of these recesses is covered by the residual metal.

10. The semiconductor device of claim 1, wherein the number of said recesses is between 20 and 50.

11. A method for manufacturing a semiconductor device having an identification structure, the method comprising: Receive a substrate; A metallization structure is formed on the substrate, wherein the metallization structure includes a recognition region, the recognition region includes a plurality of grooves arranged in at least one row, and each of these grooves is filled with a fused wire, such that the thickness of a metal layer in the metallization structure is the same as the thickness of these fused wires; and A portion of the fuses are removed from these grooves, causing the removed portion of the fuses to form a plurality of residual metals to form the identification structure, wherein the top surface of these residual metals has a recessed profile.

12. The method of claim 11, wherein the step of removing a portion of the fuses from the grooves to form the identification structure comprises: A laser beam is used to remove that portion of the aforementioned fuses.

13. The method of claim 11, wherein the fuses are formed simultaneously with the metal layer.

14. The method of claim 13, wherein the metal layer is a first metal layer (M1) in the metallized structure.

15. The method of claim 11, wherein the step of forming the metallized structure on the substrate comprises: Before removing a portion of the fuses from the grooves, the metal layer is formed on the substrate and simultaneously fills the grooves with the fuses.

16. The method of claim 15, further comprising: At least one dielectric layer is formed on the identification structure; and An opening window is formed in the dielectric layer to expose the grooves.

17. The method of claim 11, further comprising: At least one dielectric layer is formed on the identification structure; and The dielectric layer is thinned in the identification region to form a thin dielectric layer on the identification structure, wherein the thickness of the thin dielectric layer is less than the thickness of each plurality of dielectric layers in an interconnect region of the metallized structure.

18. A method for tracing production information of a semiconductor device as claimed in claim 1, the method comprising: Identify the distribution of these grooves and these fuses to obtain distribution information; and The production information of the semiconductor device is obtained by using the distributed information.

19. The method of claim 18, wherein the distribution of the grooves and the fuses is identified by a light-dark contrast between the grooves and the fuses in the identification structure.

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