Display panel, display module and display device

Abstract

The present application discloses a display panel, a display module and a display device, relating to the technical field of displays. Since at least two first electrode patterns in the display panel are connected, and one of the at least two connected first electrode patterns is connected to a first pixel circuit, one first pixel circuit can drive two first electrode patterns. At the same time, since at least two second electrode patterns are connected, and one of the at least two connected second electrode patterns is connected to a second pixel circuit, one second pixel circuit can drive two second electrode patterns. Thus, in the case where the number of electrode patterns is the same, adopting the scheme of using one pixel circuit to drive two electrode patterns can reduce the number of pixel circuits required to be designed in the second display area, and further increase the space that each pixel circuit can occupy, and the process preparation difficulty is relatively low.

Description

[0001] This disclosure claims the priority of the PCT international patent application with the application number PCT / CN2022 / 075193 and the invention title "Display Panel and Preparation Method Thereof, Display Device" filed on January 30, 2021, the entire content of which is incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technologies, and particularly to a display panel, a display module, and a display device. Background Art

[0003] Organic light-emitting diode (OLED) display panels have been widely used due to advantages such as self-luminescence, low driving voltage, and fast response speed. An OLED display panel generally includes: a plurality of pixel units, and each pixel unit includes a light-emitting device and a pixel circuit connected to the light-emitting device.

[0004] In related technologies, in order to increase the screen-to-body ratio of a display panel, a camera of a display device can be disposed in the display area of the display panel. And in order to increase the transmittance of the area where the camera is located, generally, the pixel circuits of each pixel unit in the area where the camera is located (i.e., the camera area) are disposed in a non-camera area. The pixel circuits located in the non-camera area are connected to the light-emitting devices located in the camera area through connection traces, so as to provide driving signals for the light-emitting devices located in the camera area to drive the light-emitting devices to emit light.

[0005] However, since the pixel circuits connected to the light-emitting devices in the camera area need to be designed in the non-camera area, it may lead to a relatively large number of pixel circuits that need to be designed in the non-camera area, and further lead to too small a space that each pixel circuit can occupy, making it difficult to fabricate in terms of technology. Summary of the Invention

[0006] This application provides a display panel, a display module, and a display device, which can solve the problem that it is difficult to fabricate a display panel in related technologies. The technical solutions are as follows:

[0007] On the one hand, a display panel is provided, and the display panel includes:

[0008] a substrate, the substrate having a first display area and a second display area at least partially surrounding the first display area;

[0009] a driving circuit layer on one side of the substrate, the driving circuit layer including a plurality of first pixel circuits and a plurality of second pixel circuits located in the second display area;

[0010] And a first electrode layer, the first electrode layer at least includes a plurality of first - type electrode patterns, the plurality of first - type electrode patterns includes a plurality of first electrode patterns located in the first display area, and a plurality of second electrode patterns located in the second display area;

[0011] Wherein, at least two of the first electrode patterns are connected to one of the plurality of first pixel circuits, and at least two of the second electrode patterns are connected to one of the plurality of second pixel circuits.

[0012] Optionally, the display panel further includes:

[0013] A plurality of first connection traces, the plurality of first connection traces are located in the first display area;

[0014] A plurality of second connection traces, the plurality of second connection traces extend from the second display area to the first display area along the pixel row direction, and are located in the first display area and the second display area;

[0015] A plurality of third connection traces, the plurality of third connection traces are located in the second display area;

[0016] Wherein, at least two of the first electrode patterns are connected by one of the first connection traces, and one of the at least two first electrode patterns is connected to one of the first pixel circuits by one of the second connection traces, at least two of the second electrode patterns are connected by one of the third connection traces, and one of the at least two second electrode patterns is connected to one of the second pixel circuits.

[0017] Optionally, the display panel further includes a plurality of fourth connection traces and a plurality of fifth connection traces, the plurality of fourth connection traces and the plurality of fifth connection traces both extend from the second display area to the first display area along the pixel row direction; the first electrode layer further includes a plurality of second - type electrode patterns and a plurality of third - type electrode patterns;

[0018] The plurality of second - type electrode patterns includes a plurality of third electrode patterns located in the first display area, and a plurality of fourth electrode patterns located in the second display area, the third electrode patterns are connected to one of the first pixel circuits by one of the fourth connection traces, and the fourth electrode patterns are connected to one of the second pixel circuits;

[0019] The plurality of third - type electrode patterns includes a plurality of fifth electrode patterns located in the first display area, and a plurality of sixth electrode patterns located in the second display area; the fifth electrode patterns are connected to one of the first pixel circuits by the fifth connection traces.

[0020] Optionally, two adjacent first pixel circuits and three second pixel circuits form a circuit group; at least two of the second electrode patterns form an electrode pattern group, and an adjacent electrode pattern group, one fourth electrode pattern, and one sixth electrode pattern form a pattern group;

[0021] wherein, each pattern group corresponds to one circuit group, and for the corresponding pattern group and circuit group, the area where the positive projection of the pattern group on the substrate is located overlaps with the area where the positive projection of the circuit group on the substrate is located.

[0022] Optionally, for each circuit group and a pattern group corresponding to the circuit group, among the three second pixel circuits included in the circuit group, the first second pixel circuit is connected to one second electrode pattern of the electrode pattern group in the pattern group, the second second pixel circuit is connected to the fourth electrode pattern in the pattern group, and the third second pixel circuit is connected to the sixth electrode pattern in the pattern group.

[0023] Optionally, two first pixel circuits included in a part of the circuit groups in the display panel are connected to the electrode patterns in the first display area, and two first pixel circuits included in another part of the circuit groups in the display panel are connected to a fixed voltage terminal.

[0024] Optionally, the circuit group to which the first pixel circuit connected to the electrode pattern in the first display area belongs is closer to the first display area than the circuit group to which the first pixel circuit connected to the fixed voltage terminal belongs.

[0025] Optionally, the display panel includes red sub-pixels, green sub-pixels, and blue sub-pixels. The sub-pixels to which the first type of electrode patterns belong are green sub-pixels, the sub-pixels to which the second type of electrode patterns belong are red sub-pixels, and the sub-pixels to which the third type of electrode patterns belong are blue sub-pixels.

[0026] Optionally, the length of any second connection trace along the pixel row direction is less than the length of the fourth connection trace along the pixel row direction and less than the length of the fifth connection trace along the pixel row direction.

[0027] Optionally, for each connection trace among the multiple second connection traces, the multiple fourth connection traces, and the multiple fifth connection traces, the length of the connection trace along the pixel row direction is positively correlated with the distance between the electrode pattern located in the first display area to which the connection trace is connected along the pixel row direction and the second display area.

[0028] Optionally, the second display area includes a first sub-display area, a second sub-display area, and a third sub-display area. The first sub-display area and the first display area are arranged along the pixel column direction. The second sub-display area and the first display area are arranged along the pixel row direction. The third sub-display area and the first sub-display area are arranged along the pixel row direction and are arranged with the second sub-display area along the pixel column direction.

[0029] The display panel further includes: a plurality of first data lines located in the first sub-display area, a plurality of second data lines located in the second sub-display area and the third sub-display area, and a plurality of first connection lines located in the first sub-display area and the third sub-display area. The plurality of first data lines are arranged along the pixel row direction and extend along the pixel column direction. The plurality of second data lines are arranged along the pixel row direction and extend along the pixel column direction. The plurality of first connection lines are arranged along the pixel column direction and extend along the pixel row direction.

[0030] The first end of each first data line is used to be connected to a data driving circuit. The second end of each first data line is connected to the first end of a first connection line. The second end of each first connection line is connected to the first end of a second data line. Wherein, each first data line is further connected to a column of second pixel circuits located in the first sub-display area for connecting a first target electrode pattern. Each second data line is further connected to a column of first pixel circuits located in the second sub-display area for connecting a second target electrode pattern. The first target electrode pattern is at least one of a fourth electrode pattern and a sixth electrode pattern. The second target electrode pattern is at least one of a third electrode pattern and a fifth electrode pattern.

[0031] Optionally, the first target electrode pattern is a fourth electrode pattern or a sixth electrode pattern. The second target electrode pattern is a third electrode pattern or a fifth electrode pattern. The display panel further includes: a plurality of third data lines located in the first sub-display area, and a plurality of fourth data lines located in the second sub-display area and the third sub-display area.

[0032] The plurality of third data lines are arranged along the pixel row direction and extend along the pixel column direction. The first end of each third data line is used to be connected to a data driving circuit. And each third data line is further connected to a column of second pixel circuits located in the first sub-display area for connecting a second electrode pattern.

[0033] The multiple fourth data lines are arranged along the pixel row direction and extend along the pixel column direction. The first end of each fourth data line is used to connect to a data driving circuit, and each fourth data line is also connected to a column of first pixel circuits located in the second sub-display area and used to connect to the first electrode pattern.

[0034] Optionally, the second display area further includes: a fourth sub-display area and a fifth sub-display area. The fourth sub-display area is located on the side of the first display area away from the first sub-display area, and the fifth sub-display area and the fourth sub-display area are arranged along the pixel row direction; the multiple second data lines are also located in the fifth sub-display area; the display panel further includes: multiple second jumper lines, and multiple fifth data lines located in the fourth sub-display area;

[0035] The multiple fifth data lines are arranged along the pixel row direction and extend along the pixel column direction, and the multiple second jumper lines are arranged along the pixel column direction and extend along the pixel row direction; the second end of each second data line is connected to the first end of one of the second jumper lines, and the second end of each second jumper line is connected to the first end of the fifth data line; the fifth data line is also connected to a column of second pixel circuits located in the fourth sub-display area and used to connect to the first target electrode pattern.

[0036] Optionally, the display panel further includes: multiple first dummy data lines located in the third sub-display area;

[0037] The multiple first dummy data lines are arranged along the pixel row direction and extend along the pixel column direction. The first dummy data line is used to connect to a fixed voltage terminal, and the first dummy data line is also connected to a column of first pixel circuits located in the third sub-display area.

[0038] Optionally, the second display area further includes: a sixth sub-display area, and the sixth sub-display area is located on the side of the third sub-display area away from the first sub-display area; the display panel further includes: multiple seventh data lines located in the sixth sub-display area, and multiple second dummy data lines located in the sixth sub-display area;

[0039] The multiple seventh data lines are arranged along the pixel row direction and extend along the pixel column direction. Each seventh data line is used to connect to a data driving circuit, and each seventh data line is also connected to a column of second pixel circuits located in the sixth sub-display area;

[0040] The multiple second dummy data lines are arranged along the pixel row direction and extend along the pixel column direction. Each second dummy data line is used to connect to a fixed voltage terminal, and the second dummy data line is also connected to a column of first pixel circuits located in the sixth display area.

[0041] Optionally, the third connection trace is on the same layer as the first electrode layer, and both the first connection trace and the second connection trace are between the driving circuit layer and the first electrode layer.

[0042] On the other hand, a display module is provided, characterized in that the display module includes a data driving circuit and a display panel as described in the above aspect;

[0043] Wherein, the data driving circuit is connected to the first data line, the third data line, the fourth data line, and the seventh data line in the display panel.

[0044] In yet another aspect, a display device is provided, the display device includes the display module and an optical sensor as described in the above aspect, and a positive projection of the optical sensor on the display panel at least partially overlaps with a first display area of the display panel.

[0045] The beneficial effects brought by the technical solutions provided in this application at least include:

[0046] This application provides a display panel, a display module, and a display device. Since at least two first electrode patterns in the display panel are connected, and one of the at least two connected first electrode patterns is connected to a first pixel circuit, one first pixel circuit can drive two first electrode patterns. At the same time, since at least two second electrode patterns are connected, and one of the at least two connected second electrode patterns is connected to a second pixel circuit, one second pixel circuit can drive two second electrode patterns. Thus, in the case where the number of electrode patterns is the same, adopting the scheme of using one pixel circuit to drive two electrode patterns can reduce the number of pixel circuits required to be designed in the second display area, and further increase the space that each pixel circuit can occupy, and the process preparation difficulty is relatively low. Description of the Drawings

[0047] In order to more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of this application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0048] Figure 1 It is a schematic partial structure diagram of a display panel provided by an embodiment of this application;

[0049] Figure 2 is Figure 1 A schematic enlarged partial view of the display panel shown;

[0050] Figure 3 is a top view of a substrate provided by an embodiment of the present application;

[0051] Figure 4 is a partial cross-sectional view of a display panel provided by an embodiment of the present application;

[0052] Figure 5 is a partial schematic view of a first electrode layer in a second display area provided by an embodiment of the present application;

[0053] Figure 6 is a partial schematic view of a first electrode layer in a first display area provided by an embodiment of the present application;

[0054] Figure 7 is a partial schematic view of a first pattern row in a first display area provided by an embodiment of the present application;

[0055] Figure 8 is a partial structural schematic view of another display panel provided by an embodiment of the present application;

[0056] Figure 9 is Figure 8 a partial enlarged schematic view of the shown display panel;

[0057] Figure 10 is a schematic view of a data line, a transfer line, and a dummy data line of a display panel provided by an embodiment of the present application;

[0058] Figure 11 is a schematic view of a data line, a transfer line, and a dummy data line of another display panel provided by an embodiment of the present application;

[0059] Figure 12 is a schematic view of a display panel in which a first pixel circuit is not designed provided by an embodiment of the present application;

[0060] Figure 13 is a design schematic view of a two-in-one pixel circuit provided by an embodiment of the present application;

[0061] Figure 14 is a schematic view of a circuit group provided by an embodiment of the present application;

[0062] Figure 15 is a schematic view of another circuit group provided by an embodiment of the present application;

[0063] Figure 16 is an equivalent circuit diagram of a first pixel circuit or a second pixel circuit provided by an embodiment of the present application;

[0064] Figure 17 is a partial schematic view of a semiconductor layer in a display panel provided by an embodiment of the present application;

[0065] Figure 18 It is a partial schematic diagram of a first gate layer in a display panel provided by an embodiment of the present application;

[0066] Figure 19 It is a partial superimposed schematic diagram of a semiconductor layer and a first gate layer in a display panel provided by an embodiment of the present application;

[0067] Figure 20 It is a partial schematic diagram of a second gate layer in a display panel provided by an embodiment of the present application;

[0068] Figure 21 It is a partial superimposed schematic diagram of a semiconductor layer, a first gate layer, and a second gate layer in a display panel provided by an embodiment of the present application;

[0069] Figure 22 It is a partial schematic diagram of an interlayer dielectric layer in a display panel provided by an embodiment of the present application;

[0070] Figure 23 It is a partial superimposed schematic diagram of a semiconductor layer, a first gate layer, a second gate layer, and an interlayer dielectric layer in a display panel provided by an embodiment of the present application;

[0071] Figure 24 It is a partial schematic diagram of a first source-drain layer in a display panel provided by an embodiment of the present application;

[0072] Figure 25 It is a partial superimposed schematic diagram of a semiconductor layer, a first gate layer, a second gate layer, an interlayer dielectric layer, and a first source-drain layer in a display panel provided by an embodiment of the present application;

[0073] Figure 26 It is a partial schematic diagram of a passivation layer in a display panel provided by an embodiment of the present application;

[0074] Figure 27 It is a partial superimposed schematic diagram of a semiconductor layer, a first gate layer, a second gate layer, an interlayer dielectric layer, a first source-drain layer, and a passivation layer in a display panel provided by an embodiment of the present application;

[0075] Figure 28 It is a partial schematic diagram of an intermediate source-drain layer in a display panel provided by an embodiment of the present application;

[0076] Figure 29 It is a partial superimposed schematic diagram of a semiconductor layer, a first gate layer, a second gate layer, an interlayer dielectric layer, a first source-drain layer, a passivation layer, and an intermediate source-drain layer in a display panel provided by an embodiment of the present application;

[0077] Figure 30 It is a partial schematic diagram of a first planarization layer in a display panel provided by an embodiment of the present application;

[0078] Figure 31 It is a partial superimposed schematic diagram of a semiconductor layer, a first gate layer, a second gate layer, an interlayer dielectric layer, a first source-drain layer, a passivation layer, an intermediate source-drain layer, and a first planarization layer in a display panel provided by an embodiment of the present application;

[0079] Figure 32 It is a partial schematic diagram of a second source-drain layer in a display panel provided by an embodiment of the present application;

[0080] Figure 33 It is a partial superimposed schematic diagram of a semiconductor layer, a first gate layer, a second gate layer, an interlayer dielectric layer, a first source-drain layer, a passivation layer, an intermediate source-drain layer, a first planarization layer, and a second source-drain layer in a display panel provided by an embodiment of the present application;

[0081] Figure 34 It is a partial schematic diagram of a second planarization layer in a display panel provided by an embodiment of the present application;

[0082] Figure 35 It is a partial superimposed schematic diagram of a semiconductor layer, a first gate layer, a second gate layer, an interlayer dielectric layer, a first source-drain layer, a passivation layer, an intermediate source-drain layer, a first planarization layer, a second source-drain layer, and a second planarization layer in a display panel provided by an embodiment of the present application;

[0083] Figure 36 It is a flowchart of a method for manufacturing a display panel provided by an embodiment of the present application;

[0084] Figure 37 It is a partial schematic diagram of a first conductive layer in a display panel provided by an embodiment of the present application;

[0085] Figure 38 It is a partial superimposed schematic diagram after forming a first conductive layer in a display panel provided by an embodiment of the present application;

[0086] Figure 39 It is a partial schematic diagram of a first insulating layer in a display panel provided by an embodiment of the present application;

[0087] Figure 40 It is a partial superimposed schematic diagram after forming a first insulating layer in a display panel provided by an embodiment of the present application;

[0088] Figure 41 It is a partial schematic diagram of a second conductive layer in a display panel provided by an embodiment of the present application;

[0089] Figure 42It is a partial superposition schematic diagram after forming a second conductive layer in a display panel provided by an embodiment of the present application;

[0090] Figure 43 It is a partial schematic diagram of a second insulating layer in a display panel provided by an embodiment of the present application;

[0091] Figure 44 It is a partial superposition schematic diagram after forming a second insulating layer in a display panel provided by an embodiment of the present application;

[0092] Figure 45 It is a partial schematic diagram of a third conductive layer in a display panel provided by an embodiment of the present application;

[0093] Figure 46 It is a partial superposition schematic diagram after forming a third conductive layer in a display panel provided by an embodiment of the present application;

[0094] Figure 47 It is a partial schematic diagram of a third insulating layer in a display panel provided by an embodiment of the present application;

[0095] Figure 48 It is a partial superposition schematic diagram after forming a third insulating layer in a display panel provided by an embodiment of the present application;

[0096] Figure 49 It is a partial schematic diagram of a first electrode layer in a display panel provided by an embodiment of the present application;

[0097] Figure 50 It is a partial superposition schematic diagram after forming a first electrode layer in a display panel provided by an embodiment of the present application;

[0098] Figure 51 It is a partial schematic diagram of a pixel defining layer in a display panel provided by an embodiment of the present application;

[0099] Figure 52 It is a partial superposition schematic diagram after forming a pixel defining layer in a display panel provided by an embodiment of the present application;

[0100] Figure 53 It is a partial schematic diagram of a conductive layer in a display panel provided by an embodiment of the present application;

[0101] Figure 54 It is a structural schematic diagram of a display module provided by an embodiment of the present application;

[0102] Figure 55 It is a structural schematic diagram of a display device provided by an embodiment of the present application. Detailed implementation manners

[0103] To make the objectives, technical solutions, and advantages of this application clearer, the following will further describe the embodiments of this application in detail with reference to the accompanying drawings.

[0104] An embodiment of this application provides a display panel, which can be, for example, an organic light-emitting diode (OLED) display panel, a micro organic light-emitting diode (Micro OLED) display panel, a quantum dot light emitting diodes (QLED) display panel, a mini light-emitting diode (Mini LED) display panel, or a micro light-emitting diode (Micro LED) display panel, etc. The following takes the display panel as an OLED display panel as an example for introduction.

[0105] Figure 1 FIG. is a schematic partial structure diagram of a display panel provided by an embodiment of this application. Figure 2 is Figure 1 FIG. is an enlarged schematic partial view of the display panel shown. Figure 3 FIG. is a top view of a substrate provided by an embodiment of this application. Figure 4 FIG. is a partial cross-sectional view of a display panel provided by an embodiment of this application. With reference to Figures 1 to 4 the display panel 10 may include a substrate 101, a driving circuit layer 102 located on one side of the substrate 101, and a first electrode layer 103.

[0106] Among them, the substrate 101 has a first display area 101a and a second display area 101b at least partially surrounding the first display area 101a. The first display area 101a may be a full display with camera (FDC) area. The first display area 101a is a circular area or a square area.

[0107] The driving circuit layer 102 includes a plurality of first pixel circuits A1 and a plurality of second pixel circuits A2 located in the second display area 101b. Among them Figure 3 FIG. shows one first pixel circuit A1 and one second pixel circuit A2.

[0108] The first electrode layer 103 includes at least a plurality of first - type electrode patterns 1031. The plurality of first - type electrode patterns 1031 includes a plurality of first electrode patterns 1031a located in the first display area 101a and a plurality of second electrode patterns 1031b located in the second display area 101b. The display panel 10 includes a plurality of sub - pixels of different colors. Each sub - pixel may include a light - emitting device and a pixel circuit for controlling the light emission of the light - emitting device. The brightness (gray level) of sub - pixels of different colors is adjusted through the pixel circuit. Through color combination and superposition, a variety of color displays can be achieved, thus realizing the full - color display of the display panel 10. Among them, the light - emitting device may include an electrode pattern. The light emitted by the sub - pixels to which the above - mentioned plurality of first - type electrode patterns 1031 belong may have the same color.

[0109] At least two first electrode patterns 1031a are connected to one first pixel circuit A1 among the plurality of first pixel circuits A1. Thus, one first pixel circuit A1 can provide data - driving signals for two first electrode patterns 1031a. And at least two second electrode patterns 1031b are connected to one second pixel circuit A2 among the plurality of second pixel circuits A2. Thus, one second pixel circuit A2 can provide data - driving signals for two second electrode patterns 1031b.

[0110] In the embodiment of the present application, at least two first electrode patterns 1031a in the first display area 101a can be driven by one first pixel circuit A1 located in the second display area 101b, and at least two second electrode patterns 1031b in the second display area 101b can be driven by one second pixel circuit A2 located in the second display area 101b. Thus, in the case where the number of electrode patterns is the same, compared with the scheme of using one pixel circuit to drive one electrode pattern, the scheme of using one pixel circuit to drive two electrode patterns can reduce the number of pixel circuits required to be designed in the second display area 101b, and further can increase the space that each pixel circuit can occupy, and the process preparation difficulty is relatively low.

[0111] In summary, the embodiments of the present application provide a display panel. Since at least two first electrode patterns in the display panel are connected, and one of the at least two connected first electrode patterns is connected to a first pixel circuit, one first pixel circuit can drive two first electrode patterns. At the same time, since at least two second electrode patterns are connected, and one of the at least two connected second electrode patterns is connected to a second pixel circuit, one second pixel circuit can drive two second electrode patterns. Thus, when the number of electrode patterns is the same, the solution of one pixel circuit driving two electrode patterns can reduce the number of pixel circuits required to be designed in the second display area, thereby increasing the space that each pixel circuit can occupy, and the process preparation difficulty is relatively low.

[0112] In some embodiments, the base substrate 101 and the driving circuit layer 102 have a higher transmittance in the first display area 101a. For example, the base substrate 101 can be a transparent glass substrate to provide higher transparency. The driving circuit layer 102 does not have a circuit structure in the first display area 101a (that is, the first pixel circuit A1 and the second pixel circuit A2 are both arranged in the second display area 101b, but not in the first display area 101a), maintaining sufficient transparency of the driving circuit layer 102. In the display device, a sensor, such as a camera, a proximity light sensor, a 3D sensing module or other optical sensor, may be provided on the side of the base substrate 101 away from the driving circuit layer 102, and the orthographic projection of the sensor on the base substrate 101 is located in the first display area 101a. The photosensitive surface of the optical sensor faces the display surface side of the display panel 10, and is used to receive ambient light on the display surface side of the display panel 10. For example, the first electrode pattern 1031a in the first electrode layer 103, located in the first display area 101a, is made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO). This results in high light transmittance in the first display area 101a, making it suitable for placing devices with high transmittance requirements, such as cameras. This allows the display panel 10 to achieve full-screen display in the display area. An optical sensor is provided in the first display area 101a, and the optical sensor can receive external light through the film layer in the first display area 101a to achieve the corresponding function.

[0113] refer to Figure 1 and Figure 2 The display panel 10 may further include: a plurality of first connecting lines L1, a plurality of second connecting lines L2, and a plurality of third connecting lines L3. The plurality of first connecting lines L1 are located in the first display area 101a. The plurality of second connecting lines L2 extend from the second display area 101b to the first display area 101a along the pixel row direction X and are located in the first display area 101a and the second display area 101b. The plurality of third connecting lines L3 are located in the second display area 101b.

[0114] At least two first electrode patterns 1031a are connected by a first connection trace L1, and one of the at least two first electrode patterns 1031a is connected to a first pixel circuit A1 through a second connection trace L2. Thus, a first pixel circuit A1 can provide data driving signals for two first electrode patterns 1031a. Moreover, at least two second electrode patterns 1031b are connected by a third connection trace L3, and one of the at least two second electrode patterns 1031b is connected to a second pixel circuit A2. Thus, a second pixel circuit A2 can provide data driving signals for two second electrode patterns 1031b.

[0115] In an embodiment of the present application, referring to Figure 1 and Figure 2 , the display panel 10 further includes a plurality of fourth connection traces L4 and a plurality of fifth connection traces L5. The plurality of fourth connection traces L4 and the plurality of fifth connection traces L5 both extend from the second display area 101b to the first display area 101a along the pixel row direction X. Combining Figure 1 , Figure 5 and Figure 6 , the first electrode layer 103 further includes a plurality of second type electrode patterns 1032 and a plurality of third type electrode patterns 1033. The plurality of second type electrode patterns 1032 include a plurality of third electrode patterns 1032a located in the first display area 101a and a plurality of fourth electrode patterns 1032b located in the second display area 101b. The plurality of third type electrode patterns 1033 include a plurality of fifth electrode patterns 1033a located in the first display area 101a and a plurality of sixth electrode patterns 1033b located in the second display area 101b.

[0116] Among them, the third electrode pattern 1032a is connected to a first pixel circuit A1 through a fourth connection trace L4, and the fourth electrode pattern 1032b is connected to a second pixel circuit A2. The fifth electrode pattern 1033a is connected to a first pixel circuit A1 through the fifth connection trace L5, and the sixth electrode pattern 1033b is connected to a second pixel circuit A2. That is, each of the plurality of third electrode patterns 1032a and the plurality of fifth electrode patterns 1033a is driven by a first pixel circuit A1. Each of the plurality of fourth electrode patterns 1032b and the plurality of sixth electrode patterns 1033b is driven by a second pixel circuit A2.

[0117] In an embodiment of the present application, referring to Figure 7, in the first display area 101a, multiple first electrode patterns 1031a, multiple third electrode patterns 1032a, and multiple fifth electrode patterns 1033a can be arranged in multiple rows. The multiple electrode patterns arranged in a row are referred to as the first pattern row M. At least one first pattern row M includes at least two first electrode patterns 1031a, at least one third electrode pattern 1032a, and at least one fifth electrode pattern 1033a arranged in a row. At least two first electrode patterns 1031a in the first pattern row M are connected by a first connection trace L1.

[0118] Optionally, the first pattern row M is cyclically arranged in the order of the third electrode pattern 1032a, the first electrode pattern 1031a, the fifth electrode pattern 1033a, and the first electrode pattern 1031a. For example, multiple first pattern rows M are arranged in multiple rows, and each first pattern row M includes a first sub-pattern row M1 and a second sub-pattern row M2 arranged in parallel. In the first sub-pattern row M1, the third electrode pattern 1032a and the fifth electrode pattern 1033a are alternately arranged, and in the second sub-pattern row M2, multiple first electrode patterns 1031a are sequentially arranged. The number of first electrode patterns 1031a in the second sub-pattern row M2 is the same as the total number of the third electrode pattern 1032a and the fifth electrode pattern 1033a in the second sub-pattern row M2, and the first electrode pattern 1031a is arranged on the central axis of the adjacent third electrode pattern 1032a and fifth electrode pattern 1033a.

[0119] In addition, in the second display area 101b, multiple second electrode patterns 1031b, multiple fourth electrode patterns 1032b, and multiple sixth electrode patterns 1033b can be arranged in multiple rows. The electrode patterns arranged in a row are referred to as the second pattern row (not shown in the figure). At least one second pattern row includes at least two second electrode patterns 1031b, at least one fourth electrode pattern 1032b, and at least one sixth electrode pattern 1033b arranged in a row. At least two second electrode patterns 1031b in the second pattern row are connected by a third connection trace L3.

[0120] Optionally, the second pattern rows are cyclically arranged in the order of the fourth electrode pattern 1032b, the second electrode pattern 1031b, the sixth electrode pattern 1033b, and the second electrode pattern 1031b. For example, multiple second pattern rows are arranged in multiple rows, and each second pattern row includes a third sub-pattern row and a fourth sub-pattern row arranged in parallel. In the third sub-pattern row, the fourth electrode pattern 1032b and the sixth electrode pattern 1033b are alternately arranged, and in the fourth sub-pattern row, multiple second electrode patterns 1031b are sequentially arranged. The number of the second electrode patterns 1031b in the fourth sub-pattern row is the same as the total number of the fourth electrode pattern 1032b and the sixth electrode pattern 1033b in the third sub-pattern row, and the second electrode pattern 1031b is arranged on the central axis of the adjacent fourth electrode pattern 1032b and the sixth electrode pattern 1033b.

[0121] Of course, multiple first electrode patterns 1031a, multiple third electrode patterns 1032a, and multiple fifth electrode patterns 1033a can also be arranged in multiple columns, and multiple second electrode patterns 1031b, multiple fourth electrode patterns 1032b, and multiple sixth patterns can also be arranged in multiple columns. The way of arranging in multiple columns is similar to the way of arranging in multiple rows, and the embodiments of the present application will not be described in detail herein.

[0122] In the embodiments of the present application, the colors of the light emitted by the sub-pixels to which multiple second-type electrode patterns 1032 belong can be the same, and the colors of the light emitted by the sub-pixels to which multiple third-type electrode patterns 1033 belong can be the same. For example, the sub-pixels to which multiple first-type electrode patterns 1031 belong can be green sub-pixels, and the color of the light emitted by the green sub-pixels is green. The sub-pixels to which multiple second-type electrode patterns 1032 belong can be one of red sub-pixels and blue sub-pixels, and the sub-pixels to which multiple third-type electrode patterns 1033 belong can be the other of red sub-pixels and blue sub-pixels. For example, the sub-pixels to which multiple second-type electrode patterns 1032 belong can be red sub-pixels, and the sub-pixels to which multiple third-type electrode patterns 1032 belong can be blue sub-pixels. The color of the light emitted by the red sub-pixels is red, and the color of the light emitted by the blue sub-pixels is blue. That is, in the embodiments of the present application, one pixel circuit is used to drive two green sub-pixels, and one pixel circuit is used to drive one red sub-pixel or one blue sub-pixel.

[0123] In the embodiments of the present application, refer to Figure 1, Two adjacent first pixel circuits A1 and three second pixel circuits A2 form a circuit group A. At least two second electrode patterns 1031b form an electrode pattern group, and an adjacent electrode pattern group, a fourth electrode pattern 1032b, and a sixth electrode pattern 1033b form a pattern group B. Each pattern group B corresponds to a circuit group A, and for the corresponding pattern group B and circuit group A, the area where the positive projection of the pattern group B on the substrate 101 is located overlaps with the area where the positive projection of the circuit group A on the substrate 101 is located.

[0124] Optionally, for each circuit group A and the corresponding pattern group B, the space occupied by the circuit group A (five pixel circuits) is equivalent to the space occupied by the pattern group B (four electrode patterns). That is, five pixel circuits are correspondingly arranged below the four electrode patterns.

[0125] For each circuit group A and a corresponding pattern group B, among the three second pixel circuits A2 included in the circuit group A, the first second pixel circuit A2 is connected to a second electrode pattern 1031b of the electrode pattern group in the pattern group B, the second second pixel circuit A2 is connected to the fourth electrode pattern 1032b in the pattern group B, and the third second pixel circuit A2 is connected to the sixth electrode pattern 1033b in the pattern group B. That is, among the five pixel circuits included in each circuit group A, three of the second pixel circuits A2 can be used as pixel circuits for driving the four electrode patterns in the pattern group B located in the second display area 101b.

[0126] In addition, two first pixel circuits A1 included in a part of the circuit groups A in the display panel 10 are connected to the electrode patterns located in the first display area 101a, and two first pixel circuits A1 included in another part of the circuit groups A are connected to the fixed voltage terminal. That is, in the circuit groups A of the display panel 10, two first pixel circuits A1 in some circuit groups A can be used as pixel circuits for driving the electrode patterns in the first display area 101a, and the two first pixel circuits A1 in the remaining circuit groups A are not connected to the electrode patterns in the first display area 101a, but are connected to the fixed voltage terminal as dummy pixel circuits. Since the dummy pixel circuits are connected to the fixed voltage terminal, the dummy pixel circuits can be prevented from affecting the signals transmitted through the respective signal lines in the display panel 10, ensuring the display effect of the display panel 10.

[0127] In the embodiment of the present application, the circuit group A to which the first pixel circuit A1 connected to the electrode pattern of the first display area 101a belongs is closer to the first display area 101a than the circuit group A to which the first pixel circuit A1 connected to the fixed voltage terminal belongs. Thus, the length of the second connection trace L2 for connecting the electrode pattern located in the first display area 101a and the first pixel circuit A1 located in the second display area 101b can be made shorter, which can improve the reliability of signal transmission of the second connection trace L2 and ensure the display effect of the display panel 10.

[0128] In the embodiment of the present application, one first pixel circuit A1 provides data driving signals to two first electrode patterns 1031a. If the length of the second connection trace L2 connecting the first pixel circuit A1 and the two first electrode patterns 1031a is too long, it is easily affected by resistance-capacitance interference, resulting in the situation that the sub-pixels belonging to the first electrode pattern 1031a cannot be lit at low gray levels.

[0129] Therefore, referring to Figure 1 and Figure 2 , the length of any second connection trace L2 along the pixel row direction X is less than the length of the fourth connection trace L4 along the pixel row direction X and less than the length of the fifth connection trace L5 along the pixel row direction X. That is to say, compared with the third electrode pattern 1032a and the fifth electrode pattern 1033a, the first electrode pattern 1031a can be preferentially connected to the first pixel circuit A1 in the second display area 101b through the second connection trace L2. Thus, the length of the second connection trace L2 connected to the first electrode pattern 1031a can be reduced, the interference intensity of the second connection trace L2 by resistance-capacitance can be weakened, and it is ensured that each sub-pixel in the first display area 101a can be normally displayed at low gray levels.

[0130] Of course, referring to Figure 8 and Figure 9 , for each connection trace among the multiple second connection traces L2, multiple fourth connection traces L4, and multiple fifth connection traces L5, the length of the connection trace along the pixel row direction X is positively correlated with the distance between the electrode pattern located in the first display area 101a and the second display area 101b along the pixel row direction X. That is to say, the electrode patterns located in the first display area 101a are sequentially connected to the first pixel circuit A1 in the second display area 101b through the second connection traces L2.

[0131] Referring to Figure 3, the second display area 101b may include a first sub-display area 101b1, a second sub-display area 101b2, and a third sub-display area 101b3. Among them, the first sub-display area 101b1 and the first display area 101a are arranged along the pixel column direction Y, the second sub-display area 101b2 and the first display area 101a are arranged along the pixel row direction X, the third sub-display area 101b3 and the first sub-display area 101b1 are arranged along the pixel row direction X, and are arranged along the pixel column direction Y with the second sub-display area 101b2.

[0132] Among them, the second display area 101b may include one first sub-display area 101b1, two second sub-display areas 101b2, and two third sub-display areas 101b3. The first sub-display area 101b1 may be located below the first display area 101a, the two second sub-display areas 101b2 may be respectively located on both sides of the first display area 101a along the pixel row direction X, and the two third sub-display areas 101b3 may be located on both sides of the first sub-display area 101b1 along the pixel row direction X. Both the second sub-display area 101b2 and the third sub-display area 101b3 may be transition display areas of the display panel.

[0133] Reference Figure 10 , the display panel 10 may further include: a plurality of first data lines S1 located in the first sub-display area 101b1, a plurality of second data lines S2 located in the second sub-display area 101b2 and the third sub-display area 101b3, and a plurality of first transfer lines Z1 located in the first sub-display area 101b1 and the third sub-display area 101b3.

[0134] Among them, the plurality of first data lines S1 are arranged along the pixel row direction X and extend along the pixel column direction Y, the plurality of second data lines S2 are arranged along the pixel row direction X and extend along the pixel column direction Y, and the plurality of first transfer lines Z1 are arranged along the pixel column direction Y and extend along the pixel row direction X. The first end of each first data line S1 is used to connect to the data driving circuit, the second end of each first data line S1 is connected to the first end of a first transfer line Z1, and the second end of each first transfer line Z1 is connected to the first end of a second data line S2. Thus, the data driving signal provided by the data driving circuit can be transmitted through the first data line S1, the first transfer line Z1, and the second data line S2, and the data driving signals transmitted by a connected first data line S1, a first transfer line Z1, and a second data line S2 are the same.

[0135] While the third sub-display area 101b3 is farther from the boundary of the second sub-display area 101b2, the first end of the second data line S2 is closer to the boundary of the third sub-display area 101b3 and closer to the second sub-display area 101b2. In other words, the length of the second data line S2 along the pixel column direction Y can be slightly greater than the length of the second sub-display area 101b2 along the pixel column direction Y. This is done by simply ensuring that the first end of the second data line S2 is located in the third sub-display area 101b3. This facilitates connection between the first end of the second data line S2 located in the third sub-display area 101b3 and the second end of the first adapter line Z1 located in the third sub-display area 101b3.

[0136] Each first data line S1 is also connected to a column of second pixel circuits A2 located in the first sub-display area 101b1 for connecting to the first target electrode pattern, and each second data line S2 is also connected to a column of first pixel circuits A1 located in the second sub-display area 101b2 for connecting to the second target electrode pattern.

[0137] For the first data line S1 and the second data line S2 connected via a first adapter line Z1, a column of first target electrode patterns connected by the first data line S1 via a column of second pixel circuits A2, and a column of second target electrode patterns connected by the second data line S2 via a column of first pixel circuits A1 can be arranged along the pixel column direction Y. This allows the electrode patterns located in the same column in the first display area 101a and the first sub-display area 101b1 to receive the same data drive signal.

[0138] In the embodiment of the present application, the first target electrode pattern is at least one of the fourth electrode pattern 1032b and the sixth electrode pattern 1033b, and the second target electrode pattern is at least one of the third electrode pattern 1032a and the fifth electrode pattern 1033a.

[0139] As a first optional implementation, the first target electrode pattern is the fourth electrode pattern 1032b or the sixth electrode pattern 1033b, and the second target electrode pattern is the third electrode pattern 1032a or the fifth electrode pattern 1033a. Figure 10, the display panel 10 may further include: a plurality of third data lines S3 located in the first sub-display area 101b1, and a plurality of fourth data lines S4 located in the second display area 101b and the third sub-display area 101b3. The plurality of third data lines S3 are arranged along the pixel row direction X and extend along the pixel column direction Y, and the plurality of fourth data lines S4 are arranged along the pixel row direction X and extend along the pixel column direction Y. The first end of each third data line S3 and the first end of each fourth data line S4 are both used to be connected to the data driving circuit. Each third data line S3 is further connected to a column of second pixel circuits A2 located in the first sub-display area 101b1 for connecting the second electrode pattern 1031b, and each fourth data line S4 is further connected to a column of first pixel circuits A1 located in the second sub-display area 101b2 for connecting the first electrode pattern 1031a.

[0140] That is to say, the data driving signal provided by the data driving circuit can be transmitted to a column of second pixel circuits A2 located in the first sub-display area 101b1 through the third data line S3, and then drive a column of second electrode patterns 1031b connected to the column of second pixel circuits A2. And, the data driving signal provided by the data driving circuit can be transmitted to a column of first pixel circuits A1 located in the second sub-display area 101b2 through the fourth data line S4, and then drive a column of first electrode patterns 1031a connected to the column of first pixel circuits A1.

[0141] In this first implementation manner, the data driving signals obtained by the second type of electrode patterns 1032 (the third electrode pattern 1032a and the fourth electrode pattern 1032b) located in the same column in the display panel 10 are transferred and transmitted through the first jumper wire Z1. The data driving signals obtained by the third type of electrode patterns 1033 (the fifth electrode pattern 1033a and the sixth electrode pattern 1033b) located in the same column are transferred and transmitted through the first jumper wire Z1. The data driving signals obtained by the first type of electrode patterns 1031 (the first electrode pattern 1031a and the second electrode pattern 1031b) located in the same column are directly transmitted through the data lines (the third data line S3 or the fourth data line S4) connected to the data driving circuit without using the first jumper wire Z1 for transfer and transmission. Thus, the length of the data lines connected to the first type of electrode patterns 1031 (in the transfer and transmission scheme, the length of the data line is the total length of the connected data line and the jumper wire) can be reduced, and then the resistance and capacitance of the data lines can be reduced, the driving ability of the pixel circuit can be improved, and the display effect can be optimized.

[0142] Reference Figure 3, the second display area 101b may further include: a fourth sub-display area 101b4 and a fifth sub-display area 101b5. The fourth sub-display area 101b4 is located on a side of the first display area 101a away from the first sub-display area 101b1, and the fifth sub-display area 101b5 and the fourth sub-display area 101b4 are arranged along the pixel row direction X. For example, the second display area 101b may include one fourth sub-display area 101b4 and two fifth sub-display areas 101b5, one fourth sub-display area 101b4 may be located above the first display area 101a, and the two fifth sub-display areas 101b5 are respectively located on both sides of the fourth sub-display area 101b4 along the pixel row direction X. The fifth sub-display area 101b5 may be referred to as a transition display area.

[0143] Alternatively, the first display area 101a may be located within the second display area 101b, and the second display area 101b may completely surround the first display area 101a. Thus, in order to transmit data drive signals to the fourth sub-display area 101b4 of the first display area 101a, which is away from the first sub-display area 101b1, the display panel 10 may include: a plurality of second adapter lines Z2, a plurality of third adapter lines Z3, a plurality of fifth data lines S5, and a plurality of sixth data lines S6 located in the fourth sub-display area 101b4. The plurality of fifth data lines S5 are arranged along the pixel row direction X and extend along the pixel column direction Y, and the plurality of sixth data lines S6 are arranged along the pixel row direction X and extend along the pixel column direction Y. The plurality of second adapter lines Z2 are arranged along the pixel column direction Y and extend along the pixel row direction X, and the plurality of third adapter lines Z3 are arranged along the pixel column direction Y and extend along the pixel row direction X.

[0144] The second end of each second data line S2 is connected to the first end of a second adapter line Z2, and the second end of each second adapter line Z2 is connected to the first end of the fifth data line S5. The fifth data line S5 is also connected to a column of second pixel circuits A2 located in the fourth sub-display area 101b4 and connected to the first target electrode pattern. The second end of each fourth data line S4 is connected to the first end of a third adapter line Z3, and the second end of each third adapter line Z3 is connected to the first end of the sixth data line S6. The sixth data line S6 is also connected to a column of second pixel circuits A2 located in the fourth sub-display area 101b4 and connected to the second electrode pattern 1031b. Thus, the data driver circuit can sequentially provide data driver signals to the column of second pixel circuits A2 located in the fourth sub-display area 101b4 and connected to the first target electrode pattern via the first data line S1, the first adapter line Z1, the second data line S2, the second adapter line Z2, and the fifth data line S5. The data driving circuit sequentially provides data driving signals to a column of second pixel circuits A2 connected to the second electrode pattern 1031b in the fourth sub-display area 101b4 via the fourth data line S4, the third adapter line Z3, and the sixth data line S6. In other words, in this solution, each second pixel circuit A2 in the fourth sub-display area 101b4 must obtain a data driving signal via the adapter signal.

[0145] refer to Figure 3 The base substrate 101 further includes a peripheral region 101c surrounding the second display area 101b. The second ends of the plurality of second data lines S2, the plurality of second adapter lines Z2, the first ends of the plurality of fifth data lines S5, the second ends of the plurality of fourth data lines S4, the plurality of third adapter lines Z3, and the first ends of the plurality of sixth data lines S6 can all be located in the peripheral region 101c, and in an area of the fourth sub-display area 101b4 away from the first display area 101a. That is, the connection between the second data line S2 and the second adapter line Z2, the connection between the second adapter line Z2 and the fifth data line S5, the connection between the fourth data line S4 and the third adapter line Z3, and the connection between the third adapter line Z3 and the sixth data line S6 can all be located in the peripheral region 101c.

[0146] As a second optional implementation, the first target electrode pattern is one of the second electrode pattern 1031b, the fourth electrode pattern 1032b and the sixth electrode pattern 1033b, and the second target electrode pattern is one of the first electrode pattern 1031a, the third electrode pattern 1032a and the fifth electrode pattern 1033a.

[0147] In this second implementation manner, the data driving signals obtained by the second type of electrode patterns 1032 (the third electrode pattern 1032a and the fourth electrode pattern 1032b) located in the same column in the display panel 10 are transferred and transmitted through the first jumper wire Z1. The data driving signals obtained by the third type of electrode patterns 1033 (the fifth electrode pattern 1033a and the sixth electrode pattern 1033b) located in the same column are transferred and transmitted through the first jumper wire Z1. The data driving signals obtained by the first type of electrode patterns 1031 (the first electrode pattern 1031a and the second electrode pattern 1031b) located in the same column are transferred and transmitted through the first jumper wire Z1.

[0148] If the second display area 101b completely surrounds the first display area 101a, referring to Figure 11 , and the second display area 101b further includes: a fourth sub-display area 101b4 and a fifth sub-display area 101b5, then in order to transmit the data driving signal to the fourth sub-display area 101b4 of the first display area 101a away from the first sub-display area 101b1, the display panel 10 may include: a plurality of second jumper wires Z2, and a plurality of fifth data lines S5 located in the fourth sub-display area 101b4.

[0149] Among them, the plurality of fifth data lines S5 are arranged along the pixel row direction X and extend along the pixel column direction Y. The plurality of second jumper wires Z2 are arranged along the pixel column direction Y and extend along the pixel row direction X. The second end of each second data line S2 is connected to the first end of a second jumper wire Z2, and the second end of each second jumper wire Z2 is connected to the first end of the fifth data line S5. The fifth data line S5 is further connected to a column of second pixel circuits A2 in the fourth sub-display area 101b4 for connecting the first target electrode pattern. Thus, the data driving circuit can sequentially provide the data driving signal to a column of second pixel circuits A2 in the fourth sub-display area 101b4 for connecting the first target electrode pattern through the first data line S1, the first jumper wire Z1, the second data line S2, the second jumper wire Z2, and the fifth data line S5.

[0150] Referring to Figure 11 , the substrate 101 further has a peripheral area 101c surrounding the second display area 101b. The second ends of the plurality of second data lines S2, the plurality of second jumper wires Z2, and the first ends of the plurality of fifth data lines S5 can all be located in the peripheral area 101c and in the area of the fourth sub-display area 101b4 away from the first display area 101a. That is, the connection between the second data line S2 and the second jumper wire Z2, and the connection between the second jumper wire Z2 and the fifth data line S5 can both be located in the peripheral area 101c.

[0151] In the embodiment of the present application, the display panel 10 further includes: a plurality of first dummy data lines D1 located in the third sub-display area 101b3. The plurality of first dummy data lines D1 may be arranged along the pixel row direction X and extend along the pixel column direction Y. One end of the first dummy data line D1 is configured to be connected to a fixed voltage terminal, and the first dummy data line D1 is also connected to a column of first pixel circuits A1 located in the third sub-display area 101b3.

[0152] The first pixel circuit A1 located in the third sub-display area 101b3 may be a dummy pixel circuit. A dummy pixel circuit may be a pixel circuit that is not connected to any electrode pattern. The fixed voltage terminal may provide a fixed voltage signal to the dummy pixel circuit via the first dummy data line D1, thereby preventing the dummy pixel circuit from affecting the signals transmitted by the various signal lines in the display panel 10, thereby ensuring the display effect of the display panel 10.

[0153] Optionally, the first dummy data line D1 can be provided on the same layer as the other data lines (such as the second data line S2) mentioned in the above embodiment, or can be provided on different layers, which is not limited in the present embodiment. If the first dummy data line D1 is provided on the same layer as the other data lines mentioned in the above embodiment, a gap can be created between the first dummy data line D1 and the other data lines, thereby preventing the first dummy data line D1 and the other data lines from interfering with each other, allowing the first dummy data line D1 to transmit a fixed voltage signal while the other data lines transmit data drive signals.

[0154] In the first implementation described above, among the multiple first dummy data lines D1 located in the third sub-display area 101b3, the display panel 10 includes a portion of the first dummy data lines D1, which may be arranged in the same layer as the other data lines, while another portion of the first dummy data lines D1 may be arranged in a different layer from the other data lines. Optionally, each first dummy data line D1 arranged in the same layer as the other data lines may be co-linear with a second data line S2 and spaced apart therefrom. Furthermore, since the fourth data line S4 is located in the third sub-display area 101b3 and must pass through the third sub-display area 101b3 to connect to the data driver circuit, to avoid the fourth data line S4, the first dummy data line D1, which is arranged in a different layer from the fourth data line S4, is designed to be connected to a column of first pixel circuits A1 located in the third sub-display area 101b3. The column of first pixel circuits A1 located in the third sub-display area 101b3 is located in the same column as the first pixel circuits A1 located in the second sub-display area 101b2, which are connected to the fourth data line S4.

[0155] For the second implementation, the display panel 10 includes a plurality of first dummy data lines D1 located in the third sub-display area 101b3. All first dummy data lines D1 can be provided in the same layer as other data lines, or in different layers.

[0156] In an embodiment of the present application, the second display area 101b further includes a sixth sub-display area 101b6. The sixth sub-display area 101b6 can be referred to as a normal display area. Optionally, the second display area 101b includes two sixth sub-display areas 101b6, and the two sixth sub-display areas 101b6 can be respectively located on both sides of the first third sub-display area 101b3, the first sub-display area 101b1, and the second third sub-display area 101b3 along the pixel row direction X, and are located on both sides of the first second sub-display area 101b2, the first display area 101a, and the second second sub-display area 101b2 along the pixel row direction X.

[0157] The display panel 10 may further include: a plurality of seventh data lines S7 located in the sixth sub-display area 101b6, and a plurality of second dummy data lines D2 located in the sixth sub-display area 101b6. One end of each seventh data line S7 is used to connect to a data driving circuit, and each seventh data line S7 is further connected to a column of second pixel circuits A2 located in the sixth sub-display area 101b6. Thereby, the data driving circuit can provide a data driving signal to the second pixel circuit A2 through the seventh data line S7. One end of each second dummy data line D2 is used to connect to a fixed voltage terminal, and each second dummy data line D2 is further connected to a column of first pixel circuits A1 located in the sixth sub-display area 101b6. Thereby, the fixed voltage terminal can provide a fixed voltage signal to the first pixel circuit A1 through the second dummy data line D2. Among them, the first pixel circuit A1 located in the sixth sub-display area 101b6 can be a dummy pixel circuit.

[0158] In an embodiment of the present application, the third connection trace L3 can be arranged in a different layer from both the first connection trace L1 and the second connection trace L2. For example, referring to Figure 4 , the display panel 10 may include a connection layer 104 located between the driving circuit layer 102 and the first electrode layer 103. The first connection trace L1 and the second connection trace L2 can be located in the connection layer 104, that is, the first connection trace L1 and the second connection trace L2 can both be located between the driving circuit layer 102 and the first electrode layer 103. The third connection trace L3 is located in the first electrode layer 103.

[0159] Optionally, the electrode pattern included in the first electrode layer 103 may be a stacked structure of a first film layer, a second film layer, and a third film layer. The materials of the first film layer and the third film layer may be indium tin oxide (ITO), and the material of the second film layer may be silver (Ag), that is, the electrode pattern may be a stack of ITO / Ag / ITO. The third connecting trace L3 being located in the first electrode layer 103 may mean that: the third connecting trace L3 is the same as the electrode pattern, and is also a stack of ITO / Ag / ITO; or, the third connecting trace L3 may be a layer of ITO included in the electrode pattern (such as the first film layer or the third film layer).

[0160] Optionally, the connection layer 104 may include at least one conductive layer and at least one insulating layer, and an insulating layer is provided on a side of each conductive layer away from the base substrate 101 .

[0161] For example, the connection layer 104 may include: a first conductive layer 1041, a first insulating layer 1042, a second conductive layer 1043, a second insulating layer 1044, a third conductive layer 1045, and a third insulating layer 1046, stacked sequentially on a side of the driving circuit layer 102 away from the base substrate 101. Each of the first conductive layer 1041, the second conductive layer 1043, and the third conductive layer 1045 includes a plurality of first connecting traces L1 and / or a plurality of second connecting traces L2. The first insulating layer 1042 includes a first via, the second insulating layer 1044 includes a second via, and the third insulating layer 1046 includes a third via. The first conductive layer 1041 is electrically connected to the second conductive layer 1043 through the first via, the second conductive layer 1043 is electrically connected to the third conductive layer 1045 through the second via, and the third conductive layer 1045 is electrically connected to the first electrode layer 103 through the third via.

[0162] In an embodiment of the present application, the connecting lines (the second connecting line L2, the fourth connecting line L4 and the fifth connecting line L5) used to connect the first pixel circuit A1 located in the second display area 101b and the electrode pattern of the first display area 101a can be evenly distributed on the three conductive layers. By reasonably arranging the positions of the connecting lines, the spacing between adjacent connecting lines can be avoided to be too small, thereby avoiding short circuits or crosstalk problems.

[0163] It should be noted that when the area of the first display area 101a is small, or the process precision of preparing the connection traces (the second connection trace L2, the fourth connection trace L4, and the fifth connection trace L5) for connecting the first pixel circuit A1 located in the second display area 101b and the electrode pattern in the first display area 101a is high, and the width of the connection traces can be reduced, all the connection traces can be arranged in two conductive layers or even in one conductive layer. This can reduce the number of mask plates used in the manufacturing process, simplify the process, and at the same time increase the light transmittance of the first display area 101a and reduce the overall thickness of the display panel 10, realizing the thinning of the display panel 10.

[0164] Reference Figure 4 , each conductive layer is further provided with a connection portion. The connection portion can be used to connect the connection trace with the pixel circuit, or connect the connection traces located in different layers, or connect the connection trace with the electrode pattern in the first electrode layer 103. For example, the first conductive layer 1041 may include a plurality of first connection portions 1041a, the second conductive layer 1043 may include a plurality of second connection portions 1043a, and the third conductive layer 1045 may include a plurality of third connection portions 1045a.

[0165] Figure 4Taking the case where the first connection trace L1 is located in the third conductive layer 1045 and the second connection trace L2 is located in the first conductive layer 1041 as an example. In the second display area 101b, the second pixel circuit A2 is connected to the first connection portion 1041a, the first connection portion 1041a is connected to the second connection portion 1043a, the second connection portion 1043a is connected to the third connection portion 1045a, and the third connection portion 1045a is connected to an electrode pattern (the second electrode pattern 1031b, the fourth electrode pattern 1032b, or the sixth electrode pattern 1033b). If the third connection portion 1045a is connected to a second electrode pattern 1031b, then the third connection portion 1045a is further connected to the third connection trace L3, the third connection trace L3 is connected to another third connection portion 1045a, and the other third connection portion 1045a is connected to another second electrode pattern 1031b. In the first display area 101a, the second connection trace L2 is connected to the first pixel circuit A1 through a first connection portion 1041a, the second connection trace L2 is connected to the second connection portion 1043a through another first connection portion 1041a, the second connection portion 1043a is connected to the third connection portion 1045a, and the third connection portion 1045a is connected to an electrode pattern (the first electrode pattern 1031a, the third electrode pattern 1032a, or the fifth electrode pattern 1033a). If the third connection portion 1045a is connected to a first electrode pattern 1031a, then the third connection portion 1045a is further connected to the first connection trace L1, the first connection trace L1 is connected to another third connection portion 1045a, and the other third connection portion 1045a is connected to another second electrode pattern 1031b.

[0166] Among them, the orthographic projection of the third connection portion 1045a on the substrate 101 can at least partially overlap with the orthographic projection of the electrode pattern that can be connected to the third connection portion 1045a on the substrate 101, so that the electrode pattern is connected to the third connection portion 1045a through a third via hole penetrating the third insulating layer 1046. The orthographic projections of the connected second connection portion 1043a and the third connection portion 1045a on the substrate 101 at least partially overlap, so that the third connection portion 1045a is connected to the second connection portion 1043a through a second via hole penetrating the second insulating layer 1044. The orthographic projections of the connected first connection portion 1041a and the second connection portion 1043a on the substrate 101 at least partially overlap, so that the second connection portion 1043a is connected to the first connection portion 1041a through a first via hole penetrating the first insulating layer 1042. The orthographic projections of the connected first connection portion 1041a and the pixel circuit on the substrate 101 at least partially overlap, so that the first connection portion 1041a can be connected to the pixel circuit. Thus, by providing connection portions in each conductive layer, the connection between the pixel circuit and the electrode pattern can be made more stable.

[0167] Optionally, the first conductive layer 1041, the second conductive layer 1043, and the third conductive layer 1045 all include transparent conductive materials. For example, the materials of the first conductive layer 1041, the second conductive layer 1043, and the third conductive layer 1045 can be indium tin oxide or indium zinc oxide. Each insulating layer included in the connection layer 104 includes a transparent insulating material. For example, the materials of the first insulating layer 1042, the second insulating layer 1044, and the third insulating layer 1046 can be polyimide (PI).

[0168] In the embodiment of the present application, referring to Figure 4 , the display panel 10 further includes a light-emitting film layer 105, a pixel defining layer 106, a second electrode layer 107, a packaging layer 108, and a buffer layer 109. Among them, the packaging layer 108 covers the side of the second electrode layer 107 away from the substrate 101 to implement the packaging of the display panel 10. The buffer layer 109 can be located between the substrate 101 and the driving circuit layer 102.

[0169] The first electrode layer 103, the pixel defining layer 106, the light-emitting film layer 105, and the second electrode layer 107 can form a plurality of light-emitting devices, such as a plurality of OLEDs. Among them, the light-emitting film layer 105 includes a plurality of light-emitting layers 1051, the pixel defining layer 106 has a plurality of openings, each opening exposes one electrode pattern in the first electrode layer 103, each light-emitting layer 1051 is located in one opening and contacts the electrode pattern, and the portion of the second electrode layer 107 located in the opening serves as the second electrode of the light-emitting device. Thus, the sequentially stacked electrode pattern (anode), light-emitting layer 1051, and second electrode (cathode) form a light-emitting device.

[0170] The pixel circuit in the driving circuit layer 102 can be electrically connected to the light-emitting device. For example, the pixel circuit can be electrically connected to the electrode pattern of the first electrode layer 103 in the light-emitting device to control the light emission of the light-emitting device.

[0171] In some embodiments, the driver circuit layer 102 includes a semiconductor layer 10201, a first gate insulator (GI) 10202, a first gate layer (gate) 10203, a second gate insulator 10204, a second gate layer 10205, an inter-level dielectric (ILD) 10206, a first source and drain layer 10207, a passivation layer (PVX) 10208, an intermediate source and drain layer 10209, a first planarization layer (PLN) 10210, a second source and drain layer 10211, and a second planarization layer 10212, stacked sequentially on the base substrate 101. Multiple pixel circuits in the driver circuit layer 102 are arranged in an array, each pixel circuit including multiple thin film transistors. The first conductive layer 1041 in the connection layer 104 is located on a side of the second planarization layer 10212 away from the base substrate 101. The first insulating layer 1042 may be referred to as a third planar layer, the second insulating layer 1044 may be referred to as a fourth planar layer, and the third insulating layer 1046 may be referred to as a fifth planar layer. Pixel circuits in the driving circuit layer 102 may be electrically connected to the light-emitting devices via the connection layer 104 .

[0172] Optionally, the first source-drain layer 10207 may include the source and drain of the thin film transistor in each pixel circuit, and the source and drain may be spaced apart. Of course, the first source-drain layer 10207 may also include the adapter wires (first adapter wire Z1, second adapter wire Z2, and third adapter wire Z3) described in the above embodiment. The intermediate source-drain layer 10209 may include a power supply line (e.g., a VDD line) for providing a power supply signal to the display panel 10. Alternatively, the intermediate source-drain layer 10209 may also include the adapter wires (first adapter wire Z1, second adapter wire Z2, and third adapter wire Z3) described in the above embodiment. The second source-drain layer may include the data lines (first data line S1, second data line S2, third data line S3, fourth data line S4, fifth data line S5, sixth data line S6, and seventh data line S7) and dummy data lines (first dummy data line D1 and second dummy data line D2) described in the above embodiment.

[0173] It should be noted that for the design of pixel circuits in a display panel with a higher pixel resolution (pixels per inch, PPI), if only pixel circuits for driving the electrode pattern located in the second display area are provided in the sixth sub-display area (normal display area) of the second display area, and no dummy pixel circuits are provided, and each pixel circuit drives one electrode pattern, then reference Figure 12, the space that each pixel circuit can occupy in the pixel row direction can be relatively large, which is 29.8 μm (micrometers). In this solution, in order to improve the transmittance of the first display area, the pixel circuit for driving the electrode pattern in the first display area needs to be arranged in the second sub-display area (transition display area) of the second display area. This may result in different arrangements of pixel circuits in different sub-areas of the second display area, and the uniformity of pixel circuits in the display panel is poor.

[0174] Therefore, in order to improve the design uniformity of pixel circuits in the display panel, dummy pixel circuits can be designed in the sixth sub-display area. For example Figure 13 In, one first pixel circuit (dummy pixel circuit) is designed for every two second pixel circuits, that is, a design of two second pixel circuits pressing one (the design of two second pixel circuits pressing one may mean that at the position where two second pixel circuits originally need to be designed, an additional dummy pixel circuit needs to be designed). Relative to Figure 12 , at the position where four pixel circuits originally need to be designed, six pixel circuits need to be designed. However, in this solution, the space that each pixel circuit can occupy in the pixel row direction is small, which is 19.8 μm, and it is difficult to fabricate in terms of technology.

[0175] In the embodiments of the present application, since one second pixel circuit drives two second electrode patterns in the embodiments of the present application, the number of pixel circuits that need to be designed can be reduced. Relative to Figure 13 , in Figure 14 , at the position where six pixel circuits originally need to be designed, only five pixel circuits need to be designed. The space that each pixel circuit can occupy in the pixel row direction can be relatively large, which is 23.83 μm, and the preparation difficulty is low. Moreover, the pixel circuits in each sub-area of the second display area are arranged differently, and the uniformity of pixel circuits in the display panel is also good.

[0176] Referring to Figure 14 , three second pixel circuits and two first pixel circuits in five pixel circuits (one circuit group) can be arranged in the order of second pixel circuit, second pixel circuit, first pixel circuit, second pixel circuit, and first pixel circuit. Of course, referring to Figure 15 , three second pixel circuits and two first pixel circuits in five pixel circuits can also be arranged in the order of second pixel circuit, second pixel circuit, second pixel circuit, first pixel circuit, and first pixel circuit. Of course, the arrangement method can also be other methods, and the embodiments of the present application do not limit this.

[0177] In the embodiments of the present application, the equivalent circuit diagrams of the first pixel circuit and the second pixel circuit can refer to Figure 16The pixel circuit may include a plurality of thin film transistors and a storage capacitor. The plurality of thin film transistors include a first data reset control transistor T1, a threshold compensation transistor T2, a drive transistor T3, a write transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, and a third reset control transistor T7.

[0178] The storage capacitor Cst may include two capacitor plates Cst1 and Cst2. In the embodiment of the application, the capacitor plate Cst1 may be referred to as one end, the first end, the first electrode or the first storage capacitor electrode of the storage capacitor Cst, and the capacitor plate Cst2 may be referred to as the other end, the second end, the second electrode or the second storage capacitor electrode of the storage capacitor Cst.

[0179] The first reset control transistor T1 has a first electrode electrically connected to a reset power signal line to receive a reset signal Vinit, a second electrode electrically connected to a gate of a driving transistor T3, and a gate electrically connected to a reset control signal line to receive a reset control signal Reset. A first electrode of a threshold compensation transistor T2 is connected to a first electrode of the driving transistor T3, a gate electrically connected to a scan signal line to receive a scan signal Gate, and a second electrode electrically connected to the gate of the driving transistor T3. A first electrode of a data write transistor T4 is connected to a second electrode of the driving transistor T3, a gate electrically connected to a scan signal line to receive a scan signal Gate, and a second electrode electrically connected to a data line to receive a data drive signal Data. A first electrode of a first emission control transistor T5 is electrically connected to a first power signal line, a second electrode electrically connected to a second electrode of the driving transistor T3, and a gate electrically connected to an emission control signal line to receive an emission control signal EM. The gate of the second emission control transistor T6 is electrically connected to the emission control signal line to receive the emission control signal EM. A first electrode of the third reset control transistor T7 is connected to the reset power signal line to receive the reset signal Vinit. A second electrode of the third reset control transistor T7 is connected to the electrode pattern of the light-emitting device. The gate of the first reset transistor T7 is electrically connected to the reset control signal line to receive the reset control signal Reset. A first electrode of the storage capacitor Cst is electrically connected to the first power signal line, and a second electrode of the storage capacitor Cst is electrically connected to the gate of the drive transistor T3. Alternatively, the cathode of the light-emitting device may be electrically connected to the second power signal line. The first power signal line is a signal line that outputs the voltage signal VDD, and the second power signal line is a signal line that outputs the voltage signal VSS.

[0180] Figure 17It is a partial schematic diagram of the semiconductor layer in the display panel provided by the embodiments of the present application. Refer to Figure 17 , the semiconductor layer may have a curved or bent shape. The semiconductor layer includes semiconductor patterns (channel regions) and doped region patterns (source / drain doped regions) of each transistor, and the active layer patterns and doped region patterns of the transistors in the same pixel circuit are integrally provided.

[0181] It should be noted that the semiconductor layer may include an integrally formed low-temperature polycrystalline silicon layer, and the source region and the drain region can be made conductive through doping and other means to achieve electrical connection of each structure. That is, the semiconductor layer of each transistor in each pixel circuit is an integral pattern formed of p-silicon, and each transistor in the same pixel circuit includes a doped region pattern (i.e., the source region and the drain region) and a semiconductor pattern, and the semiconductor patterns of different transistors are separated from each other.

[0182] The semiconductor layer can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the above-mentioned source region and drain region can be regions doped with n-type impurities or p-type impurities.

[0183] Figure 18 It is a partial superimposed schematic diagram of the first gate layer in the display panel provided by the embodiments of the present application. Among them, the display panel includes a first gate insulating layer on the side of the semiconductor layer away from the substrate, which is used to insulate the above-mentioned semiconductor layer from the subsequently formed first gate layer. Figure 18 It shows the first gate layer included in the display panel. The first gate layer is disposed on the first gate insulating layer, so as to be insulated from the semiconductor layer. The first gate layer may include a second storage capacitor electrode Cst2, a plurality of scan signal lines g1 extending along the pixel row direction X, a plurality of reset control signal lines g2, a plurality of light emission control signal lines g3, and the first gate layer further includes the gates of each transistor.

[0184] For example, in combination with Figures 17 to 19 , the gate of the data writing transistor T4 can be the overlapping part of the scan signal line g1 and the semiconductor layer; the gate of the second light emission control transistor T6 can be the first overlapping part of the light emission control signal line g3 and the semiconductor layer, and the gate of the first light emission control transistor T5 can be the second overlapping part of the light emission control signal line g3 and the semiconductor layer. The gate of the first reset control transistor T1 is the first overlapping part of the reset control signal line g2 and the semiconductor layer, and the gate of the third reset control transistor T7 is the second overlapping part of the reset control signal line g2 and the semiconductor layer. The gate of the threshold compensation transistor T2 can be the overlapping part of the protruding structure P protruding from the scan signal line g1 and the semiconductor layer. As Figure 18 shown, the gate of the driving transistor T3 can be the second storage capacitor electrode Cst2.

[0185] It should be noted thatFigure 19 Each dashed rectangular box therein shows the overlapping parts of the first gate layer and the semiconductor layer. As the channel regions of the respective transistors, the semiconductor layers on both sides of each channel region are made conductive as the first and second poles of the respective transistors through processes such as ion doping. The source and drain of the transistor can be symmetric in structure, so there can be no physical difference between its source and drain. In the embodiments of the present application, in order to distinguish the transistors, except for the gate as the control electrode, one of the poles is directly described as the first pole and the other as the second pole. Therefore, the first and second poles of all or part of the transistors in the embodiments of the present application can be interchanged as needed.

[0186] As Figure 18 and Figure 19 shown, the scan signal line g1, the reset control signal line g2, and the light emission control signal line g3 are arranged along the pixel column direction Y. In the pixel column direction Y, the second storage capacitor electrode Cst2 (i.e., the gate of the driving transistor T3) is located between the scan signal line g1 and the light emission control signal line g3. The protruding structure P protruding from the scan signal line g1 is located on the side of the scan signal line g1 close to the light emission control signal line g3.

[0187] In addition, a second gate insulating layer may be formed on the above-mentioned first gate layer to insulate the above-mentioned first gate layer from the subsequently formed second gate layer.

[0188] Figure 20 is a partial schematic diagram of the second gate layer in a display panel provided by an embodiment of the present application, Figure 21 is a partial superimposed schematic diagram of the semiconductor layer, the first gate layer, and the second gate layer in the display panel provided by an embodiment of the present application. As Figure 20 and Figure 21 shown, the second gate layer includes a first storage capacitor electrode Cst1, a plurality of first reset power signal lines g4 extending along the pixel row direction X, and a plurality of second reset power signal lines g5 extending along the pixel row direction X. The first storage capacitor electrode Cst1 and the second storage capacitor electrode Cst2 at least partially overlap to form a storage capacitor Cst.

[0189] In addition, an interlayer dielectric layer may be formed on the above-mentioned second gate layer to insulate the above-mentioned second gate layer from the subsequently formed first source-drain layer. Referring to Figure 22 and Figure 23 for the convenience of showing the respective vias in the interlayer dielectric layer (ILD), Figures 22 to 23Via holes are represented by filled patterns. Other areas without filled patterns drawn are used to represent areas where the interlayer dielectric layer has solid materials. It should be noted that each via hole opened in the interlayer dielectric layer is for connecting the film layer formed subsequently to the film layer on the side of the interlayer dielectric layer close to the substrate. That is, each of these via holes is a via hole for film layer connection.

[0190] Figure 24 It is a partial schematic diagram of the first source-drain layer in the display panel provided by an embodiment of the present application. Figure 25 It is a partial superimposed schematic diagram of the semiconductor layer, the first gate layer, the second gate layer, the interlayer dielectric layer, and the first source-drain layer in the display panel provided by an embodiment of the present application. As Figure 24 and Figure 25 shown, the first source-drain layer includes a first connection structure h1, a second connection structure h2, a third connection structure h3, a fourth connection structure h4, a fifth connection structure h5, and a sixth connection structure h6. The first connection structure h1 is configured to connect the source (or drain) of the threshold compensation transistor T2 and the gate of the driving transistor T3. The second connection structure h2 is configured to connect the second light-emitting control transistor T6. The third connection structure h3 is configured to connect the source (or drain) of the third reset control transistor T7 and the reset power signal line g4. The fourth connection structure h4 is configured to connect the VDD signal line and the source (or drain) of the first light-emitting control transistor T5. The fifth connection structure h5 is configured to connect the source (or drain) of the data writing transistor T4 and the data line g6. The sixth connection structure h6 is configured to connect the second reset power signal line g5.

[0191] In addition, a passivation layer may be formed on the above-mentioned first source-drain layer to insulate the above-mentioned first source-drain layer from the intermediate source-drain layer formed subsequently. Referring to Figure 26 and Figure 27 , for the convenience of showing each via hole in the passivation layer (PVX), Figures 26 to 27 Via holes are represented by filled patterns. Other areas without filled patterns drawn are used to represent areas where the passivation layer has solid materials. It should be noted that each via hole opened in the passivation layer is for connecting the film layer formed subsequently to the film layer on the side of the passivation layer close to the substrate. That is, each of these via holes is a via hole for film layer connection.

[0192] Figure 28 It is a partial schematic diagram of the intermediate source-drain layer in the display panel provided by an embodiment of the present application. Figure 29 It is a partial superimposed schematic diagram of the semiconductor layer, the first gate layer, the second gate layer, the interlayer dielectric layer, the first source-drain layer, the passivation layer, and the intermediate source-drain layer in the display panel provided by an embodiment of the present application. As Figure 28 and Figure 29As shown, the intermediate source-drain layer includes a first signal line VDD1, a seventh connection structure h7, and an eighth connection structure h8. The first signal line VDD1 is configured to be connected to the fourth connection structure h4, the seventh connection structure h7 is configured to be connected to the second connection structure h2, and the eighth connection structure h8 is configured to be connected to the fifth connection structure h5.

[0193] In addition, a first planarization layer (PLN1) may be formed on the above-mentioned intermediate source-drain layer to insulate the intermediate source-drain layer from a second source-drain layer formed subsequently. Refer to Figure 30 and Figure 31 , in order to facilitate showing each via hole in the first planarization layer, Figures 30 to 31 the via holes are represented by filled patterns in

[0194] Figure 32 is a partial schematic diagram of the second source-drain layer in the display panel provided by the embodiment of the present application, Figure 33 is a stacked schematic diagram of a semiconductor layer, a first gate layer, a second gate layer, an interlayer dielectric layer, a first source-drain layer, a passivation layer, an intermediate source-drain layer, and a second source-drain layer in the display panel provided by the embodiment of the present application. As Figure 32 and Figure 33 shown, the second source-drain layer includes a second signal line VDD2, a data line g6, and a ninth connection structure h9. The second signal line VDD2 is configured to be connected to the first signal line VDD1, the data line g6 is configured to be connected to the eighth connection structure h8, and the ninth connection structure h9 is configured to be connected to the seventh connection structure h7. The traces for transmitting the VDD signal include the first signal line VDD1 and the second signal line VDD2.

[0195] In addition, a second planarization layer (PLN2) may be formed on the above-mentioned second source-drain layer to insulate the intermediate source-drain layer from a first conductive layer in a connection layer formed subsequently. Refer to Figure 34 and Figure 35 , in order to facilitate showing each via hole in the second planarization layer, Figures 34 to 35 the via holes are represented by filled patterns in

[0196] In summary, the embodiment of the present application provides a display panel. Since at least two first electrode patterns in the display panel are connected, and one of the at least two connected first electrode patterns is connected to a first pixel circuit, one first pixel circuit can drive two first electrode patterns. At the same time, since at least two second electrode patterns are connected, and one of the at least two connected second electrode patterns is connected to a second pixel circuit, one second pixel circuit can drive two second electrode patterns. Thus, when the number of electrode patterns is the same, adopting the scheme of driving two electrode patterns with one pixel circuit can reduce the number of pixel circuits required to be designed in the second display area, and further increase the space that each pixel circuit can occupy, with relatively low process preparation difficulty.

[0197] Figure 36 is a flowchart of a method for manufacturing a display panel provided by an embodiment of the present application. This method can be used to manufacture the display panel provided in the above embodiment. Refer to Figure 36 , this method may include:

[0198] Step S101: Sequentially form a buffer layer, a semiconductor layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer, a first source-drain layer, a passivation layer, an intermediate source-drain layer, a first planarization layer, a second source-drain layer, and a second planarization layer on one side of the substrate.

[0199] In the embodiment of the present application, when manufacturing a display panel, a substrate can be obtained first. Among them, the substrate can be a transparent glass substrate or a flexible substrate. Correspondingly, the manufactured display panel can be a flexible display panel. Then, each film layer in the buffer layer and the driving circuit layer can be formed on one side of the substrate. The film layers in the driving circuit layer can refer to Figures 17 to 35 . This is not elaborated in the embodiment of the present application.

[0200] Step S102: Sequentially form a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a third conductive layer, and a third insulating layer on the side of the second planarization layer away from the substrate.

[0201] Refer to Figure 37 and Figure 38 , a first conductive layer is formed on the side of the second planarization layer away from the substrate, and the first conductive layer can include a plurality of first connection parts. Refer to Figure 39 and Figure 40 , a first insulating layer (third planarization layer PLN3) is formed on the side of the first conductive layer away from the substrate. For the convenience of showing each first via hole in the first insulating layer, Figure 39 and Figure 40The first vias are represented by a filling pattern. The other regions without the filling pattern drawn are used to represent the regions where the first insulating layer has solid materials. It should be noted that each of the first vias formed in the first insulating layer is used for the subsequent formed film layer to be connected to the film layer on the side of the first insulating layer close to the substrate. That is to say, each of the first vias is a via for film layer connection.

[0202] Reference Figure 41 and Figure 42 , a second conductive layer is formed on the side of the first insulating layer away from the substrate, and the second conductive layer may include a plurality of second connection portions. Reference Figure 43 and Figure 44 , a second insulating layer (the fourth planar layer PLN4) is formed on the side of the second conductive layer away from the substrate. To facilitate showing each of the second vias in the second insulating layer, Figure 43 and Figure 44 the second vias are represented by a filling pattern. The other regions without the filling pattern drawn are used to represent the regions where the second insulating layer has solid materials. It should be noted that each of the second vias formed in the second insulating layer is used for the subsequent formed film layer to be connected to the film layer on the side of the second insulating layer close to the substrate. That is to say, each of the second vias is a via for film layer connection.

[0203] Reference Figure 45 and Figure 46 , a third conductive layer is formed on the side of the second insulating layer away from the substrate, and the third conductive layer may have a plurality of third connection portions. Reference Figure 47 and Figure 48 , a third insulating layer (the fifth planar layer PLN5) is formed on the side of the third conductive layer away from the substrate. To facilitate showing each of the second vias in the third insulating layer, Figure 47 and Figure 48 the third vias are represented by a filling pattern. The other regions without the filling pattern drawn are used to represent the regions where the third insulating layer has solid materials. It should be noted that each of the third vias formed in the third insulating layer is used for the subsequent formed film layer to be connected to the film layer on the side of the third insulating layer close to the substrate 101. That is to say, each of the third vias is a via for film layer connection.

[0204] Step S103: Form a first electrode layer, a pixel defining layer, a light-emitting film layer, a second electrode layer, and a packaging layer on the side of the third insulating layer away from the substrate.

[0205] Reference Figure 49 and Figure 50 , a first electrode layer is formed on the side of the third insulating layer away from the substrate. The first electrode layer may include a plurality of electrode patterns, and each electrode pattern can serve as the anode of a pixel device. Figure 49 and Figure 50The second electrode pattern, the fourth electrode pattern, and the sixth electrode pattern are shown.

[0206] Reference Figure 51 and Figure 52 , a pixel defining layer is formed on the side of the first electrode layer away from the substrate. The pixel defining layer may have a plurality of openings, and each opening exposes one electrode pattern in the first electrode layer. To facilitate showing each opening in the pixel defining layer, Figure 51 and Figure 52 a filling pattern is used to represent the openings, and the other areas without the drawn filling pattern are used to represent the areas of the pixel defining layer with solid materials. It should be noted that each opening formed in the pixel defining layer is for the film layer formed subsequently to be connected to the film layer on the side of the pixel defining layer close to the substrate. That is, each of these openings is for the light-emitting layer in the light-emitting film layer to contact the electrode pattern in the first electrode layer.

[0207] After forming the pixel defining layer, a light-emitting film layer, a second electrode layer, and a packaging layer can be continuously formed on the side of the pixel defining layer away from the substrate, which will not be elaborated in detail in the embodiments of the present application.

[0208] It should be noted that the preparation method of the display panel provided by the embodiments of the present application is mainly described by taking other areas (such as the first sub-display area, the third sub-display area, the fourth sub-display area, the fifth sub-display area, and the sixth sub-display area) in the second display area that are not the second sub-display area as examples. Figures 17 to 51 All take including one circuit group A along the pixel row direction and two circuit groups A along the pixel column direction as examples.

[0209] For the second sub-display area (transition display area) in the second display area, the main difference in the film layers between it and other areas in the second display area is the respective conductive layers. Reference Figure 53 , the part of the conductive layer located in the second sub-display area includes, in addition to the connection part, a second connection trace, a fourth connection trace, or a fifth connection trace. That is, the part of the conductive layer located in the second sub-display area may include a connection trace for connecting the pixel circuit located in the second sub-display area and the electrode pattern located in the first display area. Figure 53 The conductive layer in Figure 53 can be a first conductive layer, a second conductive layer, or a third conductive layer. Correspondingly,

[0210] In summary, the embodiment of the present application provides a method for manufacturing a display panel. Since at least two first electrode patterns are connected in the manufactured display panel, and one of the at least two connected first electrode patterns is connected to a first pixel circuit, one first pixel circuit can drive two first electrode patterns. At the same time, since at least two second electrode patterns are connected, and one of the at least two connected second electrode patterns is connected to a second pixel circuit, one second pixel circuit can drive two second electrode patterns. Thus, when the number of electrode patterns is the same, the scheme of using one pixel circuit to drive two electrode patterns can reduce the number of pixel circuits required to be designed in the second display area, and further increase the space that each pixel circuit can occupy, with a relatively low process manufacturing difficulty.

[0211] Figure 54 is a schematic structural diagram of a display module provided by an embodiment of the present application. As Figure 54 , the display device may include a data driving circuit 20 and the display panel 10 provided in the above embodiment. Among them, the data driving circuit 20 may be connected to the first data line S1, the third data line S3, the fourth data line S4, and the seventh data line S7 in the display panel 10 to directly provide data driving signals for the first data line S1, the third data line S3, the fourth data line S4, and the seventh data line S7. Among them, Figure 54 are all schematically shown as one first data line S1, one third data line S3, one fourth data line S4, and one seventh data line S7.

[0212] Moreover, the second data line S2 is connected to the first data line S1 through the first jumper wire Z1, and the fifth data line S5 is connected to the second data line S2 through the second jumper wire Z2. Therefore, the data driving circuit 20 provides data driving signals for the second data line S2 and the fifth data line S5 through the first data line S1. The sixth data line S6 is connected to the fourth data line S4 through the third jumper wire Z3. Therefore, the data driving circuit 20 provides data driving signals for the sixth data line S6 through the fourth data line S4.

[0213] Since the display module may have substantially the same technical effects as the display panel described in the previous embodiment, for the sake of brevity, the technical effects of the display device are not described again here.

[0214] Refer to Figure 55, embodiments of the present application provide a display device, which may include electrical components such as the display module 01 and the sensor 02 provided in the above embodiments, for example: an optical sensor. Taking the display device as a mobile phone as an example, the display device includes optical sensors such as a front camera, a proximity light sensor, and a 3D sensing module. These optical components need to receive light from the display surface side of the display device to implement corresponding functions. In the display device, the optical sensor is usually installed on the non-display surface side of the display module 01, and the photosensitive surface side of the optical sensor faces the display module 01. Among them, the orthographic projection of the optical sensor 02 on the display panel 10 at least partially overlaps with the first display area 101a in the display panel 10.

[0215] In the embodiments of the present application, the display device may be an active-matrix organic light-emitting diode (AMOLED) display device, a passive-matrix organic light-emitting diode (PMOLED) display device, a quantum dot light emitting diodes (QLED) display device, an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator, etc., any product or component with a display function.

[0216] Since the display device may have substantially the same technical effects as the display panel described in the previous embodiments, for the sake of brevity, the technical effects of the display device are not described again here.

[0217] The terms used in the embodiments section of this application are only for explaining the embodiments of this application and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this application should have the ordinary meaning understood by those of ordinary skill in the art to which this application belongs. The "first", "second", "third" and similar words used in the specification and claims of this patent application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "a" or "an" do not indicate a quantity limitation, but indicate that there is at least one. Words such as "comprising" or "including" mean that the elements or objects appearing before "comprising" or "including" cover the elements or objects listed after "comprising" or "including" and their equivalents, and do not exclude other elements or objects. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to indicate relative position relationships, and when the absolute position of the object being described changes, the relative position relationships may also change accordingly.

[0218] The above are only optional embodiments of this application and are not intended to limit this application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application shall be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, The display panel includes: a base substrate having a first display area and a second display area at least partially surrounding the first display area; a driving circuit layer located on one side of the base substrate, the driving circuit layer comprising a plurality of first pixel circuits and a plurality of second pixel circuits located in the second display area; a first electrode layer, the first electrode layer comprising a plurality of first-type electrode patterns, the plurality of first-type electrode patterns comprising a plurality of first electrode patterns located in the first display area, and a plurality of second electrode patterns located in the second display area; at least two of the first electrode patterns being connected to one of the plurality of first pixel circuits, and at least two of the second electrode patterns being connected to one of the plurality of second pixel circuits; a plurality of second connecting wires, a plurality of fourth connecting wires, and a plurality of fifth connecting wires, wherein the plurality of second connecting wires, the plurality of fourth connecting wires, and the plurality of fifth connecting wires all extend from the second display area to the first display area along a pixel row direction; One of the at least two first electrode patterns is connected to one of the first pixel circuits via one of the second connecting traces; the first electrode layer further includes a plurality of second-type electrode patterns and a plurality of third-type electrode patterns; The plurality of second-type electrode patterns include a plurality of third electrode patterns located in the first display area, and the third electrode pattern is connected to one of the first pixel circuits via one of the fourth connecting wires; The plurality of third-type electrode patterns include a plurality of fifth electrode patterns located in the first display area, the fifth electrode pattern being connected to one of the first pixel circuits via the fifth connecting wire; A length of any second connecting line along the pixel row direction is smaller than a length of the fourth connecting line along the pixel row direction, and smaller than a length of the fifth connecting line along the pixel row direction.

2. The display panel according to claim 1, wherein The display panel further includes: a plurality of first connection lines, wherein the plurality of first connection lines are located in the first display area; and a plurality of third connecting wires, wherein the plurality of third connecting wires are located in the second display area; At least two of the first electrode patterns are connected via one of the first connecting lines, at least two of the second electrode patterns are connected via one of the third connecting lines, and one of the at least two second electrode patterns is connected to one of the second pixel circuits.

3. The display panel according to claim 2, wherein The plurality of second-type electrode patterns further include a plurality of fourth electrode patterns located in the second display area; the plurality of third-type electrode patterns further include a plurality of sixth electrode patterns located in the second display area; Two adjacent first pixel circuits and three adjacent second pixel circuits constitute a circuit group; at least two adjacent second electrode patterns constitute an electrode pattern group; and an adjacent electrode pattern group, one adjacent fourth electrode pattern, and one adjacent sixth electrode pattern constitute a pattern group; Each of the pattern groups corresponds to one of the circuit groups, and for the corresponding pattern groups and circuit groups, an area where the orthographic projection of the pattern group on the substrate is located overlaps with an area where the orthographic projection of the circuit group on the substrate is located.

4. The display panel according to claim 3, wherein For each of the circuit groups and a pattern group corresponding to the circuit group, among the three second pixel circuits included in the circuit group, the first second pixel circuit is connected to a second electrode pattern of the electrode pattern group in the pattern group, the second second pixel circuit is connected to the fourth electrode pattern in the pattern group, and the third second pixel circuit is connected to the sixth electrode pattern in the pattern group.

5. The display panel according to claim 3, wherein: Two first pixel circuits included in a part of the circuit groups in the display panel are connected to the electrode pattern located in the first display area, and two first pixel circuits included in another part of the circuit groups in the display panel are connected to a fixed voltage terminal.

6. The display panel according to claim 5, wherein: The circuit group to which the first pixel circuit connected to the electrode pattern of the first display area belongs is closer to the first display area than the circuit group to which the first pixel circuit connected to the fixed voltage terminal belongs.

7. The display panel according to claim 1, wherein The display panel includes red sub-pixels, green sub-pixels and blue sub-pixels. The sub-pixels to which the first type of electrode pattern belongs are green sub-pixels, the sub-pixels to which the second type of electrode pattern belongs are red sub-pixels, and the sub-pixels to which the third type of electrode pattern belongs are blue sub-pixels.

8. The display panel according to any one of claims 1 to 7, characterized in that, For each of the multiple second connecting lines, the multiple fourth connecting lines and the multiple fifth connecting lines, the length of the connecting line along the pixel row direction is positively correlated with the distance between the electrode pattern located in the first display area to which the connecting line is connected and the second display area along the pixel row direction.

9. The display panel according to any one of claims 1 to 7, wherein: The second display area includes a first sub-display area, a second sub-display area, and a third sub-display area, the first sub-display area and the first display area are arranged along a pixel column direction, the second sub-display area and the first display area are arranged along a pixel row direction, the third sub-display area and the first sub-display area are arranged along the pixel row direction, and are arranged with the second sub-display area along the pixel column direction; The display panel further includes: a plurality of first data lines located in the first sub-display area, a plurality of second data lines located in the second sub-display area and the third sub-display area, and a plurality of first transfer lines located in the first sub-display area and the third sub-display area; the plurality of first data lines are arranged along the pixel rows and extend along the pixel columns, the plurality of second data lines are arranged along the pixel rows and extend along the pixel columns, and the plurality of first transfer lines are arranged along the pixel columns and extend along the pixel rows; The first end of each first data line is used to connect to the data driving circuit, the second end of each first data line is connected to the first end of a first adapter line, and the second end of each first adapter line is connected to the first end of a second data line; wherein, each first data line is also connected to a column of second pixel circuits located in the first sub-display area for connecting to the first target electrode pattern, and each second data line is also connected to a column of first pixel circuits located in the second sub-display area for connecting to the second target electrode pattern; the first target electrode pattern is at least one of the fourth electrode pattern and the sixth electrode pattern, and the second target electrode pattern is at least one of the third electrode pattern and the fifth electrode pattern.

10. The display panel according to claim 9, wherein The first target electrode pattern is a fourth electrode pattern or a sixth electrode pattern, and the second target electrode pattern is a third electrode pattern or a fifth electrode pattern; the display panel further includes: a plurality of third data lines located in the first sub-display area, and a plurality of fourth data lines located in the second sub-display area and the third sub-display area; The plurality of third data lines are arranged along the pixel row direction and extend along the pixel column direction, a first end of each of the third data lines is used to be connected to a data driving circuit, and each of the third data lines is also connected to a column of second pixel circuits located in the first sub-display area and connected to a second electrode pattern; The multiple fourth data lines are arranged along the pixel row direction and extend along the pixel column direction. The first end of each of the fourth data lines is used to connect to the data driving circuit, and each of the fourth data lines is also connected to a column of first pixel circuits located in the second sub-display area for connecting to the first electrode pattern.

11. The display panel according to claim 9, wherein The second display area further includes: a fourth sub-display area and a fifth sub-display area, the fourth sub-display area being located on a side of the first display area away from the first sub-display area, and the fifth sub-display area and the fourth sub-display area being arranged along the pixel row direction; the plurality of second data lines are also located in the fifth sub-display area; the display panel further includes: a plurality of second adapter lines, and a plurality of fifth data lines located in the fourth sub-display area; The multiple fifth data lines are arranged along the pixel row direction and extend along the pixel column direction, and the multiple second transfer lines are arranged along the pixel column direction and extend along the pixel row direction; the second end of each second data line is connected to the first end of a second transfer line, and the second end of each second transfer line is connected to the first end of the fifth data line; the fifth data line is also connected to a column of second pixel circuits located in the fourth sub-display area for connecting the first target electrode pattern.

12. The display panel according to claim 9, wherein The display panel further includes: a plurality of first dummy data lines located in the third sub-display area; The plurality of first dummy data lines are arranged along the pixel row direction and extend along the pixel column direction. The first dummy data lines are used to connect to a fixed voltage terminal, and the first dummy data lines are also connected to a column of first pixel circuits located in the third sub-display area.

13. The display panel according to claim 9, wherein: The second display area further includes: a sixth sub-display area located on a side of the third sub-display area away from the first sub-display area; the display panel further includes: a plurality of seventh data lines located in the sixth sub-display area, and a plurality of second dummy data lines located in the sixth sub-display area; The plurality of seventh data lines are arranged along the pixel row direction and extend along the pixel column direction, each of the seventh data lines is used for connecting to a data driving circuit, and each of the seventh data lines is further connected to a column of second pixel circuits located in the sixth sub-display area; The plurality of second dummy data lines are arranged along the pixel row direction and extend along the pixel column direction, each of the second dummy data lines is used for connecting to a fixed voltage terminal, and the second dummy data line is further connected to a column of first pixel circuits located in the sixth sub-display area.

14. The display panel according to any one of claims 2 to 6, characterized in that: The third connection trace is on the same layer as the first electrode layer, and both the first connection trace and the second connection trace are between the driving circuit layer and the first electrode layer.

15. A display module, characterized in that, The display module includes a data driving circuit and a display panel according to any one of claims 1 to 14; Wherein, the data driving circuit is connected to the first data line, the third data line, the fourth data line, and the seventh data line in the display panel.

16. A display device, characterized in that: The display device includes the display module according to claim 15 and an optical sensor, and a positive projection of the optical sensor on the display panel at least partially overlaps with the first display area in the display panel.

Images