Semiconductor structure and method of manufacturing the same

Abstract

Semiconductor structures and methods of fabricating the same are provided. A semiconductor structure includes a substrate and a first nanostructure and a second nanostructure formed above the substrate. The semiconductor structure also includes a gate structure including a first portion encircling the first nanostructure and a second portion encircling the second nanostructure. The semiconductor structure further includes a dielectric component sandwiched between the first portion and the second portion of the gate structure. Moreover, the dielectric component includes a bottom portion and a top portion above the bottom portion, and the top portion of the dielectric component includes a shell layer and a core portion encircled by the shell layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor structures and methods for manufacturing the same. Background Technology

[0002] The electronics industry is experiencing a growing demand for smaller and faster electronic devices capable of performing a greater number of increasingly complex and sophisticated functions. Consequently, there is a persistent trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been largely achieved by scaling down the size of semiconductor ICs (e.g., miniaturization), thereby increasing production efficiency and reducing associated costs. However, this miniaturization introduces greater complexity into semiconductor manufacturing processes. Therefore, continued advancements in semiconductor ICs and devices require similar advancements in semiconductor manufacturing processes and technologies.

[0003] Recently, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and mitigating short-channel effect (SCE). However, the integration of multi-gate devices in fabrication can be challenging. Summary of the Invention

[0004] According to one aspect of an embodiment of the present invention, a semiconductor structure is provided, comprising: a back-side dielectric layer; a first nanostructure and a second nanostructure located above the back-side dielectric layer; a first source / drain structure connected to the first nanostructure; a second source / drain structure connected to the second nanostructure; and a back-side source / drain isolation member sandwiched between the first source / drain structure and the second source / drain structure, wherein the bottom surface of the back-side source / drain isolation member is substantially flush with the bottom surface of the back-side dielectric layer.

[0005] According to another aspect of an embodiment of the present invention, a semiconductor structure is provided, comprising: a back-side dielectric layer; a first nanostructure and a second nanostructure extending over the back-side dielectric layer in a first direction; a gate structure located over the back-side dielectric layer and surrounding the first and second nanostructures and extending in a second direction; a first source / drain structure located over the back-side dielectric layer and connected to the first nanostructure; a second source / drain structure located over the back-side dielectric layer and connected to the second nanostructure; and a back-side source / drain isolation member extending in the first direction and separating the first source / drain structure and the second source / drain structure. The back-side source / drain isolation member comprises: a pad layer located over the sidewalls of the first and second source / drain structures; and an isolation material surrounded and covered by the pad layer.

[0006] According to another aspect of the present invention, a method for manufacturing a semiconductor structure is provided, comprising: forming a first fin structure and a second fin structure protruding from the front side of a substrate, wherein the first fin structure and the second fin structure include alternately stacked first semiconductor material layers and second semiconductor material layers; forming an isolation structure surrounding the first fin structure and the second fin structure; forming a source / drain structure over the first fin structure and the second fin structure; removing the isolation structure from the back side of the substrate to form an opening exposing the source / drain structure; etching the source / drain structure through the opening to form a deep opening through the source / drain structure; and forming a back-side source / drain isolation component in the deep opening. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G , Figure 1H , Figure 1I , Figure 1J , Figure 1K , Figure 1L , Figure 1M , Figure 1N , Figure 10 , Figure 1P , Figure 1Q , Figure 1R , Figure 1S , Figure 1T , Figure 1U , Figure 1V , Figure 1W , Figure 1X , Figure 1Y , Figure 1Z and Figure 1ZA , Figure 1ZB , Figure 1ZC , Figure 1ZD , Figure 1ZE , Figure 1ZF The illustration shows a schematic perspective view of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments.

[0009] Figure 1B-1 A schematic top view of an intermediate stage of a semiconductor structure according to some embodiments is illustrated, and Figure 1B-1 The box B1 shown corresponds to Figure 1B The structure shown.

[0010] Figure 1E-1 A schematic top view of an intermediate stage of a semiconductor structure according to some embodiments is illustrated, and Figure 1E The structure shown corresponds to Figure 1E-1 The area shown in box B1.

[0011] Figure 1K-1 A schematic top view of an intermediate stage of a semiconductor structure according to some embodiments is illustrated, and Figure 1K The structure shown corresponds to Figure 1K-1 The area shown in box B1.

[0012] Figure 1M-1 A schematic top view of an intermediate stage of a semiconductor structure according to some embodiments is illustrated, and Figure 1M The structure shown corresponds to Figure 1M-1 The area shown in box B1.

[0013] Figure 1Q-1 A schematic top view of an intermediate stage of a semiconductor structure according to some embodiments is illustrated, and Figure 1Q The structure shown corresponds to Figure 1Q-1 The area shown in box B1.

[0014] Figure 1S-1 A schematic top view of an intermediate stage of a semiconductor structure according to some embodiments is illustrated, and Figure 1S The structure shown corresponds to Figure 1S-1 The area shown in box B1.

[0015] Figure 1T-1 A schematic top view of an intermediate stage of a semiconductor structure according to some embodiments is illustrated, and Figure 1T The structure shown corresponds to Figure 1T-1 The area shown in box B2.

[0016] Figure 1X-1 A schematic top view of an intermediate stage of a semiconductor structure according to some embodiments is illustrated, and Figure 1X The structure shown corresponds to Figure 1X-1 The area shown in box B2.

[0017] Figure 1ZB-1 A schematic top view of an intermediate stage of a semiconductor structure according to some embodiments is illustrated, and Figure 1ZB The structure shown corresponds to Figure 1ZB-1 The area shown in box B2.

[0018] Figure 1ZC-1 A schematic top view of an intermediate stage of a semiconductor structure according to some embodiments is illustrated, and Figure 1ZC The structure shown corresponds to Figure 1ZC-1 The area shown in box B3.

[0019] Figure 1 ZF-1 A schematic top view of a semiconductor structure according to some embodiments is illustrated, and Figure 1ZF The structure shown corresponds to Figure 1 ZF-1 The area shown in box B3.

[0020] Figure 1T-2 , Figure 1U-1 , Figure 1V-1 , Figure 1W-1 , Figure 1X-2 , Figure 1Y-1 , Figure 1Z-1 and Figure 1ZA-1 , Figure 1ZB-2 , Figure 1ZC-2 , Figure 1ZD-1 , Figure 1 ZE-1 , Figure 1 ZF-2 The illustration shows the line A-A' according to some embodiments. Figure 1T , Figure 1U , Figure 1V , Figure 1W , Figure 1X , Figure 1Y , Figure 1Z and Figure 1ZA , Figure 1ZB , Figure 1ZC , Figure 1ZD , Figure 1ZE , Figure 1ZF A cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure.

[0021] Figure 1T-3 , Figure 1 U-2 , Figure 1V-2 , Figure 1W-2 , Figure 1X-3 , Figure 1Y-2 , Figure 1Z-2 and Figure 1ZA-2 , Figure 1 ZB-3 , Figure 1 ZC-3 , Figure 1 ZD-2 , Figure 1 ZE-2 , Figure 1 ZF-3 The illustration shows the line B-B' according to some embodiments. Figure 1T , Figure 1U , Figure 1V , Figure 1W , Figure 1X , Figure 1Y , Figure 1Z and Figure 1ZA , Figure 1ZB , Figure 1ZC , Figure 1ZD , Figure 1ZE , Figure 1ZF A cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure.

[0022] Figure 1 ZF-4 The illustration shows the path along according to some embodiments. Figure 1ZF The line C-C' shows a cross-sectional view of the semiconductor structure.

[0023] Figures 2 to 6 The illustration shows a cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure according to some other embodiments.

[0024] Figures 7A to 7C The illustration shows a schematic perspective view of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments.

[0025] Figure 8A and Figure 8B The illustration shows a schematic perspective view of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments.

[0026] Figure 8B-1 The illustration shows a cross-sectional view of a semiconductor structure 100b, which is shown above the source / drain structure along an extension direction parallel to the gate structure according to some embodiments.

[0027] Figure 8B-2 The illustration shows a cross-sectional view of a semiconductor structure 100b, which is shown above the source / drain structure along an extension direction parallel to the nanostructure, according to some embodiments.

[0028] Figure 9A and Figure 9B The illustration shows a schematic perspective view of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments.

[0029] Figure 9B-1 The illustration shows a cross-sectional view of a semiconductor structure 100c, which is shown above the source / drain structure and extends along a direction parallel to the gate structure according to some embodiments.

[0030] Figure 9B-2 The illustration shows a cross-sectional view of a semiconductor structure 100c, which is shown above the source / drain structure along an extension direction parallel to the nanostructure, according to some embodiments.

[0031] Figure 10A and Figure 10B The illustration shows a schematic perspective view of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments. Detailed Implementation

[0032] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0033] Some variations of the embodiments are described. In the various views and illustrative embodiments, similar reference numerals are used to denote similar elements. It should be understood that additional operations may be provided before, during, and after the method, and some of the described operations may be replaced or eliminated for other embodiments of the method.

[0034] The nanostructure transistors described below (e.g., nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon FETs, gate-all-around (GAA) transistor structures) can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructure transistor.

[0035] Embodiments of semiconductor structures and methods for forming them are provided. The semiconductor structure may include a first nanostructure and a second nanostructure formed on a substrate, and a gate structure surrounding the first and second nanostructures. Source / drain structures attached to the first and second nanostructures can be formed first, and then the source / drain structures can be separated into two source / drain structures by a back-side source / drain isolation component. Since the source / drain structures attached to the first and second nanostructures can be separated by the subsequently formed back-side source / drain isolation component, the distance between the first and second nanostructures can be reduced without concern about merging of the source / drain structures. Therefore, the device size can be reduced.

[0036] Figures 1A to 1ZFA schematic perspective view is shown of an intermediate stage in the fabrication of a semiconductor structure 100 according to some embodiments. Corresponding to Figures 1A to 1ZF The manufacturing process shown, including some schematic top and cross-sectional views of intermediate stages of the semiconductor structure 100, is also illustrated and will be described in more detail later. Furthermore, for clarity, the figures may have been simplified to better understand the inventive concept of this disclosure. Additional components may be added to the semiconductor structure 100, and some components described below may be replaced, modified, or eliminated.

[0037] Semiconductor structure 100 may include multi-gate devices and may be included in a microprocessor, memory, or other IC device. For example, semiconductor structure 100 may be part of an IC chip, which includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof.

[0038] First, according to some embodiments, such as Figure 1A As shown, a semiconductor stack including a first semiconductor material layer 106 and a second semiconductor material layer 108 is formed over a substrate 102. The substrate 102 may be a semiconductor wafer, such as a silicon wafer. Optionally or additionally, the substrate 102 may include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0039] In some embodiments, a first semiconductor material layer 106 and a second semiconductor material layer 108 are alternately stacked over a substrate 102 to form a semiconductor stack. In some embodiments, the first semiconductor material layer 106 and the second semiconductor material layer 108 are made of different semiconductor materials. In some embodiments, the first semiconductor material layer 106 is made of SiGe, and the second semiconductor material layer 108 is made of silicon. It should be noted that, although Figure 1AThe diagram shows two first semiconductor material layers 106 and two second semiconductor material layers 108, but the semiconductor structure may include more or fewer first semiconductor material layers 106 and second semiconductor material layers 108. For example, the semiconductor structure may include two to five first semiconductor material layers 106 and two to five second semiconductor material layers 108.

[0040] The first semiconductor material layer 106 and the second semiconductor material layer 108 can be formed using low-pressure chemical vapor deposition (LPCVD), epitaxial growth processes, other suitable methods, or combinations thereof. In some embodiments, the epitaxial growth process includes molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE).

[0041] According to some embodiments, such as Figure 1B As shown, after the first semiconductor material layer 106 and the second semiconductor material layer 108 are formed as semiconductor material stacks above the substrate 102, the semiconductor material stacks are patterned to form fin structures 104-1, 104-2 and 104-3 extending in the first direction (i.e. the X direction). Figure 1B-1 A schematic top view of an intermediate stage of a semiconductor structure 100 according to some embodiments is shown, and Figure 1B-1 The box B1 shown corresponds to Figure 1B The structure shown.

[0042] In some embodiments, fin structures 104-1, 104-2, and 104-3 protrude from the front side of substrate 102. In some embodiments, fin structures 104-1, 104-2, and 104-3 include a base fin structure 105 and a semiconductor material stack, the semiconductor material stack including a first semiconductor material layer 106 and a second semiconductor material layer 108 formed above the base fin structure 105.

[0043] In some embodiments, the patterning process includes forming a mask structure over a semiconductor material stack and etching the semiconductor material stack and the underlying substrate 102 through the mask structure. In some embodiments, the mask structure is a multilayer structure including a pad oxide layer and a nitride layer formed over the pad oxide layer. The pad oxide layer may be made of silicon oxide, which may be formed by thermal oxidation or CVD, and the nitride layer may be made of silicon nitride, which may be formed by CVD (such as LPCVD or plasma-enhanced CVD (PECVD)).

[0044] After forming fin structures 104-1, 104-2, and 104-3, according to some embodiments, such as Figure 1CAs shown, an insulating liner 110 is formed to cover the lower sidewalls of fin structures 104-1, 104-2, and 104-3, and an insulating structure 112 is formed above the insulating liner 110. In some embodiments, the insulating liner 110 is made of a single dielectric material or multiple dielectric materials. In some embodiments, the insulating liner 110 includes an oxide layer and a nitride layer formed above the oxide layer. In some embodiments, the insulating structure 112 is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), other suitable insulating materials, or combinations thereof.

[0045] The isolation pad 110 and isolation structure 112 can be formed by conformally forming a pad layer covering the fin structures 104-1, 104-2, and 104-3, forming an insulating material over the pad layer, and recessing the pad layer and insulating material to form an isolation pad 110 and an isolation structure 112. According to some embodiments, the isolation structure 112 is configured to electrically isolate the active region of a semiconductor structure (e.g., fin structures 104-1, 104-2, and 104-3) and is also referred to as a shallow trench isolation (STI) component. In some embodiments, the isolation structure 112 is formed directly over the substrate 102 surrounding the fin structures 104-1, 104-2, and 104-3 without forming the isolation pad 110.

[0046] According to some embodiments, such as Figure 1D As shown, after forming the isolation structure 112, a capping layer 114 is formed over the top surface of the isolation structure 112. The capping layer 114 can be configured to protect the gate structure formed subsequently in subsequent manufacturing processes. In some embodiments, the capping layer 114 is made of a high-k dielectric material. In some embodiments, the capping layer 114 is made of a dielectric material with a k value greater than 7. In some embodiments, the capping layer 114 is made of HfO2, ZrO2, or HfAlO2. x HfSiO x It is made of materials such as Al2O3. In some embodiments, the thickness of the capping layer 114 is in the range of about 5 nm to about 15 nm.

[0047] According to some embodiments, after the capping layer 114 is formed, such as Figure 1E and Figure 1E-1 As shown, pseudo-gate structures 116-1, 116-2, 116-3, and 116-4 are formed across the fin structures 104-1, 104-2, and 104-3 and extend above the capping layer 114 in the second direction (i.e., the Y direction). More specifically, Figure 1E-1 A schematic top view of an intermediate stage of a semiconductor structure 100 according to some embodiments is illustrated, and Figure 1E The structure shown corresponds to Figure 1E-1 The area shown in box B1.

[0048] Pseudo-gate structures 116-1, 116-2, 116-3, and 116-4 can be used to define the source / drain region and channel region of the resulting semiconductor structure 100. In some embodiments, pseudo-gate structures 116-1, 116-2, 116-3, and 116-4 include a pseudo-gate dielectric layer 118 and a pseudo-gate electrode layer 120. In some embodiments, the pseudo-gate dielectric layer 118 is made of one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), HfO2, HfZrO, HfSiO, HfTiO, HfAlO, or combinations thereof. In some embodiments, the pseudo-gate dielectric layer 118 is formed using thermal oxidation, CVD, ALD, physical vapor deposition (PVD), other suitable methods, or combinations thereof.

[0049] In some embodiments, the dummy gate electrode layer 120 is made of a conductive material, including polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), or combinations thereof. In some embodiments, the dummy gate electrode layer 120 is formed using CVD, PVD, or combinations thereof.

[0050] The formation of dummy gate structures 116-1, 116-2, 116-3, and 116-4 may include conformally forming a dielectric material as a dummy gate dielectric layer 118. Subsequently, a conductive material may be formed over the dielectric material as a dummy gate electrode layer 120, and a hard mask layer 122 may be formed over the conductive material. Next, the dielectric and conductive materials can be patterned using the hard mask layer 122 to form the dummy gate structures 116-1, 116-2, 116-3, and 116-4. In some embodiments, the hard mask layer 122 comprises multiple layers, such as an oxide layer 124 and a nitride layer 126. In some embodiments, the oxide layer 124 is silicon oxide, and the nitride layer 126 is silicon nitride.

[0051] According to some embodiments, such as Figure 1F As shown, after forming the dummy gate structures 116-1, 116-2, 116-3, and 116-4, a gate spacer 128 is formed along and covers the opposing sidewalls of the dummy gate structures 116-1, 116-2, 116-3, and 116-4. The gate spacer 128 can be configured to separate the source / drain structure (formed subsequently) from the dummy gate structures 116-1, 116-2, 116-3, and 116-4. In some embodiments, the gate spacer 128 is made of a dielectric material such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and / or combinations thereof.

[0052] According to some embodiments, such as Figure 1G As shown, after the gate spacer 128 is formed, a source / drain recess 130 is formed near the gate spacer 128. More specifically, the fin structures 104-1, 104-2, and 104-3 are not covered by the dummy gate structures 116-1, 116-2, 116-3, and 116-4, and the gate spacer 128 is recessed.

[0053] In some embodiments, the fin structures 104-1, 104-2, and 104-3 are recessed by performing an etching process. The etching process may be an anisotropic etching process, such as dry plasma etching, and the dummy gate structures 116-1, 116-2, 116-3, and 116-4, as well as the gate spacer 128, may be used as an etching mask during the etching process.

[0054] According to some embodiments, such as Figure 1H As shown, after the source / drain groove 130 is formed, the first semiconductor material layer 106 exposed by the source / drain groove 130 is laterally recessed to form a notch 132.

[0055] In some embodiments, an etching process is performed to laterally recess the first semiconductor material layer 106 of the fin structures 104-1, 104-2, and 104-3 from the source / drain groove 130. In some embodiments, during the etching process, the first semiconductor material layer 106 has a greater etch rate (e.g., etch amount) than the second semiconductor material layer 108, thereby forming a groove 132 between adjacent second semiconductor material layers 108. In some embodiments, the etching process is isotropic etching, such as dry chemical etching, remote plasma etching, wet chemical etching, other suitable techniques, and / or combinations thereof.

[0056] Next, according to some embodiments, such as Figure 1I As shown, an internal spacer 134 is formed in a recess 132 between the second semiconductor material layers 108. The internal spacer 134 can be configured to separate the source / drain structure from the gate structure formed in a subsequent manufacturing process. In some embodiments, the internal spacer 134 has curved sidewalls. In some embodiments, the internal spacer 134 is made of a dielectric material such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or combinations thereof.

[0057] According to some embodiments, such as Figure 1JAs shown, after the internal spacer 134 is formed, the capping layer 114 not covered by the dummy gate structures 116-1, 116-2, 116-3, and 116-4 and the gate spacer 128 is removed. In some embodiments, the etching process is isotropic etching, such as dry chemical etching, remote plasma etching, wet chemical etching, other suitable techniques, and / or combinations thereof.

[0058] After removing the exposed portion of the capping layer 114, sacrificial structures can be formed and embedded within the fin structures 104-1, 104-2, and 104-3, so that they can be replaced in subsequent manufacturing processes during the formation of the back-side conductive vias. More specifically, according to some embodiments, such as Figure 1K and Figure 1K-1 Deep grooves 136 are formed in some parts of fin structures 104-1, 104-2 and 104-3. Figure 1K-1 A schematic top view of an intermediate stage of a semiconductor structure 100 according to some embodiments is illustrated, and Figure 1K The structure shown corresponds to Figure 1K-1 The area shown in box B1.

[0059] The deep trench 136 can be formed by forming a mask layer with patterned openings and etching fin structures 104-1, 104-2, and 104-3 through the openings. In some embodiments, the fin structures 104-1, 104-2, and 104-3 are etched by performing isotropic etching, such as dry chemical etching, remote plasma etching, wet chemical etching, other suitable techniques, and / or combinations thereof. In some embodiments, the bottom surface of the deep trench 136 is lower than the bottom surface of the isolation structure 112.

[0060] Subsequently, according to some embodiments, such as Figure 1L As shown, a deep sacrificial structure 138 is formed in the deep trench 136. The deep sacrificial structure 138 is configured to be subsequently removed and replaced via a back-side conductive via. In some embodiments, the deep sacrificial structure 138 is made of an epitaxial material. In some embodiments, the deep sacrificial structure 138 is made of undoped SiGe. In some embodiments, the bottom surface of the deep sacrificial structure 138 is lower than the bottom surface of the isolation structure 112.

[0061] Next, according to some embodiments, such as Figure 1M and Figure 1M-1 As shown, a source / drain structure 140 is formed in the source / drain groove 130. Figure 1M-1 A schematic top view of an intermediate stage of a semiconductor structure 100 according to some embodiments is illustrated, and Figure 1M The structure shown corresponds to Figure 1M-1 The area shown in box B1.

[0062] In some embodiments, each of the source / drain structures 140 is formed above fin structures 104-1, 104-2, and 104-3 and extends continuously above fin structures 104-1, 104-2, and 104-3. That is, according to some embodiments, the source / drain structures 140 formed above fin structures 104-1, 104-2, and 104-3 are merged together to form a continuous source / drain structure 140. In some embodiments, the source / drain structures 140 are in direct contact with the deep sacrificial structure 138.

[0063] In some embodiments, the source / drain structure 140 is formed using an epitaxial growth process, such as MBE, MOCVD, VPE, other suitable epitaxial growth processes, or combinations thereof. In some embodiments, the source / drain structure 140 is made of any suitable material, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or combinations thereof. In some embodiments, the source / drain structure 140 is in-situ doped during the epitaxial growth process. For example, the source / drain structure 140 may be boron (B) doped epitaxially grown SiGe. For example, the source / drain structure 140 may be carbon-doped epitaxially grown Si to form a silicon:carbon (Si:C) source / drain device, phosphorus-doped epitaxially grown Si to form a silicon:phosphorus (Si:P) source / drain device, or carbon and phosphorus doped epitaxially grown Si to form a silicon-carbon phosphor (SiCP) source / drain device. In some embodiments, the source / drain structure 140 is doped in one or more implantation processes following the epitaxial growth process.

[0064] According to some embodiments, such as Figure 1N As shown, after forming the source / drain structure 140, a contact etch stop layer (CESL) 142 is conformally formed to cover the source / drain structure 140 and the pseudo-gate structures 116-1, 116-2, 116-3 and 116-4, and an interlayer dielectric (ILD) layer 144 is formed above the contact etch stop layer 142.

[0065] In some embodiments, the contact etch stop layer 142 is made of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, other suitable dielectric materials, or combinations thereof. The dielectric material of the contact etch stop layer 142 can be conformally deposited over the semiconductor structure by performing CVD, ALD, other application methods, or combinations thereof.

[0066] The interlayer dielectric layer 144 may comprise a multilayer made of various dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon phosphosilicate glass (PSG), borosilicate glass (BPSG), or other suitable low-k dielectric materials. The interlayer dielectric layer 144 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0067] According to some embodiments, such as Figure 10 As shown, after depositing the contact etch stop layer 142 and the interlayer dielectric layer 144, a planarization process such as CMP or etch-back process is performed until the gate electrode layer 120 of the pseudo gate structures 116-1, 116-2, 116-3 and 116-4 is exposed.

[0068] Subsequently, according to some embodiments, such as Figure 1P As shown, the first semiconductor material layer 106 of the dummy gate structures 116-1, 116-2, 116-3, and 116-4, and the fin structures 104-1, 104-2, and 104-3 is removed to form a gate trench 146. More specifically, according to some embodiments, the first semiconductor material layer 106 of the dummy gate structures 116-1, 116-2, 116-3, and 116-4, and the fin structures 104-1, 104-2, and 104-3 is removed to form nanostructures 108' (including) a second semiconductor material layer 108 having fin structures 104-1, 104-2, and 104, respectively. Figure 1Q-1 The nanostructures shown are 108-1', 108-2', and 108-3'.

[0069] The removal process may include one or more etching processes. For example, when the dummy gate electrode layer 120 is polysilicon, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the dummy gate electrode layer 120. Subsequently, plasma dry etching, dry chemical etching, and / or wet etching can be used to remove the dummy gate dielectric layer 118. The first semiconductor material layer 106 can be removed by performing a selective wet etching process, such as an APM (e.g., an ammonia-hydrogen peroxide-water mixture) etching process. For example, the wet etching process uses an etchant such as ammonium hydroxide (NH4OH), TMAH, ethylenediamine catechol (EDP), and / or potassium hydroxide (KOH) solution.

[0070] Next, according to some embodiments, such as Figure 1Q and Figure 1Q-1 As shown, a gate structure 148, including gate structures 148-1, 148-2, 148-3, and 148-4, is formed around the nanostructure 108'. More specifically, Figure 1Q-1 A schematic top view of an intermediate stage of a semiconductor structure 100 according to some embodiments is shown, and Figure 1Q The structure shown corresponds to Figure 1Q-1 The area shown in box B1.

[0071] According to some embodiments, the gate structure 148 surrounds the nanostructure 108' to form a full-ring gate transistor structure. In some embodiments, the gate structure 148 includes a conductive material (such as Ti, TiN, and / or W) having dopants (such as La, Zr, Hf, etc.).

[0072] In some embodiments, a trimming process is performed prior to forming the gate structure 148 such that the nanostructure 108' in the channel region enclosed by the gate structure 148 is narrower than the nanostructure below the gate spacer 128 and between the inner spacer 134.

[0073] In some embodiments, each of the gate structures 148 includes a gate dielectric layer 150 and a gate electrode layer 152. In some embodiments, although Figure 1Q Not shown, but an interface layer is formed prior to the formation of the gate dielectric layer 150. In some embodiments, the interface layer is an oxide layer formed around the nanostructure 108' and on the exposed portion of the base fin structure 105. In some embodiments, the interface layer is formed by performing a thermal process.

[0074] In some embodiments, the gate dielectric layer 150 is formed over the interface layer such that the nanostructure 108' is surrounded (e.g., wrapped) by the gate dielectric layer 150. Furthermore, according to some embodiments, the gate dielectric layer 150 also covers the gate spacer 128, the inner spacer 134, and the sidewalls of the nanostructure 108'. In some embodiments, the gate dielectric layer 150 is made of one or more layers of dielectric material, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, or combinations thereof. In some embodiments, the gate dielectric layer 150 is formed using CVD, ALD, other suitable methods, or combinations thereof.

[0075] In some embodiments, the gate electrode layer 152 is formed on the gate dielectric layer 150. In some embodiments, the gate electrode layer 152 is made of one or more layers of conductive material, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, or combinations thereof. In some embodiments, the gate electrode layer 152 is formed using CVD, ALD, electroplating, other applicable methods, or combinations thereof. Other conductive layers (such as work function metal layers) may also be formed in the gate structure 148, although they are not shown in the figures. After the gate dielectric layer 150 and the gate electrode layer 152 are formed, a planarization process such as CMP or an etch-back process may be performed until the protective layer 164 is exposed.

[0076] According to some embodiments, such as Figure 1R As shown, after forming the gate structure 148, an etch-back process is performed to form a groove over the gate structure 148, and a metal capping layer 154 and a mask structure 156 are formed in the groove. In some embodiments, an etching process is performed to form the groove. In some embodiments, the etching process is isotropic etching, such as dry chemical etching, remote plasma etching, wet chemical etching, other suitable techniques, and / or combinations thereof. In some embodiments, the gate spacer 128 is partially removed in the etching process, such that the groove has a T-shape in cross-sectional view.

[0077] According to some embodiments, after the groove is formed, a metal capping layer 154 is formed over the top surface of the gate structure 148. In some embodiments, the metal capping layer 154 is made of a metal, such as W, Re, Ir, Co, Ni, Ru, Mo, Al, Ti, Ag, Al, other suitable metals, or multiples thereof. In some embodiments, the metal capping layer 154 and the metal gate electrode layer 152 are made of different materials. In some embodiments, the metal capping layer 154 covers both the gate dielectric layer 150 and the gate electrode layer 152 and contacts the sidewall of the gate spacer 128. In some embodiments, the top surface of the metal capping layer 154 is lower than the top of the gate spacer 128.

[0078] According to some embodiments, such as Figure 1RAs shown, after the metal capping layer 154 is formed, a mask structure 156 is formed in a recess above the metal capping layer 154 and above the gate spacer 128. In some embodiments, the mask structure is a two-layer structure including a pad layer 158 and a body layer 160 above the pad layer 158. The mask structure 156 is configured to protect the gate spacer 128 and the gate structure 148 during a subsequent etching process for forming contact plugs. In some embodiments, the mask structure 156 has a narrower bottom portion and a wider top portion. In some embodiments, the mask structure 156 has a T-shape in cross-sectional view. In some embodiments, the mask structure 156 is in direct contact with the contact etch stop layer 142.

[0079] In some embodiments, the pad layer 158 is made of a dielectric material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), oxygen-doped silicon carbonitride (Si(O)CN), silicon oxide (SiO2), or combinations thereof. In some embodiments, the dielectric material used to form the pad layer 158 is conformally deposited using methods such as ALD, CVD (such as LPCVD, PECVD, HDP-CVD, or HARP).

[0080] In some embodiments, the body layer 160 is made of a dielectric material such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), oxygen-doped silicon carbonitride (Si(O)CN), or combinations thereof. In some embodiments, the dielectric material for the body layer 160 is formed over the pad layer 158 using methods such as CVD (e.g., FCVD, LPCVD, PECVD, HDP-CVD, or HARP), ALD, etc., to overfill the groove. In some embodiments, the body layer 160 and the pad layer 158 are made of different materials. In some embodiments, the body layer 160 is made of an oxide (such as silicon oxide), and the pad layer 158 is made of a nitrogen-containing dielectric (such as silicon nitride or silicon oxynitride). Subsequently, according to some embodiments, such as... Figure 1R As shown, a planarization process is performed on the body layer 160 and the pad layer 158 until the interlayer dielectric layer 144 is exposed. Planarization can be CMP, etch-back process, or a combination thereof.

[0081] According to some embodiments, such as Figure 1S and Figure 1S-1 As shown, after the mask structure 156 is formed, source / drain contacts 162 are formed through the interlayer dielectric layer 144 and the contact etch stop layer 142 above the source / drain structure 140. More specifically, Figure 1S-1 A schematic top view of an intermediate stage of a semiconductor structure 100 according to some embodiments is illustrated, and Figure 1SThe structure shown corresponds to Figure 1S-1 The area shown in box B1.

[0082] In some embodiments, some of the source / drain contacts 162 overlap with more than one of the fin structures 104-1, 104-2, and 104-3. The formation of the source / drain contacts 162 may include patterning an interlayer dielectric layer 144 and a contact etch stop layer 142 to form contact openings that partially expose the source / drain structure 140, forming a silicide layer (not shown), and forming a conductive material over the silicide layer. The patterning process may include forming a patterned mask layer over the interlayer dielectric layer 144 using a photolithography process, followed by an anisotropic etching process. The silicide layer may be formed by forming a metal layer over the top surface of the source / drain structure 140 and annealing the metal layer to react with the source / drain structure 140. Unreacted metal layers may be removed after the silicide layer is formed. The silicide layer may be made of WSi, NiSi, TiSi, TaSi, PtSi, WSi, CoSi, etc.

[0083] After the silicide layer is formed, a conductive material can be formed in the contact openings to form source / drain contacts 162. The conductive material may include aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt, tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), copper silicide, tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminum nitride (TiAl), titanium aluminum nitride (TiAlN), other suitable conductive materials, or combinations thereof. In some embodiments, the conductive material used to form the source / drain contacts 162 is different from the conductive material used to form the gate structure. The conductive material can be formed using processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other used process.

[0084] A pad and / or barrier layer (not shown) may be formed prior to the conductive material forming the source / drain contact 162. The pad may be made of silicon nitride, but any other suitable dielectric may be used as an alternative. The barrier layer may be made of tantalum nitride, but other materials such as tantalum, titanium, titanium nitride, etc., may be used.

[0085] According to some embodiments, such as Figure 1TAs shown, after the source / drain contacts 162 are formed, a front-end structure 164 is formed over the mask structure 156, the interlayer dielectric layer 144, and the source / drain contacts 162, and a carrier substrate 166 is formed over the front-end structure 164. In some embodiments, the front-end structure 164 includes an etch stop layer and various components (not shown) formed thereon, such as multilayer interconnect structures (e.g., contacts to the gate, vias, lines, intermetallic dielectric layers, passivation layers, etc.). After the front-end structure 164 is formed, the carrier substrate 166 is attached to the front-end structure 164 to support the semiconductor structure in subsequent manufacturing processes.

[0086] Figure 1T-2 , Figure 1U-1 , Figure 1V-1 , Figure 1W-1 , Figure 1X-2 , Figure 1Y-1 , Figure 1Z-1 and Figure 1ZA-1 , Figure 1ZB-2 , Figure 1ZC-2 , Figure 1ZD-1 , Figure 1 ZE-1 , Figure 1 ZF-2 The diagram illustrates a view along line A-A' according to some embodiments (e.g., along the source / drain structure and above the source / drain structure and in a direction parallel to the extension direction of the gate structure). Figure 1T , Figure 1U , Figure 1V , Figure 1W , Figure 1X , Figure 1Y , Figure 1Z and Figure 1ZA , Figure 1ZB , Figure 1ZC , Figure 1ZD , Figure 1ZE , Figure 1ZF A cross-sectional view of the intermediate stage of manufacturing semiconductor structure 100. Figure 1T-3 , Figure 1 U-2 , Figure 1V-2 , Figure 1W-2 , Figure 1X-3 , Figure 1Y-2 , Figure 1Z-2 and Figure 1ZA-2 , Figure 1 ZB-3 , Figure 1 ZC-3 , Figure 1 ZD-2 , Figure 1 ZE-2 , Figure 1 ZF-3 The diagram illustrates a view along line B-B' (e.g., along the source / drain structure and above the source / drain structure, and in a direction parallel to the extension direction of the nanostructure) according to some embodiments. Figure 1T , Figure 1U , Figure 1V , Figure 1W , Figure 1X , Figure 1Y , Figure 1Z and Figure 1ZA , Figure 1ZB , Figure 1ZC , Figure 1ZD , Figure 1ZE , Figure 1ZF A cross-sectional view of the intermediate stage of manufacturing semiconductor structure 100. Figure 1T-1 A schematic top view of an intermediate stage of a semiconductor structure 100 according to some embodiments is illustrated, and Figure 1T The structure shown corresponds to Figure 1T-1 The area shown in box B2.

[0087] According to some embodiments, such as Figure 1T , Figure 1T-2 and Figure 1T-3 As shown, after attaching the carrier substrate 166 to the front-end structure 164, the substrate 102 is inverted, and the back side of the substrate 102 is planarized. More specifically, according to some embodiments, such as Figure 1T , Figure 1T-2 and Figure 1T-3 As shown, planarization is performed on substrate 102 until the isolation structure 112 and the deep sacrificial structure 138 are exposed. The planarization process can be an etching process, a CMP process, a mechanical polishing process, a dry polishing process, or a combination thereof.

[0088] It's understandable, although in order to better understand the manufacturing process... Figure 1T , Figure 1U , Figure 1V , Figure 1W , Figure 1X , Figure 1Y , Figure 1Z , Figure 1ZA , Figure 1ZB , Figure 1ZC , Figure 1ZD , Figure 1ZE , Figure 1T-2 , Figure 1U-1 , Figure 1V-1 , Figure 1W-1 , Figure 1X-2 , Figure 1Y-1 , Figure 1Z-1 , Figure 1ZA-1 , Figure 1ZB-2 , Figure 1ZC-2 , Figure 1ZD-1 , Figure 1 ZE-1 , Figure 1 ZF-2 and Figure 1T-3 , Figure 1 U-2 , Figure 1V-2 , Figure 1W-2 , Figure 1X-3 , Figure 1Y-2 , Figure 1Z-2 , Figure 1ZA-2 , Figure 1 ZB-3 , Figure 1 ZC-3 , Figure 1 ZD-2 , Figure 1 ZE-2 , Figure 1 ZF-3 The display is upside down, but for clarity, the spatial position of the elements (e.g., top part, bottom part, topmost, bottommost, etc.) is based on... Figures 1A to 1S The original locations shown are used to describe them, so they can be consistent with those previously described. For example, because... Figure 1T The structure shown is inverted, so the top surface of the source / drain structure 140 refers to the surface that contacts the source / drain contact 162, and the bottom surface of the source / drain structure 140 refers to the surface that contacts the base fin structure 105.

[0089] After removing the substrate 102, the source / drain structure 140 is cut into individual portions from the back side of the structure via a back-side source / drain isolation component. More specifically, according to some embodiments, such as Figure 1U , Figure 1U-1 and Figure 1 U-2 As shown, the base fin structure 105 and deep sacrificial structure 138 of fin structures 104-1, 104-2, and 104-3 are etched to form grooves, and a mask structure 168 is formed in the grooves. In some embodiments, the mask structure 168 is made of a different dielectric material than that used to form the isolation structure 112. In some embodiments, the mask structure 168 is made of SiN, SiCN, SiOC, SiOCN, HfO2, ZrO2, or HfAlO. x HfSiO x It is made of materials such as Al2O3. In some embodiments, the mask structure 168 is made of nitride and the isolation structure is made of oxide.

[0090] After the mask structure 168 is formed, according to some embodiments, such as Figure 1V , Figure 1V-1 and Figure 1V-2 As shown, the isolation structure 112 is removed to form the opening 170. In some embodiments, the isolation structure 112 is removed by performing isotropic etching, such as dry chemical etching, remote plasma etching, wet chemical etching, other suitable techniques, and / or combinations thereof. During the etching process, the base fin structure 105 and the deep sacrificial structure 138 are protected by the mask structure 168 and the isolation pad 110. Furthermore, according to some embodiments, such as... Figure 1V-1 As shown, the source / drain structure 140 is partially exposed by the opening 170.

[0091] Subsequently, according to some embodiments, such as Figure 1W , Figure 1W-1 and Figure 1W-2As shown, the source / drain structure 140 exposed by the opening 170 is etched to form a deep opening 172. More specifically, according to some embodiments, the deep opening 172 is formed through the source / drain structure 140 to form separate source / drain structures 140', which include separate source / drain structures 140-1', 140-2', and 140-3'. In some embodiments, source / drain structure 140-1' is attached to nanostructure 108-1' of fin structure 104-1, source / drain structure 140-2' is attached to nanostructure 108-2' of fin structure 104-2, and source / drain structure 140-3' is attached to nanostructure 108-3' of fin structure 104-3. In some embodiments, the sidewalls of the source / drain structures 140-1', 140-2', and 140-3' are substantially aligned with the sidewalls of the isolation liner 110.

[0092] In some embodiments, the source / drain contact 162 is partially exposed by a deep opening 172. In some embodiments, the contact etch stop layer 142 is exposed by the deep opening 172. Meanwhile, the gate structure 148 is protected by the capping layer 114 and the gate spacer 128, and therefore the gate structure 148 is not significantly damaged during the etching process. In some embodiments, the capping layer 114 is completely removed during the etching process. In some embodiments, a portion of the gate dielectric layer 150 exposed by the opening 170 is also removed during the etching process. In some embodiments, the etching process is isotropic etching, such as dry chemical etching, remote plasma etching, wet chemical etching, other suitable techniques, and / or combinations thereof.

[0093] Next, according to some embodiments, such as Figure 1X , Figure 1X-1 , Figure 1X-2 and Figure 1X-3 As shown, a back-side source / drain isolation component 174 is formed in the opening 170 and the deep opening 172. Figure 1X-1 A schematic top view of an intermediate stage of a semiconductor structure 100 according to some embodiments is illustrated, and Figure 1X The structure shown corresponds to Figure 1X-1 The area shown in box B2.

[0094] In some embodiments, each of the back-side source / drain isolation components 174 includes a pad layer 176 and an isolation material 178 formed over the pad layer 176. The pad layer 176 is configured in subsequent manufacturing processes to protect the source / drain structures 140-1', 140-2', and 140-3'. In some embodiments, such as Figure 1X-2As shown, the pad layer 176 covers the sidewalls of the isolation pad 110 and the sidewalls of the exposed source / drain structures 140-1', 140-2', and 140-3'. Furthermore, according to some embodiments, the pad layer 176 also covers and directly contacts the exposed surfaces of the source / drain contacts 162 and the contact etch stop layer 142. In some embodiments, the pad layer 176 is made of a nitride (e.g., SiN). In some embodiments, the pad layer 176 and the isolation pad 110 are made of the same material.

[0095] According to some embodiments, such as Figure 1X As shown, after the padding layer 176 is formed, an insulating material 178 is formed over the padding layer 176, and openings 170 and 172 are completely filled by the insulating material 178. In some embodiments, the insulating material 178 and the padding layer 176 are made of different dielectric materials. In some embodiments, the insulating material 178 is silicon oxide, silicon nitride, silicon oxynitride (SiON), other suitable insulating materials, or combinations thereof. The padding layer 176 and the insulating material 178 can be formed by performing chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. After the padding layer 176 and the insulating material 178 are formed, according to some embodiments, such as Figure 1X As shown, a polishing process (e.g., CMP) can be performed until the deep sacrificial structure 138 is exposed.

[0096] According to some embodiments, a back-side source / drain isolation member 174 is formed through the source / drain structure 140 to separate the source / drain structure 140 into source / drain structures 140-1', 140-2', and 140-3'. In some embodiments, the back-side source / drain isolation member 174 is formed along a first direction parallel to the extension direction of the nanostructure 108'. Therefore, although the source / drain structures 140 initially formed above the fin structures 104-1, 104-2, and 104-3 are merged together, they can be separated into individual parts by the subsequently formed back-side source / drain isolation member 174. That is, the distance between the fin structures 104-1, 104-2, and 104-3 can be relatively small without concern about the merging of the source / drain structures 140-1', 140-2', and 140-3'. In some embodiments, the source / drain contact 162 covers two source / drain structures 140' (e.g., source / drain structures 140-2' and 140-3') and a back-side source / drain isolation component 174.

[0097] After forming the back-side source / drain isolation component 174 to cut the source / drain structure 140 from the back side, the base fin structure 105 can be replaced with a dielectric layer. More specifically, according to some embodiments, such as Figure 1Y , Figure 1Y-1and Figure 1Y-2 As shown, the top of the deep sacrificial structure 138 is removed to form a recess, and a via mask structure 180 is formed in the recess above the deep sacrificial structure 138. The via mask structure 180 is configured to protect the deep sacrificial structure 138 during a subsequent etching process. In some embodiments, the via mask structure 180 is made of a dielectric material that has etch selectivity for the base fin structure 105. In some embodiments, the via mask structure 180 is made of SiO2, SiN, SiCN, SiOC, SiOCN, HfO2, ZrO2, or HfAlO2. x HfSiO x It is made from Al2O3 and other substances.

[0098] Next, according to some embodiments, such as Figure 1Z , Figure 1Z-1 and Figure 1Z-2 As shown, the base fin structure 105 is removed to form a trench, and a back-side dielectric layer 182 is formed in the trench. In some embodiments, the base fin structure 105 is removed by performing an etching process. In some embodiments, the etching process is isotropic etching, such as dry chemical etching, remote plasma etching, wet chemical etching, other suitable techniques, and / or combinations thereof. After the base fin structure 105 is removed, the gate structure 148, the internal spacer 134, and the source / drain structure 140' may be exposed by the trench. In some embodiments, the source / drain structure 140' is also etched during the etching process, such that the bottom of the source / drain structure 140' is removed.

[0099] According to some embodiments, such as Figure 1Z , Figure 1Z-1 and Figure 1Z-2 As shown, after removing the base fin structure 105, a back-side dielectric layer 182 is formed in the trench, and a polishing process (e.g., CMP) is performed until the deep sacrificial structure 138 is exposed. In some embodiments, the via mask structure 180 is removed during the polishing process. Figure 1Z , Figure 1Z-1 and Figure 1Z-2 As shown, according to some embodiments, the base fin structure 105 is replaced by a back-side dielectric layer 182. Replacing the base fin structure 105 can reduce leakage in the resulting device, thereby improving device performance (e.g., off-state current). In some embodiments, the back-side dielectric layer 182 is in direct contact with the gate structure 148, the internal spacer 134, the nanostructure 108', and the source / drain structure 140'.

[0100] In some embodiments, the bottom surface 140'BS of the source / drain structure 140' (i.e., the top surface of the back dielectric layer 182) is higher than the bottom surface 108'BS of the bottom nanostructure 108', as in some embodiments. Figure 1Z-2As shown. In some embodiments, the bottom surface 140'BS of the source / drain structure 140' (i.e., the top surface of the back-side dielectric layer 182) is substantially flush with the bottom surface 108'CS of the bottommost nanostructure 108' in the channel region. Furthermore, according to some embodiments, the bottom surface 140'BS of the source / drain structure 140' (i.e., the top surface of the back-side dielectric layer 182) is also higher than the bottom surfaces of the bottommost internal spacer 134 and the gate structure 148.

[0101] In some embodiments, the back-side dielectric layer 182 is made of a dielectric material such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide, other suitable insulating materials, multilayers thereof, and / or combinations thereof. In some embodiments, the back-side dielectric layer 182 is made of a different dielectric material than that used to form the via mask structure 180 and the back-side source / drain isolation component 174. For example, the via mask structure 180 and the back-side source / drain isolation component 174 are made of oxides (such as silicon oxide), and the back-side dielectric layer 182 is made of a nitrogen-containing dielectric (such as silicon nitride or silicon oxynitride). In some embodiments, the formation of the back-side dielectric layer 182 includes depositing dielectric material to overfill trenches and subsequently planarizing portions of the dielectric material. The deposition process may be CVD (such as FCVD, LPCVD, PECVD, HDP-CVD, or HARP), ALD, other suitable technologies, and / or combinations thereof.

[0102] According to some embodiments, such as Figure 1ZA , Figure 1ZA-1 and Figure 1ZA-2 As shown, after replacing the base fin structure 105 with the back-side dielectric layer 182, the deep sacrificial structure 138 is removed to form the back-side conductive via opening 184 exposing the source / drain structure 140'. In some embodiments, the deep sacrificial structure 138 is removed by performing an etching process. In some embodiments, the etching process is isotropic etching, such as dry chemical etching, remote plasma etching, wet chemical etching, other applicable techniques and / or combinations thereof.

[0103] In some embodiments, the source / drain structure 140' is also partially removed during the etching process. In some embodiments, the back-side conductive via opening 184 is narrower than the source / drain structure 140', so the source / drain structure 140' has a recessed portion below the back-side conductive via opening 184 and a higher portion around the back-side conductive via opening 184. In some embodiments, the bottom surface 140'RS of the recessed portion of the source / drain structure 140' overlapping with the back-side conductive via opening 184 is lower than the bottom surface 140'BS of the source / drain structure 140 overlapping with the back-side dielectric layer 182. In some embodiments, the bottom surface 140'RS of the recessed portion of the source / drain structure 140' overlapping with the back-side conductive via opening 184 is lower than the bottom surface 108'BS of the bottommost nanostructure 108'. In some embodiments, the bottom surface 140'RS of the recessed portion of the source / drain structure 140' that overlaps with the back-side conductive via opening 184 is lower than the bottom inner spacer 134.

[0104] Next, according to some embodiments, such as Figure 1ZB , Figure 1ZB-1 , Figure 1ZB-2 and Figure 1 ZB-3 As shown, a back-side conductive via 186 is formed in the back-side conductive via opening 184. Figure 1ZB-1 A schematic top view of an intermediate stage of a semiconductor structure 100 according to some embodiments is illustrated, and Figure 1ZB The structure shown corresponds to Figure 1ZB-1 The area shown in box B2.

[0105] In some embodiments, the back-side conductive via 186 includes a pad 188 formed on the sidewall of the back-side conductive via opening 184 and a conductive layer 190 that completely fills the back-side conductive via opening 184. In some embodiments, the conductive layer 190 is surrounded by the pad 188 and contacts the source / drain structure 140'.

[0106] In some embodiments, the pad 188 is made of Ti, Ta, TiN, TaN, etc. In some embodiments, the conductive layer 190 is made of Ru, W, Co, Al, Mo, or a material containing the aforementioned metals. The pad 188 and the conductive layer 190 can be formed by performing chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0107] According to some embodiments, such as Figure 1ZC , Figure 1ZC-1 , Figure 1ZC-2 and Figure 1 ZC-3As shown, after forming the back-side conductive via 186, a patterning process is performed to form a back-side gate isolation component. More specifically, a patterned mask structure 192 with an opening 194 is formed to cover the back side of the structure. Figure 1ZC-1 A schematic top view of an intermediate stage of a semiconductor structure 100 according to some embodiments is shown, and Figure 1ZC The structure shown corresponds to Figure 1ZC-1 The area shown in box B3.

[0108] In some embodiments, the patterned mask structure 192 includes a first mask layer 196 and a second mask layer 198, both of which have openings 194. In some embodiments, the openings 194 are vertically overlapped with the gate structure (e.g., Figure 1ZC-1 Some portions of the gate structures 148-1, 148-2, and 148-4 shown. In some embodiments, opening 194 partially exposes the back-side source / drain isolation member 174 and the back-side dielectric layer 182. In some embodiments, opening 194 also partially exposes the back-side conductive via 186. In some embodiments, opening 194 exposes more than one back-side conductive via 186. In some embodiments, one of openings 194 exposes one back-side conductive via 186, and one of openings 194 exposes two back-side conductive vias 186.

[0109] In some embodiments, the first mask layer 196 is made of titanium nitride (TiN), carbon-doped silicon dioxide (e.g., SiO2:C), titanium oxide (TiO), boron nitride (BN), other suitable materials, and / or combinations thereof. In some embodiments, the second mask layer 198 is made of silicon nitride (SiN), silicon oxynitride (SiON), and / or combinations thereof. The materials of the first mask layer 196 and the second mask layer 198 may be sequentially deposited over the back-side source / drain isolation member 174 and the back-side dielectric layer 182. Photoresist may be formed over the second mask layer 198, for example, by spin-coating, and the photoresist may be patterned by exposing it to light using a suitable photomask. Depending on whether a positive or negative photoresist is used, the exposed (or unexposed) portions of the photoresist may be removed. The photoresist may be used to etch the materials used to form the first mask layer 196 and the second mask layer 198 to form the opening 194.

[0110] According to some embodiments, such as Figure 1ZD , Figure 1ZD-1 and Figure 1 ZD-2As shown, after the patterned mask structure 192 is formed, a first etching process is performed to remove the isolation material 178 of the back-side source / drain isolation component 174 exposed by the opening 194 to form the trench 200. In some embodiments, the first etching process is isotropic etching, such as dry chemical etching, remote plasma etching, wet chemical etching, other applicable techniques, and / or combinations thereof. During the first etching process, the isolation material 178 of the back-side source / drain isolation component 174 exhibits good etch selectivity for retaining unetched or slightly etched material for forming the pad layer 176, the back-side dielectric layer 182, and the back-side conductive via 186. That is, according to some embodiments, the source / drain structure 140' is protected by the pad layer 176 during the first etching process.

[0111] Subsequently, according to some embodiments, such as Figure 1ZE , Figure 1 ZE-1 and Figure 1 ZE-2 As shown, a second etching process is performed through the opening 194 and trench 200 of the patterned mask structure 192. More specifically, portions of the gate structures 148-1, 148-2, and 148-4 that vertically overlap with the trench 200 are etched to form a trench 202 through the gate structures 148-1, 148-2, and 148-4. In some embodiments, the trench 202 is formed to separate the gate structures 148-1, 148-2, and 148-4 into various individual portions. Furthermore, according to some embodiments, the metal capping layer 154 and the mask structure 156, including the pad layer 158 and the body layer 160, that vertically overlap with the trench 200 are also partially etched during the second etching process to ensure that the trench 202 completely cuts through the gate structures 148-1, 148-2, and 148-4. That is, according to some embodiments, the trench 202 passes through the gate structures 148-1, 148-2 and 148-4 and extends into the mask structure 156.

[0112] Furthermore, according to some embodiments, the corners of the back-side dielectric layer 182, the isolation pad 110, the pad layer 176, and the pad 188, as well as the conductive layer 190 of the back-side conductive via 186 exposed by the opening 194, are also partially etched to form a groove 204 during the second etching process. In some embodiments, the source / drain contact 162 is also partially etched during the second etching process. In some embodiments, after performing the second etching process, the back-side conductive via 186 overlapping the opening 194 and the source / drain contact 162 have rounded corners. In some embodiments, the second mask layer 198 of the patterned mask structure 192 is also etched (i.e., thinned) during the second etching process.

[0113] Next, according to some embodiments, such as Figure 1ZF , Figure 1 ZF-1 , Figure 1 ZF-2 , Figure 1 ZF-3 and Figure 1 ZF-4 As shown, dielectric material is formed in opening 194, trench 200, trench 202 and recess 204, and a planarization process is performed to form back-side gate isolation component 206. Figure 1 ZF-1 A schematic top view of a semiconductor structure 100 according to some embodiments is illustrated, and Figure 1ZF The structure shown corresponds to Figure 1 ZF-1 The area shown in box B3. Figure 1 ZF-4 The illustration shows the path along according to some embodiments. Figure 1ZF The line C-C' shows a cross-sectional view of the semiconductor structure 100.

[0114] According to some embodiments, the back-side gate isolation component 206 is configured to separate the gate structures 148-1, 148-2, and 148-4 into multiple electrically isolated portions. In some embodiments, the dielectric material used to form the back-side gate isolation component 206 has a dielectric constant of less than about 7. In some embodiments, the dielectric material used to form the back-side gate isolation component 206 is a dielectric material such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), oxygen-doped silicon carbonitride (Si(O)CN), silicon oxide (SiO2), or combinations thereof.

[0115] In some embodiments, dielectric material for forming the back-side gate isolation member 206 is deposited to overfill the opening 194, trench 200, trench 202, and recess 204, and according to some embodiments, a planarization process is performed to remove portions of the dielectric material until the back-side conductive via 186 is exposed. In some embodiments, the first mask layer 196 and the second mask layer 198 are also removed. The planarization process can be a CMP or an etch-back process. According to some embodiments, after the planarization process is performed, the bottom surfaces of the back-side gate isolation member 206, the back-side dielectric layer 182, the back-side conductive via 186, and the back-side source / drain isolation member 174 are substantially flush with each other.

[0116] As previously described, during the manufacturing process on the front side of the structure, the source / drain structures 140 attached to nanostructures 108-1', 108-2', and 108-3' are merged into a single continuous source / drain structure 140, and during the subsequent manufacturing process on the back side of the structure, the continuous source / drain structure 140 is divided into separate source / drain structures 140' by a back-side source / drain isolation component 174. More specifically, according to some embodiments, source / drain structure 140-1' is attached to nanostructure 108-1', source / drain structure 140-2' is attached to nanostructure 108-2', source / drain structure 140-3' is attached to nanostructure 108-3', and source / drain structures 104-1', 140-2', and 140-3' are separated from each other.

[0117] Furthermore, according to some embodiments, since the source / drain structure 140 is patterned to form separate source / drain structures 140-1', 140-2', and 140-3', the source / drain structures 140-1', 140-2', and 140-3' have substantially straight sidewalls, such as... Figure 1 ZF-2 As shown.

[0118] Furthermore, according to some embodiments, a back-side conductive via 186 is formed from the back side of the structure and connected to the source / drain structure 140' (e.g. Figure 1 ZF-2 (The source / drain structures 140-1' and 140-3' are shown). In some embodiments, the back-side conductive via 186 has a thickness ranging from about 10 nm to about 30 nm.

[0119] Furthermore, according to some embodiments, such as Figure 1ZF As shown, some of the gate structures (e.g., gate structures 148-1, 148-2, and 148-4) are divided into separate portions from the back side of the structure by a back-side gate isolation member 206. In some embodiments, the back-side gate isolation member 206 has a wider portion 206W in the back-side dielectric layer 182 and a narrower portion 206N in the gate structure 148-4, as shown. Figure 1ZF As shown. In some embodiments, the distance between the wider portion 206W and the gate structure (e.g., gate structure 148-4) is greater than about 0.5 nm. In some embodiments, the back-side gate isolation member 206 has an extension 206E extending into the mask structure 156. In some embodiments, the extension 206E has a thickness of less than about 200 nm.

[0120] In some embodiments, the back-side gate isolation member 206 contacts the back-side source / drain isolation member 174, the gate structure 148, and the back-side conductive via 186. In some embodiments, the back-side gate isolation member 206 vertically overlaps the source / drain contact 162. In some embodiments, the source / drain contact 162 below the back-side gate isolation member 206 has a curved top surface, as described in some embodiments. Figure 1 ZF-4 As shown.

[0121] Figure 2 The illustration shows a cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure 100 according to some other embodiments. The materials and processes used to fabricate the semiconductor structure 100 can be... Figures 1A to 1ZF The materials and processes shown are similar or identical, except that no formation is formed. Figure 1D In addition to the cover layer 114 shown, as in some embodiments Figure 2 As shown.

[0122] More specifically, according to some embodiments, the following is performed: Figures 1A to 1C The process shown involves forming an isolation structure 112 around fin structures 104-1, 104-2, and 104-3, and then forming pseudo-gate structures 116-1, 116-2, 116-3, and 116-4 across fin structures 104-1, 104-2, and 104-3 and directly covering the isolation structure 112, as shown. Figure 2 As shown. Then, according to some embodiments, the following is executed. Figures 1E to 1ZF The process shown is used to form a semiconductor structure 100, which is related to Figure 1ZF , Figure 1 ZF-1 , Figure 1 ZF-2 and Figure 1 ZF-3 The semiconductor structure 100 shown is similar or the same, and will not be described again here.

[0123] Figure 3 The illustration shows a cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure 100 according to some other embodiments. The materials and processes used to fabricate the semiconductor structure 100 may be the same as those previously described. Figures 1A to 1ZF The materials and processes shown are similar or identical, except for their deep sacrificial structure ratio. Figure 1L The deep sacrificial structure shown is thicker than (e.g., measured along the Z direction perpendicular to the X and Y directions).

[0124] More specifically, according to some embodiments, such as Figure 3 As shown, execute Figures 1A to 1KThe process is shown, and then a deep sacrificial structure 138' is formed in a deep trench. The process material used to form the deep sacrificial structure 138' is the same as the process material previously described for forming the deep sacrificial structure 138, except that the deep sacrificial structure 138' is thicker than the deep sacrificial structure 138. In some embodiments, the top surface of the deep sacrificial structure 138' is higher than the top surface of the isolation structure 112, and the bottom surface of the deep sacrificial structure 138' is lower than the bottom surface of the isolation structure 112. According to some embodiments, after forming the deep sacrificial structure 138', the following is performed: Figures 1M to 1ZF The process shown is used to form a semiconductor structure 100, which is related to Figure 1ZF , Figure 1 ZF-1 , Figure 1 ZF-2 and Figure 1 ZF-3 The semiconductor structure 100 shown is similar or the same, and will not be described again here.

[0125] Figure 4 The illustration shows a cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure 100 according to some other embodiments. The materials and processes used to fabricate the semiconductor structure 100 may be the same as those previously described. Figures 1A to 1ZF The materials and processes shown are similar or identical, except for their deep sacrificial structure ratio. Figure 1L The deep sacrificial structure shown is thicker than (e.g., measured along the Z direction perpendicular to the X and Y directions).

[0126] More specifically, according to some embodiments, the following is performed: Figures 1A to 1K The process shown involves forming a deep sacrificial structure 138” in a deep trench. Figure 4 As shown. The process material used to form the deep sacrificial structure 138” is the same as the process material previously described for forming the deep sacrificial structure 138, except that the deep sacrificial structure 138” is thicker than the deep sacrificial structure 138. In some embodiments, the top surface of the deep sacrificial structure 138” is substantially flush with the top surface of the isolation structure 112, and then the bottom surface of the deep sacrificial structure 138” is lower than the bottom surface of the isolation structure 112. According to some embodiments, after forming the deep sacrificial structure 138”, the following steps are performed: Figures 1M to 1ZF The process shown is used to form a semiconductor structure 100, which is related to Figure 1ZF , Figure 1 ZF-1 , Figure 1 ZF-2 and Figure 1 ZF-3 The semiconductor structure 100 shown is similar or the same, and will not be described again here.

[0127] Figure 5 The illustration shows a cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure 100 according to some other embodiments. The materials and processes used to fabricate the semiconductor structure 100 may be the same as those previously described. Figures 1A to 1ZF The materials and processes shown are similar or identical, except for their deep sacrificial structure ratio. Figure 1LThe deep sacrificial structure shown is thin (e.g., measured along the Z direction perpendicular to the X and Y directions).

[0128] More specifically, according to some embodiments, the following is performed: Figures 1A to 1K The process shown involves forming a deep sacrificial structure 138”' in a deep trench, as... Figure 5 As shown. The process material used to form the deep sacrificial structure 138”' is the same as the process material previously described for forming the deep sacrificial structure 138, except that the deep sacrificial structure 138”' is thinner than the deep sacrificial structure 138. In some embodiments, the top surface of the deep sacrificial structure 138”' is lower than the top surface of the isolation structure 112, and the bottom surface of the deep sacrificial structure 138”' is higher than the bottom surface of the isolation structure 112. Then, according to some embodiments, the following is performed: Figures 1M to 1ZF The process shown is used to form a semiconductor structure 100, which is related to Figure 1ZF , Figure 1 ZF-1 , Figure 1 ZF-2 and Figure 1 ZF-3 The semiconductor structure 100 shown is similar or the same, and will not be described again here.

[0129] Figure 6 The illustration shows a cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure 100 according to some other embodiments. The materials and processes used to fabricate the semiconductor structure 100 may be the same as those previously described. Figures 1A to 1ZF The materials and processes shown are similar or identical, except for their deep sacrificial structure ratio. Figure 1L The deep sacrificial structure shown is thin (e.g., measured along the Z direction perpendicular to the X and Y directions).

[0130] More specifically, according to some embodiments, the following is performed: Figures 1A to 1K The process is shown, and then a deep sacrificial structure 138” is formed in the deep trench, as shown. Figure 6 As shown. The process material used to form the deep sacrificial structure 138”” is the same as the process material previously described for forming the deep sacrificial structure 138, except that the deep sacrificial structure 138”” is thinner than the deep sacrificial structure 138 (e.g., measured along the Z direction perpendicular to the X and Y directions). In some embodiments, the top surface of the deep sacrificial structure 138”” is lower than the top surface of the isolation structure 112, and the bottom surface of the deep sacrificial structure 138”” is substantially flush with the bottom surface of the isolation structure 112. Then, according to some embodiments, the following is performed: Figures 1M to 1ZF The process shown is used to form a semiconductor structure 100, which is related to Figure 1ZF , Figure 1 ZF-1 , Figure 1 ZF-2 and Figure 1 ZF-3 The semiconductor structure 100 shown is similar or the same, and will not be described again here.

[0131] Figures 7A to 7CA schematic perspective view of an intermediate stage in the fabrication of a semiconductor structure 100a according to some embodiments is shown. The semiconductor structure 100a may be similar to the previously described semiconductor structure 100, except that the shape of its back-side source / drain isolation component differs from that in semiconductor structure 100. Some processes and materials used to form the semiconductor structure 100a may be similar to or the same as those described above for forming the semiconductor structure 100, and will not be repeated here.

[0132] According to some embodiments, execution is similar to Figures 1A to 1ZC The process shown is to form a similar Figure 1ZC The semiconductor structure shown has a non-uniform sidewall above the gate structure 148, but the back-side source / drain isolation component 174a has a non-uniform sidewall. Figure 7A As shown. More specifically, according to some embodiments, the pad layer 176a of the back-side source / drain isolation component 174a has a thinner portion (e.g., measured along the Y direction parallel to the extension direction of the gate structure) on the side attached to the gate structure 148-4, such that the isolation material 178a formed thereon also has a wider portion (e.g., measured along the Y direction parallel to the extension direction of the gate structure) near the gate structure 148-4, as... Figure 7A As shown. In some embodiments, the isolation material 178a of the back-side source / drain isolation component 174a continuously tapers from one side near the gate structure 148-4 to the opposite side of the gate structure 148-4.

[0133] Subsequently, according to some embodiments, the previously described procedures are performed. Figure 1ZD The first etching process shown removes the isolation material 178a of the back-side source / drain isolation component 174a exposed by the opening 194 to form a trench 200a, as... Figure 7B As shown. In some embodiments, the isolation material 178a of the back-side source / drain isolation component 174a is not completely removed. That is, according to some embodiments, the retained portion 178a' of the isolation material of the back-side source / drain isolation component 174a is retained in the opening 200a, as shown. Figure 7B As shown.

[0134] Next, according to some embodiments, the following will be performed: Figure 1ZE and Figure 1ZF The process shown is used to form semiconductor structure 100a, such as Figure 7CAs shown. Similarly, according to some embodiments, a back-side gate isolation member 206a is formed through the gate structure 148-4 to separate the gate structure 148-4 into two separate portions. Furthermore, according to some embodiments, a retained portion 178a' of the isolation material of the back-side source / drain isolation member 174a is in direct contact with the back-side gate isolation member 206a and sandwiched between the back-side gate isolation member 206a and the pad layer 176a, as shown. Figure 7C As shown. The processes and materials used to form the back-side source / drain isolation component 174a (including pad layer 176a and isolation material 178a) and the back-side gate isolation component 206a are similar to or the same as those used to form the back-side source / drain isolation component 174 (including pad layer 176 and isolation material 178) and the back-side gate isolation component 206a, and will not be described in detail here.

[0135] Figure 8A and Figure 8B A schematic perspective view of intermediate stages in the fabrication of semiconductor structure 100b according to some embodiments is shown. According to some embodiments, semiconductor structure 100b may be similar to the previously described semiconductor structure 100, except that its back-side conductive vias do not have pads. Some processes and materials used to form semiconductor structure 100b may be similar to or the same as those previously described for forming semiconductor structure 100, and will not be repeated here.

[0136] According to some embodiments, it is possible to perform similar actions. Figures 1A to 1ZA The process is shown, and then a back-side conductive via 186b is formed in the back-side via opening, as shown. Figure 8A As shown. In some embodiments, the back-side conductive via 186b is made of a single conductive material, such as Ru, W, Co, Al, Mo, or a material containing the aforementioned metals. The conductive material can be formed by performing chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. In some embodiments, the conductive material of the back-side conductive via 186b is in direct contact with the back-side dielectric layer 182 and the insulating pad 110.

[0137] According to some embodiments, the above-described procedure is performed after the back-side conductive via 186b is formed. Figures 1ZC to 1ZF The process shown is used to form a semiconductor structure 100b with a back-side gate isolation component 206b, such as Figure 8B , Figure 8B-1 and Figure 8B-2 As shown. Figure 8B-1 A cross-sectional view of a semiconductor structure 100b, shown above the source / drain structure, is illustrated according to some embodiments, along an extension direction parallel to the gate structure 148. Figure 8B-2A cross-sectional view of a semiconductor structure 100b is shown, which is a source / drain structure along an extension direction parallel to the nanostructure 108' according to some embodiments and shown above the source / drain structure.

[0138] In some embodiments, the conductive material of the back-side conductive via 186b is in direct contact with the back-side gate isolation member 206b. The processes and materials used to form the back-side gate isolation member 206b are similar to or the same as those used to form the back-side gate isolation member 206, and will not be described again here.

[0139] Figure 9A and Figure 9B A schematic perspective view of an intermediate stage in the fabrication of a semiconductor structure 100c according to some embodiments is shown. According to some embodiments, the semiconductor structure 100c may be similar to the previously described semiconductor structure 100, except that its back-side conductive vias are shorter than those in the semiconductor structure 100 (e.g., measured along the Z direction perpendicular to the X and Y directions). Some processes and materials used to form the semiconductor structure 100c may be similar to or the same as those previously described for forming the semiconductor structure 100, and will not be repeated here.

[0140] According to some embodiments, it is possible to perform similar actions. Figures 1A to 1Z The process is shown, and then the deep sacrificial structure is removed to form the back-side conductive via opening 184c, as... Figure 9A As shown. In some embodiments, an etching process is performed to remove the deep sacrificial structure until the source / drain structure 140' is exposed. Furthermore, the source / drain structure 140' is not significantly recessed during the etching process.

[0141] According to some embodiments, the above-described procedure is performed after the back-side conductive via opening 184c is formed. Figures 1ZB to 1ZF The process shown is used to form a semiconductor structure 100c with a back-side conductive via 186c, such as Figure 9B , Figure 9B-1 and Figure 9B-2 As shown. Figure 9B-1 A cross-sectional view of a semiconductor structure 100c shown is illustrated, which is a source / drain structure extending parallel to the gate structure 148 according to some embodiments and is shown above the source / drain structure. Figure 9B-2 The illustration shows a cross-sectional view of a semiconductor structure 100c, which is shown above the source / drain structure, along an extension direction parallel to the nanostructure 108' according to some embodiments.

[0142] In some embodiments, the top surface of the back-side conductive via 186c is lower than the bottom surface of the gate structure 148-4, as shown in some embodiments. Figure 9B-2As shown in the inverted position. The process and materials for forming the back-side conductive via 186c are similar to or the same as those for forming the back-side conductive via 186, and will not be described again here.

[0143] Figure 10A and Figure 10B A schematic perspective view of an intermediate stage in the fabrication of a semiconductor structure 100d according to some embodiments is shown. According to some embodiments, the semiconductor structure 100d may be similar to the previously described semiconductor structure 100, except that its source / drain structure beneath the back-side dielectric layer is thicker than that of the semiconductor structure 100. Some processes and materials used to form the semiconductor structure 100d may be similar to or the same as those previously described for forming the semiconductor structure 100, and will not be repeated here.

[0144] According to some embodiments, it is possible to perform similar actions. Figures 1A to 1Y The process is shown, and then the base fin structure is removed to form a trench, and a back-side dielectric layer 182d is formed in the trench, as shown. Figure 10A As shown. According to some embodiments, similar to Figure 1Z The structures described herein can be removed by performing an etching process, exposing the gate structure 148, internal spacers 134, and source / drain structure 140d' by trenches. In some embodiments, the source / drain structure 140d' is lightly etched during the etching process, and according to some embodiments, the bottommost surface 140'BSd of the source / drain structure 140d' remains below the bottommost surface of the bottommost nanostructure 108', as... Figure 10A As shown. In some embodiments, the bottom surface 140'BSd of the source / drain structure 140d' is higher than the bottom surface of the bottom inner spacer 134 according to some embodiments.

[0145] According to some embodiments, the above-described procedure is performed after the base fin structure 105 is replaced by the back-side dielectric layer 182d. Figures 1ZA to 1ZF The process shown is used to form a semiconductor structure of 100d, such as Figure 10B As shown. The processes and materials used to form the source / drain structure 140d' and the back-side dielectric layer 182d are similar to or the same as those used to form the source / drain structure 140d' and the back-side dielectric layer 182d, and will not be described again here.

[0146] As device size continues to shrink, adjacent source / drain structures tend to merge. To prevent this merging of source / drain structures on adjacent fins, the distance between fins cannot be too small, which may limit further reduction in device size. In some embodiments, back-side source / drain isolation components (e.g.) Figure 1XThe back-side source / drain isolation component 174 shown will merge the source / drain structure (e.g., from the back side of the device) from the device. Figure 1M The source / drain structure 140 shown is cut into separate parts (e.g., Figure 1X The source / drain structures 140-1', 140-2', and 140-3' are shown. Therefore, the distance (e.g., pitch) between fin structures (e.g., fin structures 104-1, 104-2, and 104-3) can be reduced without worrying about the merging of the source / drain structures.

[0147] It should be understood that the elements shown in semiconductor structures 100 and 100a to 100d can be combined and / or interchanged. For example, the semiconductor structure may include Figure 7C The back-side gate isolation component 206a and shown Figure 10A The source / drain structure shown is 140d'.

[0148] In addition, it should be noted that Figures 1A to 10B The same components can be represented by the same designation and may include the same or similar materials, and can be formed by the same or similar processes; therefore, for the sake of brevity, these redundant details have been omitted. Furthermore, although... Figures 1A to 10B It's about the method description, but it should be understood that... Figures 1A to 10B The disclosed structure is not limited to methods, but can exist independently of methods. Similarly, Figures 1A to 10B The methods shown are not limited to the disclosed structures, but can exist independently of these structures. Furthermore, according to some embodiments, the nanostructures described above may include nanowires, nanosheets, or other suitable nanostructures.

[0149] Furthermore, although the disclosed methods are illustrated and described above as a series of actions or events, it should be understood that the illustrated order of such actions or events may be changed in some other embodiments. For example, some actions may occur in a different order, and / or simultaneously with other actions or events besides those shown and / or described above. Moreover, implementing one or more aspects or embodiments described above may not require all the actions shown. Furthermore, one or more of the actions described above may be performed in one or more individual actions and / or stages.

[0150] Furthermore, the terms “approximately,” “substantially,” “essentially,” and “about” described above take into account minor variations and can vary across different technologies and within the range of deviations understood by those skilled in the art. For example, when used in conjunction with an event or situation, these terms can refer to a situation where the event or situation occurred precisely or where the event or situation was very close to occurring.

[0151] Embodiments for forming semiconductor structures can be provided. The semiconductor structure may include a first nanostructure and a second nanostructure, as well as a gate structure surrounding the first and second nanostructures. A first source / drain structure is connected to the first nanostructure, and a second source / drain structure is connected to the second nanostructure. The first and second source / drain structures may initially be merged together and then separated into individual portions by subsequently formed back-side source / drain isolation components. Since the first and second source / drain structures can then be separated, the distance between the nanostructures can be reduced without the risk of source / drain structure merging at adjacent nanostructures. Therefore, device size can be reduced, and the performance of the semiconductor structure can be improved.

[0152] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a back-side dielectric layer and a first nanostructure and a second nanostructure located above the back-side dielectric layer. The semiconductor structure also includes a first source / drain structure connected to the first nanostructure and a second source / drain structure connected to the second nanostructure. The semiconductor structure further includes a back-side source / drain isolation component sandwiched between the first and second source / drain structures. Furthermore, the bottom surface of the back-side source / drain isolation component is substantially flush with the bottom surface of the back-side dielectric layer.

[0153] The semiconductor structure described above also includes a gate structure surrounding the first nanostructure and the second nanostructure, wherein the bottom surface of the gate structure is lower than the top surface of the back dielectric layer.

[0154] The semiconductor structure described above also includes: a first internal spacer formed between the first nanostructures, wherein the back-side dielectric layer is in direct contact with the gate structure and the first internal spacer.

[0155] The semiconductor structure described above also includes a back-side gate isolation component, which is formed to pass through the back-side dielectric layer and through the gate structure to separate the gate structure into a first part and a second part.

[0156] In the above semiconductor structure, the back-side gate isolation component is in contact with the back-side source / drain isolation component.

[0157] In the above semiconductor structure, the back-side source / drain isolation component includes: a pad layer covering the sidewalls of the first source / drain structure and the second source / drain structure; and an isolation material surrounded by the pad layer.

[0158] The semiconductor structure described above also includes a source / drain contact formed above the first source / drain structure, wherein the source / drain contact is in direct contact with the pad layer of the back-side source / drain isolation component.

[0159] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a back-side dielectric layer and a first nanostructure and a second nanostructure extending over the back-side dielectric layer along a first direction. The semiconductor structure also includes a gate structure located over the back-side dielectric layer and surrounding the first and second nanostructures, extending in a second direction. The semiconductor structure further includes a first source / drain structure located over the back-side dielectric layer and connected to the first nanostructure, and a second source / drain structure located over the back-side dielectric layer and connected to the second nanostructure. The semiconductor structure also includes a back-side source / drain isolation member extending in the first direction and separating the first and second source / drain structures. Furthermore, the back-side source / drain isolation member includes a pad layer located over the sidewalls of the first and second source / drain structures, and an isolation material surrounded and covered by the pad layer.

[0160] The semiconductor structure described above also includes: a source / drain contact covering the first source / drain structure, the back-side source / drain isolation component, and the second source / drain structure.

[0161] In the above semiconductor structure, the source / drain contact is in contact with the pad layer of the back-side source / drain isolation component.

[0162] The semiconductor structure described above also includes a back-side conductive via formed below the first source / drain structure, wherein the back-side conductive via is vertically overlapped with the source / drain contacts.

[0163] In the above semiconductor structure, the bottom surface of the gate structure is lower than the bottom surface of the first source / drain structure.

[0164] In some embodiments, a method for manufacturing a semiconductor structure is provided. The method includes forming a first fin structure and a second fin structure projecting from the front side of a substrate. Furthermore, the first fin structure and the second fin structure include alternately stacked first and second semiconductor material layers. The method also includes forming an isolation structure surrounding the first and second fin structures and forming source / drain structures over the first and second fin structures. The method further includes removing the isolation structure from the back side of the substrate to form an opening exposing the source / drain structures, and etching the source / drain structures through the opening to form a deep opening through the source / drain structures. The method also includes forming a back-side source / drain isolation component in the deep opening.

[0165] In the above method, the source / drain structure is separated into a first source / drain structure and a second source / drain structure.

[0166] The above method further includes: removing the first semiconductor material layer of the first fin structure and the second fin structure to form the first nanostructure and the second nanostructure; and forming a gate structure surrounding the first nanostructure and the second nanostructure, wherein the first source / drain structure is connected to the first nanostructure and the second source / drain structure is connected to the second nanostructure.

[0167] The above method further includes: forming a back-side gate isolation trench that passes through the back-side source / drain isolation component and through the gate structure; and forming a back-side gate isolation component in the back-side gate isolation trench, wherein the gate structure is separated into a first part and a second part by the back-side gate isolation component.

[0168] The above method further includes: removing the substrate from the back side of the substrate to form a trench; and forming a back-side dielectric layer in the trench.

[0169] The above method further includes: forming a deep trench in the first fin structure; and forming a deep sacrificial structure in the deep trench, wherein the source / drain structure is formed above the deep sacrificial structure.

[0170] The above method further includes: removing the deep sacrificial structure to form a back-side conductive via opening; and forming a back-side conductive via in the back-side conductive via opening.

[0171] The above method also includes: forming a capping layer over the isolation structure; and partially removing the capping layer before forming the source / drain structure.

[0172] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made within the invention without departing from its spirit and scope.

Claims

1. A semiconductor structure, comprising: Backside dielectric layer; The first nanostructure and the second nanostructure extend in a first direction and are located above the back-side dielectric layer; A first source / drain structure is connected to the first nanostructure; A second source / drain structure is connected to the second nanostructure; as well as A back-side source / drain isolation component extends in a first direction and is sandwiched between the first source / drain structure and the second source / drain structure. The bottom surface of the back-side source / drain isolation component is substantially flush with the bottom surface of the back-side dielectric layer, and the first source / drain structure and the second source / drain structure extend in the same cross section in the second direction.

2. The semiconductor structure according to claim 1, further comprising: A gate structure surrounds the first nanostructure and the second nanostructure, wherein the bottom surface of the gate structure is lower than the top surface of the back-side dielectric layer.

3. The semiconductor structure according to claim 2, further comprising: First internal spacers are formed between the first nanostructures. The back-side dielectric layer is in direct contact with the gate structure and the first internal spacer.

4. The semiconductor structure according to claim 2, further comprising: A back-side gate isolation component is formed through the back-side dielectric layer and through the gate structure to separate the gate structure into a first portion and a second portion.

5. The semiconductor structure according to claim 4, wherein, The back-side gate isolation component is in contact with the back-side source / drain isolation component.

6. The semiconductor structure according to claim 1, wherein, The back-side source / drain isolation component includes: A liner layer covering the sidewalls of the first source / drain structure and the second source / drain structure; and The insulating material is surrounded by the padding layer.

7. The semiconductor structure according to claim 6, further comprising: A source / drain contact is formed above the first source / drain structure, wherein the source / drain contact is in direct contact with the pad layer of the back-side source / drain isolation component.

8. A semiconductor structure, comprising: Backside dielectric layer; The first nanostructure and the second nanostructure extend over the back-side dielectric layer in a first direction. A gate structure is located above the back-side dielectric layer and surrounds the first nanostructure and the second nanostructure and extends in the second direction; A first source / drain structure is located above the back dielectric layer and connected to the first nanostructure; The second source / drain structure is located above the back dielectric layer and connected to the second nanostructure; A back-side source / drain isolation component extends in the first direction and separates the first source / drain structure and the second source / drain structure, the first source / drain structure and the second source / drain structure extending in the same cross-section in the second direction, wherein the back-side source / drain isolation component includes: A liner layer is located above the sidewalls of the first source / drain structure and the sidewalls of the second source / drain structure; and an insulating material is surrounded and covered by the liner layer.

9. The semiconductor structure according to claim 8, further comprising: Source / drain contacts cover the first source / drain structure, the back-side source / drain isolation component, and the second source / drain structure.

10. The semiconductor structure according to claim 9, wherein, The source / drain contact contacts the padding layer of the back-side source / drain isolation component.

11. The semiconductor structure according to claim 9, further comprising: A back-side conductive via is formed below the first source / drain structure, wherein the back-side conductive via vertically overlaps the source / drain contact.

12. The semiconductor structure according to claim 8, wherein, The bottom surface of the gate structure is lower than the bottom surface of the first source / drain structure.

13. A method for manufacturing a semiconductor structure, comprising: A first fin structure and a second fin structure extending in a first direction protruding from the front side of the substrate are formed, wherein the first fin structure and the second fin structure include alternately stacked first semiconductor material layers and second semiconductor material layers; An isolation structure is formed around the first fin structure and the second fin structure; A source / drain structure is formed above the first fin structure and the second fin structure; The isolation structure is removed from the back side of the substrate to form an opening that exposes the source / drain structure; The source / drain structure is etched through the opening to form a deep opening through the source / drain structure; and A back-side source / drain isolation component is formed in the deep opening, separating the source / drain structure into a first source / drain structure and a second source / drain structure, the first source / drain structure and the second source / drain structure extending in the same cross section in a second direction.

14. The method for manufacturing a semiconductor structure according to claim 13, wherein, The first source / drain structure and the second source / drain structure are separated.

15. The method for manufacturing a semiconductor structure according to claim 13, further comprising: Remove the first semiconductor material layer from the first fin structure and the second fin structure to form the first nanostructure and the second nanostructure; and A gate structure is formed that encapsulates and surrounds the first nanostructure and the second nanostructure. The first source / drain structure is connected to the first nanostructure, and the second source / drain structure is connected to the second nanostructure.

16. The method for manufacturing a semiconductor structure according to claim 15, further comprising: Form a back-side gate isolation trench that passes through the back-side source / drain isolation component and through the back-side gate structure; and A back-side gate isolation component is formed in the back-side gate isolation trench. The gate structure is separated into a first part and a second part by the back-side gate isolation component.

17. The method for manufacturing a semiconductor structure according to claim 13, further comprising: The substrate is removed from the back side of the substrate to form a trench; and A back-side dielectric layer is formed in the trench.

18. The method for manufacturing a semiconductor structure according to claim 13, further comprising: Deep grooves are formed in the first fin structure; and A deep sacrificial structure is formed in the deep trench. The source / drain structure is formed above the deep sacrificial structure.

19. The method for manufacturing a semiconductor structure according to claim 18, further comprising: Remove the deep sacrificial structure to form a back-side conductive via opening; and A back-side conductive via is formed in the opening of the back-side conductive via.

20. The method for manufacturing a semiconductor structure according to claim 13, further comprising: A cover layer is formed above the isolation structure; and The capping layer is partially removed before the source / drain structure is formed.

Images