High electron mobility transistor and method for manufacturing the same

Abstract

The present disclosure provides a high electron mobility transistor and a method for preparing the same. The high electron mobility transistor includes a substrate, an epitaxial layer, a source, a drain, a gate, and a stress compensation layer: the epitaxial layer includes at least: a first semiconductor layer and a second semiconductor layer arranged on the first semiconductor layer, the first semiconductor layer and the second semiconductor layer being a heterostructure; the source, the drain, and the gate are arranged on the epitaxial layer at intervals, and the gate is arranged between the source and the drain. By arranging a stress compensation layer with a piezoelectric coefficient opposite to that of the second semiconductor layer on the side wall of the gate facing the drain, an inverse piezoelectric stress opposite to that of the second semiconductor layer can be generated under high voltage to reduce the stress deformation of the second semiconductor layer under high voltage, thereby increasing the breakdown electric field strength of the second semiconductor layer. The two-dimensional electron gas concentration at the gate edge can also be reduced to adjust the electric field strength at the gate edge, thereby improving the voltage resistance of the device and reducing the need for multi-level field plates, thereby simplifying the preparation process of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a high electron mobility transistor and a preparation method thereof. Background Art

[0002] Gallium nitride-based compound semiconductor materials are widely used in the production of high-voltage, high-frequency electronic devices and light-emitting devices due to their advantages such as large bandgap, good thermal stability, radiation resistance, acid and alkali resistance, direct bandgap, and easy formation of heterojunction device structures. As an important gallium nitride electronic device, gallium nitride-based high electron mobility field-effect transistor (HEMT) has a wide range of applications in high-power radio frequency applications and high-efficiency power conversion applications. With the continuous improvement of gallium nitride material quality, epitaxial device structure design and device manufacturing process, the radio frequency and power performance of gallium nitride HEMT devices are also constantly improving. Compared with first-generation silicon devices and second-generation gallium arsenide devices, the most significant feature of gallium nitride power devices is that higher voltage resistance and power density can be achieved by optimizing materials and device processes.

[0003] However, the actual breakdown voltage of GaN HEMTs manufactured in existing technologies still differs significantly from their theoretical breakdown voltage limit. Therefore, in order to achieve high-power, high-voltage devices, increasing the operating voltage of GaN-based compound semiconductor devices has become a pressing technical issue. Summary of the Invention

[0004] The main technical problem solved by the present disclosure is how to increase the operating voltage of gallium nitride-based compound semiconductor devices.

[0005] To solve the above technical problems, the first technical solution adopted by the present disclosure is to provide a high electron mobility transistor, which includes:

[0006] substrate;

[0007] An epitaxial layer is arranged on the surface of the substrate, and the epitaxial layer at least includes: a first semiconductor layer and a second semiconductor layer arranged on the first semiconductor layer, and the first semiconductor layer and the second semiconductor layer are heterogeneous structures;

[0008] A source electrode, a drain electrode and a gate electrode are arranged on the epitaxial layer at intervals, and the gate electrode is arranged between the source electrode and the drain electrode; wherein the gate electrode has a sidewall facing the drain electrode;

[0009] The stress compensation layer is disposed on the second semiconductor layer and contacts the side wall of the gate. The piezoelectric coefficient of the stress compensation layer is opposite to that of the second semiconductor layer.

[0010] Wherein, the stress compensation layer and the drain electrode are spaced apart.

[0011] Wherein, along the arrangement direction from the gate to the drain, the ratio of the width of the stress compensation layer to the width of the region between the gate and the drain is 2% to 20%.

[0012] The material of the stress compensation layer is nitrogen-faced nitride or oxygen-faced zinc oxide.

[0013] Wherein, the nitrogen-faced nitride includes nitrogen-faced gallium nitride.

[0014] The thickness of the stress compensation layer is smaller than the thickness of the gate.

[0015] The stress compensation layer includes a plurality of sub-stress compensation layers, and the plurality of sub-stress compensation layers are arranged at intervals on the sidewalls of the gate.

[0016] Among them, high electron mobility transistors also include:

[0017] A passivation layer is provided between the source electrode and the gate electrode and between the gate electrode and the drain electrode, and the passivation layer covers the stress compensation layer; and the thickness of the passivation layer is greater than or equal to the thickness of the stress compensation layer.

[0018] The second semiconductor layer includes a gallium-faced AlGaN layer; or the second semiconductor layer includes an AlN insertion layer, a gallium-faced AlGaN layer and a GaN cap layer.

[0019] To solve the above technical problems, the second technical solution adopted by the present disclosure is to provide a method for preparing a high electron mobility transistor, the method comprising:

[0020] providing a substrate;

[0021] forming an epitaxial layer on a surface of a substrate, wherein the epitaxial layer comprises at least a first semiconductor layer and a second semiconductor layer disposed on the first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are heterogeneous structures;

[0022] forming a stress compensation layer on the epitaxial layer, wherein the piezoelectric coefficient of the stress compensation layer is opposite to the piezoelectric coefficient of the second semiconductor layer;

[0023] A source electrode, a drain electrode and a gate electrode are arranged on the epitaxial layer, and the source electrode, the drain electrode and the gate electrode are arranged spaced apart from each other; the gate electrode has a side wall facing the drain electrode, and the stress compensation layer contacts the side wall.

[0024] The step of forming a stress compensation layer on the epitaxial layer comprises:

[0025] Preparing a patterned mask layer on a side of the first semiconductor layer away from the substrate, wherein the patterned mask layer is configured to be hollowed out within a preset range of the sidewall contact of the gate;

[0026] growing a stress compensation layer on the patterned mask layer and the first semiconductor layer;

[0027] The patterned mask layer and the stress compensation layer on the patterned mask layer are removed.

[0028] The step of forming a stress compensation layer on the epitaxial layer comprises:

[0029] forming a first stress compensation layer on a side of the first semiconductor layer away from the substrate;

[0030] The first stress compensation layer is etched to retain the second stress compensation layer within a preset range in contact with the sidewall of the gate, thereby obtaining a stress compensation layer.

[0031] Wherein, after forming the stress compensation layer on the epitaxial layer and before providing the source, drain and gate on the epitaxial layer, the method further includes:

[0032] forming a passivation layer on a side of the stress compensation layer and the first semiconductor layer away from the substrate;

[0033] The source, drain and gate are provided on the epitaxial layer, including:

[0034] The passivation layer is etched to form openings and a source electrode, a drain electrode and a gate electrode are prepared at the openings.

[0035] Beneficial effects of the embodiments of the present disclosure: Different from the prior art, the embodiments of the present disclosure provide a high electron mobility transistor and a method for preparing the same. The high electron mobility transistor includes a substrate, an epitaxial layer, a source, a drain, a gate, and a stress compensation layer: the epitaxial layer is arranged on the surface of the substrate, and the epitaxial layer at least includes: a first semiconductor layer and a second semiconductor layer arranged on the first semiconductor layer, and the first semiconductor layer and the second semiconductor layer are heterogeneous structures; the source, the drain, and the gate are arranged on the epitaxial layer at intervals from each other, and the gate is arranged between the source and the drain; wherein the gate has a sidewall facing the drain; the stress compensation layer is arranged on the second semiconductor layer and contacts the sidewall of the gate; the piezoelectric coefficient of the stress compensation layer is opposite to the piezoelectric coefficient of the second semiconductor layer. In this way, by arranging a stress compensation layer with a piezoelectric coefficient opposite to that of the second semiconductor layer on the side wall of the gate facing the drain, an inverse piezoelectric stress opposite to that of the second semiconductor layer can be generated under high voltage to reduce the stress deformation of the second semiconductor layer under high voltage, thereby increasing the breakdown electric field strength of the second semiconductor layer; at the same time, the two-dimensional electron gas concentration at the gate edge can be reduced to adjust the electric field strength at the gate edge, thereby improving the voltage resistance of the device and reducing the need for multi-level field plates, thereby simplifying the device preparation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 1 is a schematic structural diagram of an embodiment of a high electron mobility transistor provided by an embodiment of the present disclosure;

[0037] Figure 2 yes Figure 1 Schematic diagram of the cross-sectional structure at AA in the middle;

[0038] Figure 3 1 is a schematic structural diagram of another embodiment of a high electron mobility transistor provided by an embodiment of the present disclosure;

[0039] Figure 4 1 is a flow chart of an embodiment of a method for manufacturing a high electron mobility transistor provided by an embodiment of the present disclosure;

[0040] Figure 5 yes Figure 4 Schematic diagram of the structure corresponding to steps S1 to S5;

[0041] Figure 6 yes Figure 4 Flow chart of step S3 in an embodiment;

[0042] Figure 7 yes Figure 6 Schematic diagram of the structure corresponding to steps S311 to S313;

[0043] Figure 8 yes Figure 4 A schematic flow chart of another embodiment of step S3;

[0044] Figure 9 yes Figure 8 Schematic diagram of the structure corresponding to steps S321 to S322. DETAILED DESCRIPTION

[0045] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the embodiments of the present disclosure.

[0046] The terms "first", "second" and "third" in the embodiments of the present disclosure are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second" and "third" can explicitly or implicitly include at least one of the features. In the description of the embodiments of the present disclosure, the meaning of "multiple" is at least two, for example, two, three, etc., unless otherwise clearly and specifically defined. All directional indications in the embodiments of the present disclosure (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0047] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present disclosure. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0048] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings and examples.

[0049] See also Figure 1 and Figure 2 , Figure 1 1 is a schematic structural diagram of an embodiment of a high electron mobility transistor provided by an embodiment of the present disclosure. Figure 2 yes Figure 1 Schematic diagram of the cross-sectional structure at AA in the middle.

[0050] The high electron mobility transistor 100 includes a substrate 10 and an epitaxial layer 20 disposed on the surface of the substrate 10. The epitaxial layer includes at least a first semiconductor layer 13 and a second semiconductor layer 14 disposed on the first semiconductor layer 13. The first semiconductor layer 13 and the second semiconductor layer 14 are heterostructured.

[0051] The source 17 , the drain 18 , and the gate 16 are disposed on the epitaxial layer 20 at intervals, and the gate 16 is disposed between the source 17 and the drain 18 . The gate 16 has a sidewall facing the drain 18 .

[0052] The stress compensation layer 15 is disposed on the second semiconductor layer 14 and contacts the sidewall of the gate 16 . The piezoelectric coefficient of the stress compensation layer 15 is opposite to that of the second semiconductor layer 14 .

[0053] In some embodiments, the epitaxial layer 20 includes a first semiconductor layer 13 and a second semiconductor layer 14 , and the substrate 10 may be gallium nitride. The first semiconductor layer 13 is directly disposed on one side of the substrate 10 .

[0054] It should be noted that in the following description, unless it is emphasized that gallium nitride is gallium-face gallium nitride or nitrogen-face gallium nitride, it refers to gallium-face gallium nitride.

[0055] In some embodiments, the epitaxial layer 20 includes a nucleation layer 11, a buffer layer 12, a first semiconductor layer 13, and a second semiconductor layer 14 sequentially stacked on a substrate 10. The substrate 10 may be at least one of silicon, silicon carbide, sapphire, or aluminum oxide.

[0056] In some embodiments, the high electron mobility transistor 100 includes a substrate 10, a nucleation layer 11, a buffer layer 12, a first semiconductor layer 13, a second semiconductor layer 14, and a stress compensation layer 15 stacked in sequence from bottom to top; and also includes: a source 17, a gate 16, and a drain 18 arranged on the second semiconductor layer 14 and spaced apart from each other, wherein the stress compensation layer 15 is arranged on the side of the gate 16 facing the drain 18.

[0057] In some embodiments, the high electron mobility transistor 100 further includes a passivation layer 19 . The passivation layer 19 is disposed on a side of the epitaxial layer 20 away from the substrate 10 and covers the epitaxial layer 20 and the stress compensation layer 15 .

[0058] Exemplarily, the nucleation layer 11 can be a GaN layer or an AlN layer. The main function of the nucleation layer 11 is to provide the necessary nucleation centers for high-temperature GaN growth, reduce the interface free energy between the high-temperature GaN and the substrate 10 to promote the adsorption of reactant atoms on the substrate 10 and the lateral growth of GaN.

[0059] Exemplarily, the buffer layer 12 is a GaN layer or an AlGaN layer. The buffer layer 12 can be a single layer structure or a multilayer structure, without limitation herein. When the buffer layer 12 includes multiple AlGaN layers, the Al content in each AlGaN layer can be the same or different.

[0060] The first semiconductor layer 13 and the second semiconductor layer 14 form a heterostructure, with a two-dimensional electron gas forming at the interface between the first semiconductor layer 13 and the second semiconductor layer 14. Exemplarily, the first semiconductor layer 13 is a high-temperature GaN layer. The first semiconductor layer 13 is a conductive layer along the length of the high electron mobility transistor 100 caused by an applied electric field. That is, the first semiconductor layer 13 serves as a channel layer. The second semiconductor layer 14 can be a single-layer structure or a multi-layer structure. When the second semiconductor layer 14 is a single-layer structure, it includes a gallium-faced AlGaN layer. When the second semiconductor layer 14 is a multi-layer structure, that is, when the second semiconductor layer 14 is a composite second semiconductor layer, it includes an AlN intercalation layer, a gallium-faced AlGaN layer, and a GaN cap layer. The AlN intercalation layer, the gallium-faced AlGaN layer, and the GaN cap layer are sequentially stacked on the first semiconductor layer 13. A bandgap discontinuity exists between the first semiconductor layer 13 and the second semiconductor layer 14. Electrons generated in the second semiconductor layer 14 due to the piezoelectric effect fall into the first semiconductor layer 13, generating a two-dimensional electron gas (2DEG) of high-mobility conductive electrons in the first semiconductor layer 13, thereby forming a carrier channel 131. The second semiconductor layer 14 and the first semiconductor layer 13 define an interface, and the carrier channel 131 of the 2DEG is located at this interface.

[0061] The source electrode 17, the drain electrode 18, and the gate electrode 16 are arranged on the surface of the second semiconductor layer 14 away from the substrate 10. The gate electrode 16 is located between the source electrode 17 and the drain electrode 18, and is spaced apart from the drain electrode 18 and the source electrode 17 respectively. The gate electrode 16 forms a Schottky contact with the second semiconductor layer 14. The source electrode 17 and the drain electrode 18 form an ohmic contact with the second semiconductor layer 14 respectively. The source electrode 17 and the drain electrode 18 are respectively configured to be electrically connected to the carrier channel 131. The source electrode 17 and the drain electrode 18 can be at least one of Ti, Al, Ni and Au respectively. The gate electrode 16 can be a metal material such as nickel, nickel-manganese alloy, nickel-chromium alloy, and nickel-molybdenum-iron alloy. The materials of the gate electrode 16, the source electrode 17 and the drain electrode 18 are not limited here and are selected according to actual needs.

[0062] The stress-compensating layer 15 is disposed on the surface of the second semiconductor layer 14 away from the substrate 10. The stress-compensating layer 15 is disposed between the gate 16 and the drain 18, and is spaced apart from the drain 18. The stress-compensating layer 15 contacts the surface of the gate 16 on the side closest to the drain 18. The piezoelectric coefficient of the stress-compensating layer 15 is opposite to that of the second semiconductor layer 14. The stress-compensating layer 15 can generate an inverse piezoelectric strain stress opposite to that of the second semiconductor layer 14, reducing the stress strain of the second semiconductor layer 14 under high voltage. This can thereby increase the breakdown voltage of the second semiconductor layer 14, improve the stress state of the high electron mobility transistor 100 under high voltage and high power conditions, and enhance the reliability of the high electron mobility transistor 100.

[0063] Furthermore, in the prior art, to increase the breakdown voltage of the device, a multi-level metal field plate is provided on the side of the passivation layer 19 between the gate 16 and the drain 18 away from the substrate 10, or on the side of the gate 16 away from the substrate 10. However, the actual breakdown voltage of the device is still significantly different from its theoretical breakdown voltage limit when the multi-level metal field plate is used to increase the breakdown voltage. However, the embodiment of the present disclosure adjusts the distribution of the two-dimensional electron gas and the electric field distribution by providing a stress compensation layer 15, thereby reducing the peak electric field intensity near the gate 16 and thereby improving the breakdown voltage performance of the high electron mobility transistor 100. Compared with a multi-level metal field plate, it can better improve the breakdown voltage and the ability to withstand the electric field near the gate 16, thereby reducing the need for a multi-level field plate, thereby simplifying the device manufacturing process.

[0064] It should be noted that the following description of the width is described in the extension direction parallel to the substrate 10 and perpendicular to the gate 16, the description of the thickness is described in the direction perpendicular to the substrate 10, and the description of the length is described in the extension direction of the gate 16.

[0065] In some embodiments, the thickness of the stress-compensating layer 15 is between 20 nm and 1000 nm, and the thickness of the stress-compensating layer 15 is less than that of the gate 16. The stress-compensating layer 15 requires a certain thickness. If the stress-compensating layer 15 is too thin, for example, if the thickness of the stress-compensating layer 15 is less than 20 nm, the inverse piezoelectric deformation stress generated by the stress-compensating layer 15, which is opposite to that of the second semiconductor layer 14, is small, and the effect of reducing the stress deformation of the second semiconductor layer 14 under high voltage is not significant. If the stress-compensating layer 15 is too thick, for example, if the thickness of the stress-compensating layer 15 is greater than 1000 nm, it will affect the subsequent fabrication of the passivation layer 19 and the field plate. It should be understood that the thickness of the stress-compensating layer 15 is related to the piezoelectric coefficient of the stress-compensating layer 15 and the stress requirements of the stress-compensating layer 15. The optimal thickness range of the stress-compensating layer 15 can be determined through testing.

[0066] In some other embodiments, the ratio of the width of the stress compensation layer 15 to the width of the region between the gate 16 and the drain 18 along the arrangement direction from the gate 16 to the drain 18 is 2% to 20%. For example, the width of the stress compensation layer 15 along the arrangement direction from the gate 16 to the drain 18 is 0.5 μm to 10 μm;

[0067] It should be understood that the width of the stress compensation layer 15 , like the thickness of the stress compensation layer 15 , will also affect the compensation effect of the stress compensation layer 15 .

[0068] In some embodiments, the material of the stress-compensating layer 15 is nitrogen-faced nitride or oxygen-faced zinc oxide. This allows the stress-compensating layer 15 formed by the nitrogen-faced nitride or oxygen-faced oxidative properties to have a pressure coefficient opposite to that of the second semiconductor layer 14 in the epitaxial layer 20. In some embodiments, when the material of the stress-compensating layer 15 is nitrogen-faced nitride, the nitrogen-faced nitride may be nitrogen-faced gallium nitride. The stress-compensating layer 15 may also be made of other piezoelectric materials, as long as the piezoelectric coefficient is opposite to that of the second semiconductor layer 14. This is not particularly limited and may be selected based on actual needs.

[0069] In some embodiments, the cross-sectional area of ​​the stress-compensating layer 15 in a direction parallel to the substrate 10 is rectangular, and the length of the stress-compensating layer 15 is consistent with the length of the gate 16. In other embodiments, the cross-sectional area of ​​the stress-compensating layer 15 in a direction parallel to the substrate 10 can be a fan-shaped, parallelogram-shaped, or other shape, as long as the thickness and width requirements of the stress-compensating layer 15 are met.

[0070] See also Figure 1 and Figure 3 , Figure 3 It is a schematic structural diagram of another embodiment of a high electron mobility transistor provided in an embodiment of the present disclosure.

[0071] In this embodiment, the stress compensation layer 15 includes a plurality of sub-stress compensation layers 151, and the plurality of sub-stress compensation layers 151 are spaced apart along the extension direction of the gate 16. The shapes and / or sizes of the different sub-stress compensation layers 151 can be the same, or the shapes and sizes of the different sub-stress compensation layers 151 can be different, which is not limited here. Figure 3 As shown, in this embodiment, each stress compensation sub-layer 151 has the same shape and size, and the cross-sectional area of ​​each stress compensation sub-layer 151 in a direction parallel to the substrate 10 is rectangular. In some embodiments, the intervals between two adjacent stress compensation sub-layers 151 are the same.

[0072] In some embodiments, see Figure 1 The passivation layer 19 is disposed between the gate 16 and the source 17, and between the gate 16 and the drain 18, and covers the stress compensation layer 15 and a portion of the second semiconductor layer 14. The thickness of the passivation layer 19 is greater than or equal to the thickness of the stress compensation layer 15. The passivation layer 19 can be a dielectric material such as silicon dioxide, silicon nitride, or aluminum nitride.

[0073] The present disclosure provides a high electron mobility transistor 100. The high electron mobility transistor 100 includes a substrate 10, an epitaxial layer 20, a source 17, a drain 18, a gate 16, and a stress compensation layer 15. The epitaxial layer 20 is disposed on the surface of the substrate 10 and includes at least a first semiconductor layer 13 and a second semiconductor layer 14 disposed on the first semiconductor layer 13, wherein the first semiconductor layer 13 and the second semiconductor layer 14 are heterojunction structures. The source 17, the drain 18, and the gate 16 are disposed on the epitaxial layer at intervals, with the gate 16 disposed between the source 17 and the drain 18. The gate 16 has a sidewall facing the drain 18. The stress compensation layer 15 is disposed on the second semiconductor layer 14 and contacts the sidewall of the gate 16. The piezoelectric coefficient of the stress compensation layer 15 is opposite to that of the second semiconductor layer 14. By setting a stress compensation layer 15 with a piezoelectric coefficient opposite to that of the second semiconductor layer 14 on the side wall of the gate 16 facing the drain 18, an inverse piezoelectric stress opposite to that of the second semiconductor layer 14 can be generated under high voltage to reduce the stress deformation of the second semiconductor layer 14 under high pressure, thereby increasing the breakdown electric field strength of the second semiconductor layer 14. It can also reduce the two-dimensional electron gas concentration at the edge of the gate 16 and adjust the electric field strength at the edge of the gate 16, thereby improving the voltage resistance of the device and reducing the need for multi-level field plates, thereby simplifying the device preparation process.

[0074] The present disclosure provides a method for preparing a high electron mobility transistor 100, which is used to prepare the high electron mobility transistor 100. The specific steps of the method for preparing the high electron mobility transistor 100 are as follows:

[0075] See also Figure 4 and Figure 5 , Figure 4 1 is a flow chart of an embodiment of a method for preparing a high electron mobility transistor provided by an embodiment of the present disclosure. Figure 5 yes Figure 4 Schematic diagram of the structure corresponding to steps S1 to S5.

[0076] S1: Provide a substrate.

[0077] Specifically, the substrate 10 is at least one of silicon, silicon carbide, sapphire, aluminum oxide or gallium nitride.

[0078] S2: forming an epitaxial layer on the surface of the substrate, wherein the epitaxial layer at least includes: a first semiconductor layer and a second semiconductor layer disposed on the first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are a heterostructure.

[0079] Specifically, the epitaxial layer 20 includes at least a first semiconductor layer 13 and a second semiconductor layer 14 , and the first semiconductor layer 13 and the second semiconductor layer 14 are heterogeneous structures.

[0080] In this embodiment, the epitaxial layer 20 includes a nucleation layer 11, a buffer layer 12, a first semiconductor layer 13, and a second semiconductor layer 14, which are sequentially stacked on a substrate 10. The substrate 10 can be at least one of silicon, silicon carbide, sapphire, or aluminum oxide. Specifically, the nucleation layer 11 and the buffer layer 12 are sequentially grown on the substrate 10 using MOCVD (Metal-organic Chemical Vapor Deposition). The nucleation layer 11 can be a GaN layer or an AlN layer, with a growth temperature of 600°C to 1200°C and a thickness of 10nm to 500nm. The buffer layer 12 can be a GaN layer or an AlGaN layer. The growth temperature of the buffer layer 12 is 900°C to 1200°C; the thickness of the buffer layer 12 is 100nm to 10μm. The buffer layer 12 can be a single-layer structure or a multi-layer structure, which is not limited here. When the buffer layer 12 comprises multiple AlGaN layers, the Al content in each AlGaN layer can be the same or different. The nucleation layer 11 and the buffer layer 12 can also be prepared using other methods, which are not limited here.

[0081] In some embodiments, the epitaxial layer 20 only includes the first semiconductor layer 13 and the second semiconductor layer 14 , and the substrate 10 may be gallium nitride. The first semiconductor layer 13 is directly disposed on one side of the substrate 10 .

[0082] The first semiconductor layer 13 and the second semiconductor layer 14 can be fabricated by first growing a high-temperature GaN layer using MOCVD. The high-temperature GaN layer serves as the first semiconductor layer 13. Then, the second semiconductor layer 14 is grown on the side of the first semiconductor layer 13 away from the substrate 10 using MOCVD.

[0083] The first semiconductor layer 13 is grown at a temperature of 1000°C to 1200°C, and has a thickness of 100 nm to 1 μm. The second semiconductor layer 14 is grown at a temperature of 1000°C to 1200°C, and has a thickness of 5 nm to 50 nm. The second semiconductor layer 14 can have a single-layer structure or a multi-layer structure.

[0084] In one embodiment, the second semiconductor layer 14 is a single-layer structure, and the second semiconductor layer 14 includes a gallium-faced AlGaN layer.

[0085] In another embodiment, the second semiconductor layer 14 is a multilayer structure including an AlN intercalation layer, a gallium-faced AlGaN layer, and a GaN cap layer, which are sequentially stacked and grown on the first semiconductor layer 13 .

[0086] S3: forming a stress compensation layer on the epitaxial layer, wherein the piezoelectric coefficient of the stress compensation layer is opposite to the piezoelectric coefficient of the second semiconductor layer.

[0087] Specifically, forming the stress compensation layer 15 on the epitaxial layer 20 involves growing the stress compensation layer 15 on a side of the second semiconductor layer 14 away from the substrate 10 using MBE (Molecular Beam Epitaxy). The piezoelectric coefficient of the stress compensation layer 15 is opposite to that of the second semiconductor layer 14. The growth temperature of the stress compensation layer 15 is 300° C. to 1000° C., and the thickness of the stress compensation layer 15 is 20 nm to 1000 nm.

[0088] In one embodiment, forming the stress compensation layer 15 on the epitaxial layer 20 specifically includes the following steps:

[0089] See also Figure 6 and Figure 7 , Figure 6 yes Figure 4 The flowchart of step S3 in the embodiment is as follows: Figure 7 yes Figure 6 Schematic diagram of the structure corresponding to steps S311 to S313.

[0090] S311: preparing a patterned mask layer on a side of the second semiconductor layer away from the substrate, wherein the patterned mask layer is configured to be hollowed out within a preset range of the sidewall contact of the gate.

[0091] Specifically, a patterned mask layer 141 is formed on the side of the second semiconductor layer 14 away from the substrate 10. The patterned mask layer 141 can be made of a high-temperature-resistant material such as silicon dioxide or silicon nitride. The patterned mask layer 141 covers a portion of the second semiconductor layer 14. An opening structure 142 is formed in the area not covering the second semiconductor layer 14. The size of the opening structure 142 is within the predetermined range of the sidewall contact of the gate 16. In other words, the patterned mask layer 141 is configured to be hollowed out within the predetermined range of the sidewall contact of the gate 16.

[0092] S312: growing a stress compensation layer on the patterned mask layer and the second semiconductor layer.

[0093] Specifically, a stress compensation layer 15 is grown on the side of the patterned mask layer 141 away from the substrate 10 using MBE, and is also grown at the opening structure 142. The stress compensation layer 15 covers the patterned mask layer 141 and a portion of the second semiconductor layer 14. The thickness of the stress compensation layer 15 is uniform everywhere.

[0094] S313: removing the patterned mask layer and the stress compensation layer on the patterned mask layer.

[0095] Specifically, the patterned mask layer 141 and the stress compensation layer 15 on the surface of the patterned mask layer 141 away from the substrate 10 are removed by chemical etching, and the stress compensation layer 15 in the opening structure 142 is retained.

[0096] In another embodiment, forming the stress compensation layer 15 on the epitaxial layer 20 specifically includes the following steps:

[0097] See also Figure 8 and Figure 9 , Figure 8 yes Figure 4 A flow chart of another embodiment of step S3 is shown in FIG. Figure 9 yes Figure 8 Schematic diagram of the structure corresponding to steps S321 to S322.

[0098] S321: preparing a first stress compensation layer on a side of the second semiconductor layer away from the substrate.

[0099] Specifically, the first stress compensation layer 152 is formed by MBE on the side of the second semiconductor layer 14 away from the substrate 10, and the first stress compensation layer 152 completely covers the second semiconductor layer 14. The thickness of the first stress compensation layer 152 is the same everywhere.

[0100] S322: etching the first stress compensation layer, leaving the second stress compensation layer within a preset range in contact with the sidewall of the gate, to obtain a stress compensation layer.

[0101] Specifically, the first stress compensation layer 152 is etched, and the second stress compensation layer 153 in the contact area of ​​the sidewall of the gate 16 is retained to obtain the patterned stress compensation layer 15. That is, the second stress compensation layer 153 is the patterned stress compensation layer 15.

[0102] S4: preparing a passivation layer on a side of the stress compensation layer and the second semiconductor layer away from the substrate.

[0103] Specifically, a passivation layer 19 is formed on a side of the second semiconductor layer 14 away from the substrate 10. The passivation layer 19 covers the second semiconductor layer 14 and the stress compensation layer 15. The thickness of the passivation layer 19 is greater than or equal to the thickness of the stress compensation layer 15. The passivation layer 19 can be made of a dielectric material such as silicon dioxide, silicon nitride, or aluminum nitride.

[0104] S5: Arranging a source, a drain, and a gate on the epitaxial layer, wherein the source, the drain, and the gate are spaced apart from each other; the gate has a sidewall facing the drain, and the stress compensation layer is in contact with the sidewall.

[0105] Specifically, the passivation layer 19 is etched to form an opening to expose a portion of the second semiconductor layer 14, and a source electrode 17, a drain electrode 18, and a gate electrode 16 are formed in the opening. In other words, the source electrode 17, the drain electrode 18, and the gate electrode 16 are disposed on the surface of the second semiconductor layer 14 away from the substrate 10. The gate electrode 16 is located between the source electrode 17 and the stress compensation layer 15, and is spaced apart from the drain electrode 18 and the source electrode 17, respectively. The stress compensation layer 15 is in contact with the sidewall of the gate electrode 16 facing the drain electrode 18.

[0106] In a specific embodiment, first, a portion of the passivation layer 19 is removed to partially expose the second semiconductor layer 14 to form a first exposure portion 191. There are multiple first exposure portions 191, and the multiple first exposure portions 191 are arranged at intervals. Only one source electrode 17 is prepared on each first exposure portion 191, and only one drain electrode 18 is prepared on each first exposure portion 191. The source electrode 17 and the drain electrode 18 are arranged at intervals. The source electrode 17 and the drain electrode 18 can each be at least one of Ti, Al, Ni and Au. The source electrode 17 and the drain electrode 18 can also be other materials, which are not limited here and can be selected according to actual needs. When preparing the source electrode 17 and the drain electrode 18, the metal material can be first evaporated, and then annealed in an annealing furnace after peeling, so that the source electrode 17 and the drain electrode 18 form ohmic contact with the second semiconductor layer 14 at the first exposure portion 191. The annealing temperature of the source electrode 17 and the drain electrode 18 is 500°C to 800°C. In this embodiment, the source electrode 17 and the drain electrode 18 are prepared by evaporation. In other optional embodiments, the source electrode 17 and the drain electrode 18 can be prepared by other methods such as sputtering, which is not limited here.

[0107] Then, a portion of the passivation layer 19 is removed to partially expose the second semiconductor layer 14 to form a second exposed portion 192. A gate 16 is prepared on the second exposed portion 192. The gate 16 is located between the stress compensation layer 15 and the source 17, and contacts the side of the stress compensation layer 15 close to the source 17. The gate 16 is also located between the source 17 and the drain 18. The gate 16 can be made of metal materials such as nickel, nickel-manganese alloy, nickel-chromium alloy, and nickel-molybdenum-iron alloy. The material of the gate 16 is not limited here and is selected according to actual needs. When preparing the gate 16, the metal material can be evaporated first, and then annealed in an annealing furnace after peeling, so that the gate 16 forms a Schottky contact with the second semiconductor layer 14 at the second exposed portion 192. The annealing temperature of the gate 16 is 300°C to 600°C. In this embodiment, the gate 16 is prepared by evaporation. In other optional embodiments, the gate 16 can be prepared by other methods such as sputtering, which are not limited here.

[0108] The following mainly prepares a high electron mobility transistor, including the following implementation methods.

[0109] First embodiment:

[0110] (1) An AlN nucleation layer was grown on a 6-inch silicon substrate using a MOCVD device. The silicon substrate surface was first heat treated in a high-temperature hydrogen environment at 1060°C to remove oxides from the silicon substrate surface. Trimethylaluminum (TMAl) was pre-flowed at a flow rate of 50 sccm for 1 min. Ammonia at a flow rate of 5000 sccm and TMAl at a flow rate of 400 sccm were then introduced at 1080°C for 50 min to obtain an AlN nucleation layer with a thickness of 200 nm.

[0111] (2) Using MOCVD equipment to continue growing a high-resistance buffer layer on the AlN nucleation layer of step (1), the high-resistance buffer layer includes a three-layer AlGaN structure, and the Al composition of each layer of the AlGaN structure is different; the Al composition of the three-layer AlGaN structure is 75%, 50% and 25% respectively. Among them, the growth conditions for growing the AlGaN structure with an Al composition of 75% are: MO (high-purity metal organic compound) flow rate, wherein trimethyl gallium (TriMethyl ② The growth conditions for growing an AlGaN structure with an Al component of 50% are: MO flow rate, wherein the TMGa flow rate is 58 sccm, the TMAl flow rate is 450 sccm, and the ammonia flow rate is 2000 sccm; the surface temperature is 1050°C, the growth time is 50 min, and the thickness of the AlGaN structure with an Al component of 50% is 900 nm; ③ The growth conditions for growing an AlGaN structure with an Al component of 25% are: MO flow rate, wherein the TMGa flow rate is 180 sccm, the TMAl flow rate is 450 sccm, and the ammonia flow rate is 2000 sccm; the surface temperature is 1050°C, the growth time is 45 min, and the thickness of the AlGaN structure with an Al component of 25% is 1500 nm.

[0112] (3) A high-resistance GaN layer is grown on the high-resistance buffer layer of step (2) using an MOCVD device. The high-resistance GaN layer also serves as a buffer layer. The high-resistance GaN layer is a GaN layer grown under low temperature and low pressure conditions. The TMGa flow rate is 200 sccm, the ammonia flow rate is 12,000 sccm, the surface temperature is 980°C, the growth rate is 2.5 μm / h, the growth time is 50 min, and the thickness of the high-resistance GaN layer is 3,000 nm.

[0113] (4) Using MOCVD equipment, a high-temperature GaN first semiconductor layer is continued to be grown on the high-resistance GaN layer in step (3); the growth conditions of the high-temperature GaN first semiconductor layer are: TMGa flow rate is 200 sccm, while the ammonia flow rate is 30,000 sccm, the surface temperature is 1080°C, the growth rate is 2 μm / h, the growth time is 6 minutes, and the thickness of the high-temperature GaN first semiconductor layer is 200 nm.

[0114] (5) Use MOCVD equipment to continue growing the second semiconductor layer on the high-temperature GaN first semiconductor layer of step (4). The growth conditions of the second semiconductor layer are: surface temperature of 1080°C, ammonia flow rate of 8000sccm; the growth conditions of the AlN intercalation layer are: TMAl flow rate of 400sccm, growth time of 16s, and thickness of the AlN intercalation layer of 1nm; the growth conditions of the AlGaN second semiconductor layer are: TMAl flow rate of 400sccm, TMGa flow rate of 180sccm. The corresponding AlGaN second semiconductor layer with an Al component of 25% has a growth time of 80s, and the thickness of the AlGaN second semiconductor layer is 20nm; the growth conditions of the GaN cap layer are: TMGa flow rate of 150sccm, growth time of 15s, and thickness of the GaN cap layer of 2nm.

[0115] (6) A 300 nm silicon dioxide patterned mask layer is grown on the surface of the second semiconductor layer in step (5), and a hole is opened in the silicon dioxide patterned mask layer by photolithography and etching to expose a notch structure where a stress compensation layer needs to be grown.

[0116] (7) Using MBE to grow a 200 nm oxygen-face zinc oxide stress compensation layer at the notch structure of step (6), and using chemical etching to remove the oxygen-face zinc oxide on the surface of the silicon dioxide layer patterned mask layer and the side of the silicon dioxide layer patterned mask layer away from the silicon substrate.

[0117] (8) A silicon dioxide passivation layer is grown on the oxygen-faced zinc oxide stress compensation layer, the silicon dioxide passivation layer covering the second semiconductor layer and the oxygen-faced zinc oxide stress compensation layer. The thickness of the silicon dioxide passivation layer is 1000 nm.

[0118] (9) Etching a portion of the silicon dioxide passivation layer, opening holes in the source and drain regions, and exposing a portion of the second semiconductor layer to form a first exposed portion. Evaporating a Ti / Al / Ni / Au composite metal layer, peeling it off, and placing it in a rapid annealing furnace. After tempering at 650°C, the source and drain electrodes form ohmic contacts with the second semiconductor layer at the first exposed portion.

[0119] (10) Part of the silicon dioxide passivation layer is etched, and a hole is opened in the gate area to expose part of the second semiconductor layer to form a second exposed portion. The gate is photoetched on the second exposed portion and then a Ni / Au metal layer is evaporated. After peeling, it is placed in a rapid annealing furnace and tempered at 400°C to form a Schottky contact with the second semiconductor layer.

[0120] Second embodiment:

[0121] (1) An AlN nucleation layer was grown on a 6-inch silicon substrate using a MOCVD device. The silicon substrate surface was first heat treated in a high-temperature hydrogen environment at 1060°C to remove oxides from the surface of the silicon substrate. A TMAl flow rate of 50 sccm was pre-flowed for 1 min. Ammonia flow rates of 5000 sccm and TMAl flow rates of 400 sccm were then introduced at 1080°C for 50 min to obtain an AlN nucleation layer with a thickness of 200 nm.

[0122] (2) A high-resistance GaN layer is grown on the AlN nucleation layer of step (1) using an MOCVD device. The high-resistance GaN layer serves as a buffer layer. The high-resistance GaN layer is a GaN layer grown under low temperature and low pressure conditions. The TMGa flow rate is 200 sccm, the ammonia flow rate is 12,000 sccm, the surface temperature is 980°C, the growth rate is 2.5 μm / h, the growth time is 50 min, and the thickness of the high-resistance GaN layer is 3,000 nm.

[0123] (3) Using MOCVD equipment to continue growing a high-temperature GaN first semiconductor layer on the high-resistance GaN layer in step (2); the growth conditions of the high-temperature GaN first semiconductor layer are: TMGa flow rate of 200 sccm, ammonia flow rate of 30,000 sccm, surface temperature of 1080°C, growth rate of 2 μm / h, growth time of 6 minutes, and the thickness of the high-temperature GaN first semiconductor layer is 200 nm.

[0124] (4) Using MOCVD equipment, continue to grow the second semiconductor layer on the GaN first semiconductor layer of step (3). The growth conditions of the second semiconductor layer are: surface temperature of 1080 ° C, ammonia flow rate of 8000 sccm; the growth conditions of the AlN intercalation layer are: TMAl flow rate of 400 sccm, growth time of 16 s, and the thickness of the AlN intercalation layer is 1 nm; the growth conditions of the AlGaN second semiconductor layer are: TMAl flow rate of 400 sccm, TMGa flow rate of 180 sccm, the corresponding AlGaN second semiconductor layer with an Al component of 25% is grown for 80 s, and the thickness of the AlGaN second semiconductor layer is 20 nm; the growth conditions of the GaN cap layer are: TMGa flow rate of 150 sccm, growth time of 15 s, and the thickness of the GaN cap layer is 2 nm.

[0125] (5) A stress compensation layer is grown on the surface of the second semiconductor layer in step (4), and a nitrogen-faced GaN layer with a thickness of 100 nm is grown using MBE. The stress compensation layer in other areas except near the gate is removed by photolithography and etching to obtain a patterned nitrogen-faced GaN layer stress compensation layer.

[0126] (6) A silicon dioxide passivation layer is grown on the stress compensation layer of step (5), the silicon dioxide passivation layer covers the second semiconductor layer and the nitrogen-faced GaN layer stress compensation layer, and the thickness of the passivation layer is 1000 nm.

[0127] (7) Etching a portion of the silicon dioxide passivation layer, opening holes in the source and drain regions, and exposing a portion of the second semiconductor layer to form a first exposed portion. Evaporating a Ti / Al / Ni / Au composite metal layer, peeling it off, and placing it in a rapid annealing furnace. After tempering at 650°C, the source and drain electrodes form ohmic contacts with the second semiconductor layer at the first exposed portion.

[0128] (8) Etching a portion of the silicon dioxide passivation layer, opening a gate area, exposing a portion of the second semiconductor layer to form a second exposed portion, photolithography the gate on the second exposed portion, and then evaporating a Ni / Au metal layer. After peeling, the layer is placed in a rapid annealing furnace and annealed at 400°C to form a Schottky contact with the second semiconductor layer.

[0129] The present disclosure provides a method for fabricating a high electron mobility transistor (HEMT), comprising: providing a substrate; forming an epitaxial layer on a surface of the substrate, the epitaxial layer comprising at least a first semiconductor layer and a second semiconductor layer disposed on the first semiconductor layer, the first semiconductor layer and the second semiconductor layer being a heterostructure; forming a stress compensation layer on the epitaxial layer, wherein the piezoelectric coefficient of the stress compensation layer is opposite to the piezoelectric coefficient of the second semiconductor layer; disposing a source electrode, a drain electrode, and a gate electrode on the epitaxial layer, the source electrode, the drain electrode, and the gate electrode being spaced apart from each other; the gate electrode having a sidewall facing the drain electrode, the stress compensation layer contacting the sidewall. By disposing the stress compensation layer having a piezoelectric coefficient opposite to that of the second semiconductor layer on the sidewall of the gate electrode facing the drain electrode, an inverse piezoelectric stress opposite to that of the second semiconductor layer can be generated under high voltage, thereby reducing stress deformation of the second semiconductor layer under high voltage and thereby increasing the breakdown electric field strength of the second semiconductor layer. Furthermore, the two-dimensional electron gas concentration at the gate edge can be reduced to regulate the gate edge electric field strength, thereby reducing the need for multi-stage field plates and simplifying the device fabrication process.

[0130] The above description is merely an implementation method of the embodiment of the present disclosure and does not limit the patent scope of the embodiment of the present disclosure. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of the embodiment of the present disclosure, or directly or indirectly applied in other related technical fields, shall be included in the patent protection scope of the embodiment of the present disclosure.

Claims

1. A high electron mobility transistor, characterized in that include: substrate; an epitaxial layer disposed on a surface of the substrate, the epitaxial layer comprising at least: a first semiconductor layer and a second semiconductor layer disposed on the first semiconductor layer, the first semiconductor layer and the second semiconductor layer being a heterostructure; A source electrode, a drain electrode and a gate electrode are arranged on the epitaxial layer at intervals, and the gate electrode is arranged between the source electrode and the drain electrode; wherein the gate electrode has a sidewall facing the drain electrode; a stress compensation layer, disposed on the second semiconductor layer and in contact with the sidewall of the gate; the piezoelectric coefficient of the stress compensation layer is opposite to the piezoelectric coefficient of the second semiconductor layer; The thickness of the stress compensation layer is greater than 20 nm and less than or equal to 1000 nm.

2. The high electron mobility transistor according to claim 1, wherein The stress compensation layer is spaced apart from the drain electrode.

3. The high electron mobility transistor according to claim 2, wherein: Along an arrangement direction from the gate to the drain, a ratio of a width of the stress compensation layer to a width of a region between the gate and the drain is 2% to 20%.

4. The high electron mobility transistor according to claim 1, wherein The material of the stress compensation layer is nitrogen-faced nitride or oxygen-faced zinc oxide.

5. The high electron mobility transistor according to claim 4, wherein: The nitrogen-faced nitride includes nitrogen-faced gallium nitride.

6. The high electron mobility transistor according to claim 1, wherein The thickness of the stress compensation layer is smaller than the thickness of the gate.

7. The high electron mobility transistor according to claim 1, wherein The stress compensation layer includes a plurality of sub-stress compensation layers, and the plurality of sub-stress compensation layers are disposed at intervals on the sidewall of the gate.

8. The high electron mobility transistor according to claim 1, wherein The high electron mobility transistor further comprises: A passivation layer is provided between the source electrode and the gate electrode and between the gate electrode and the drain electrode, and the passivation layer covers the stress compensation layer; and the thickness of the passivation layer is greater than or equal to the thickness of the stress compensation layer.

9. The high electron mobility transistor according to claim 1, wherein: The second semiconductor layer includes a gallium-faced AlGaN layer; or the second semiconductor layer includes an AlN insertion layer, a gallium-faced AlGaN layer and a GaN cap layer.

10. A method for preparing a high electron mobility transistor, characterized in that: include: providing a substrate; forming an epitaxial layer on the surface of the substrate, wherein the epitaxial layer at least comprises: a first semiconductor layer and a second semiconductor layer disposed on the first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are heterogeneous structures; forming a stress compensation layer on the epitaxial layer, wherein the piezoelectric coefficient of the stress compensation layer is opposite to the piezoelectric coefficient of the second semiconductor layer; and the thickness of the stress compensation layer is greater than 20 nm and less than or equal to 1000 nm; A source, a drain and a gate are arranged on the epitaxial layer, and the source, the drain and the gate are spaced apart from each other; the gate has a side wall facing the drain, and the stress compensation layer is in contact with the side wall.

11. The preparation method according to claim 10, characterized in that: The forming of a stress compensation layer on the epitaxial layer comprises: Preparing a patterned mask layer on a side of the second semiconductor layer away from the substrate, wherein the patterned mask layer is configured to be hollowed out within a preset range of the sidewall contact of the gate; growing the stress compensation layer on the patterned mask layer and the second semiconductor layer; The patterned mask layer and the stress compensation layer on the patterned mask layer are removed.

12. The preparation method according to claim 10, characterized in that The forming of a stress compensation layer on the epitaxial layer comprises: forming a first stress compensation layer on a side of the second semiconductor layer away from the substrate; The first stress compensation layer is etched to retain the second stress compensation layer within a preset range in contact with the sidewall of the gate, thereby obtaining the stress compensation layer.

13. The preparation method according to claim 10, characterized in that After forming the stress compensation layer on the epitaxial layer and before providing the source, drain and gate on the epitaxial layer, the method further includes: forming a passivation layer on a side of the stress compensation layer and the second semiconductor layer away from the substrate; The step of providing a source electrode, a drain electrode and a gate electrode on the epitaxial layer comprises: The passivation layer is etched to form openings and the source electrode, the drain electrode and the gate electrode are prepared at the openings.

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