Semiconductor device to be etched and method for manufacturing the same

Abstract

The application discloses a semiconductor device to be etched, a preparation method of the semiconductor device to be etched, a semiconductor device and an etching method of the semiconductor device. The semiconductor device to be etched comprises a semiconductor device body and a mask layer. The semiconductor device body comprises a surface to-be-etched layer. The mask layer is located on the to-be-etched layer. The mask layer is a patterned structure and has a plurality of openings for exposing the to-be-etched layer. The upper width of the cross section of the opening is greater than the lower width. The surface of the to-be-etched layer corresponding to the opening of the mask layer is formed with a plurality of pits. Metal nanoparticles are arranged in the pits. The semiconductor device can improve the etching rate when photoelectrochemical etching is performed, and the groove sidewall is not damaged.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device to be etched and a preparation method thereof, a semiconductor device and an etching method thereof. BACKGROUND

[0002] Wide Band Gap (WBG) semiconductor (such as silicon carbide SiC and gallium nitride GaN) materials are considered to be the most potential materials in the next generation of power electronic devices. Wide Band Gap semiconductor materials have excellent semiconductor characteristics such as wide band gap, high breakdown, high frequency, etc. For example, the breakdown field strength of GaN material is more than 10 times that of Si-based semiconductor, which makes the superior performance of GaN material have a broad application prospect in the fields of radio frequency microwave and power electronics.

[0003] In existing gallium nitride-based devices, whether it is a radio frequency device, a power device or a light-emitting device, in order to form a step shape, a trench shape of a trench gate or a gallium nitride structure of a certain shape, etching of the gallium nitride layer is required. In the prior art, etching of gallium nitride is mainly divided into two categories: one is dry etching, and the other is wet etching. However, due to the larger trench shape of gallium nitride-based power devices or radio frequency devices than that of silicon-based devices, such as the width of the trench gate of a gallium nitride-based HEMT (High Electron Mobility Transistor) device being 0.3-0.8 microns (and the width of the trench can be up to 1 micron in order to increase the width of the gate), when using dry etching, due to the larger size and slower etching rate, and when etching a larger size step or trench, the trench sidewall will be damaged more seriously, forming more dangling bonds, which is not conducive to the migration of charge carriers. Wet etching process is not conducive to the formation of vertical steps and vertical trench structures, because wet etching has isotropy, which can keep the etching rate consistent in all directions.

[0004] In the prior art, there is a photoelectrochemical etching system for etching gallium nitride. The photoelectrochemical etching method uses ultraviolet light emitted by an ultraviolet light source to irradiate the surface of the gallium nitride through an etching solution, and generates holes by using UV light irradiation, thereby enabling photoelectrochemical etching. However, the existing photoelectrochemical etching method has the disadvantage that the distance between the gallium nitride layer to be etched and the ultraviolet light source is far, and the gallium nitride layer to be etched is usually a smooth surface, resulting in unsatisfactory absorption of ultraviolet light, which requires long-time ultraviolet irradiation for etching, greatly prolonging the etching time. SUMMARY

[0005] The present application aims to provide a semiconductor device to be etched and a preparation method thereof, a semiconductor device and an etching method thereof, for improving the etching rate.

[0006] The object of the present application is achieved by the following technical solutions:

[0007] A semiconductor device to be etched, comprising:

[0008] a semiconductor device body, the semiconductor device body comprising a surface of a layer to be etched;

[0009] a mask layer, the mask layer being located on the layer to be etched, the mask layer being a patterned structure and having a plurality of openings for exposing the layer to be etched, the upper width of the cross section of the opening being greater than the lower width, the surface of the layer to be etched corresponding to the openings of the mask layer forming a plurality of pits, and the pits being provided with metal nanoparticles.

[0010] Preferably, the upper surface of the mask layer also forms a plurality of pits, the depth of the pits being 60-120 nm, and the opening diameter of the pits being 60-120 nm.

[0011] Preferably, the metal nanoparticles are silver or copper metal particles, and the diameter of the metal nanoparticles ranges from 50-80 nm.

[0012] Preferably, the layer to be etched is a nitride layer containing group III elements, and the material of the mask layer is silicon oxide or silicon nitride.

[0013] A method for preparing a semiconductor device to be etched, comprising:

[0014] Step S1: forming a patterned mask layer on the layer to be etched on the surface of the semiconductor device body, the mask layer having a plurality of openings, the upper width of the cross section of the opening being greater than the lower width;

[0015] Step S2: forming a plurality of pits on the surface of the layer to be etched corresponding to the openings of the mask layer;

[0016] Step S3: forming metal nanoparticles in the pits.

[0017] Preferably, the step S1 comprises:

[0018] Step S11: forming a mask material layer on the layer to be etched on the surface of the semiconductor device body, the thickness of the mask material layer being 200-500 nm, and forming a photoresist layer on the mask material layer;

[0019] Step S12: exposing and developing the photoresist layer to form a patterned photoresist layer;

[0020] Step S13: using the patterned photoresist layer as a mask, removing part of the mask material layer by wet etching to form a patterned mask layer, and removing the remaining photoresist layer.

[0021] Preferably, the step S2 comprises: forming a plurality of pits on the surface of the to-be-etched layer corresponding to the opening of the mask layer and the surface of the mask layer by using a plasma bombardment method.

[0022] Preferably, in the plasma bombardment method, the gas flow is 80-150 sccm, the acceleration voltage is 300-400 KeV, and the bombardment time is 10-40 s.

[0023] Preferably, the step S3 comprises: coating the suspension liquid containing metal nanoparticles on the mask layer and the to-be-etched layer, and after drying, only the metal nanoparticles are retained in the pits.

[0024] An etching method, comprising:

[0025] Step T1: placing the to-be-etched semiconductor device of any one of the above embodiments in a photoelectrochemical etching system, immersing the to-be-etched semiconductor device in an etching solution, and irradiating the to-be-etched semiconductor device with ultraviolet light to perform etching.

[0026] Preferably, the photoelectrochemical etching system comprises: a power supply, an ultraviolet lamp, a bearing table, a container containing an etching solution, an ammeter, and a PH tester, the bearing table is arranged at the bottom of the container and is used to support the to-be-etched semiconductor device, the anode plate of the power supply is used to connect to the to-be-etched semiconductor device, the cathode plate of the power supply is used to be placed in the etching solution, thereby forming an etching loop, the ammeter is arranged in the etching loop, and the ammeter is used to detect the change trend of the current in the etching loop, and the PH tester is arranged in the etching solution and is used to monitor the PH value of the etching solution.

[0027] The step T1 comprises: placing the to-be-etched semiconductor device on the bearing table at the bottom of the container containing the etching solution, controlling the power supply to form an etching loop, and simultaneously using the ultraviolet lamp to irradiate the to-be-etched layer of the to-be-etched semiconductor device and the mask layer to perform etching.

[0028] Preferably, the etching method further comprises:

[0029] Step T2: removing the residues of the metal nanoparticles on the to-be-etched semiconductor device, and cleaning and drying the to-be-etched semiconductor device.

[0030] A semiconductor device obtained by using the etching method of any one of the above embodiments.

[0031] Preferably, the semiconductor device is a gallium nitride-based LED device, a laser, a HEMT device, or a MOS transistor.

[0032] Compared with the prior art, the present application has at least the following beneficial effects:

[0033] By setting a pit on the surface of the layer to be etched of the semiconductor device body at the opening of the mask layer and setting a metal nanoparticle in the pit, when the photoelectrochemical etching is performed on the semiconductor device to be etched, when the incident light irradiates on the layer to be etched, the refraction and reflection of the metal nanoparticle and the diffuse scattering effect of the pit can effectively prolong the contact time and action time of the incident light with the layer to be etched, thereby improving the etching rate and realizing the effective absorption of the incident light. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D 、 Figure 1E is a structural schematic diagram of the preparation method of the semiconductor device to be etched according to an embodiment of the present application;

[0035] Figure 2 is a flowchart of the preparation method of the semiconductor device to be etched according to an embodiment of the present application;

[0036] Figure 3 is a structural schematic diagram of the photoelectrochemical etching system according to an embodiment of the present application;

[0037] Figure 4 is a top view of the semiconductor device to be etched according to an embodiment of the present application, which has pits formed on the layer to be etched and the mask layer;

[0038] Figure 5 is a structural schematic diagram of the semiconductor device according to an embodiment of the present application.

[0039] In the figure: 1, semiconductor device body; 2, mask material layer; 201, mask layer; 3, layer to be etched; 300, pit; 4, opening; 5, photoresist layer; 6, metal nanoparticle; 7, ultraviolet lamp; 8, power supply; 80, anode plate; 81, cathode plate; 9, bearing table; 10, container; 11, PH tester; 12, ammeter. DETAILED DESCRIPTION

[0040] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and thus description of the same will be simplified or omitted.

[0041] The expression position and direction of the words described in the present application are illustrated by taking the drawings as an example, but changes can also be made according to needs, and the changes are included in the protection scope of the present application.

[0042] Embodiment 1

[0043] With reference to Figures 1A to 2 The present embodiment provides a semiconductor device to be etched and a preparation method thereof, and the semiconductor device to be etched includes a semiconductor device body 1 and a mask layer 201.

[0044] The present application does not limit the specific structure and type of the semiconductor device body 1, which can be a gallium nitride-based LED device, a HEMT device, a power device, or a MOS transistor, etc. The semiconductor device body 1 can also be a to-be-etched device formed in an intermediate step of manufacturing the above-mentioned devices, which refers to a semiconductor device that needs to be etched subsequently. No matter what type of device is listed above, as long as gallium nitride (or doped gallium nitride) needs to be etched during the manufacturing process, the method mentioned in the present solution can be used for preparation.

[0045] Taking the formation of a HEMT device as an example. The formed HEMT device includes a substrate, a channel layer, a barrier layer, a gate recess structure, a gate recess gate dielectric layer, and a gate electrode in the barrier layer, and a source and drain electrode, etc.

[0046] The substrate can be a silicon substrate, a sapphire substrate, a silicon carbide substrate, or a gallium nitride substrate, etc., and is preferably a gallium nitride substrate.

[0047] If a gallium nitride substrate is selected and an epitaxial layer structure is manufactured thereon, since the HEMT device structure is a gallium nitride system, the gallium nitride crystal formed by homoepitaxy has good quality and fewer defects, and there is no stress caused by lattice mismatch, and there is no need to form an additional buffer structure; if a sapphire substrate or a silicon carbide substrate is used as the substrate, a buffer layer needs to be formed on the substrate first, and the buffer layer can be an AlN layer. The buffer layer mainly relieves the lattice mismatch between the substrate and the gallium nitride epitaxial structure layer, and reduces the stress between the substrates.

[0048] The channel layer and the barrier layer are grown on the substrate to form an AlGaN / GaN heterojunction structure.

[0049] The channel layer can be a GaN channel layer formed by vapor phase epitaxy, and the barrier layer can be an AlGaN barrier layer, wherein the content of Al is 10-20 mol%. A recess is etched in the gate region of the barrier layer, and the width of the recess is 0.8 microns. In order to increase the area of the gate, the width of the recess can be set to more than 1 micron, and the depth is about 100 nm.

[0050] In the process of forming the gate trench, dry etching not only has a slow etching rate, but also causes more severe damage to the trench sidewalls during trench formation. This damages GaN bonding on the sidewalls, resulting in more dangling bonds, which is not conducive to carrier migration.

[0051] To address the aforementioned issues, in this embodiment, the semiconductor device body 1 includes a surface layer 3 to be etched. The surface layer 3 to be etched can be at least one of the N-type layer, active layer, P-type layer, and barrier layer in the semiconductor device body 1. The semiconductor device body 1 can be a structure including a substrate, a buffer layer, an N-type layer, an active layer (light-emitting layer), a P-type layer, a barrier layer, etc. This embodiment does not impose specific limitations and may also include an electron blocking layer, etc.

[0052] refer to Figures 1A to 1E , Figure 4 As shown, the mask layer 201 is located on the layer 3 to be etched. The material of the mask layer 201 is preferably silicon oxide or silicon nitride. The mask layer 201 has a patterned structure and has a number of openings 4 for exposing the layer 3 to be etched. Specifically, the openings 4 extend from the top of the mask layer 201 to the bottom of the mask layer 201. The upper width of the opening 4 perpendicular to the extension direction is greater than the lower width, and the size of the opening 4 can gradually decrease from top to bottom.

[0053] The surface of the layer to be etched 3 at the opening 4 of the mask layer 201 has several pits 300, specifically, such as Figure 1D As shown, a pit 300 is formed on the bottom surface of an opening 4. The bottom surface of an opening 4 is the part of the surface of the layer 3 to be etched that is exposed through the opening 4. Metal nanoparticles 6 are disposed in the pit 300. Specifically, when the semiconductor device to be etched is placed in a photoelectrochemical etching system for photoelectrochemical etching, the pit 300 and the metal nanoparticles 6 disposed in the pit 300 allow incident light to irradiate the layer 3 to be etched at the opening 4 of the corresponding mask layer 201. The refraction effect of the metal nanoparticles 6 combined with the diffuse scattering effect of the pit 300 can effectively prolong the contact time and interaction time between the incident light and the layer 3 to be etched, thereby achieving sufficient and effective absorption of the incident light and improving the etching rate. As etching proceeds, the metal particles in the pit 300 on the surface of the layer to be etched will sink to the inner wall of the formed via or trench under the action of gravity, and continue to play a refraction role, eventually forming a vertical step, vertical via, or vertical trench structure of the layer 3 to be etched. Applying voltage and light during wet etching accelerates the etching process. The etching rate in the illuminated area (exposed area) is much higher than that in the unilluminated area (area blocked by mask layer 201). This results in a better etching morphology and avoids damage to GaN bonding on the sidewalls and the formation of more dangling bonds, as is the case with dry etching, thus ensuring carrier migration.

[0054] As a further implementation of the present embodiment, the upper surface of the mask layer 201 is also formed with a plurality of pits 300, specifically, as shown in Figure 1E The pits 300 are formed on the upper surface of the mask layer 201 where no opening 4 is provided and the inner side wall of the opening 4, and the depth of the pits 300 on the mask layer 201 and the diameter of the opening 4 are respectively 60-120nm, for example, 70nm, 80nm, 90nm, 100nm, 110nm. Specifically, the pits 300 on the mask layer 201, especially the pits 300 on the side wall of the trapezoidal structure mask layer 201 and the metal particles in the pits can effectively refract the incident light into the to-be-etched layer 3 at the opening 4 of the corresponding mask layer 201, achieving the light focusing effect of the incident light, further prolonging the contact time and action time of the incident light with the to-be-etched layer 3, improving the utilization rate of the incident light, and thus improving the etching rate.

[0055] As a further implementation of the present embodiment, the metal nanoparticles 6 are preferably silver or copper metal particles, and the diameter of the metal nanoparticles 6 ranges from 50nm to 80nm. The arrangement of the metal nanoparticles 6 is helpful for the absorption of the incident light by the to-be-etched layer during the subsequent photoelectrochemical etching system etching of the to-be-etched layer. Specifically, during the photoelectrochemical etching process, the etching solution has weak acidity. The metal nanoparticles 6 first need to ensure that they will not react in an acidic environment and will not affect the effects of refraction and reflection of the incident light. Secondly, the metal nanoparticles 6 also need to have high light reflection performance and cannot absorb the incident light. Therefore, the silver or copper metal particles with the above diameter range not only will not react with the etching solution, but also can prolong the contact time of the incident light with the to-be-etched layer 3 through the diffuse scattering effect of the pits 300 and the refraction and reflection of the metal nanoparticles 6, improve the action time of the to-be-etched layer 3 with the incident light, and improve the coupling degree between the incident light and the metal nanoparticles 6, so as to achieve the maximum absorption of the incident light, thereby greatly improving the utilization rate of the incident light, and finally achieving the effect of improving the etching rate.

[0056] As a further implementation of the present embodiment, the to-be-etched layer 3 is a nitride layer containing group III elements, and specifically, the to-be-etched layer 3 is a gallium nitride (GaN) layer.

[0057] Referring to Figures 1A to 1E , Figure 2 The present embodiment also provides a preparation method of the to-be-etched semiconductor device according to any one of the above embodiments, which comprises steps S1-S3.

[0058] Step S1: forming a patterned mask layer 201 on the to-be-etched layer 3 on the surface of the semiconductor device body 1, the to-be-etched layer 3 being a gallium nitride layer, and the mask layer 201 having a plurality of openings 4, the upper width of the cross section of the opening 4 being greater than the lower width.

[0059] As a further implementation form of the present embodiment, step S1 comprises: steps S11-S13.

[0060] Step S11: Forming a mask material layer 2 on the surface of the semiconductor device body 1 to be etched layer 3, specifically, the material of the mask material layer 2 is preferably silicon nitride or silicon oxide, which can be formed on the surface of the semiconductor device body 1 to be etched layer 3 by chemical vapor deposition or atomic layer deposition, the thickness of the mask material layer 2 is 200-500nm, which is thicker than the thickness of the traditional mask material layer 2, which can ensure that the entire thickness of the mask material layer will not be processed during the subsequent plasma treatment, and there will still be a certain thickness of the mask material layer remaining as a thickness etching mask structure from the thickness direction, and then spin coating a photoresist layer 5 on the mask material layer 2.

[0061] Step S12: Exposing and developing the photoresist layer 5 to form a patterned photoresist layer 5. Exposure and development can be carried out using known techniques, which will not be described here.

[0062] Step S13: Using the patterned photoresist layer 5 as a mask, removing part of the mask material layer 2 by wet etching to form a patterned mask layer 201. Since wet etching is isotropic etching, it will form a patterned mask layer 201 with a large upper end and a small lower end in the opening 4 of the mask material layer 2. Such a patterned structure facilitates subsequent surface treatment of the mask layer 201 and the formation of metal nanoparticles 6 on the surface. After forming the patterned mask layer 201, the remaining photoresist layer 5 is removed by ashing.

[0063] Step S2: Forming a plurality of pits 300 on the surface of the to-be-etched layer 3 corresponding to the opening 4 of the mask layer 201.

[0064] As a further implementation form of the present embodiment, step S2 comprises: using a plasma bombardment method to form a plurality of pits 300 on the surface of the to-be-etched layer 3 corresponding to the opening 4 of the mask layer 201, preferably using an inert gas plasma with a larger atomic diameter to bombard the entire surface, for example, argon plasma, which has a larger atomic diameter and energy, and can form the desired pits 300 on the surface of the mask layer 201 and the to-be-etched layer 3.

[0065] The pits 300 can also be formed by first coating a metal film on the to-be-etched layer 3 and the mask layer 201, then removing part of the structure on the to-be-etched layer 3 and the mask layer 201 by wet etching, and finally removing the metal film, but the pits 300 are preferably formed by the plasma bombardment method which has a simpler process.

[0066] When the mask layer 201 is silicon nitride, since silicon nitride (Si3N4) has three crystal structures, namely, α, β and γ (trigonal, hexagonal and cubic silicon nitride), no matter what crystal structure of silicon nitride, under high-energy plasma bombardment, due to the weak bond energy between the crystal boundaries and atoms, it is easy to be bombarded to form the pits 300. When the mask layer 201 is silicon oxide (silicon dioxide), silicon dioxide is a long-range ordered arrangement of silicon atoms and oxygen atoms to form a crystalline state, and a short-range ordered or long-range disordered arrangement to form an amorphous silicon dioxide. In the silicon dioxide crystal, the silicon atom is at the center of the tetrahedron, and the four oxygen atoms are at the four corners of the tetrahedron. Many such tetrahedrons are connected through the oxygen atoms at the corners, and each oxygen atom is shared by two tetrahedrons, that is, each oxygen atom is combined with two silicon atoms. No matter whether it is a crystalline or amorphous silicon dioxide material, under plasma bombardment, the atomic bond at the weak atomic bond will be bombarded to form the pits 300. Therefore, the silicon nitride and silicon oxide are selected as the mask layer 201, which not only can effectively play a masking role in photoelectrochemical etching, but also is conducive to the formation of the desired pits 300.

[0067] As a further embodiment of the present embodiment, in the plasma bombardment method, the argon gas flow is 80-150 sccm, the acceleration voltage is 300-400 KeV, and the bombardment time is 10-40 s. Using the above parameters for plasma bombardment, the pits 300 with a depth of 60-120 nm and an opening 4 diameter of 60-120 nm can be formed.

[0068] It should be noted that, taking the N-type gallium nitride layer or the P-type gallium nitride layer as an example, since the N-type gallium nitride layer or the P-type gallium nitride layer has crystal boundaries or defects, the atomic energy at the crystal boundaries or defects is weak, and the pits are easy to form under plasma bombardment. When the pits 300 are formed by the plasma bombardment method, the pits 300 will also be formed on the exposed gallium nitride layer. Since the exposed area will be removed eventually, the formation of the pits 300 on the exposed gallium nitride layer will not affect the device performance. During the plasma bombardment process, the thickness of the mask layer 201 will be thinned, but since the thickness of the mask layer 201 is thick, it will not affect the patterning structure.

[0069] Step S3: Forming metal nanoparticles 6 in the pits 300.

[0070] Specifically, first, the suspension containing the metal nanoparticles 6 is prepared, silver or copper metal nanoparticles 6 are selected, the metal nanoparticles 6 are placed in an organic solvent, the organic solvent can be benzene, toluene, xylene, pentane, hexane, octane, styrene, trichloroethylene, ethylene glycol ether, etc. common organic solvents, and then a suspension containing the metal nanoparticles 6 is formed after high-speed stirring at 400-600 rpm. Then, the suspension containing the metal nanoparticles 6 is coated on the mask layer 201 and the layer to be etched 3, and dried in a vacuum for 5-30 min, the drying temperature is controlled at 120-150 degrees Celsius, and after the organic solvent volatilizes, only the metal nanoparticles 6 remain in the pits 300.

[0071] Example 2

[0072] Referring to Figures 3 to 5 The semiconductor device of the present embodiment is obtained by using the following etching method, which comprises the following steps T1, which can further comprise the following step T2.

[0073] Step T1: Place the semiconductor device to be etched of any one of the above embodiments 1 in a photoelectrochemical etching system, immerse the semiconductor device to be etched in the etching solution, and irradiate ultraviolet light on the semiconductor device to be etched to perform etching.

[0074] As a further embodiment of the present embodiment, the photoelectrochemical etching system comprises a power supply 8, an ultraviolet lamp 7, a support table 9, a container 10 containing the etching solution, an ammeter 12 and a PH tester 11, the support table 9 is arranged at the bottom of the container 10 and is used to support the semiconductor device to be etched, the material of the support table 9 is not limited here, which can support and not react with the reaction solution, such as metal, ceramic or organic material. The height of the support table can be 0.1-5 mm. The anode plate 80 of the power supply 8 is used to connect to the semiconductor device to be etched, the cathode plate 81 of the power supply 8 is used to be placed in the etching solution, thereby forming an etching loop, the ammeter 12 is electrically connected in the etching loop, the ammeter 12 is used to detect the change trend of the current in the etching loop, and the PH tester 11 is arranged in the etching solution and is used to monitor the PH value of the etching solution.

[0075] Specifically, after the semiconductor device to be etched is placed on the support table 9 at the bottom of the container 10 containing the etching solution, the anode plate 80 of the power supply 8 is connected to the semiconductor device to be etched, the cathode plate 81 of the power supply 8 is used to be placed in the etching solution, the power supply 8 provides etching current, the etching solution acts as an electrolyte and a corrosive solution, and a complete etching loop is formed after the power supply 8 is controlled to be powered on, and at the same time, the ultraviolet lamp 7 is used to irradiate the etching layer 3 and the mask layer 201 of the semiconductor device to be etched. Etching is performed. It should be noted that the positions where the probes of the ammeter 12 and the PH tester 11 are placed are best not to block ultraviolet light. During the etching process, the electrode on the etching layer 3 is connected to the anode of the power supply 8, and the cathode of the power supply 8 is connected to the etching solution through the cathode plate 81. After the power supply 8 is powered on, the current flows through the anode of the power supply 8, the ammeter 12, the gallium nitride layer to be etched, the etching solution, and the cathode of the power supply 8.

[0076] Further, as the etching solution, an etching solution obtained by mixing a potassium hydroxide (KOH) aqueous solution and a potassium peroxydisulfate (K2S2O8) aqueous solution can be used. This etching solution is prepared by mixing 0.001M-0.005M of the KOH aqueous solution and 0.05M-0.1M of the K2S2O8 aqueous solution at a ratio of 1:1.

[0077] It should be noted that the KOH aqueous solution alone is alkaline, and the K2S2O8 aqueous solution alone is acidic. If the concentration of the KOH aqueous solution is too high (for example, greater than 0.01M), the etching solution mixed with the KOH aqueous solution and the K2S2O8 aqueous solution will become alkaline. By moderately reducing the concentration of the KOH aqueous solution, the etching solution mixed with the KOH aqueous solution and the K2S2O8 aqueous solution can be made acidic.

[0078] By irradiating the etching layer 3 with ultraviolet light having a wavelength of 365nm or less, pairs of holes and electrons are generated in the GaN layer to be etched. Through the generated holes, the GaN is decomposed into Ga 3+ and N2 (Formula 1), and further, Ga 3+ is oxidized by hydroxide ions (OH - ) to form gallium oxide (Ga2O3) (Formula 2). The generated gallium oxide Ga2O3 is dissolved in acid (or base). In this way, electrochemical etching of GaN is performed. It should be noted that the generated holes react with water, and water is decomposed to produce oxygen (Formula 3).

[0079] GaN(s)+3h + →Ga 3+ +0.5N2(g)↑ (Formula 1)

[0080] Ga 3+ +3OH -→ 0.5Ga2O3 + 1.5H2O (l) (Formula 2)

[0081] H2O (l) + 2h + → 0.5O2(g)↑ + 2H + (Formula 3)

[0082] As a further embodiment of the present embodiment, after step T2: etching is completed, the residue of the metal nanoparticles 6 on the semiconductor device to be etched is removed, the semiconductor device to be etched is cleaned and dried, and specifically, the cleaning includes the metal nanoparticles 6 remaining on the surface to be etched and the participating etching solution, the residual metal nanoparticles 6 are removed using 10% dilute nitric acid, then the semiconductor device to be etched is cleaned using deionized water and dried using nitrogen, and finally the remaining mask layer 201 is removed using a wet etching or dry etching commonly used in the art.

[0083] Comparative Example 1:

[0084] In the present comparative example, the preparation method of the semiconductor device to be etched includes steps S11-S13.

[0085] Step S11: Taking the preparation of a HEMT device as an example, a mask material layer 2 is formed on the etching layer 3 on the surface of the semiconductor device body 1 by chemical vapor deposition or atomic layer deposition, the semiconductor device body 1 includes a substrate layer, a channel layer, and a barrier layer arranged in order from bottom to top, the etching layer 3 is a gallium nitride layer, the mask layer 201 is arranged on the channel layer, the mask layer 201 is a silicon oxide material and has a thickness of 400 nm, and the etching layer 3 is the channel layer on the semiconductor device body 1, at this time, a step structure is formed in the channel layer and is used to form an electrode later.

[0086] Step S12: The photoresist layer 5 is exposed and developed to form a patterned photoresist layer 5.

[0087] Step S13: Taking the patterned photoresist layer 5 as a mask, part of the mask material layer 2 is removed by wet etching to form a patterned mask layer 201. The etching method of the semiconductor device to be etched includes steps T1 and T2:

[0088] Step T1: The semiconductor device to be etched of the present comparative example is placed in the photoelectrochemical etching system containing the etching solution of Example 2, the etching solution is a mixture of 0.002M KOH aqueous solution and 0.05M K2S2O8 aqueous solution in a ratio of 1:1, a complete etching loop is formed after the power supply 8 is powered on, the power supply 8 is powered on in a constant voltage mode for electrochemical etching, the voltage value is kept at 10V, the etching time is 30min, and the irradiation wavelength is below 362nm ultraviolet light.

[0089] Step T2: After etching, deionized water is used for cleaning, and nitrogen is used for drying. Then, the remaining mask structure layer is removed, and the etching of the semiconductor device to be etched is completed.

[0090] Comparative Example 2:

[0091] The semiconductor device to be etched in this comparative example and the semiconductor device to be etched in Comparative Example 1 are the same batch of devices, and the etching methods are basically the same. The only difference is that in step T1, the etching time of this comparative example is 60 min.

[0092] Comparative Example 3:

[0093] The semiconductor device to be etched in this comparative example and the semiconductor device to be etched in Comparative Example 1 are the same batch of devices, and the etching methods are basically the same. The only difference is that in step T1, the etching time of this comparative example is 90 min.

[0094] Application Example 1:

[0095] The semiconductor device to be etched in this application example and the semiconductor device to be etched in Comparative Example 1 are the same batch of devices, and the etching methods are basically the same. The only difference is that (1) the preparation method of the semiconductor device to be etched further includes steps S2 and S3; (2) in step T1, the etching time of this comparative example is 30 min; (3) the method of step T2 is different.

[0096] Step S2: A plasma bombardment method is used, in which the argon gas flow is 100 sccm, the acceleration voltage is 350 KeV, and the bombardment time is 20 s. A plurality of pits 300 are formed on the surface of the opening 4 of the mask layer 201 corresponding to the etching layer 3. After processing by FIB, the depth is measured to be in the range of 100 nm, and the diameter of the opening 4 is in the range of 80 nm.

[0097] Step S3: Silver nanoparticles are placed in a benzene solvent, and then a suspension containing metal nanoparticles 6 is formed after high-speed stirring at 500 rpm. The suspension containing metal nanoparticles 6 is coated on the mask layer 201 and the etching layer 3, and is dried under vacuum for 20 min, with the drying temperature controlled at 120 degrees Celsius. After the organic solvent is volatilized, only the metal nanoparticles 6 remain in the pits 300.

[0098] Step T2: After etching, 10% dilute nitric acid is used to easily remove the residual metal particles. After removing the metal particles, deionized water is used for cleaning, and nitrogen is used for drying. Then, the remaining mask structure layer is removed, and the etching of the semiconductor device to be etched is completed.

[0099] Application Example 2:

[0100] The semiconductor devices to be etched in the present application example and application example 1 are the same batch of devices, and the etching method is basically the same, the difference is only that in step T1, the etching time of the present application example is 60 min.

[0101] Application Example 3

[0102] The semiconductor devices to be etched in the present application example and application example 1 are the same batch of devices, and the etching method is basically the same, the difference is only that in step T1, the etching time of the present application example is 90 min.

[0103] The etching depth of the semiconductor devices to be etched in the comparative examples 1 to 3 and the application examples 1 to 3 was measured by the FIB processing test method, and the roughness root mean square was calculated, and the test results are shown in Table 1.

[0104] Table 1

[0105] Serial Number Experimental content Etching time Etching depth Root mean square roughness 1 Comparative Example 1 30min 20nm 0.52nm 2 Comparative Example 2 60min 58nm 0.54nm 3 Comparative Example 3 90min 85nm 0.56nm 4 Application Example 1 30min 150nm 0.50nm 5 Application Example 2 60min 415nm 0.58nm 6 Application Example 3 90min 635nm 0.55nm

[0106] From the data in Table 1 above, it can be seen that in the application examples of the present application, compared with comparative examples 1 to 3 without pits 300 and metal nanoparticles 6, the etching depth of the semiconductor device to be etched with metal nanoparticles 6 for photoelectrochemical etching is obviously greater than the etching speed of the prior art semiconductor device to be etched without metal nanoparticles 6 for photoelectrochemical etching, and at the same time, it will not affect the roughness of etching, and at the same time, it also guarantees the quality of etching, improves the etching efficiency, and also guarantees the quality of etching.

[0107] Although the embodiments of the present application have been shown and described above, it should be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those skilled in the art can make changes, modifications, replacements and variations to the above embodiments without departing from the principles and purposes of the present application within the scope of the present application. All these changes should be within the protection scope of the claims of the present application.

Claims

1. A semiconductor device to be etched, characterized in that, include: A semiconductor device body, the semiconductor device body including a surface layer to be etched; A mask layer is located on the layer to be etched. The mask layer has a patterned structure and has several openings for exposing the layer to be etched. The upper width of the opening cross-section is greater than the lower width, and the size of the opening gradually decreases from top to bottom. Several pits are formed on the exposed surface of the layer to be etched corresponding to the opening and on the sidewall of the mask layer, respectively; the depth of the pits is 60-120nm and the opening diameter of the pits is 60-120nm. Metal nanoparticles are disposed within the recess; the metal nanoparticles are silver or copper metal particles, and the diameter of the metal nanoparticles ranges from 50 to 80 nm. When incident light shines on the layer to be etched and the mask layer, the pit diffuses the incident light, and the metal nanoparticles reflect and refract the incident light to prolong the contact time between the incident light and the layer to be etched.

2. The semiconductor device to be etched according to claim 1, characterized in that, The layer to be etched is a nitride layer containing group III elements, and the mask layer is made of silicon oxide or silicon nitride.

3. A method for fabricating a semiconductor device to be etched, characterized in that, include: Step S1: A patterned mask layer is formed on the layer to be etched on the surface of the semiconductor device body. The mask layer has a plurality of openings, the upper width of the opening cross-section is greater than the lower width, and the size of the opening gradually decreases from top to bottom. Step S2: A plurality of pits are formed on the exposed surface of the layer to be etched corresponding to the opening and on the sidewall of the mask layer; the depth of the pits is 60-120nm and the opening diameter of the pits is 60-120nm. Step S3: Form metal nanoparticles within the pit; the metal nanoparticles are silver or copper metal particles, and the diameter of the metal nanoparticles ranges from 50 to 80 nm; When incident light shines on the layer to be etched and the mask layer, the pit diffuses the incident light, and the metal nanoparticles reflect and refract the incident light to prolong the contact time between the incident light and the layer to be etched.

4. The preparation method according to claim 3, characterized in that, Step S1 includes: Step S11: A mask material layer is formed on the layer to be etched on the surface of the semiconductor device body. The thickness of the mask material layer is 200-500nm. A photoresist layer is formed on the mask material layer. Step S12: Expose and develop the photoresist layer to form a patterned photoresist layer; Step S13: Using a patterned photoresist layer as a mask, a portion of the mask material layer is removed by wet etching to form a patterned mask layer, and the remaining photoresist layer is removed.

5. The preparation method according to claim 3, characterized in that, Step S2 includes: using a plasma bombardment method to form a plurality of pits on the surface of the layer to be etched corresponding to the opening of the mask layer and on the surface of the mask layer.

6. The preparation method according to claim 5, characterized in that, In the plasma bombardment method, the gas flow rate is 80-150 sccm, the accelerating voltage is 300-400 keV, and the bombardment time is 10-40 s.

7. The preparation method according to claim 3, characterized in that, Step S3 includes: coating the mask layer and the layer to be etched with a suspension containing metal nanoparticles, and drying it so that only the metal nanoparticles remain in the pits.

8. An etching method, characterized in that, include: Step T1: Place the semiconductor device to be etched according to any one of claims 1-2 into a photoelectrochemical etching system, immerse the semiconductor device to be etched in the etching solution, and irradiate the semiconductor device to be etched with ultraviolet light to perform etching.

9. The etching method according to claim 8, characterized in that, The photoelectrochemical etching system includes: a power supply, an ultraviolet lamp, a support stage, a container containing etching solution, an ammeter, and a pH meter. The support stage is located at the bottom of the container and is used to support the semiconductor device to be etched. The anode plate of the power supply is connected to the semiconductor device to be etched, and the cathode plate of the power supply is placed in the etching solution to form an etching circuit. The ammeter is located in the etching circuit and is used to detect the current change trend in the etching circuit. The pH meter is located in the etching solution and is used to monitor the pH value of the etching solution. Step T1 includes: placing the semiconductor device to be etched on a support platform at the bottom of a container containing etching solution, controlling the power supply to be energized to form an etching circuit, and simultaneously using an ultraviolet lamp to irradiate the etchable layer and the mask layer of the semiconductor device to be etched to perform etching.

10. The etching method according to claim 9, characterized in that, The etching method further includes: Step T2: Remove the residue of metal nanoparticles on the semiconductor device to be etched, and clean and dry the semiconductor device to be etched.

11. A semiconductor device, characterized in that, The semiconductor device is obtained using the etching method described in any one of claims 8-10.

12. The semiconductor device according to claim 11, characterized in that, The semiconductor device is a gallium nitride-based LED device, a laser, a HEMT device, or a MOS transistor.

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