Fabrication of silicon carbide and nitride structures on a carrier substrate

Abstract

Methods, apparatus, and systems for forming a semiconductor structure. A first oxide layer located on a set of group III nitride layers formed on a silicon carbide substrate is bonded with a first oxide layer located on a carrier substrate to form an oxide layer located between the carrier substrate and the set of group III nitride layers. The silicon carbide substrate has a doped layer. The silicon carbide substrate having the doped layer is etched using a photoelectrochemical etching process, wherein a doping level of the doped layer is such that the doped layer is removed and a silicon carbide layer in the silicon carbide substrate remains unetched. A semiconductor structure is formed using the silicon carbide layer and the set of group III nitride layers.

Description

Technical Field

[0001] This disclosure generally relates to semiconductors, and more specifically, to methods for forming semiconductor structures, and more specifically, to forming silicon carbide and nitride structures on a carrier substrate. Background Technology

[0002] Silicon carbide and group III nitrides, such as gallium nitride, are ideal semiconductors for signal processing and quantum applications. Compared to other materials currently used in low-loss photonics and on-chip nonlinear optics, such as silicon, silicon dioxide, and silicon nitride, these materials have a wide bandgap greater than 3 eV and a larger nonlinear optical coefficient.

[0003] Silicon carbide (SiC) is a semiconductor material containing silicon and carbon. Silicon carbide can be used in devices for quantum information processing and other purposes. For example, color centers in a silicon carbide structure can be used to provide optical readings indicating the spin state of its electrons. Each color center is a qubit in quantum computing. The state of a qubit can be logic "0", logic "1", or a superposition of both states. For example, color centers can be incorporated into photonic devices, such as microcavities for waveguide elements.

[0004] Fabricating devices on silicon carbide structures can be challenging. For example, devices formed using thin films of silicon carbide and Group III nitrides may be more difficult to fabricate than expected compared to other materials such as silicon. Thin-film devices comprise one or more thin-film layers, where the thickness of the thin-film layers can range from nanometers to several micrometers.

[0005] Compared to materials such as silicon, the quality of thin-film devices using silicon carbide and group III nitrides formed on wafers may not be as good as desired. Therefore, a method and apparatus are desired that take into account at least some of the problems discussed above, as well as other potential issues. For example, a method and apparatus are desired that overcome the technical problems concerning the formation of silicon carbide and group III nitride structures with desired quality. Summary of the Invention

[0006] Embodiments of this disclosure provide a method for forming a semiconductor structure. A set of Group III nitride layers is formed on a silicon carbide substrate. The silicon carbide substrate includes a doped layer. The doping level of the doped layer is such that the doped layer is etched using a photoelectrochemical etching process while other portions of the silicon carbide substrate remain unetched. A first oxide layer is formed on the set of Group III nitride layers. The set of Group III nitride layers is located between the first oxide layer and the silicon carbide substrate. The first oxide layer is bonded to a second oxide layer on a carrier substrate to form an oxide layer located between the carrier substrate and the set of Group III nitride layers. The silicon carbide substrate is polished. Polishing is stopped when a portion of the doped layer in the silicon carbide substrate is exposed. The silicon carbide substrate is etched using photoelectrochemical etching such that when that portion of the doped layer in the silicon carbide substrate is exposed, the doped layer is removed, leaving the silicon carbide layer in the silicon carbide substrate intact. A semiconductor structure is formed using the silicon carbide layer and the set of Group III nitride layers.

[0007] Another embodiment of this disclosure provides a method for forming a semiconductor structure. A first oxide layer on a set of Group III nitride layers formed on a silicon carbide substrate is bonded to a second oxide layer on a carrier substrate to form an oxide layer between the carrier substrate and the set of Group III nitride layers. The silicon carbide substrate has a doped layer. The silicon carbide substrate with the doped layer is etched using a photoelectrochemical etching process, wherein the doping level of the doped layer is such that the doped layer is removed and the silicon carbide layer in the silicon carbide substrate remains unetched. A semiconductor structure is formed using the silicon carbide layer and the set of Group III nitride layers.

[0008] Another embodiment of this disclosure provides a product management system including manufacturing equipment and a control system. The control system controls the manufacturing equipment to bond a first oxide layer on a set of Group III nitride layers formed on a silicon carbide substrate to a second oxide layer on a carrier substrate to form an oxide layer between the carrier substrate and the set of Group III nitride layers. The silicon carbide substrate has a doped layer. The silicon carbide substrate with the doped layer is etched using a photoelectrochemical etching process. The doping level of the doped layer is such that the doped layer is removed and the silicon carbide layer in the silicon carbide substrate remains unetched. A semiconductor structure is formed using the silicon carbide layer and the set of Group III nitride layers.

[0009] The features and functions may be implemented independently in various embodiments of this disclosure, or may be combined in other embodiments, wherein more details may be learned with reference to the following description and accompanying drawings. Attached Figure Description

[0010] The appended claims set forth novel features that are considered characteristic of the illustrative embodiments. However, the illustrative embodiments and their preferred uses, further objects and features, will be best understood by referring to the following detailed description of the illustrative embodiments of this disclosure when read in conjunction with the accompanying drawings, wherein:

[0011] Figure 1 It is an illustration of a cross-sectional view of a silicon carbide substrate according to an illustrative embodiment;

[0012] Figure 2 It is an illustration of a cross-sectional view of a group III nitride layer on a silicon carbide substrate according to an illustrative embodiment;

[0013] Figure 3 It is a diagram of a cross-sectional view of a structure formed using a set of Group III nitride layers according to an illustrative embodiment;

[0014] Figure 4 It is an illustration of a cross-sectional view of silicon dioxide deposited on a silicon carbide substrate overlay structure formed on the bonding surface of a silicon carbide substrate according to an illustrative embodiment.

[0015] Figure 5 It is an illustration of a cross-sectional view of a carrier substrate according to an illustrative embodiment;

[0016] Figure 6 It is an illustration of a cross-sectional view of a silicon carbide substrate bonded to a carrier substrate according to an illustrative embodiment;

[0017] Figure 7 It is a diagram showing a cross-sectional view of a silicon carbide substrate with a portion removed according to an illustrative embodiment;

[0018] Figure 8 It is an illustration of a cross-sectional view of a silicon carbide device layer according to an illustrative embodiment;

[0019] Figure 9 It is an illustration of a cross-sectional view of a substrate according to an illustrative embodiment;

[0020] Figure 10 It is an illustration of a cross-sectional view of the workpiece bonded to a carrier substrate according to an illustrative embodiment;

[0021] Figure 11 It is a diagram showing a cross-sectional view of silicon carbide material being removed from a silicon carbide substrate according to an illustrative embodiment;

[0022] Figure 12 It is an illustration of a cross-sectional view of silicon carbide material etched to reach the silicon carbide device layer according to an illustrative embodiment;

[0023] Figure 13It is an illustration of a cross-sectional view of a workpiece according to an illustrative embodiment;

[0024] Figure 14 It is an illustration of a cross-sectional view of the silicon carbide material removed according to an illustrative embodiment;

[0025] Figure 15 It is an illustration of a cross-sectional view of the doped layer within reach of the silicon carbide device layer according to an illustrative embodiment;

[0026] Figure 16 It is a diagram of waveguide-coupled optical resonators and filters based on illustrative examples;

[0027] Figure 17 It is a diagram of a cross-sectional view of a waveguide-coupled optical resonator and filter according to an illustrative embodiment;

[0028] Figure 18 It is a diagram of an integrated optical waveguide containing a quantum memory, based on an illustrative example;

[0029] Figure 19 This is an illustration of a cross-sectional view of an integrated optical waveguide containing a waveguide-coupled quantum memory according to an illustrative embodiment;

[0030] Figure 20 This is a cross-sectional view of the waveguide according to the illustrative embodiment;

[0031] Figure 21 This is another cross-sectional view of the waveguide according to the illustrative embodiment;

[0032] Figure 22 This is yet another cross-sectional view of the waveguide according to the illustrative embodiment;

[0033] Figure 23 This is another cross-sectional view of the waveguide according to the illustrative embodiment;

[0034] Figure 24 This is another example of a silicon carbide substrate having a set of group III nitride layers according to an illustrative embodiment;

[0035] Figure 25 It is a flowchart illustration of a method for forming a semiconductor structure according to an illustrative embodiment;

[0036] Figure 26 It is a flowchart illustration of a method for forming a semiconductor structure according to an illustrative embodiment;

[0037] Figure 27 It is an illustration of a flowchart of a method for joining components according to an illustrative embodiment;

[0038] Figure 28 It is an illustration of a flowchart of a method for forming a semiconductor structure according to an illustrative embodiment; and

[0039] Figure 29 This is a block diagram illustration of a product management system according to an illustrative implementation. Detailed Implementation

[0040] The illustrative embodiments recognize and consider one or more different considerations. For example, the illustrative embodiments recognize and consider that currently used techniques can produce non-uniform polycrystalline silicon carbide films on wafers. Furthermore, the illustrative embodiments recognize and consider that when using current techniques to obtain the desired thickness for thin-film devices, material damage can occur in the silicon carbide film, resulting in undesirable optical absorption or scattering.

[0041] Furthermore, the illustrative embodiments recognize and consider that current technologies for fabricating silicon carbide (SiC) nanophotons are primarily limited to epitaxial growth of 3C-SiC (cubic crystal structure) on silicon (Si). The illustrative embodiments also recognize and consider that, although 3C-SiC is readily undercut on Si or silicon dioxide (SiO2) due to the chemical etch selectivity between SiC and Si / SiO2, 3C-SiC devices may suffer from undesirable optical losses due to dislocations, residual doping, high film strain, and interface defects at the Si-SiC growth interface.

[0042] The illustrative embodiments recognize and consider that, in order to mitigate interface defects, 3C-SiC can be transferred to another substrate and the previous interface can be etched away. However, the illustrative embodiments recognize and consider that 3C-SiC contains high inhomogeneous strain due to lattice mismatch with the Si substrate. In contrast to 3C-SiC films grown on Si substrates, the illustrative embodiments recognize and consider that single-crystal blocks and homoepitaxially grown 4H-SiC and 6H-SiC (hexagonal crystal structures) contain lower crystal strain and lower growth residual doping. Therefore, the illustrative embodiments recognize and consider that the 4H-SiC platform has great potential for photonics and other related fields. The illustrative embodiments recognize and consider that, since homoepitaxial growth of 4H-SiC on silicon carbide substrates produces crystal materials with very few lattice defects, photonics has also studied hexagonal SiC polymorphs of silicon carbide, such as 4H-SiC. The illustrative embodiments recognize and consider that, given that the material is grown on a bulk 4H-SiC substrate, existing methods for isolating the 4H-SiC thin film are limited, making chemical etching of the currently used base substrate impossible.

[0043] Illustrative embodiments recognize and consider that hexagonal silicon carbide thin films are suitable for photonics applications, while allowing for flexible patterning designs and stacked layers. Therefore, illustrative embodiments provide methods, apparatus, and systems for using silicon carbide and nitrides, such as Group III nitrides, to form structures with desired film thickness uniformity while reducing damage or defects. In one illustrative example, the method forms a semiconductor structure. A first oxide layer on a set of Group III nitride layers formed on a silicon carbide substrate is combined with a second oxide layer on a carrier substrate to form an oxide layer between the carrier substrate and the set of Group III nitride layers. The silicon carbide substrate has a doped layer. The silicon carbide substrate with the doped layer is etched using a photoelectrochemical etching process, wherein the doping level of the doped layer is such that the doped layer is removed and the silicon carbide layer in the silicon carbide substrate remains unetched. A semiconductor structure can be formed using the silicon carbide layer and the set of Group III nitride layers.

[0044] One or more illustrative examples enable the use of silicon carbide as a platform to fabricate semiconductor structures to provide photonic functionality. These semiconductor structures include at least one of optical waveguides and optical resonators. The functions of these structures include serving as splitters, directional couplers, grating couplers, microrings for filters, microdisks for filters, nonlinear optical frequency converters, light emitters, and other types of functions. The illustrative examples enable the fabrication of these and other types of structures using wafer-scale silicon carbide thin films while maintaining low optical loss.

[0045] As used in this article, when the phrase "at least one of" is used with a list of items, it means that different combinations of one or more of the listed items can be used, and it is possible that only one of each item in the list is required. In other words, "at least one of" refers to any combination of items and the number of items that can be used from the list, but not all items in the list are required. The item can be a specific object / thing or category.

[0046] For example, but not limited to, "at least one of project A, project B, or project C" can include project A, project A and project B, or project B. The example can also include project A, project B, and project C, or project B and project C. Of course, any combination of these projects can exist. In some illustrative examples, "at least one" can be, for example, but not limited to, two projects A; one project B; and ten projects C; four projects B and seven projects C; or other suitable combinations.

[0047] This document discloses detailed embodiments of the claimed structures and methods. However, it should be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods, which can be embodied in various forms. Furthermore, each example given in conjunction with the various embodiments is intended to be illustrative, not restrictive.

[0048] Furthermore, the accompanying drawings are not necessarily drawn to scale, as some features may be exaggerated to show details of specific components. Therefore, the specific structural and functional details disclosed herein should not be construed as limiting, but merely as a representative basis for instructing those skilled in the art to employ the methods and structures of this disclosure in various ways.

[0049] For the purposes of description below, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives shall be used in connection with the illustrative examples in the disclosure, as oriented in the accompanying drawings. The term “positioned on” means that a first element, such as a first structure, exists on a second element, such as a second structure, wherein an intervening element, such as an interface structure, such as an interface layer, may exist between the first and second elements.

[0050] In this disclosure, when an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, the element may be directly on the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly on" another element, "directly over" another element, or "on" another element and in direct contact with it, there are no intervening elements, and the element is in contact with the other element.

[0051] The methods, steps, and structures described below do not constitute a complete process flow for manufacturing integrated circuits. This disclosure can be practiced in conjunction with integrated circuit manufacturing technologies currently used in the art, and only a number of commonly practiced processing steps are included as needed to understand different instances of this disclosure. The accompanying drawings show a cross-section of a portion of an integrated circuit during manufacturing and are not drawn to scale but rather reversed to illustrate different illustrative features of this disclosure.

[0052] In an illustrative example, the method for fabricating a semiconductor structure may utilize two or more layers of silicon carbide with different doping types. In this illustrative example, the silicon carbide layers are epitaxially grown on a base silicon carbide substrate in wafer form. One or more silicon carbide layers can be doped by implantation. The silicon carbide layers having the base silicon carbide substrate can be collectively referred to as the silicon carbide substrate. Furthermore, an epitaxial Group III nitride layer may be grown over the topmost silicon carbide layer in the silicon carbide substrate.

[0053] Furthermore, one or more optional layers of the epitaxial Group III nitride layer may be present or grown on the first Group III nitride layer. Examples of Group III nitride layers that can be used include, for example, aluminum nitride (AlN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), and other Group III nitrides.

[0054] In an illustrative example, the features may be at least one patterned and etched into or deposited on a Group III nitride layer. The top of the structure may be covered with an insulator of low refractive index, such as an oxide layer formed of silicon dioxide. The oxide layer is a silicon dioxide layer deposited on a carrier substrate, which is also in wafer form. In an illustrative example, two wafers are joined together.

[0055] In illustrative examples, the initial underlying silicon carbide substrate can be at least partially removed by grinding. In these depicted examples, grinding can be at least one of mechanical grinding, polishing, or chemical mechanical polishing (CMP). Mechanical grinding of the silicon carbide substrate may produce a silicon carbide layer that can have an uneven thickness. When grinding is performed over a distance measured in centimeters, the uniformity may be low.

[0056] Subsequently, photoelectrochemical etching (PEC) can be performed to selectively remove the exposed non-uniform silicon carbide layer until an etching-stopping silicon carbide layer is reached. In this example, photoelectrochemical etching can be performed from either the carbon or silicon side of the silicon carbide substrate. Silicon carbide is a crystalline material and can have either a silicon or carbon side depending on its orientation. This silicon carbide layer serves as an etching-stopping layer, compared to the silicon carbide material removed using PEC etching, and can be semi-insulating or at least one of different doping polarities.

[0057] In the illustrative examples, using the techniques described in the illustrative examples, the resulting silicon carbide layer on the group III nitride layer can be thinner than 1 μm, and in some cases, thinner than 50 nm.

[0058] In illustrative examples, additional planarization steps may be used. For instance, mechanical polishing or chemical mechanical polishing may be performed after at least one of material growth or photoelectrochemical (PEC) etching of the silicon carbide layer substrate. These methods can be used to reduce roughness at various interfaces.

[0059] Now for reference Figure 1-8 A cross-sectional diagram of a method for forming a semiconductor structure is depicted according to an illustrative embodiment. Figure 1 This illustration depicts a cross-sectional view of a silicon carbide substrate according to an illustrative embodiment. As depicted, the silicon carbide (SiC) substrate 100 can be in the form of a wafer. For example, the silicon carbide substrate 100 can be a hexagonal silicon carbide wafer. In this example, the silicon carbide material can be, for example, a 4H or 6H crystal polytype. As depicted, in this example, the silicon carbide material has a non-centrosymmetric and polar crystal structure. As depicted, the wafer can, for example, have an area of ​​25 square centimeters or more.

[0060] In this illustrative example, the silicon carbide substrate 100 has a bonding surface 102 and an etched surface 104. More specifically, the etched surface 104 may be a carbon surface or a silicon surface of the silicon carbide substrate 100. In this example, the bonding surface 102 is a surface on which additional material for a semiconductor structure is formed.

[0061] Additionally, the silicon carbide substrate 100 has a doped layer 106. Doping can be performed using any currently available doping technique to form the doped layer 106, including at least one of diffusion or ion implantation. The doped layer 106 can be a layer with a thickness ranging from about 50 nanometers to tens of micrometers.

[0062] In this illustrative example, the doped layer 106 may be a p-type layer or an n-type silicon carbide layer. The doping concentration allows the doped layer 106 to be etched using a photoelectrochemical etching process. In this illustrative example, the doping ensures that the doped layer 106 is etched by the photoelectrochemical etching process, while other portions of the silicon carbide substrate 100 below and in direct contact with the doped layer 106 remain unetched.

[0063] Next, turn to Figure 2 This illustration depicts a cross-sectional view of a set of Group III nitride layers on a silicon carbide substrate, according to an illustrative embodiment. In this illustrative example, the same reference numerals may be used in multiple figures. This repetition of reference numerals in different figures denotes the same elements in different figures.

[0064] As depicted, in this example, a set of Group III nitride layers 200 are grown on the bonding surface 102 of a silicon carbide substrate 100. The set of Group III nitride layers 200 can be grown using currently available techniques for forming nitride layers.

[0065] As used herein, “a group” when used in relation to an item refers to one or more items. For example, “a group of Group III nitride layers 200” refers to one or more of Group III nitride layers 200. As depicted, the group of Group III nitride layers 200 can be thin film layers in which the thickness of each of these thin film layers ranges from a fraction of a nanometer to several micrometers. For example, a thin film layer can be less than one micrometer.

[0066] In this illustrative example, the group III nitride layer 200 includes at least one of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium aluminum gallium nitride (InAlGaN), or other suitable group III nitrides. In this example, the group III nitride layer 200 includes an AlN layer at least 10 nanometers thick. Other AlN, GaN, or Al... x Ga 1-x The N-layer can optionally be grown on top of this layer. These additional layers can be, for example, from nanometers to hundreds of micrometers thick. In this example, the number 'x' represents the material stoichiometry of the Al:Ga ratio, and 'x' can have a value between 0 and 1.

[0067] Next, turn to Figure 3 The illustration depicts a cross-sectional view of a structure formed using a set of Group III nitride layers, according to an illustrative embodiment. As depicted, a first metal 300 and a second metal 302 are formed on a set of Group III nitride layers 200. The first metal 300 and the second metal 302 can be formed using currently known techniques, including industry-standard photolithography and deposition techniques.

[0068] Alternatively, the group III nitride layer 200 can be patterned and etched using currently known techniques such as defining a hard mask, etching the group III nitride material, and removing the hard mask. In this example, the patterning during etching forms a first opening 304 and a second opening 306 in the group III nitride layer 200 to expose the bonding surface 102.

[0069] Now for reference Figure 4This illustration depicts a cross-sectional view of silicon dioxide deposited on a structure covering a silicon carbide substrate, formed at the bonding surface of the substrate according to an illustrative embodiment. In this illustrative example, the first oxide layer 400 is silicon dioxide deposited on a bonding surface 102 exposed in a first opening 304 and a second opening 306 of the first metal 300, a second metal 302, a set of Group III nitride layers 200, and the group of Group III nitride layers 200. Silicon dioxide can be deposited to form the first oxide layer 400 using known techniques such as plasma-enhanced chemical vapor deposition, sputtering, or another suitable known technique for forming the first oxide layer 400.

[0070] As depicted, the first oxide layer 400 has a first surface 402. In this example, chemical mechanical polishing (CMP) can be used to process the first surface 402 to improve flatness and reduce surface roughness. Furthermore, the first surface 402 of the first oxide layer 400 can be treated or activated to become a hydrophilic surface.

[0071] Now transferred to Figure 5 This illustration depicts a cross-sectional view of a carrier substrate according to an illustrative embodiment. In this illustrative example, the carrier substrate 500 can take many different forms. For example, the carrier substrate 500 can be one of a silicon carbide substrate, a silicon substrate, an alumina substrate, a gallium oxide substrate, a silicon dioxide substrate, an aluminum nitride substrate, a gallium nitride substrate, and other suitable substrates.

[0072] As depicted, the carrier substrate 500 has a second oxide layer 502 with a second surface 504. In this example, the second oxide layer 502 is composed of silicon dioxide. The second surface 504 may also be chemically mechanically polished and treated or activated to be a hydrophilic surface.

[0073] In illustrative examples, Figure 4 The silicon carbide substrate 100 and Figure 5 The carrier substrates 500 can be bonded to each other. In this illustrative example, the carrier substrate 500 is a substrate for a semiconductor structure. On the other hand, the silicon carbide substrate 100 includes silicon carbide material that serves as a set of silicon carbide device layers for forming a semiconductor structure.

[0074] As described, Figure 4 The first surface 402 of the first oxide layer 400 on the bonding surface 102 of the silicon carbide substrate 100 can be positioned to... Figure 5The second oxide layer 502 in the first oxide layer 400 contacts the second surface 504 of the second oxide layer 502. Van der Waals force bonding occurs through the contact between the first surface 402 of the first oxide layer 400 and the second surface 504 of the second oxide layer 502. These substrates bonded to each other through the oxide layers can be annealed. Annealing can be performed at a temperature of at least 150°C to enhance the bonding formed between the oxide layers of the two substrates.

[0075] Now for reference Figure 6 This illustration depicts a cross-sectional view of a silicon carbide substrate bonded to a carrier substrate, according to an illustrative embodiment. In this illustrative example, a silicon carbide substrate 100 and a carrier substrate 500 are bonded together to form an oxide layer 600. The carrier substrate 500 is a substrate for the semiconductor structure to be formed. The oxide layer 600 is a dielectric layer for the semiconductor structure. In other illustrative examples, other types of dielectrics may be used to form the dielectric layer in addition to or instead of the oxide layer 600.

[0076] Now for reference Figure 7 A cross-sectional view showing a portion of a silicon carbide substrate removed is depicted according to an illustrative embodiment. As depicted, the silicon carbide substrate 100 is thinned. This thinning can be performed in stages. For example, the silicon carbide substrate 100 can be ground from the etched surface 104 until the doped layer 106 in the silicon carbide substrate 100 is reached. In the example depicted here, the grinding is a mechanical grinding that removes most of the silicon carbide substrate 100 down to the doped layer 106. In this illustrative example, the grinding can stop at or extend into the doped layer 106.

[0077] Now for reference Figure 8 A cross-sectional view of the silicon carbide device layer is illustrated according to an illustrative embodiment. Further thinning can be performed using a photoelectrochemical (PEC) etching process when the doped layer 106 is reached. As depicted, PEC etching is performed on one side of the silicon carbide substrate 100 having etched surface 104, which is not performed using currently available techniques.

[0078] This method can be used to remove the doped layer 106. Selective doping is employed such that other portions of the silicon carbide substrate 100 beneath the doped layer 106 are not removed by the photoelectrochemical etching process. Therefore, the doped layer 106 in the silicon carbide substrate 100 serves as a sacrificial layer.

[0079] The portion of the silicon carbide substrate 100 below the doped layer 106 is retained as a silicon carbide device layer 800. The silicon carbide device layer 800 is an example of a set of silicon carbide layers. In other illustrative examples, multiple silicon carbide layers may be present for forming a semiconductor structure. These additional semiconductor carbide layers may have different doping levels that distinguish them.

[0080] In this illustrative example, the silicon carbide device layer 800 is a thin film layer. In this illustrative example, the silicon carbide device layer 800 has a thickness of about 10 nanometers to several micrometers. In some illustrative examples, the silicon carbide device layer 800 is between about 50 nanometers and about 500 nanometers. Furthermore, one or more semiconductor structures can be fabricated on the carrier substrate 500 using an assembly including the silicon carbide device layer 800, a set of Group III nitride layers 200, and an oxide layer 600.

[0081] Compared to other currently used techniques, the silicon carbide device layer 800 can achieve a higher quality level by using the doped layer 106 and a photoelectrochemical etching process. For example, the silicon carbide device layer 800 can be a polycrystalline film with desired uniformity on the wafer. Furthermore, the silicon carbide device layer 800 can have reduced inconsistencies or defects, leading to reduced undesirable optical absorption or scattering. In addition, in the illustrative example, besides producing the desired film thickness uniformity, the method can also lead to desired epitaxial growth of the desired quality. For example, using the steps in the illustrative example, a thickness variation of less than 50 nm may occur on a 100 mm wafer.

[0082] Figure 1-8 The illustrations of methods for forming semiconductor structures are examples of one possible illustrative implementation. The examples presented in these figures are not intended to limit the implementation of other illustrative examples. For instance, in another illustrative example, at least one of the Group III nitride layer 200, the first metal 300, or the second metal 302 may be omitted.

[0083] Next, turn to Figures 9 to 12 A cross-sectional view is illustrated in the method for forming a semiconductor structure according to an illustrative embodiment. First, refer to... Figure 9 The illustration depicts a cross-sectional view of the substrate according to an illustrative embodiment. As depicted, the silicon carbide substrate 900 includes a base substrate 902, a doped layer 904, and a silicon carbide device layer 906.

[0084] As depicted, the base substrate 902 is a bulk 4H-SiC wafer with a wafer normal miscut of 4 degrees or other small angles axially offset from the (0001) crystal orientation. The doped layer 904 is the first layer grown as an epitaxial layer of the doped 4H-SiC and is a sacrificial portion of the silicon carbide substrate 900. In this example, 4H-SiC is deposited with the desired thickness and doping specifications to form the silicon carbide device layer 906 in the silicon carbide substrate 900.

[0085] Furthermore, a set of Group III nitride layers, an aluminum nitride (AlN) layer 908, and a gallium nitride (GaN) layer 910 are grown on the silicon carbide device layer 906. In this example, the aluminum nitride layer 908 is an epitaxially grown undoped AlN buffer layer. The gallium nitride layer 910 can be formed to the desired specifications using metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). The doping of the gallium nitride layer 910 can be selected during the growth stage depending on the application.

[0086] As depicted, a first oxide layer 912 is deposited on a gallium nitride layer 910. In this example, silicon dioxide (SiO2) can be deposited using methods such as plasma-enhanced chemical vapor deposition (PECVD), sputtering, or atomic layer deposition to form the first oxide layer 912. In this illustrative example, the growth of the individual layers proceeds in the direction of arrow 914. These different layers form the workpiece 916.

[0087] Now for reference Figure 10 A cross-sectional view illustrating a method for bonding a workpiece to a carrier substrate is depicted according to an illustrative embodiment. As depicted, with Figure 9 Compared to the view of workpiece 916 in the image, workpiece 916 is flipped over. Workpiece 916 can then be bonded to a carrier substrate 1000 having a second oxide layer 1002. In this example, a bonding surface 1001 and an etched surface are shown. As depicted, the etched surface can be a silicon surface or a carbon surface of the silicon carbide substrate 900.

[0088] In this illustrative example, the carrier substrate 1000 may be silicon carbide, silicon, silicon dioxide, aluminum oxide, or other suitable materials. As depicted, the second oxide layer 1002 is formed using thermal oxidation, plasma-enhanced chemical vapor deposition (PEVCD), sputtering, atomic-level deposition, or other suitable methods.

[0089] In this illustrative example, bonding can be achieved through contact between oxide layers. In this example, after contact, annealing is performed at a temperature of approximately 200°C.

[0090] exist Figure 11 The illustration depicts a cross-sectional view of silicon carbide material removed from a silicon carbide substrate, according to an illustrative embodiment. In this figure, a first oxide layer 912 and a second oxide layer 1002 are bonded together to form an oxide layer 1100.

[0091] As depicted, the silicon carbide substrate 900 is thinned by mechanical polishing and can be polished by chemical mechanical polishing (CMP) as shown in section 1102. Section 1102 represents the silicon carbide material that has been removed. As shown, in this example, the removal extends into the doped layer 904.

[0092] In this example, mechanical polishing is used to remove a portion, rather than all, of the doped 904 layer. In some cases, mechanical polishing may be suitable on length scales, such as from micrometers to millimeters. However, due to the larger length scales and the desired film thickness across the entire wafer, and furthermore, the forces and stresses involved in such material removal may introduce undesirable inconsistencies such as lattice defects, dislocations, and crystal strain.

[0093] In this illustrative example, mechanical polishing is stopped when the polishing extends into the doped layer 904. For example, mechanical polishing can be stopped when the doped layer 904 is still about a few micrometers thick.

[0094] Go to Figure 12 A cross-sectional view of silicon carbide material etched to reach a silicon carbide device layer is depicted according to an illustrative embodiment. As depicted, in this cross-sectional view, as shown in portion 1200, the remaining portion of the doped layer 904 is removed using a photoelectrochemical etching process. This etching exposes the silicon carbide device layer 906 without removing material from it. The dopant and doping level in the doped layer 904 are selected such that the doped layer 904 can be etched without removing material from the silicon carbide device layer 906.

[0095] Photoelectrochemical etching allows for dopant-type selective etching, in which the doped layer 904 is removed to expose the silicon carbide device layer 906. In this illustrative example, compared to mechanical polishing, the silicon carbide device layer 906 can exhibit desired properties, such as a clean crystal surface and a lower defect density.

[0096] In this illustrative example, an optochemical etching process can be performed while the doped layer 904 is in contact with a solution such as dilute potassium hydroxide or hydrofluoric acid and water.

[0097] Furthermore, the carrier substrate 1000 with different layers can be illuminated using light wavelengths having photon energies corresponding to those above the bandgap of silicon carbide. In this depicted example, since the bandgap of the light source is approximately 3.2 eV, the light source contains wavelengths shorter than 390 nm for 4H-SiC. A voltage bias can be applied between a contact on one of the doped layers of the sample and a platinum electrode in an aqueous solution. The etching selectivity of p-type, n-type, and intrinsic materials can be tuned and optimized by controlling the magnitude and direction of the DC voltage bias. Because photoelectrochemical etching involves wet chemistry and is selective depending on the doping type, the final result of the silicon carbide and Group III nitride films exhibits the desired uniformity and planarity across the entire wafer. This is in contrast to currently available techniques such as smart dicing, which uses ion implantation to create amorphous layers at a defined depth. In the illustrative example, photoelectrochemical etching avoids introducing new point defects or dopants into the silicon carbide and Group III nitride films.

[0098] Next, Figure 13-15 This is a cross-sectional view of a workpiece etched using photoelectrochemical etching according to an illustrative embodiment. (Reference) Figure 13 The illustration depicts a cross-sectional view of a workpiece according to an illustrative embodiment. As depicted, workpiece 1300 is the result of bonding a silicon carbide substrate to a carrier substrate, wherein an oxide layer is formed between the two substrates.

[0099] In this illustrative example, workpiece 1300 includes a silicon substrate 1301, which includes a doped layer 1302, a doped silicon carbide device layer 1304, a silicon carbide device layer 1306, an aluminum nitride (AlN) layer 1308, a gallium nitride (GaN) layer 1310, an oxide layer 1312, and a carrier substrate 1314. In this example, the doped layer 1302 is the top layer and is not located among the other layers in the silicon substrate 1301, as depicted in other previous examples. Workpiece 1300 has a bonding surface 1305 and an etched surface 1303. As depicted, the etched surface 1303 can be a silicon surface or a carbon surface.

[0100] As depicted, doped layer 1302 is an n-type layer. In other illustrative examples, doped layer 1302 may be a p-type layer. Doping differences are chosen to avoid etching of the doped silicon carbide device layer 1304. In other words, the doping level and doping type of the doped silicon carbide device layer 1304 can be selected such that the layer serves as an etch stop layer for photoelectrochemical etching processes.

[0101] In this depicted example, the doped layer 1302 is a sacrificial layer that can be etched using a photoelectrochemical etching process. The doping level of the doped layer 1302 has a sufficiently different doping type, density, or both from the doped silicon carbide device layer 1304, which has a doping type and level that defines the etch stop layer. In this example, when the doped layer 1302 has a doping level greater than 1 x 10⁻⁶, the doping layer 1302 is a sacrificial layer that can be etched using a photoelectrochemical etching process. 18 cm -3 The concentration of doped silicon carbide device layer 1304 is at least 1x10. 18 cm -3 Etching selectivity can be maximized when the doping concentration and the dopant type are opposite to those of the doped layer 1302.

[0102] In this illustrative example, the dopant type used for doped layer 1302 is n-type, while the dopant type used for doped silicon carbide device layer 1304 is p-type. If doped silicon carbide device layer 1304 requires a different type of dopant, such as a p-type dopant, the type of dopant used in doped layer 1302 can be changed to an n-type dopant.

[0103] In another illustrative example, the sacrificial layer, the doped layer 1302, the etch stop layer, and the doped silicon carbide device layer 1304 are doped to approximately 1 x 10⁻⁶. 17 cm -3 Concentrations of 1x10 or higher. 17 cm -3 At higher doping levels, the etching rate of silicon carbide can depend on the voltage bias present during the photoelectrochemical etching process. The etching rate initially varies more significantly with doping concentration and is a factor that imparts selectivity to photoelectrochemical etching based on doping type.

[0104] Furthermore, the doped silicon carbide device layer 1304 can be, for example, about 100 nanometers or more thick. The silicon device layer beneath the doped silicon carbide device layer 1304 can be of any desired thickness formed by growth. For example, these layers can be from about 50 nanometers to 200 micrometers thick and have customizable doping concentrations. Nitride layers, such as AlN layers and GaN layers, can each have thicknesses suitable for specific semiconductor devices.

[0105] In this illustrative example, a voltage bias can be applied to the surface of the doped layer 1302 via an ohmic contact. Furthermore, the surface of the silicon carbide layer is in contact with an aqueous potassium hydroxide solution and exposed to light with energy above the band gap. In this example, the light may have a wavelength shorter than 390 nanometers.

[0106] Go to Figure 14A cross-sectional view of the removed silicon carbide material is illustrated according to an illustrative embodiment. In this illustrative example, substrate thinning is performed by grinding and polishing to remove silicon carbide material from the doped layer 1302, as seen through portion 1400 representing the removed silicon carbide material. This polishing can be mechanical polishing, chemical mechanical polishing, or a combination of both. As can be seen in this example, a portion of the doped layer 1302 remains after grinding and chemical mechanical polishing.

[0107] exist Figure 15 The illustration depicts a cross-sectional view of a doped layer within the reach of a silicon carbide device layer, according to an illustrative embodiment. In this illustrative example, the doped layer 1302 is etched using a photoelectrochemical etching process to reach the doped silicon carbide device layer 1304, which in this example is an etch stop layer. Section 1500 shows the removed silicon carbide material.

[0108] therefore, Figure 1-15 The illustrated method enables the formation of silicon carbide layers for use in devices with desired characteristics. For example, silicon carbide device layers can be formed on a wafer-scale to achieve desired uniformity in layer thickness. Furthermore, silicon carbide device layers can be formed with reduced material damage levels, thus avoiding undesirable optical absorption or scattering. Through these methods, the desired quality of silicon carbide layers for device use can be achieved on larger surfaces, such as wafers, compared to existing technologies.

[0109] Next, turn to Figure 16 A diagram illustrating a waveguide-coupled optical resonator and filter is provided, based on illustrative examples. As depicted, the waveguide-coupled optical resonator and filter 1600 is a semiconductor device formed on a carrier substrate 1602 having an oxide layer 1604, an aluminum nitride layer 1606, and a silicon carbide layer 1608. It can be used... Figure 1-8 , Figure 9-12 and Figure 13-15 The method illustrated in the middle forms a carrier substrate 1602 having an oxide layer 1604, an aluminum nitride layer 1606, and a silicon carbide layer 1608.

[0110] In this illustrative example, the aluminum nitride layer 1606 is in direct contact with the silicon carbide layer 1608. In other examples, one or more other layers may be located between the aluminum nitride layer 1606 and the silicon carbide layer 1608.

[0111] In this example, the waveguide-coupled optical resonator and filter 1600 has three components. As depicted, the waveguide-coupled optical resonator and filter 1600 includes a linear waveguide 1601, a linear waveguide 1603, and a ring waveguide 1605. In this example, the waveguide-coupled optical resonator and filter 1600 can filter selected wavelengths of light. For example, light traveling through the linear waveguide 1601 can enter the ring waveguide 1605. The ring waveguide 1605 can transmit light of one or more selected wavelengths to the linear waveguide 1603, which acts as a filter to transmit light from the linear waveguide 1601 to the linear waveguide 1603.

[0112] refer to Figure 17 A cross-sectional view of a waveguide-coupled optical resonator and filter is illustrated according to an illustrative embodiment. The figure shows the cross-sectional view along... Figure 16 The image shows a cross-sectional view of the waveguide-coupled optical resonator and filter 1600, taken by line 17-17. In this example, oxide layers are bonded to form oxide layer 1604. Subsequently, aluminum nitride layer 1606 and silicon carbide layer 1608 can be etched to form a structure that forms linear waveguide 1601, linear waveguide 1603, and ring waveguide 1605.

[0113] refer to Figure 18 An illustration of an integrated optical waveguide incorporating a quantum memory is depicted, based on an illustrative example. As depicted, the quantum memory device 1800 is a semiconductor device formed on a carrier substrate 1802 having an oxide layer 1804, aluminum nitride regions, and silicon carbide regions. In this example, an integrated optical waveguide incorporating a quantum memory can be used... Figure 1-8 , Figure 9-12 and Figure 13-15 The method illustrated in the middle forms a carrier substrate 1802 having an oxide layer 1804, an aluminum nitride region, and a silicon carbide region.

[0114] As depicted, the aluminum nitride region has sides 1801 and 1803. The silicon carbide region has sides 1805 and 1807.

[0115] In this example, the quantum memory device 1800 includes a quantum memory 1810 and an integrated optical waveguide 1811. The quantum memory 1810 is coupled to the integrated optical waveguide 1811. The quantum memory 1810 can be formed from defects in silicon carbide material within a silicon carbide region. These defects can be, for example, point defects selected from double vacancies, silicon single vacancies, other vacancy complexes, transition metal ions, or rare earth ions within the silicon carbide region. The quantum memory 1810 can emit photons 1812, depending on the electron spin associated with the defect or color center, and the state in which the photon can become entangled with the electron spin state. The photons 1812 emitted from the quantum memory 1810 can travel into the integrated optical waveguide 1811.

[0116] refer to Figure 19 A cross-sectional view of an integrated optical waveguide incorporating a quantum memory is illustrated according to an illustrative embodiment. In this figure, the cross-section along... Figure 18 The cross-sectional view of quantum memory device 1800 taken from line 19-19 in the figure.

[0117] Go to Figure 20-23 The illustrations depict the fabricated waveguide structures according to one or more illustrative embodiments. These depicted waveguide structures can be used... Figure 1-8 , Figure 9-12 and Figure 13-15 The method is illustrated in the diagram. These waveguides can also be used to replace... Figure 16 and 18 The optical waveguide structure depicted in the image, in Figure 17 and 19 The cross-section of the optical waveguide structure is illustrated in the figure.

[0118] refer to Figure 20 A cross-sectional view of the waveguide is depicted according to an illustrative embodiment. As illustrated, waveguide 2000 is an example of a strip waveguide that can be formed in the illustrative example.

[0119] In this depicted example, waveguide 2000 is formed on carrier substrate 2002. Oxide layer 2004 is located on carrier substrate 2002. Aluminum nitride layer 2006 is located on oxide layer 2004, and silicon carbide region is located on aluminum nitride layer 2006. As shown in the figure, silicon carbide region has been patterned and etched to form waveguide 2000.

[0120] As used herein, a region is a non-infinitely extending layer. In this example, the region has defined sides. As depicted, the silicon carbide region has sides 2001 and 2003.

[0121] A coating 2010 covers the silicon carbide region and the aluminum nitride layer 2006. In this example, the coating 2010 is in direct contact with the silicon carbide region and the aluminum nitride layer 2006. The coating 2010 may comprise a material selected from at least one of air, vacuum, photoresist, polymer, silicon nitride, silicon dioxide, or some other materials. In other words, in some illustrative examples, the coating 2010 may comprise more than one type of material. In this example, the coating 2010 has a lower refractive index than the silicon carbide region.

[0122] In this illustrative example, the carrier substrate 2002 has a thickness of approximately 100 µm. In this example, the oxide layer 2004 has a thickness of approximately 3.0 µm. The aluminum nitride layer 2006 has a thickness of approximately 200 nm, and the silicon carbide region has a thickness of approximately 300 nm and a width of approximately 1.0 µm. The cladding layer 2010 has a thickness of approximately 500 nm to approximately 5.0 µm.

[0123] In this illustrative example, the silicon carbide layer can be etched to form silicon carbide regions, while the aluminum nitride layer 2006 is not etched. This etching can be performed after bonding.

[0124] Figure 20 The cross-section of the waveguide 2000 structure depicted can be used to form components of a semiconductor structure. For example, the silicon carbide region can be replicated to form four regions. The two outer regions can each be part of a linear waveguide, and the two inner regions can be used for a ring waveguide.

[0125] Next, turn to Figure 21 Another cross-sectional view of the waveguide is depicted according to an illustrative embodiment. As depicted, waveguide 2100 is an example of a ribbed waveguide that can be formed in the illustrative example.

[0126] In this illustrative example, waveguide 2100 is formed on carrier substrate 2102. Oxide layer 2104 is located on carrier substrate 2102. Aluminum nitride layer 2106 is located on oxide layer 2104, and silicon carbide layer 2108 is located on aluminum nitride layer 2106. Furthermore, rib regions 2110 are silicon carbide regions extending from silicon carbide layer 2108. As shown in the figure, silicon carbide layer 2108 has been patterned and etched to form waveguide 2100 in the form of a ribbed waveguide with rib regions 2110.

[0127] Waveguide 2100 also has a cladding 2112 covering the silicon carbide layer 2108 and the rib region 2110. In this example, the cladding 2112 is in direct contact with these components. The cladding 2112 has a lower refractive index than the silicon carbide layer 2108 and the rib region 2110.

[0128] In this illustrative example, the carrier substrate 2102 has a thickness of approximately 100 µm. In this example, the oxide layer 2004 has a thickness of approximately 3.0 µm.

[0129] The aluminum nitride layer 2106 has a thickness of approximately 200 nm. The silicon carbide layer 2108 has a thickness of approximately 100 nm. The ribbed region 2110 extending from the silicon carbide layer 2008 has a thickness of approximately 200 nm and a width of approximately 1.0 µm. The cladding layer 2112 has a thickness of approximately 500 nm to approximately 5.0 µm.

[0130] exist Figure 22 In the illustration, another cross-sectional view of the waveguide is depicted according to an illustrative embodiment. As shown, waveguide 2200 is an example of an embedded ridge waveguide structure.

[0131] In this depicted example, waveguide 2200 is formed on carrier substrate 2202. Oxide layer 2204 is located on carrier substrate 2202. Gallium nitride region is located on oxide layer 2204 within cavity 2208 in oxide layer 2204. Aluminum nitride region is located on gallium nitride region within cavity 2208 in oxide layer 2204. The aluminum nitride region and gallium nitride region are examples of a group of Group III nitride regions that can be buried in cavity 2208.

[0132] A region is a layer having defined sides and may be located within another material. In this example, the gallium nitride region has sides 2201 and 2203 in a cavity 2208 in the oxide layer 2204. The aluminum nitride region has sides 2205 and 2207 in a cavity 2208 in the oxide layer 2204.

[0133] In this example, a silicon carbide layer 2214 is located on the oxide layer 2204 and the aluminum nitride region. As shown in the figure, the silicon carbide layer 2214, the aluminum nitride region, and the gallium nitride region in the cavity 2208 of the oxide layer 2204 form a waveguide 2200. The aluminum nitride region and the gallium nitride region form ridges 2220 buried in the oxide layer 2204. The refractive index of at least one of the aluminum nitride region or the gallium nitride region is higher than the refractive index of the oxide layer 2204.

[0134] As depicted, waveguide 2200 has a cladding layer 2222 covering a silicon carbide layer 2214. In this illustrative example, the cladding layer 2222 is in direct contact with the silicon carbide layer 2214. The refractive index of the cladding layer 2222 is lower than that of the silicon carbide layer 2214.

[0135] In this illustrative example, the carrier substrate 2202 has a thickness of approximately 100 µm. In this example, the oxide layer 2204 has a thickness of approximately 3.3 µm. The aluminum nitride layer 2210 has a thickness of approximately 100 nm, and the gallium nitride layer 2212 has a thickness of approximately 200 nm. These two layers in cavity 2208 have a width of approximately 1.0 µm. As depicted, the silicon carbide layer 2214 has a thickness of approximately 200 nm. The cladding layer 2222 has a thickness of approximately 500 nm to approximately 5.0 µm.

[0136] In this example, the aluminum nitride layer and the gallium nitride region are etched to form the aluminum nitride region and the gallium nitride region, respectively. A first oxide layer is formed to bury the aluminum nitride region and the gallium nitride region. This first oxide layer is then bonded to a second oxide layer on the carrier substrate 2202. The first oxide layer and the second oxide layer can then be bonded to form oxide layer 2204.

[0137] In this illustrative example, the operations described in the illustrative example can be used to manufacture... Figure 22 The semiconductor structure depicted in the diagram. For example, a Group III nitride layer can be patterned and etched before the deposition of oxide and wafer bonding. The waveguide structure can be integrated with a lateral (horizontal) diode and doped for active electronics and a depletion layer in the silicon carbide layer 2214. The doped regions can be fabricated by mask implantation followed by annealing, or by doping the substrate (SiC and GaN) during growth followed by patterning and etching, or a combination thereof. Applying an electric field across the pn junction or between metal contacts of these materials can be used to tune the resonant frequency of an optical resonator or the light emission frequency of an embedded single-photon emitter.

[0138] Now for reference Figure 23 Another cross-sectional view of the waveguide is depicted according to an illustrative embodiment. As illustrated, waveguide 2300 is another example of an embedded optical waveguide structure.

[0139] In this depicted example, waveguide 2300 is formed on carrier substrate 2302. Oxide layer 2304 is located on carrier substrate 2302. Gallium nitride region is located on oxide layer 2304 within cavity 2308 in oxide layer 2304. Aluminum nitride region is located on gallium nitride region within cavity 2308 in oxide layer 2304. Aluminum nitride region has side surface 2301 and side surface 2303. Gallium nitride region has side surface 2305 and side surface 2307. As depicted, aluminum nitride region and gallium nitride region form ridge 2317 buried within cavity 2308 in oxide layer 2304.

[0140] In this example, a silicon carbide layer 2314 is located on the oxide layer 2304 and the aluminum nitride region. Furthermore, a rib region extends from the silicon carbide layer 2314. As shown in the figure, the rib region 2316 is a portion of the silicon carbide extending from the silicon carbide layer 2314 and can be referred to as the silicon carbide region. As depicted, the silicon carbide layer 2314, the rib region 2316, the aluminum nitride region, and the gallium nitride region within the cavity 2308 of the oxide layer 2304 form a waveguide 2300.

[0141] As depicted, waveguide 2300 has a cladding 2322 covering silicon carbide layer 2314 and rib region 2316. As depicted, cladding 2322 is in direct contact with silicon carbide layer 2314 and rib region 2316. The refractive index of cladding 2322 is lower than that of silicon carbide layer 2314 and rib region 2316.

[0142] In this illustrative example, the carrier substrate 2302 has a thickness of approximately 100 µm. In this example, the oxide layer 2304 has a thickness of approximately 3.3 µm. The aluminum nitride region has a thickness of approximately 100 nm, and the gallium nitride region has a thickness of approximately 200 nm. These two regions in cavity 2308 have a width of approximately 1.0 µm. As depicted, the silicon carbide layer 2214 has a thickness of approximately 100 nm. The ribbed region 2316 has a width of approximately 1.0 µm and a thickness of approximately 200 nm. The cladding layer 2322 has a thickness of approximately 500 nm to approximately 5.0 µm.

[0143] supply Figure 20-23 The diagrams of waveguide structures in the diagrams serve as examples of a type of semiconductor structure that can be fabricated based on one or more illustrative examples. These diagrams are not intended to limit the ways in which other illustrative examples can be implemented.

[0144] For example, the thicknesses of these layers and regions illustrated are examples of thicknesses that can be used in thin film implementations. These thicknesses do not imply limitations on thicknesses that can be used in other illustrative examples.

[0145] Furthermore, the number and type of Group III nitride layers and regions can be related to Figure 20-23 The differences are those shown in the diagram. For example, in addition to or instead of the depicted aluminum nitride (AlN) and gallium nitride (GaN) layers, indium nitride (InN) layers and indium aluminum gallium nitride (InAlGaN) layers can be used.

[0146] As another example, other types of semiconductor structures can be fabricated in addition to or in place of waveguide structures. For instance, semiconductor structures may include at least one of a superconducting single-photon detector, a light emitter, a quantum memory using point defects within a silicon carbide device layer, or other suitable types of components within a semiconductor structure.

[0147] Other examples of semiconductor structures having one or more silicon carbide device layers and one or more Group III nitride layers that can be fabricated using the operations in one or more illustrative examples include microelectromechanical systems and photonic components comprising waveguide-coupled four-port and two-port ring resonators or filters. In yet another illustrative example, superconducting materials can be deposited in a manner that allows superconducting nanowire single-photon detectors and logic components to operate at low temperatures alongside photonic, electrical, and mechanical components.

[0148] As another example, for slot waveguides, optical modes of a lower refractive index cladding or vacuum outside the substrate can be selected by etching two closely spaced ridges together. The spacing can be, for example, less than a few hundred nanometers. As yet another example, a suspended waveguide can be fabricated by photolithographically patterning and then chemically etching away oxide (SiO2) in the selective regions, stacking materials similar to those depicted in these figures. This will produce optical spatial modes that extend more into air or vacuum than into the oxide layer.

[0149] Next reference Figure 24 Another example of a silicon carbide substrate having a set of Group III nitride layers is depicted according to an illustrative embodiment. In this illustrative example, workpiece 2400 is formed and can be coupled with a carrier substrate, such as... Figure 5 An example of a layer bonded to a carrier substrate 500.

[0150] In this example, the silicon carbide substrate in workpiece 2400 includes a base substrate 2404, a p-type silicon carbide layer 2406, an n-type silicon carbide layer 2408, an undoped silicon carbide layer 2410, and a p-type silicon carbide layer 2412. As depicted, the p-type silicon carbide layer 2406 is a sacrificial layer for photoelectrochemical etching. The other silicon carbide layers are examples of silicon carbide device layers that can be used to form semiconductor structures. In this example, the n-type silicon carbide layer 2408 can also be used as an etch stop layer in addition to serving as a device layer.

[0151] In this illustrative example, the base substrate 2404 has a thickness of approximately 350 µm. As depicted, the sacrificial layer, the p-type silicon carbide layer 2406, has a thickness of approximately 5 µm. In this example, the n-type silicon carbide layer 2408 has a thickness of approximately 0.1 µm; the undoped silicon carbide layer 2410 has a thickness of approximately 0.2 µm; and the p-type silicon carbide layer 2412 has a thickness of approximately 0.1 µm.

[0152] As depicted, Group III nitride layers are grown on a p-type silicon carbide layer 2412 in a silicon carbide substrate. These Group III nitride layers include an undoped aluminum nitride layer 2414 and an undoped gallium nitride layer 2416. In this illustrative example, the undoped aluminum nitride layer 2414 has a thickness of about 0.1 µm, and the undoped gallium nitride layer 2416 has a thickness of about 0.4 µm.

[0153] In this depicted example, oxide layer 2418 is deposited on undoped gallium nitride layer 2416. In this example, oxide layer 2418 has a thickness of approximately 0.2 µm.

[0154] Using workpiece 2400, thin films of silicon carbide and group III nitrides can be stacked on top of a material with a low refractive index (n), such as SiO2, for example, SiO2 with n of approximately 1.4, single-crystal AlN / GaN with n of 2.1 / 2.3, and 4H-SiC with n of 2.6. As a result, optical modes in photonic devices can remain within at least one of the silicon carbide or group III nitride layers without radiating or losing light energy to the underlying bulk substrate material.

[0155] Furthermore, the silicon carbide layer in the Group III nitride layer depicted in workpiece 2400 can be used to create pin junctions within the silicon carbide material. In this example, the use of an undoped aluminum nitride layer 2414 can be advantageous compared to an exposed surface of SiC or a direct interface between silicon carbide and oxide, and can result in fewer unpassivated interface states (especially at low temperatures). In the illustrative example, the use of one or more additional Group III nitride layers is optional.

[0156] A diagram of workpiece 2400 is provided as an example of one way in which a silicon carbide substrate having a set of group III nitride layers can be implemented. This illustration is not intended to limit the implementation of other illustrative examples.

[0157] For example, other illustrative examples may have other numbers of layers and a silicon carbide substrate. In some illustrative examples, the layer adjacent to the sacrificial layer may be an undoped layer, rather than a layer with the opposite doping type to the sacrificial layer. In yet another illustrative example, three, five, or some other number of Group III nitride layers may be used. Furthermore, example thicknesses of these layers are provided as examples of thicknesses that can be used with thin film layers. Other thicknesses may be used in other examples.

[0158] Next, turn to Figure 25The illustration depicts a flowchart of a method for forming a semiconductor structure according to an illustrative embodiment. The method begins by bonding a first oxide layer on a set of Group III nitride layers formed on a silicon carbide substrate with a second oxide layer on a carrier substrate to form an oxide layer between the carrier substrate and the set of Group III nitride layers (operation 2500). The silicon carbide substrate has a doped layer.

[0159] This method uses a photoelectrochemical etching process to etch a silicon carbide substrate with a doped layer (operation 2502). The doping level of the doped layer is such that the doped layer is removed while the silicon carbide device layer in the silicon carbide substrate remains unetched. In operation 2502, the doped layer is a sacrificial layer that enables the formation of the silicon carbide device layer on a substrate, such as a wafer, having at least one of the desired thickness uniformity or desired optical performance level of the silicon carbide device layer. In operation 2502, photoelectrochemical etching is performed on an etching surface, which can be the silicon surface of the silicon carbide material, or, for example, the carbon surface of the silicon carbide material. Photoelectrochemical etching can also be performed on an etching surface that is the silicon surface of the silicon carbide material.

[0160] This method uses a silicon carbide device layer and the Group III nitride layer to form a semiconductor structure (operation 2504). The method then terminates. In this example, the silicon carbide device layer and the Group III nitride layer can be thin film layers. The semiconductor structure is selected from at least one of the following: optical waveguides using point defects within the silicon carbide device layer, slot waveguides, ridge waveguides, rib waveguides, buried optical waveguides, suspended waveguides, optical resonators, photon-emitting quantum memories, or some other suitable structures. The semiconductor structure may include multiple components. For example, the semiconductor structure may include multiple waveguides of the same or different types. As another example, the semiconductor structure may include one or more waveguides and a quantum memory. These and other components can be selected to provide one or more desired functions of the semiconductor structure.

[0161] Next reference Figure 26 The illustration depicts a flowchart of a method for forming a semiconductor structure according to an illustrative embodiment. The method begins by forming a set of Group III nitride layers on a silicon carbide substrate (operation 2600). The silicon carbide substrate includes a doped layer. The doped layer has a doping level such that it is etched using a photoelectrochemical etching process, while other portions of the silicon carbide substrate remain unetched. In other illustrative examples, the formation of the set of Group III nitride layers may include etching the set of Group III nitride layers to form a structure.

[0162] The method involves forming a first oxide layer on the Group III nitride layer, wherein the Group III nitride layer is located between the first oxide layer and the silicon carbide substrate (operation 2602). The method further involves bonding the first oxide layer to a second oxide layer on a carrier substrate to form an oxide layer located between the carrier substrate and the Group III nitride layer (operation 2604).

[0163] The method involves polishing a silicon carbide substrate (operation 2606). Polishing is stopped when a portion of the doped layer in the silicon carbide substrate is exposed (operation 2608). In operation 2608, the exposed portion of the doped layer can be the top of the doped layer or a portion of the doped layer.

[0164] This method uses photoelectrochemical etching to etch a silicon carbide substrate such that when the portion of the doped layer in the silicon carbide substrate is exposed, the doped layer is removed and the silicon carbide device layer in the silicon carbide substrate is retained (operation 2610).

[0165] This method uses a silicon carbide device layer and a Group III nitride layer to form a semiconductor structure (operation 2612). The method then terminates.

[0166] Next, turn to Figure 27 The diagram illustrates the connecting components according to the illustrative embodiment. Figure 27 The flowchart in the document is used for... Figure 25 Operation 2500 and Figure 26 An example of one implementation of operation 2604 in the example.

[0167] The method begins by bringing a first surface of a first oxide layer into contact with a second surface of a second oxide layer (operation 2700). In operation 2700, intermolecular interactions occur between the first and second oxide layers. These intermolecular interactions include, for example, at least one of van der Waals forces, hydrogen bonds, or strong covalent bonds.

[0168] The method anneales the first and second oxide layers while bringing the first surface into direct contact with the second surface to form an oxide layer located between the carrier substrate and a set of Group III nitride layers (operation 2702). In this example, the annealing in operation 2702 is optional. The method then terminates.

[0169] Go to Figure 28 The illustration depicts a flowchart of a method for forming a semiconductor structure according to an illustrative embodiment. The method begins by bonding a first oxide layer on a silicon carbide substrate with a second oxide layer on a carrier substrate to form an oxide layer located between the carrier substrate and the silicon carbide substrate (operation 2800).

[0170] In operation 2800, the silicon carbide substrate has a doped layer. Furthermore, in one illustrative example, the first oxide layer is in direct contact with the silicon carbide substrate. In another illustrative example, a set of intercalation layers, such as a set of Group III nitride layers, are located between the first silicon layer and the silicon carbide substrate.

[0171] This method uses a photoelectrochemical etching process to etch a silicon carbide substrate with a doped layer (operation 2802). In operation 2802, the doping level of the doped layer is such that the doped layer is removed and the silicon carbide device layer in the silicon carbide substrate remains unetched.

[0172] This method uses a silicon carbide device layer to form a semiconductor structure (operation 2804). In operation 2804, other materials can also be used to form the semiconductor structure. For example, the group III layer or region can be formed in this operation. Furthermore, at least one of a cladding layer, a metal layer, or a metal region can be formed in operation 2804 to form the semiconductor structure.

[0173] The flowcharts and block diagrams depicting different embodiments illustrate the architecture, functionality, and operation of some possible implementations of the apparatus and methods in the illustrative embodiments. In this regard, each block in the flowchart or block diagram may represent at least one of a module, segment, function, or operation or step. For example, one or more blocks may be implemented as instructions in program code, hardware, or a combination of program code and hardware to control manufacturing equipment used to manufacture semiconductor structures. When implemented in hardware, the hardware may take the form, for example, an integrated circuit manufactured or configured to perform one or more operations in the flowchart or block diagram. When implemented as a combination of program code and hardware, the implementation may take the form of firmware. Each block in the flowchart or block diagram may be implemented using a dedicated hardware system performing different operations, or a combination of dedicated hardware and program code executed by the dedicated hardware, to operate manufacturing equipment to manufacture semiconductor structures.

[0174] In some alternative implementations of the illustrative embodiments, one or more functions marked in the boxes may occur in a different order than those shown in the figures. For example, in some cases, depending on the functions involved, two boxes may be displayed substantially simultaneously and consecutively, or sometimes these boxes may occur in reverse order. Moreover, in addition to the illustrated boxes in the flowchart or block diagram, other boxes may be added.

[0175] For example, the bonding in operation 2604 is shown to occur prior to etching the silicon carbide substrate in operation 2610. In other illustrative examples, the bonding in operation 2604 may occur after etching in operation 2610. As another example, alternative to or other than the silicon dioxide shown and described in the figures, other dielectrics with desired properties, such as a desired dielectric constant, may be used.

[0176] Now transferred to Figure 29 A block diagram of a product management system is illustrated according to an illustrative embodiment. The product management system 2900 is a physical hardware system. In this illustrative example, the product management system 2900 includes at least one of a manufacturing system 2902 or a maintenance system 2904.

[0177] Manufacturing system 2902 is configured to manufacture products. As depicted, manufacturing system 2902 includes manufacturing equipment 2906. Manufacturing equipment 2906 includes at least one of processing equipment 2908 or assembly equipment 2910.

[0178] Processing equipment 2908 is equipment for manufacturing components for forming parts of a product. Processing equipment 2908 can be used to manufacture at least one of metal parts, composite parts, semiconductors, circuits, fasteners, ribs, skin panels, spars, antennas, or other suitable types of parts.

[0179] For example, processing equipment 2908 may include machines and tools. These machines and tools may be at least one of drills, hydraulic presses, furnaces, molds, composite tape laying machines, vacuum systems, lathes, or other suitable types of equipment.

[0180] Regarding the manufacture of semiconductor components, the processing equipment 2908 may include at least one of the following: an epitaxial reactor, an oxidation system, a diffusion system, an etching machine, a cleaning machine, a bonding machine, a dicing machine, a wafer saw, an ion implanter, a physical vapor deposition system, a chemical vapor deposition system, a lithography system, an electron beam lithography system, a plasma etching machine, a die attaching machine, a wire bonding machine, a die covering system, forming equipment, a hermetic sealing machine, an electrical tester, an aging furnace, a heat preservation oven, a UV eraser, or other suitable type of equipment.

[0181] Assembly equipment 2910 is equipment used to assemble parts to form products such as chips, integrated circuits, computers, aircraft, or some other product. Assembly equipment 2910 may also include machines and tools. These machines and tools may be at least one of robotic arms, tracks, fastener installation systems, track-based drilling systems, or robots.

[0182] In this illustrative example, maintenance system 2904 includes maintenance equipment 2912. Maintenance equipment 2912 may include any equipment required for maintaining the product. Maintenance equipment 2912 may include tools for performing various operations on parts of the product. These operations may include at least one of disassembling parts, refurbishing parts, inspecting parts, reworking parts, manufacturing replacement parts, or at least one of other operations for maintaining the product. These operations may be used for routine maintenance, inspection, upgrades, refurbishment, or other types of maintenance operations.

[0183] In illustrative examples, maintenance equipment 2912 may include an ultrasonic inspection device, an X-ray imaging system, a vision system, a drill bit, tracks, and other suitable devices. In some cases, maintenance equipment 2912 may include processing equipment 2908, assembly equipment 2910, or both, to produce and assemble the parts required for maintenance.

[0184] The product management system 2900 also includes a control system 2914. The control system 2914 is a hardware system and may also include software or other types of components. The control system 2914 is configured to control the operation of at least one of the manufacturing system 2902 or the maintenance system 2904. Specifically, the control system 2914 can control the operation of at least one of the processing equipment 2908, the assembly equipment 2910, or the maintenance equipment 2912.

[0185] The hardware in control system 2914 can be implemented using hardware that may include computers, circuits, networks, and other types of devices. This control can take the form of direct control of manufacturing equipment 2906. For example, robots, computer-controlled machines, and other equipment can be controlled by control system 2914. In other illustrative examples, control system 2914 can manage the operations performed by human operator 2916 during product manufacturing or maintenance. For example, control system 2914 can assign tasks, provide instructions, display models, or perform other operations to manage the operations performed by human operator 2916. In these illustrative examples, the different steps described and illustrated in the fabrication of semiconductor structures using silicon carbide and Group III nitride layers can be implemented using control system 2914.

[0186] In various illustrative examples, operator 2916 may operate and interact with at least one of manufacturing equipment 2906, maintenance equipment 2912, or control system 2914. Such interaction may occur to manufacture other components of semiconductor structures and products, such as semiconductor devices or components used in products such as aircraft, spacecraft, communication systems, microelectromechanical systems, photonic devices, or superconducting single-photon detectors.

[0187] Therefore, illustrative examples provide methods, apparatus, and systems for fabricating semiconductor structures. In one illustrative example, a method forms a semiconductor structure. A first oxide layer on a set of Group III nitride layers formed on a silicon carbide substrate is bonded to a second oxide layer on a carrier substrate to form an oxide layer between the carrier substrate and the set of Group III nitride layers. The silicon carbide substrate has a doped layer. The silicon carbide substrate with the doped layer is etched using a photoelectrochemical etching process, wherein the doping level of the doped layer is such that the doped layer is removed and the silicon carbide layer in the silicon carbide substrate remains unetched. A semiconductor structure is formed using the silicon carbide layer and the set of Group III nitride layers.

[0188] Furthermore, the method in the illustrative examples is suitable for processing large-area wafers, such as those with an area of ​​10 cm². 2 Or larger wafers. The illustrative examples are compatible with currently used methods for these types of wafers to produce low-loss, high-thickness-uniformity silicon carbide and group III nitride-based crystal structures on low-refractive-index insulators. This enables the production of active and passive integrated photonic and electronic products using silicon carbide and group III nitrides.

[0189] For example, illustrative examples may include the following combination: wafer bonding, followed by grinding / polishing or chemical mechanical polishing to thin the silicon carbide substrate, and then photoelectrochemical etching from the carbon surface of the silicon carbide substrate. By utilizing its material-selective etching properties, the photoelectrochemical etching used in the listed examples planarizes the silicon carbide layer into a clean crystal interface, resulting in a uniform silicon carbide film thickness.

[0190] To facilitate photoelectrochemical etching, an electrode can be attached to another doped layer of silicon carbide located beneath the surface to be etched or the doped layer to be etched, and the second electrode can be placed in an etching solution. Performing photoelectrochemical etching in this manner provides a different approach to producing silicon carbide on an insulating film compared to currently used techniques. Furthermore, the method in the illustrative examples can be used to produce submicron-thick films of silicon carbide and Group III nitrides while preserving the structure beneath the doped layer (e.g., pin junction) and the exposed silicon carbide surface.

[0191] In illustrative examples, the final restructure can take many different forms. For example, but not limited to, the semiconductor structure can be selected from at least one of optical waveguides using point defects within a silicon carbide device layer, slot waveguides, ridge waveguides, rib waveguides, buried optical waveguides, suspended waveguides, optical resonators, or photonic quantum memories. In other words, the semiconductor structure can include one or more of these devices, and can include multiple devices of the same type.

[0192] Various illustrative embodiments have been presented for purposes of illustration and description, and are not intended to be exhaustive or limited to the embodiments disclosed. The various illustrative examples describe components that perform actions or operations. In the illustrative embodiments, components may be configured to perform the described actions or operations. For example, the structure of a component may have a configuration or design that provides the component with the ability to perform the actions or operations described in the illustrative examples as being performed by the component. Furthermore, for the purposes of this document, the terms “comprising,” “including,” “having,” “containing,” and variations thereof are intended to encompass in a manner similar to the term “comprising” as an open-ended transitional term, but do not exclude any additional or other elements.

[0193] Furthermore, this disclosure includes implementation methods according to the following terms:

[0194] Clause 1. A method for forming a semiconductor structure, the method comprising:

[0195] (2600) A set of Group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) are formed on a silicon carbide substrate (100, 1003), wherein the silicon carbide substrate (100, 1003) includes a doped layer (106, 904, 1302), and wherein the doping level of the doped layer (106, 904, 1302) is such that the doped layer (106, 904, 1302) is etched using a photoelectrochemical etching process, while other portions of the silicon carbide substrate (100, 1003) remain unetched;

[0196] (2602) A first oxide layer (402, 912) is formed on the group of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), wherein the group of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is located between the first oxide layer (402, 912) and the silicon carbide substrate (100, 1003);

[0197] (2604) The first oxide layer (402, 912) is bonded to the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form a first oxide layer (504, 1002) located on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2402). The oxide layers (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) between the group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2104, 2204, 2304) and the group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2004, 2104, 2204, 2304);

[0198] (2606) Grind the silicon carbide substrate (100, 1003);

[0199] (2608) Stop polishing when a portion of the doped layer (106, 904, 1302) in the silicon carbide substrate (100, 1003) is reached;

[0200] (2610) A photoelectrochemical etching process is used to etch silicon carbide substrates (100, 1003) such that when the portion of the doped layers (106, 904, 1302) in the silicon carbide substrates (100, 1003) is exposed, the doped layers (106, 904, 1302) are removed, while the silicon carbide device layers (100, 906) in the silicon carbide substrates (100, 1003) are retained; and

[0201] (2612) A semiconductor structure is formed using silicon carbide device layers (100, 906) and group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

[0202] Clause 2. The method of Clause 1, wherein the first oxide layer (402, 912) is bonded to the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form a first oxide layer (504, 1002) located on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302). The oxide layers (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) between the group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) and the group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) are etched after etching the silicon carbide substrate (100, 1003).

[0203] Clause 3. The method of any one of the preceding clauses, wherein a first oxide layer (402, 912) is bonded to the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form a first oxide layer (504, 1002) located on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the group III nitride layers (200, 908, 910, 1...). The oxide layers (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) between the group of group III nitride layers (308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) are etched after etching the group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

[0204] Clause 4. The method of any one of the preceding clauses, wherein the first oxide layer (402, 912) is bonded to the first oxide layer (504, 1002) on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form a first oxide layer (504, 1002) located on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402). The oxide layers (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) between the group III nitride layers (302, 2402) and the oxide layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) are etched before the silicon carbide substrate (100, 1003).

[0205] Clause 5. The method of any one of the preceding clauses, wherein the first oxide layer (402, 912) is bonded to the first oxide layer (504, 1002) on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form a first oxide layer (504, 1002) located on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402). The oxide layers (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) between the group III nitride layers (102, 2202, 2302, 2402) and the oxide layers (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) between the group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2004, 2104, 2204, 2304) comprise:

[0206] (2700) The first surface of the first oxide layer (402, 912) is brought into contact with the second surface of the first oxide layer (504, 1002), wherein intermolecular interactions occur between the first oxide layer (402, 912) and the first oxide layer (504, 1002); and

[0207] The first oxide layer (402, 912) and the first oxide layer (504, 1002) are annealed (2702) while the first surface is brought into direct contact with the second surface to form an oxide layer (600, 1100, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

[0208] Clause 6. The method of any one of the preceding clauses, wherein the silicon carbide substrate (100, 1003) is etched using a photoelectrochemical etching process such that when a portion of the doped layer (106, 904, 1302) in the silicon carbide substrate (100, 1003) is exposed, the doped layer (106, 904, 1302) is removed and the silicon carbide device layer (100, 906) in the silicon carbide substrate (100, 1003) is retained, comprises:

[0209] One of the silicon and carbon faces of a silicon carbide substrate (100, 1003) is etched using a photoelectrochemical etching process, such that when a portion of the doped layer (106, 904, 1302) in the silicon carbide substrate (100, 1003) is exposed, the doped layer (106, 904, 1302) is removed, while the silicon carbide device layer (100, 906) in the silicon carbide substrate (100, 1003) remains.

[0210] Clause 7. The method of any one of the preceding clauses, wherein the doped layer (106, 904, 1302) is a sacrificial layer that enables the formation of a silicon carbide device layer (100, 906) on a wafer, the silicon carbide device layer (100, 906) having at least one of a desired thickness uniformity or a desired level of optical performance.

[0211] Clause 8. The method described in Clause 1, wherein the semiconductor structure is selected from at least one of optical waveguides using point defects within silicon carbide device layers (100, 906), slot waveguides, ridge waveguides, rib waveguides, buried optical waveguides, suspended waveguides, optical resonators, or photonic emission quantum memories.

[0212] Clause 9. The method of any one of the preceding clauses, wherein the silicon carbide device layer (100, 906) and the group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) are thin film layers.

[0213] Clause 10. The method described in Clause 1, wherein the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) is one of a silicon carbide substrate (100, 1003), a silicon substrate, an aluminum oxide substrate, a gallium oxide substrate, a silicon dioxide substrate, an aluminum nitride substrate, and a gallium nitride substrate.

[0214] Clause 11. The method of any one of the preceding clauses, wherein the group III nitride layer (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) comprises at least one of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and indium aluminum gallium nitride (InAlGaN).

[0215] Clause 12. A method for forming a semiconductor structure, the method comprising:

[0216] (2800) A first oxide layer (402, 912) located on a set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) formed on silicon carbide substrates (100, 1003) is combined with a first oxide layer (504, 1002) located on a carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form a first oxide layer (402, 912) located on a carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402). The oxide layers (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) between the group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) and the group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), wherein the silicon carbide substrate (100, 1003) has doped layers (106, 904, 1302);

[0217] (2082) A silicon carbide substrate (100, 1003) with doped layers (106, 904, 1302) is etched using a photoelectrochemical etching process, wherein the doping level of the doped layers (106, 904, 1302) is such that the doped layers (106, 904, 1302) are removed and the silicon carbide device layers (100, 906) in the silicon carbide substrate (100, 1003) remain unetched; and

[0218] (2804) The semiconductor structure is formed using silicon carbide device layers (100, 906) and group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

[0219] Clause 13. The method described in Clause 12 further includes:

[0220] (2606) The silicon carbide substrate (100, 1003) is ground before etching; and

[0221] (2608) Before etching the silicon carbide substrate (100, 1003), the grinding of the silicon carbide substrate (100, 1003) is stopped when a portion of the doped layer (106, 904, 1302) in the silicon carbide substrate (100, 1003) is reached.

[0222] Clause 14. The method described in any one of Clauses 12-13 further comprises:

[0223] (2600) Forming the group III group nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) on silicon carbide substrates (100, 1003); and

[0224] (2602) A first oxide layer (402, 912) is formed on the group of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), wherein the group of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is located between the first oxide layer (402, 912) and the silicon carbide substrate (100, 1003).

[0225] Clause 15. The method of any one of Clauses 12-14, wherein a first oxide layer (402, 912) located on a group III nitride layer (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) formed on a silicon carbide substrate (100, 1003) is combined with a first oxide layer (504, 1002) located on a carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402). The formation of oxide layers (600, 1100, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) between the carrier substrates (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2310, 2312) and the group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is performed after etching the silicon carbide substrate (100, 1003).

[0226] Clause 16. The method of any one of Clauses 12-15, wherein a first oxide layer (402, 912) is bonded to the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form a first oxide layer (504, 1002) located on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the group III nitride layers (200, 908, 91). The oxide layers (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) between the group of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) are etched after etching the group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

[0227] Clause 17. The method of any one of Clauses 12-16, wherein a first oxide layer (402, 912) located on a group III nitride layer (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) formed on a silicon carbide substrate (100, 1003) is combined with a first oxide layer (504, 1002) located on a carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402). The formation of oxide layers (600, 1100, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) between the carrier substrates (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2310, 2312) and the group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is performed before etching the silicon carbide substrate (100, 1003).

[0228] Clause 18. The method of any one of Clauses 12-17, wherein the first oxide layer (402, 912) located on the group III group nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) formed on the silicon carbide substrate (100, 1003) and the first oxide layer (402, 912) located on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) formed on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) are... The bonding of 504, 1002) to form an oxide layer (600, 1100, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) between a carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2212, 2310, 2312) and the group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) comprises:

[0229] (2700) The first surface of the first oxide layer (402, 912) is brought into contact with the second surface of the first oxide layer (504, 1002), wherein intermolecular interactions occur between the first oxide layer (402, 912) and the first oxide layer (504, 1002); and

[0230] (2702) Anneal the first oxide layer (402, 912) and the first oxide layer (504, 1002) while making the first surface directly contact the second surface to form an oxide layer (600, 1100, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the group III nitride layer (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

[0231] Clause 19. The method of any one of Clauses 12-18, wherein the doped layer (106, 904, 1302) is a sacrificial layer that enables the formation of a silicon carbide device layer (100, 906) on a wafer, the silicon carbide device layer (100, 906) having at least one of a desired thickness uniformity or a desired level of optical performance.

[0232] Clause 20. The method of any one of Clauses 12-19, wherein the semiconductor structure is selected from at least one of optical waveguides using point defects in silicon carbide device layers (100, 906), slot waveguides, ridge waveguides, rib waveguides, buried optical waveguides, suspended waveguides, optical resonators, or photonic emission quantum memories.

[0233] Clause 21. The method of any one of Clauses 12-20, wherein the silicon carbide device layer (100, 906) and the group III nitride layer (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) are thin film layers.

[0234] Clause 22. The method of any one of Clauses 12-21, wherein the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) is one of a silicon carbide substrate (100, 1003), a silicon substrate, an aluminum oxide substrate, a gallium oxide substrate, a silicon dioxide substrate, an aluminum nitride substrate, and a gallium nitride substrate.

[0235] Clause 23. The method of any one of Clauses 12-22, wherein the group III nitride layer (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) comprises at least one of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and indium aluminum gallium nitride (InAlGaN).

[0236] Clause 24. A method for forming a semiconductor structure, the method comprising:

[0237] (2800) A first oxide layer (402, 912) on a silicon carbide substrate (100, 1003) is bonded to a first oxide layer (504, 1002) on a carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form a first oxide layer (504, 1002) on a carrier substrate (500, 1000, 1314). The oxide layers (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) between the silicon carbide substrates (100, 1003) and the silicon carbide substrates (1602, 1802, 2002, 2102, 2202, 2302), wherein the silicon carbide substrates (100, 1003) have doped layers (106, 904, 1302);

[0238] (2802) The silicon carbide substrate (100, 1003) having the doped layers (106, 904, 1302) is etched using a photoelectrochemical etching process, wherein the doping level of the doped layers (106, 904, 1302) is such that the doped layers (106, 904, 1302) are removed and the silicon carbide device layers (100, 906) in the silicon carbide substrate (100, 1003) remain unetched; and

[0239] (2804) A semiconductor structure is formed using the silicon carbide device layers (100, 906).

[0240] Clause 25. The method described in Clause 24, wherein etching a silicon carbide substrate (100, 1003) having a doped layer (106, 904, 1302) using a photoelectrochemical etching process comprises:

[0241] The carbon surface of a silicon carbide substrate (100, 1003) with doped layers (106, 904, 1302) is etched using a photoelectrochemical etching process, wherein the doping level of the doped layers (106, 904, 1302) is such that the doped layers (106, 904, 1302) are removed and the silicon carbide device layer (100, 906) in the silicon carbide substrate (100, 1003) remains unetched.

[0242] Clause 26. The method of any one of Clauses 24-25, wherein the first oxide layer (402, 912) is in direct contact with the silicon carbide substrate (100, 1003).

[0243] Clause 27. The method of any one of Clauses 24-26, wherein a set of Group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) are located between the first oxide layer (402, 912) and the silicon carbide substrate (100, 1003).

[0244] Clause 28. A product management system (2900) comprising:

[0245] Manufacturing equipment (2914); and

[0246] Control system, wherein the control system controls the manufacturing equipment (2914) in the following ways:

[0247] A first oxide layer (402, 912) on a set of Group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) formed on a silicon carbide substrate (100, 1003) is combined with a first oxide layer (504, 1002) on a carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form a first oxide layer (402, 912) on the carrier substrate (500, 1003). The oxide layers (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) between the group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) and the group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), wherein the silicon carbide substrate (100, 1003) has doped layers (106, 904, 1302);

[0248] Silicon carbide substrates (100, 1003) with doped layers (106, 904, 1302) were etched using a photoelectrochemical etching process, wherein the doping level of the doped layers (106, 904, 1302) was such that the doped layers (106, 904, 1302) were removed while the silicon carbide device layers (100, 906) in the silicon carbide substrates (100, 1003) remained unetched; and

[0249] A semiconductor structure is formed using silicon carbide device layers (100, 906) and group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

[0250] Clause 29. The product management system (2900) described in Clause 28, wherein the control system controls the manufacturing equipment (2914) to further include:

[0251] Before etching the silicon carbide substrates (100, 1003), the silicon carbide substrates (100, 1003) are polished; and

[0252] Before etching the silicon carbide substrate (100, 1003), the grinding of the silicon carbide substrate (100, 1003) is stopped when a portion of the doped layer (106, 904, 1302) in the silicon carbide substrate (100, 1003) is reached.

[0253] Clause 30. The product management system (2900) of any one of Clauses 28-29, wherein the control system controls the manufacturing equipment (2914) in the following manner:

[0254] The group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) are formed on the silicon carbide substrates (100, 1003); and

[0255] A first oxide layer (402, 912) is formed on the group of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), wherein the group of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is located between the first oxide layer (402, 912) and the silicon carbide substrate (100, 1003).

[0256] Clause 31. The product management system (2900) of any one of Clauses 28-30, wherein the semiconductor structure is selected from at least one of optical waveguides using point defects in silicon carbide device layers (100, 906), slot waveguides, ridge waveguides, rib waveguides, embedded optical waveguides, suspended waveguides, optical resonators, or photonic quantum memories.

[0257] Clause 32. The product management system (2900) of any one of Clauses 28-31, wherein the silicon carbide device layer (100, 906) and the group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) are thin film layers.

[0258] Clause 33. The product management system (2900) of any one of Clauses 28-32, wherein the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) is one of a silicon carbide substrate (100, 1003), a silicon substrate, an aluminum oxide substrate, a gallium oxide substrate, a silicon dioxide substrate, an aluminum nitride substrate, and a gallium nitride substrate.

[0259] Clause 34. The product management system (2900) of any one of Clauses 28-33, wherein the group III nitride layer (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) comprises at least one of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and indium aluminum gallium nitride (InAlGaN).

[0260] Clause 41. A semiconductor structure comprising:

[0261] Substrates (500, 1000, 1314, 1602, 1802);

[0262] Oxide layers (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) on the substrates (500, 1000, 1314, 1602, 1802);

[0263] A set of Group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2004, 2104, 2204, 2304) on the oxide layers (600, 1100, 1312, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312); and

[0264] A set of silicon carbide layers (100, 906, 1306, 2008, 2108, 2214, 2314) on the group III nitride layer (200).

[0265] Clause 42. The semiconductor structure described in Clause 41, wherein the group of Group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1804, 2004, 2104, 2204, 2304) on the oxide layers (600, 1100, 1312, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is a group of Group III nitride regions.

[0266] Clause 43. The semiconductor structure described in Clause 42, wherein the group III nitride region is buried within a cavity (2208) in an oxide layer (600).

[0267] Clause 44. The semiconductor structure described in Clause 43 further includes:

[0268] A cladding layer (2222) on the group of silicon carbide layers (2214), wherein the refractive index of the cladding layer (2222) is lower than the refractive index of the group of silicon carbide layers (2224).

[0269] Clause 45. The semiconductor structure of any one of Clauses 41-44, wherein the group of silicon carbide layers (100, 906, 1306) is a group of silicon carbide regions.

[0270] Clause 46. The semiconductor structure described in Clause 45, wherein the group of Group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2004, 2104, 2204, 2304) on the oxide layers (600, 1100, 1312, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is a group of Group III nitride regions.

[0271] Clause 47. The semiconductor structure described in Clause 46 further includes:

[0272] Defects in the silicon carbide material in the group of silicon carbide layers (1808).

[0273] Clause 48. The semiconductor structure described in Clause 47, wherein the defect is one of a double vacancy, a silicon single vacancy, other vacancy complexes, a transition metal ion, and a rare earth ion.

[0274] Clause 49. The semiconductor structure described in Clause 45, wherein the group of silicon carbide regions forms a waveguide.

[0275] Clause 50. The semiconductor structure described in Clause 49 further includes:

[0276] The cladding layers (2010, 2112, 2322) on the group of silicon carbide regions have a refractive index lower than that of the group of silicon carbide regions.

[0277] Clause 51. The semiconductor structure described in Clause 50, wherein the cladding (2010, 2112, 2322) comprises at least one material selected from air, vacuum, photoresist, polymer, silicon dioxide, or silicon nitride.

[0278] Clause 52. The semiconductor structure described in Clause 51, wherein the group of silicon carbide layers (100, 906, 1306) includes a silicon carbide layer (2108, 2314) and a silicon carbide region extending from the silicon carbide layer (2108).

[0279] Clause 53. The semiconductor structure described in Clause 52 further includes:

[0280] A cladding layer (2112, 2322) on a silicon carbide layer (2108) and a silicon carbide region, wherein the refractive index of the cladding layer (2112, 2322) is lower than that of the silicon carbide layer (2108) and the silicon carbide region.

[0281] Clause 54. The semiconductor structure described in Clause 51, wherein the group III nitride layer (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is in direct contact with the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304).

[0282] Clause 55. The semiconductor structure described in Clause 51, wherein the group of silicon carbide layers is in direct contact with the group of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

[0283] Clause 56. The semiconductor structure described in Clause 51, wherein the substrate (500, 1000, 1314, 1602, 1802) is one of a silicon carbide substrate, a silicon substrate, an aluminum oxide substrate, a gallium oxide substrate, a silicon dioxide substrate, an aluminum nitride substrate, and a gallium nitride substrate.

[0284] Clause 57. The semiconductor structure described in Clause 51, wherein the group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) comprise at least one of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and indium aluminum gallium nitride (InAlGaN).

[0285] Clause 58. The semiconductor structure described in Clause 51, wherein the group of silicon carbide layers and the group of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) are thin film layers.

[0286] Clause 59. The semiconductor structure described in Clause 51, wherein the semiconductor structure is selected from at least one of optical waveguides, slot waveguides, ridge waveguides, rib waveguides, embedded optical waveguides, suspended waveguides, or optical resonators.

[0287] Clause 60. A semiconductor structure comprising:

[0288] Substrates (500, 1000, 1314, 1602, 1802);

[0289] Oxide layers (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) on substrates (500, 1000, 1314, 1602, 1802); and

[0290] A set of silicon carbide layers (100, 906, 1306, 2008, 2108, 2214, 2314) on a substrate (500, 1000, 1314, 1602, 1802).

[0291] Clause 61. The semiconductor structure described in Clause 60, wherein the group of silicon carbide layers (100, 906, 1306, 2008, 2108, 2214, 2314) on the substrate (500, 1000, 1314, 1602, 1802) are in direct contact with the oxide layers (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304).

[0292] Clause 62. The semiconductor structure described in any one of Clauses 60-61 further comprises:

[0293] A group of Group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) on an oxide layer (600) such that the group of Group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) are located between the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) and the group of silicon carbide layers (100, 906, 1306, 2008, 2108, 2214, 2314).

[0294] Clause 63. The semiconductor structure of any one of Clauses 60-62, wherein the group of silicon carbide layers (100, 906, 1306, 2008, 2108, 2214, 2314) is a group of silicon carbide regions.

[0295] Clause 64. The semiconductor structure of any one of Clauses 60-63, wherein the group of silicon carbide layers (100, 906, 1306, 2008, 2108, 2214, 2314) comprises a silicon carbide layer (2108, 2314) and a silicon carbide region extending from the silicon carbide layer.

[0296] Clause 65. The semiconductor structure described in Clause 64 further includes:

[0297] The silicon carbide layer (2108) and the silicon carbide region have cladding layers (2112, 2322) with a refractive index lower than that of the silicon carbide layer (2108, 2314) and the silicon carbide region.

[0298] Clause 66. The semiconductor structure described in Clause 65, wherein the cladding (2112, 2322) comprises at least one material selected from air, vacuum, photoresist, polymer, silicon dioxide or silicon nitride.

[0299] Clause 67. The semiconductor structure of any one of Clauses 60-66, wherein the group of silicon carbide layers (100, 906, 1306, 2008, 2108, 2214, 2314) is a group of thin film layers.

[0300] Clause 68. The semiconductor structure of claim 60, wherein the substrate (500, 1000, 1314, 1602, 1802) is one of silicon carbide substrate, silicon substrate, aluminum oxide substrate, gallium oxide substrate, silicon dioxide substrate, aluminum nitride substrate and gallium nitride substrate.

[0301] Many modifications and variations will be apparent to those skilled in the art. Furthermore, different illustrative embodiments may provide different features compared to other desired embodiments. One or more embodiments are selected and described in order to best explain the principles and practical applications of the embodiments and to enable others skilled in the art to understand the disclosure of the various embodiments, wherein various modifications are suitable for the specific purpose under consideration.

Claims

1. A method for forming a semiconductor structure, the method comprising: forming (2600) a set of Group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) on a silicon carbide substrate (100, 1003), wherein the silicon carbide substrate (100, 1003) includes a doped layer (106, 904, 1302), and wherein the doped layer (106, 904, 1302) has a doping level such that the doped layer (106, 904, 1302) is etched using a photoelectrochemical etching process while other portions of the silicon carbide substrate (100, 1003) remain unetched; forming (2602) a first oxide layer on the set of Group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), wherein the set of Group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is between the first oxide layer and the silicon carbide substrate (100, 1003); bonding (2604) the first oxide layer to a first oxide layer on a carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form an oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the set of Group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312); lapping (2606) the silicon carbide substrate (100, 1003); stopping (2608) lapping when a portion of the doped layer (106, 904, 1302) in the silicon carbide substrate (100, 1003) is reached; etching (2610) the silicon carbide substrate (100, 1003) using the photoelectrochemical etching process such that the doped layer (106, 904, 1302) is removed and a silicon carbide device layer in the silicon carbide substrate (100, 1003) is preserved when the portion of the doped layer (106, 904, 1302) in the silicon and Step (2612) forms the semiconductor structure using the silicon carbide device layer and the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

2. The method of claim 1, wherein step (2604) is performed after etching the silicon carbide substrate (100, 1003).

3. The method of any of the preceding claims, wherein step (2604) is performed after etching a group III nitride layer in the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

4. The method of any of claims 1-2, wherein step (2604) is performed before etching the silicon carbide substrate (100, 1003).

5. The method of any of claims 1-2, wherein step (2604) comprises: Step (2700) contacts a first surface of a first oxide layer on the set of group III nitride layers with a second surface of a first oxide layer on the carrier substrate, wherein intermolecular interactions occur between the two first oxide layers; and Step (2702) anneals the two first oxide layers while the first surface is in direct contact with the second surface to form an oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

6. The method of any of claims 1-2, wherein step (2610) comprises: etching one of a silicon face and a carbon face of the silicon carbide substrate (100, 1003) using the photoelectrochemical etching process such that the doped layer (106, 904, 1302) is removed and the silicon carbide device layer in the silicon carbide substrate (100, 1003) is preserved when the portion of the doped layer (106, 904, 1302) in the silicon carbide substrate (100, 1003) is exposed.

7. The method of any of claims 1-2, wherein the doped layer (106, 904, 1302) is a sacrificial layer that enables formation of the silicon carbide device layer on a wafer with at least one of a desired thickness uniformity or a desired level of optical performance, and / or wherein the semiconductor structure is selected from at least one of an optical waveguide, a slot waveguide, a rib waveguide, a buried optical waveguide, a suspended waveguide, an optical resonator, or a photonic emission quantum memory that uses point defects within the silicon carbide device layer.

8. The method of any of claims 1-2, wherein the silicon carbide device layer and the group III nitride layer (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) are thin film layers, wherein the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) is one of a silicon carbide substrate (100, 1003), a silicon substrate, an aluminum oxide substrate, a gallium oxide substrate, a silicon dioxide substrate, an aluminum nitride substrate, and a gallium nitride substrate, and / or wherein the group III nitride layer (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) includes at least one of gallium nitride (GaN), aluminum nitride (AIN), indium nitride (InN), and indium aluminum gallium nitride (InAlGaN).

9. A method for forming a semiconductor structure, the method comprising: bonding (2800) a first oxide layer located on a group III nitride layer (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) formed on a silicon carbide substrate (100, 1003) with a first oxide layer located on a carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form an oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) between the carrier substrate (500, 1000, 1314, 1602, 1 802, 2002, 2102, 2202, 2302, 240 2) and the group III nitride layer (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), wherein the silicon carbide substrate (100, 1003) has a doped layer (106, 904, 1302). Step (2082) etching the silicon carbide substrate (100, 1003) having the doped layer (106, 904, 1302) using a photoelectrochemical etching process, wherein the doping level of the doped layer (106, 904, 1302) is such that the doped layer (106, 904, 1302) is removed and a silicon carbide device layer in the silicon carbide substrate (100, 1003) remains unetched; and Step (2804) forming the semiconductor structure using the silicon carbide device layer and the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

10. The method of claim 9, further comprising: Step (2606) lapping the silicon carbide substrate (100, 1003) prior to etching the silicon carbide substrate (100, 1003); Step (2608) stopping lapping of the silicon carbide substrate (100, 1003) when a portion of the doped layer (106, 904, 1302) in the silicon carbide substrate (100, 1003) is reached prior to etching the silicon carbide substrate (100, 1003); Step (2600) forming the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) on the silicon carbide substrate (100, 1003); and / or Step (2602) forming a first oxide layer on the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), wherein the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is between the first oxide layer and the silicon carbide substrate (100, 1003).

11. The method of any of claims 9-10, wherein step (2800) is performed after etching the silicon carbide substrate (100, 1003).

12. The method of any of claims 9-10, wherein step (2800) is performed after etching a group III nitride layer in the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

13. The method of any of claims 9-10, wherein step (2800) is performed prior to etching the silicon carbide substrate (100, 1003).

14. The method of any of claims 9-10, wherein step (2800) comprises: step (2700) contacting a first surface of a first oxide layer on the set of Group III nitride layers with a second surface of a first oxide layer on the carrier substrate, wherein intermolecular interactions occur between the two first oxide layers; and step (2702) annealing the two first oxide layers while the first surface is in direct contact with the second surface to form the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the set of Group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

15. The method of any of claims 9-10, wherein the doped layer (106, 904, 1302) is a sacrificial layer that enables formation of a silicon carbide device layer on a wafer having at least one of a desired thickness uniformity or a desired level of optical performance, wherein the semiconductor structure is selected from at least one of an optical waveguide, a slot waveguide, a rib waveguide, a buried optical waveguide, a suspended waveguide, an optical resonator, or a photonic emission quantum memory using point defects within the silicon carbide device layer, wherein the silicon carbide device layer and the set of Group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) are thin film layers, wherein the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) is one of a silicon carbide substrate (100, 1003), a silicon substrate, an aluminum oxide substrate, a gallium oxide substrate, a silicon dioxide substrate, an aluminum nitride substrate, and a gallium nitride substrate, and / or wherein the set of Group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212 2310, 2312) includes at least one of gallium nitride (GaN), aluminum nitride (AIN), indium nitride (InN), and indium aluminum gallium nitride (InAlGaN).

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