High electron mobility transistor against single event effects and method of manufacturing the same

Abstract

The embodiment of the present application relates to the technical field of semiconductor devices, in particular to a high electron mobility transistor (HEMT) resistant to single event effects and a preparation method thereof, comprising: a substrate and a nucleation layer, a buffer layer, a channel layer and a barrier layer stacked on the substrate in sequence; a source and a drain located on the barrier layer, and the source and the drain form ohmic contact with the barrier layer respectively; a nitride layer located on the barrier layer, and the nitride layer is located between the source and the drain; an enhanced passivation layer located on both sides of the nitride layer, the enhanced passivation layer covers the sidewall and at least part of the top wall of the nitride layer; a gate located on the nitride layer, the bottom of the gate is in contact with the enhanced passivation layer, and the bottom of the gate forms ohmic contact or Schottky contact with the nitride layer. The embodiment of the present application can solve the problem that the existing HEMT is burned out by single event effects under long-time irradiation environment, and the device is broken down in advance.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor devices, and particularly relate to a high electron mobility transistor resistant to single event effects and a preparation method thereof. BACKGROUND

[0002] Gallium nitride (GaN) is a representative of the third generation of semiconductor materials, and has a wide band gap, superior radiation resistance, a high avalanche breakdown field, good thermal conductivity, and a high electron drift rate under a strong field, compared with silicon or gallium arsenide. Therefore, GaN-based power devices are widely used in the fields of lasers, LEDs, microwaves, and radio frequencies. A high electron mobility transistor (HEMT) is a heterojunction field effect transistor, and has high-frequency, high-power, high-temperature resistance, and strong anti-radiation capabilities due to the existence of a high-mobility two-dimensional electron gas (2DEG) in the heterojunction.

[0003] Currently, a passivation layer is usually arranged on both sides of the nitride layer of the high electron mobility transistor (HEMT) to enhance the ability of the HEMT to resist single event effects. However, when the high electron mobility transistor is subjected to single event effects, not only the edge of the nitride layer has a high peak electric field, but also the passivation layer around the nitride layer is also subjected to a high peak electric field. The high electron mobility transistor (HEMT) is likely to exceed the critical breakdown field of the passivation layer under a long-time irradiation environment, thereby accelerating single event burnout and causing the HEMT device to break down prematurely. SUMMARY

[0004] Embodiments of the present application provide a high electron mobility transistor resistant to single event effects and a preparation method thereof, which enhances the critical breakdown field of both sides of the nitride to improve the ability of the electron mobility transistor to resist single event effects.

[0005] To solve the above technical problem, embodiments of the present application provide a high electron mobility transistor resistant to single event effects, which includes a substrate and a nucleation layer, a buffer layer, a channel layer, and a barrier layer stacked in sequence on the substrate; a source electrode and a drain electrode located on the barrier layer and forming ohmic contacts with the barrier layer, respectively; a nitride layer located on the barrier layer and between the source electrode and the drain electrode; an enhanced passivation layer located on both sides of the nitride layer, the enhanced passivation layer covering the sidewalls and at least part of the top wall of the nitride layer; and a gate electrode located on the nitride layer, the bottom of the gate electrode being in contact with the enhanced passivation layer, and the bottom of the gate electrode forming an ohmic contact or a Schottky contact with the nitride layer.

[0006] In some example embodiments, the material of the enhanced passivation layer comprises one of HfO2, TiO2, ZrO2, Y2O3, La2O3, Ta2O5, SiO2, Si3N4.

[0007] In some example embodiments, the height of the enhanced passivation layer is 90nm-400nm in the direction from the gate to the nitride layer.

[0008] In some example embodiments, the material of the nitride layer comprises P-type gallium nitride or P-type aluminum nitride.

[0009] In some example embodiments, the single event effect resistant high electron mobility transistor further comprises: a first passivation layer between the enhanced passivation layer on the side of the nitride layer close to the source and the source; and a second passivation layer between the enhanced passivation layer on the side of the nitride layer close to the drain and the drain.

[0010] In some example embodiments, the critical breakdown field strength of the material of the enhanced passivation layer is greater than the critical breakdown field strength of the material of the first passivation layer, and the critical breakdown field strength of the material of the enhanced passivation layer is greater than the critical breakdown field strength of the material of the second passivation layer.

[0011] In some example embodiments, the material of the first passivation layer comprises one of SiO2, Al2O3, Si3N4; and / or the material of the second passivation layer comprises one of SiO2, Al2O3, Si3N4.

[0012] In some example embodiments, the height of the enhanced passivation layer is greater than or equal to the height of the first passivation layer in the direction from the gate to the nitride layer; and / or the height of the enhanced passivation layer is greater than or equal to the height of the second passivation layer in the direction from the gate to the nitride layer.

[0013] In another aspect, the present application also provides a method for manufacturing a single event effect resistant high electron mobility transistor, comprising: providing a substrate; forming a nucleation layer, a buffer layer, a channel layer and a barrier layer in sequence on the substrate; forming an epitaxial layer on the side of the barrier layer away from the channel layer; etching the epitaxial layer to form a nitride layer; forming a source and a drain on the barrier layer; forming an enhanced passivation material layer on the side of the nitride layer close to the source and the side of the nitride layer close to the drain; etching the enhanced passivation material layer to form an enhanced passivation layer; the enhanced passivation layer covering the sidewall and at least part of the top wall of the nitride layer; forming a gate on the nitride layer; and leading electrodes above the gate, the source and the drain.

[0014] In some example embodiments, when the etching of the enhanced passivation material layer exposes part of the surface of the barrier layer, the method for manufacturing the anti-single particle effect high electron mobility transistor further comprises: forming a passivation material layer above the barrier layer, the source electrode, the drain electrode, the enhanced passivation layer and the gate electrode; and etching the passivation material layer to form a first passivation layer and a second passivation layer.

[0015] The technical scheme provided in the embodiments of the present application has at least the following advantages:

[0016] The embodiments of the present application are directed to the problem that the existing anti-single particle effect high electron mobility transistor is easy to exceed the critical breakdown field in a long irradiation environment, resulting in accelerated single particle burnout and premature breakdown of the device. The embodiments of the present application provide an anti-single particle effect high electron mobility transistor and a manufacturing method thereof. An enhanced passivation layer is arranged at the region where the device is easy to break down (i.e. the two sides of the nitride layer). The enhanced passivation layer can well withstand the high peak electric field at the edge of the nitride layer, thereby greatly improving the anti-single particle effect capability of the electron mobility transistor. The enhanced passivation layer covers the sidewall and at least part of the top wall of the nitride layer, plays a role in enhancing the critical breakdown field of the two sides of the nitride, and enables the device to withstand higher voltage, thereby improving the working life and reliability of the device, and having good application prospect. BRIEF DESCRIPTION OF DRAWINGS

[0017] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which are illustrative, but not restrictive, of the present embodiments, unless otherwise specified, the figures in the drawings do not constitute a proportional limitation.

[0018] Figure 1 A structural schematic diagram of a high electron mobility transistor of a conventional structure in the related art;

[0019] Figure 2 A simulation schematic diagram of electric field distribution of a high electron mobility transistor of a conventional structure in the related art under the action of single particle effect;

[0020] Figure 3 A structural schematic diagram of an anti-single particle effect high electron mobility transistor provided by an embodiment of the present application;

[0021] Figure 4 A structural schematic diagram of an anti-single particle effect high electron mobility transistor provided by another embodiment of the present application;

[0022] Figure 5 A flowchart of a manufacturing method of an anti-single particle effect high electron mobility transistor provided by an embodiment of the present application;

[0023] Figures 6-11 A preparation method of an anti-single particle effect high electron mobility transistor provided by an embodiment of the present application corresponds to a cross-sectional structure schematic diagram of each step;

[0024] Figure 12 A flowchart of a preparation method of an anti-single particle effect high electron mobility transistor provided by another embodiment of the present application;

[0025] Figures 13-15 A preparation method of an anti-single particle effect high electron mobility transistor provided by another embodiment of the present application corresponds to a cross-sectional structure schematic diagram of each step;

[0026] Figure 16 An electric field distribution simulation schematic diagram of an anti-single particle effect high electron mobility transistor provided by an embodiment of the present application under the action of a single particle effect. DETAILED DESCRIPTION

[0027] As known from the background art, the existing high electron mobility transistor is likely to exceed the critical breakdown field of the passivation layer under long-time irradiation environment, thereby accelerating single particle burnout and causing the device to break down prematurely.

[0028] With the continuous development of space satellites, space exploration and other space technologies, the demand for high-temperature-resistant, high-power, miniaturized and extreme radiation environment-adaptable power systems is increasingly obvious. As one of the core representatives of wide bandgap semiconductor technology, gallium nitride-based power devices have the advantages of high breakdown voltage, small on-resistance, high-temperature resistance and radiation resistance compared with traditional silicon devices, and can meet the application requirements of new generation of spacecraft power systems. In the universe, there are various high-energy particles, and space systems are always threatened by high-energy particles in such an environment.

[0029] When high-energy ions act on these integrated circuits and semiconductor devices, a series of effects will be triggered, one of which is single event effect. Single event effect refers to a radiation effect that causes the state of an electronic device to change abnormally when a single high-energy particle enters the sensitive area of the device. It is a phenomenon that occurs with the trend of designing electronic devices towards smaller feature sizes and higher device densities. The most important failure mode is single event burnout of power devices. Single event burnout has become a key technology that restricts the development of aerospace anti-radiation fields. Mature silicon-based devices do not have strong anti-radiation ability due to their own material properties, making it difficult to apply them to the field of aerospace anti-radiation. The advantages of gallium nitride power devices are highlighted. Although there has been some research on single event burnout of third-generation wide-bandgap devices, the threshold voltage of single event burnout of all material devices is very low and much lower than the breakdown voltage of the device itself, which has serious reliability problems. It is urgent to develop new transistor structures with enhanced single event burnout resistance.

[0030] In related technologies, conventional passivation layers are usually used on both sides of the nitride to enhance the ability of the device to resist single event effects. Referring to Figure 1 , a high electron mobility transistor of a conventional structure includes a substrate 100, a nucleation layer 101, a buffer layer 102, a channel layer 103, a barrier layer 104, a source 105, a drain 106, and a nitride layer 107. The nitride layer 107 is located between the source 105 and the drain 106. A gate 109 is provided above the nitride layer 107. Conventional passivation layers 120 are provided on both sides of the nitride layer 107. The edges of the conventional passivation layers 120 close to the nitride layer 107 are flush with the outer edges of the nitride layer 107. The high electron mobility transistor of the conventional structure withstands high peak electric fields by providing conventional passivation layers 120 on both sides of the nitride layer 107.

[0031] Figure 2 An electric field distribution simulation result schematic diagram of a high electron mobility transistor of a conventional structure under the action of single event effects is shown. As Figure 2 shown, when the high electron mobility transistor of the conventional structure withstands single event effects, not only will the edges of the nitride layer 107 have a high peak electric field, but the conventional passivation layers 120 around the nitride layer 107 will also withstand a high peak electric field (as Figure 2As shown at middle A, the lighter the color, the higher the peak electric field intensity. The conventional passivation layer 120 can be formed by atomic layer deposition (ALD), and the conventional passivation layer 120 formed by ALD has a critical breakdown electric field intensity of about 5 MV / cm. The conventional passivation layer 120 can also be formed by plasma enhanced chemical vapor deposition (PECVD), and the conventional passivation layer 120 formed by PECVD also has a critical breakdown electric field intensity of about 5 MV / cm. Therefore, the high electron mobility transistor of the conventional structure, whether the conventional passivation layer 120 is formed by ALD or PECVD, is prone to exceed the critical breakdown electric field in a long irradiation environment, thereby accelerating single event burnout and causing the device to break down prematurely.

[0032] To solve the above technical problems, the embodiments of the present application provide a high electron mobility transistor resistant to single event effects, comprising: a substrate and a nucleation layer, a buffer layer, a channel layer and a barrier layer stacked in sequence on the substrate; a source and a drain located on the barrier layer and forming ohmic contacts with the barrier layer, respectively; a nitride layer located on the barrier layer and between the source and the drain; an enhanced passivation layer located on both sides of the nitride layer, the enhanced passivation layer covering the sidewalls and at least part of the top wall of the nitride layer; and a gate located on the nitride layer, the bottom of the gate being in contact with the enhanced passivation layer and the bottom of the gate forming an ohmic contact or a Schottky contact with the nitride layer. The embodiments of the present application enhance the critical breakdown electric field on both sides of the nitride layer by arranging the enhanced passivation layer on both sides of the nitride layer, thereby improving the ability of the high electron mobility transistor to resist single event effects.

[0033] The embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art can understand that in the embodiments of the present application, many technical details are presented in order to make the reader better understand the present application. However, the technical solutions claimed by the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0034] Reference is made to Figure 3, an embodiment of the present application provides a high electron mobility transistor with resistance to single particle effect, including: a substrate 100 and a nucleation layer 101, a buffer layer 102, a channel layer 103 and a barrier layer 104 stacked in sequence on the substrate 100; a source 105 and a drain 106 located on the barrier layer 104, and the source 105 and the drain 106 respectively form an ohmic contact with the barrier layer 104; a nitride layer 107 located on the barrier layer 104, and the nitride layer 107 is located between the source 105 and the drain 106; an enhanced passivation layer 108 located on both sides of the nitride layer 107, the enhanced passivation layer 108 covering the sidewalls and at least a portion of the top wall of the nitride layer 107; a gate 109 located on the nitride layer 107, the bottom of the gate 109 contacting the enhanced passivation layer 108, and the bottom of the gate 109 forming an ohmic contact or a Schottky contact with the nitride layer 107.

[0035] The single-event effect-resistant high-electron-mobility transistors provided in the embodiments of this application can be used in power conversion circuits in aerospace systems. Because space contains a variety of high-energy particles, aerospace systems are constantly threatened by these particles. Single-event effects can easily cause single-event burnout in GaN power devices, leading to premature device breakdown. To address this technical issue, this application deposits an enhanced passivation layer 108 with a high critical breakdown electric field in the device's breakdown-prone region (i.e., the edge of the nitride layer 107), enabling it to withstand higher voltages and thereby improving the operating life and reliability of the aerospace power system.

[0036] like Figure 3 As shown, the enhanced passivation layer 108 is located on both side edges of the nitride layer 107, covering the two outer side walls of the nitride layer 107 and the top wall edge of the nitride layer 107, thereby enhancing the passivation of the nitride layer 107. The enhanced passivation layer 108 can well withstand the high peak electric field at the two side edges of the nitride layer, thereby greatly improving the device's ability to resist single particle effects.

[0037] It should be noted that the enhanced passivation layer 108 located at the edges of the nitride layer 107 on both sides is usually made of a material with a high critical breakdown electric field strength, and the critical breakdown electric field strength of the material of the enhanced passivation layer 108 is greater than the critical breakdown electric field strength of the material of the conventional passivation layer. Generally, the material of the enhanced passivation layer 108 can be one of hafnium oxide (HfO2), titanium oxide (TiO2), zirconium oxide (ZrO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), silicon dioxide (SiO2), and silicon nitride (Si3N4). The use of a material with a high critical breakdown electric field strength for the enhanced passivation layer 108 enables the enhanced passivation layer 108 to well withstand the high peak electric field at the edge of the nitride layer 107, thereby significantly improving its ability to resist single-particle effects.

[0038] In some embodiments, the enhancement passivation layer 108 is located between the source 105 and the drain 106, as shown in FIG. 1. Figure 3 As shown, the enhancement passivation layer 108 located on the side of the nitride layer 107 close to the source 105, one side of the enhancement passivation layer 108 is in contact with the source 105, and the other side is in contact with the nitride layer 107; that is, the enhancement passivation layer 108 located on the left side of the nitride layer 107, the left side of the enhancement passivation layer 108 is in contact with the source 105, and the right side is in contact with the nitride layer 107. Similarly, the enhancement passivation layer 108 located on the side of the nitride layer 107 close to the drain 106, one side of the enhancement passivation layer 108 is in contact with the nitride layer 107, and the other side is in contact with the drain 106; that is, the enhancement passivation layer 108 located on the right side of the nitride layer 107, the left side of the enhancement passivation layer 108 is in contact with the nitride layer 107, and the right side is in contact with the drain 106.

[0039] In some embodiments, the material of the nitride layer 107 includes P-type gallium nitride (P-GaN) or P-type aluminum nitride (P-AlN). Preferably, the material of the nitride layer 107 is P-type GaN, and generally, the material of the nitride layer 107 is P-type GaN doped with Mg. The thickness of the nitride layer 107 is 10 nm to 40 nm along the thickness direction of the substrate 100.

[0040] In some exemplary embodiments, the height of the enhancement passivation layer 108 is 90 nm to 400 nm along the direction in which the gate 109 points to the nitride layer 107. Here, the thickness direction of the substrate 100 is the same as the direction in which the gate 109 points to the nitride layer 107, and the thickness of the nitride layer 107 is the height of the nitride layer 107. As can be seen from FIG. 1, Figure 3 It can be seen from FIG. 1 that the height of the enhancement passivation layer 108 is significantly higher than the height of the nitride layer 107, and the enhancement passivation layer 108 completely covers the two side walls of the nitride layer 107, and the enhancement passivation layer 108 partially covers the top wall of the nitride layer 107. Specifically, the enhancement passivation layer 108 covers the two side edge positions of the top wall of the nitride layer 107, and plays a role in enhancing the passivation of the two sides and the top of the nitride layer 107.

[0041] In some embodiments, the material of the substrate 100 includes one of sapphire, silicon carbide (SiC), silicon (Si), and gallium nitride. The direction in which the lower surface of the substrate 100 points to the upper surface of the substrate 100 is the thickness direction, and the thickness of the substrate 100 is 30 nm to 200 nm. It should be noted that the thicknesses of the film layers in the following embodiments of the present application are all the thicknesses of the film layers in the thickness direction.

[0042] In some embodiments, the material of the nucleation layer 101 includes one of gallium nitride, aluminum nitride, and aluminum gallium nitride (AlGaN). Preferably, the material of the nucleation layer 101 is aluminum nitride. The thickness of the nucleation layer 101 is 30-100 nm.

[0043] In some embodiments, the material of the buffer layer 102 includes one or more of gallium nitride, aluminum nitride, and aluminum gallium nitride. The thickness of the buffer layer 102 is 0.5-5 μm.

[0044] In some embodiments, the material of the channel layer 103 includes one of gallium nitride and aluminum gallium nitride. Preferably, the material of the buffer layer 102 and the channel layer 103 is gallium nitride. The thickness of the channel layer 103 is 50-500 nm.

[0045] In some embodiments, the material of the barrier layer 104 is AlGaN with a wurtzite structure. Specifically, the material of the barrier layer 104 is Al x Ga (1-x) N. When the barrier layer 104 is Al x Ga (1-x) N, the composition of Al (the value of x) is 0.1-0.2. The thickness of the barrier layer 104 is 10-40 nm.

[0046] In some embodiments, the source 105 and the drain 106 can be made of a metal combination of Ti / Al / Ni / Au or Ti / Al / Pt / Au, so that the source 105 and the drain 106 form ohmic contacts with the barrier layer 104, respectively.

[0047] In some embodiments, the gate 109 is made of a metal that can form ohmic contact or Schottky contact with the nitride layer 107.

[0048] In some exemplary embodiments, the material of the enhancement passivation layer 108 includes one of hafnium oxide (HfO2), titanium oxide (TiO2), zirconium oxide (ZrO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), silicon dioxide (SiO2), and silicon nitride (Si3N4).

[0049] The material of the enhancement passivation layer 108 in the embodiments of the present application is made of a material with a high critical breakdown field strength, so that the enhancement passivation layer 108 can well withstand the high peak electric field at the edge of the nitride layer 107, thereby greatly improving its ability to resist single event effects.

[0050] The above-mentioned embodiments of the present application illustrate the case where an enhanced passivation layer 108 having a high critical breakdown electric field strength is provided on both sides of the nitride layer 107 of a high electron mobility transistor resistant to single particle effects. In other embodiments, the enhanced passivation layer 108 on both sides of the nitride layer 107 does not contact the source 105 and the drain 106, and a passivation layer is further provided between the enhanced passivation layer 108 on both sides of the nitride layer 107 and the source 105 and the drain 106, respectively. The passivation layer can be made of conventional passivation layer materials, which plays a role in reducing costs.

[0051] refer to Figure 4 In some other embodiments, the above-mentioned single-particle effect resistant high electron mobility transistor further includes: a first passivation layer 110, the first passivation layer 110 is located between the enhanced passivation layer 108 on the side of the nitride layer 107 close to the source 105 and the source 105; and a second passivation layer 111, the second passivation layer 111 is located between the enhanced passivation layer on the side of the nitride layer 107 close to the drain 106 and the drain 106.

[0052] like Figure 4 As shown, the first passivation layer 110 is located between the enhanced passivation layer 108 and the source electrode 105 on the side of the nitride layer 107 close to the source electrode 105, and the second passivation layer 111 is located between the enhanced passivation layer and the drain electrode 106 on the side of the nitride layer 107 close to the drain electrode 106. In other words, the first passivation layer 110 is located between the enhanced passivation layer 108 and the source electrode 105 on the left side of the nitride layer 107, and the second passivation layer 111 is located between the enhanced passivation layer and the drain electrode 106 on the right side of the nitride layer 107. In the embodiment of the present application, an enhanced passivation layer 108 with a high critical breakdown electric field strength is provided on both sides of the nitride layer 107 to enhance the ability of the edges of the nitride layer 107 to resist the single-ion effect. Then, a passivation layer made of a conventional passivation material is provided between the enhanced passivation layer 108 and the source electrode 105 and the drain electrode 106 to reduce the manufacturing cost of the device.

[0053] In some exemplary embodiments, the critical breakdown electric field strength of the material of the enhanced passivation layer 108 is greater than the critical breakdown electric field strength of the material of the first passivation layer 110 , and the critical breakdown electric field strength of the material of the enhanced passivation layer 108 is greater than the critical breakdown electric field strength of the material of the second passivation layer 111 .

[0054] In some exemplary embodiments, the material of the first passivation layer 110 includes one of silicon oxide (SiO2), aluminum oxide (Al2O3), and silicon nitride (Si3N4); and / or the material of the second passivation layer 111 includes one of silicon oxide (SiO2), aluminum oxide (Al2O3), and silicon nitride (Si3N4).

[0055] In some example embodiments, the material of the first passivation layer 110 and the material of the second passivation layer 111 can be the same or different. Similarly, the height of the first passivation layer 110 and the height of the second passivation layer 111 can be the same or different.

[0056] In particular, since the first passivation layer 110 and the second passivation layer 111 can be fabricated at the same time, preferably, the material of the first passivation layer 110 and the material of the second passivation layer 111 are the same, and the height of the first passivation layer 110 and the height of the second passivation layer 111 are the same. In the direction of the gate 109 pointing to the nitride layer 107, the height of the first passivation layer 110 and the height of the second passivation layer 111 are 90-300 nm.

[0057] In some example embodiments, in the direction of the gate 109 pointing to the nitride layer 107, the height of the enhanced passivation layer 108 is greater than or equal to the height of the first passivation layer 110; and / or in the direction of the gate 109 pointing to the nitride layer 107, the height of the enhanced passivation layer 108 is greater than or equal to the height of the second passivation layer 111.

[0058] In particular, in the direction of the gate 109 pointing to the nitride layer 107, the height of the enhanced passivation layer 108 can be greater than the height of the first passivation layer 110, or equal to the height of the first passivation layer 110. Similarly, in the direction of the gate 109 pointing to the nitride layer 107, the height of the enhanced passivation layer 108 can be greater than the height of the second passivation layer 111, or equal to the height of the second passivation layer 111.

[0059] Referring to Figure 3 and Figure 4 In some example embodiments, the single event effect resistant high electron mobility transistor further comprises: an insertion layer 112, the insertion layer 112 is located between the channel layer 103 and the barrier layer 104. The insertion layer 112 is used to improve the carrier mobility, and the material of the insertion layer 112 includes but is not limited to AlN, InAlN, AlGaN.

[0060] Referring to Figure 5 The embodiments of the present application also provide a preparation method of a single event effect resistant high electron mobility transistor, which comprises the following steps:

[0061] Step S1, providing a substrate, and forming a nucleation layer, a buffer layer, a channel layer and a barrier layer which are sequentially stacked on the substrate.

[0062] Step S2, forming an epitaxial layer on the side of the barrier layer away from the channel layer.

[0063] Step S3, etching the epitaxial layer to form a nitride layer.

[0064] Step S4, forming a source and a drain on the barrier layer.

[0065] Step S5, forming an enhanced passivation material layer on the source and the side of the nitride layer close to the source, the drain and the side of the nitride layer close to the drain.

[0066] Step S6, etching the enhanced passivation material layer to form an enhanced passivation layer; the enhanced passivation layer covers the sidewall and at least part of the top wall of the nitride layer.

[0067] Step S7, forming a gate on the nitride layer.

[0068] Step S8, leading out electrodes above the gate, the source and the drain.

[0069] Specifically, in the preparation of high electron mobility transistors, first, a substrate 100 is provided, and a nucleation layer 101, a buffer layer 102, a channel layer 103 and a barrier layer 104 are sequentially stacked on the substrate 100. Before forming the stacked film layers on the substrate 100, the substrate 100 is first pretreated and heat treated, and the nucleation layer 101 is deposited by a metal organic chemical vapor deposition (MOCVD) process. On the nucleation layer 101, the buffer layer 102 and the channel layer 103 are sequentially deposited by the MOCVD process; on the channel layer 103, the barrier layer 104 is deposited by the MOCVD process; preferably, the material of the barrier layer 104 is Al x Ga (1-x) N, wherein the value of x is between 0.1 and 0.2. In the embodiments of the present application, the thickness of the substrate 100 is 30-200 nm; the thickness of the nucleation layer 101 is 30-100 nm; the thickness of the buffer layer 102 is 0.5-5 μm; the thickness of the channel layer 103 is 50-500 nm; and the thickness of the barrier layer 104 is 10-40 nm.

[0070] In step S1, the operation steps of the pretreatment and heat treatment of the substrate 100 are as follows: the substrate 100 is ultrasonically cleaned with acetone, anhydrous ethanol solution and deionized water, and the substrate 100 is heat treated at 1050°C for 10 minutes in a hydrogen atmosphere. In the process of depositing the nucleation layer 101, the pressure in the MOCVD process is 10-100 Torr, the Al source flow rate is 10-100 sccm, the ammonia flow rate is 3000-6000 sccm, the hydrogen flow rate is 1000-2000 sccm, and the temperature is 900°C.

[0071] In the process of depositing the buffer layer 102 and the channel layer 103, the pressure in the reaction chamber in the MOCVD process is 10 Torr-100 Torr, the flow rate of Ga source is 50 μmol / min-100 μmol / min, the flow rate of ammonia is 3000 sccm-6000 sccm, the flow rate of hydrogen is 1000 sccm-2000 sccm, and the temperature is 900 °C.

[0072] In the process of depositing the barrier layer 104, the pressure in the reaction chamber in the MOCVD process is 10 Torr-100 Torr, the flow rate of Al source is 10 μmol / min-30 μmol / min, the flow rate of Ga source is 30 μmol / min-90 μmol / min, the flow rate of ammonia is 3000 sccm-6000 sccm, the flow rate of hydrogen is 1000 sccm-2000 sccm, and the temperature is 900 °C.

[0073] Referring to Figure 6 An epitaxial layer 107' is formed on the side of the barrier layer 104 away from the channel layer 103. Specifically, the epitaxial layer 107' with a thickness of 60 nm-90 nm is deposited by the MOCVD process. Here, the material of the epitaxial layer 107' is P-type gallium nitride or P-type aluminum nitride.

[0074] In the process of depositing the epitaxial layer 107', the pressure in the reaction chamber in the MOCVD process is 10 Torr-100 Torr, the flow rate of Ga source is 50 μmol / min-100 μmol / min, the flow rate of ammonia is 3000 sccm-6000 sccm, the flow rate of hydrogen is 1000 sccm-2000 sccm, and the temperature is 900 °C.

[0075] Referring to Figure 7 The epitaxial layer 107' is etched to form the nitride layer 107. Specifically, the epitaxial layer 107' is etched by patterning the epitaxial layer 107' to expose the surface of the barrier layer 104 except the part covered by the nitride layer 107.

[0076] Referring to Figure 8 The source 105 and the drain 106 are formed on the barrier layer 104. Specifically, a mask is made on the barrier layer 104, the source 105 and the drain 106 are deposited by the electron beam evaporation process, and annealing is performed at 850 °C to form the source 105 and the drain 106. Preferably, the material of the source 105 and the drain 106 is a combination of Ti / Al / Ni / Au, in which the thickness of Ti is 20 nm-100 nm, the thickness of Al is 100 nm-300 nm, the thickness of Ni is 20 nm-200 nm, and the thickness of Au is 20 nm-200 nm.

[0077] Referring toFigure 9 An enhanced passivation material layer 108' is formed on the side of the source 105 and the nitride layer 107 close to the source 105, and on the side of the drain 106 and the nitride layer 107 close to the drain 106. The material of the enhanced passivation material layer 108' is a material with high critical breakdown field, for example, the material of the enhanced passivation material layer 108' includes one of HfO2, TiO2, ZrO2, Y2O3, La2O3 or Ta2O5.

[0078] Reference is made to Figure 10 The enhanced passivation material layer 108' is etched to form an enhanced passivation layer 108; the enhanced passivation layer 108 covers the sidewalls and at least part of the top wall of the nitride layer 107.

[0079] Reference is made to Figure 11 A gate 109 is formed on the nitride layer 107. Specifically, a mask is made on the nitride layer 107, and the gate 109 is deposited by an electron beam evaporation process. The material of the gate 109 is a combination of metals of Ni and Au, wherein the thickness of the metal Ni is 20nm-100nm, and the thickness of the metal Au is 50nm-500nm.

[0080] Finally, electrodes are led out above the gate 109, the source 105 and the drain 106 to obtain the single event effect resistant high electron mobility transistor as shown in Figure 3 .

[0081] In other embodiments, reference is made to Figure 12 After the gate 109 is formed on the nitride layer 107 and before electrodes are led out above the gate 109, the source 105 and the drain 106, the method for preparing the single event effect resistant high electron mobility transistor further includes:

[0082] Step S701: forming a passivation material layer above the barrier layer, the source, the drain, the enhanced passivation layer and the gate.

[0083] Step S702: etching the passivation material layer to form a first passivation layer and a second passivation layer.

[0084] In this embodiment, in addition to the enhanced passivation layer 108 with higher critical breakdown field intensity being arranged on both side edges of the nitride layer 107, a passivation layer with conventional passivation material is arranged between the enhanced passivation layer 108 and the source 105 and the drain 106. Reference is made to Figure 13 When the enhanced passivation material layer 108' is etched, part of the surface of the barrier layer 104 is exposed to form the enhanced passivation layer 108 covering the sidewalls and the top edge of the nitride layer 107. The enhanced passivation layer 108 beside the source 105 and the enhanced passivation layer 108 beside the drain 106 are etched away to expose the surface of the barrier layer 104 except the area covered by the enhanced passivation layer 108 and the nitride layer 107.

[0085] refer to Figure 14 , a gate 109 is formed on the nitride layer 107. Specifically, a mask is formed on the nitride layer 107, and the gate 109 is deposited using an electron beam evaporation process. The gate 109 is made of a Ni / Au combination metal, wherein the thickness of the Ni metal is 20nm to 100nm, and the thickness of the Au metal is 50nm to 500nm.

[0086] refer to Figure 15 A passivation material layer 110' is formed above the barrier layer 104, source electrode 105, drain electrode 106, enhanced passivation layer 108, and gate electrode 109. Passivation material layer 110' covers the surfaces of the barrier layer 104, source electrode 105, drain electrode 106, enhanced passivation layer 108, and gate electrode 109. Specifically, a plasma-enhanced chemical vapor deposition (PECVD) process is used to deposit passivation material layer 110' with a thickness of 50 nm to 400 nm above the barrier layer 104, source electrode 105, drain electrode 106, enhanced passivation layer 108, and gate electrode 109. During the PECVD process for depositing passivation material layer 110', the reaction chamber pressure is 0.5 Pa to 30 Pa, the reaction chamber temperature is 200° C. to 350° C., and monosilane and nitrous oxide gases, or monosilane and ammonia gases, are simultaneously introduced into the reaction chamber. The material of the passivation material layer 110 ′ includes one of SiO 2 , Al 2 O 3 , and Si 3 N 4 .

[0087] Finally, the passivation material layer 110' is etched to form a first passivation layer 110 and a second passivation layer 111, and the following is obtained: Figure 4 The high electron mobility transistor shown is shown. Specifically, since the first passivation layer 110 and the second passivation layer 111 are deposited simultaneously, they are typically made of the same material. Similarly, since the first passivation layer 110 and the second passivation layer 111 are etched simultaneously, they are typically of the same thickness. Alternatively, holes may be opened in the passivation layers above the source 105, drain 106, and gate 109 to extract the electrodes, thereby obtaining a high electron mobility transistor.

[0088] In the embodiment of the present application, the material of the enhanced passivation layer 108 is a material with a very high critical breakdown electric field, such as HfO2, TiO2, ZrO2, Y2O3, La2O3, Ta2O5, etc.; the passivation material layer 110' is made of conventional materials, such as SiO2, Al2O3, Si3N4, etc.

[0089] Figure 16The simulation result of the electric field distribution of the high electron mobility transistor under the action of the single particle effect is shown. As shown in Figure 16 the high electron mobility transistor of the embodiment of the present application originally located at the edge of the nitride layer 107 under the single particle effect, after the enhanced passivation layer 108 is added at the edge of the nitride layer 107, the enhanced passivation layer 108 bears the high peak electric field (as shown in B in Figure 16 the embodiment of the present application). The embodiment of the present application adds an enhanced passivation layer 108 with high breakdown field strength around the nitride layer 107, which can well bear the high peak electric field at the edge of the nitride layer 107, thereby greatly improving the ability to resist the single particle effect.

[0090] According to the above technical solutions, the existing high electron mobility transistor with anti-single particle effect is easy to exceed the critical breakdown electric field in the long-time irradiation environment, resulting in the problems of single particle burnout acceleration and device breakdown in advance. The embodiment of the present application provides a high electron mobility transistor with anti-single particle effect and a preparation method thereof. The enhanced passivation layer 108 is arranged at the region prone to breakdown of the device (i.e. both sides of the nitride layer 107), and the enhanced passivation layer 108 can well bear the high peak electric field at the edge of the nitride layer 107, thereby greatly improving the ability of the high electron mobility transistor to resist the single particle effect. The enhanced passivation layer 108 covers the sidewall and at least part of the top wall of the nitride layer 107, plays a role in enhancing the critical breakdown electric field of both sides of the nitride layer 107, so that the device can bear higher voltage, thereby improving the working life and reliability of the device.

[0091] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments of the present application, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, therefore the protection scope of the present application should be limited by the scope defined in the claims.

Claims

1. A high electron mobility transistor resistant to single event effects, characterized in that: include: A substrate and a nucleation layer, a buffer layer, a channel layer and a barrier layer sequentially stacked on the substrate; a source electrode and a drain electrode located on the barrier layer, wherein the source electrode and the drain electrode respectively form an ohmic contact with the barrier layer; a nitride layer located on the barrier layer, and the nitride layer is located between the source electrode and the drain electrode; an enhanced passivation layer located on both sides of the nitride layer, wherein the enhanced passivation layer covers the sidewalls and at least a portion of the top wall of the nitride layer; a gate located on the nitride layer, wherein the bottom of the gate contacts the enhanced passivation layer, and the bottom of the gate forms an ohmic contact or a Schottky contact with the nitride layer; The transistor further includes: a first passivation layer, the first passivation layer being located between the enhanced passivation layer on a side of the nitride layer close to the source electrode and the source electrode; a second passivation layer, the second passivation layer being located between the enhanced passivation layer on a side of the nitride layer close to the drain electrode and the drain electrode; The critical breakdown electric field strength of the material of the enhanced passivation layer is greater than that of the material of the first passivation layer, and the critical breakdown electric field strength of the material of the enhanced passivation layer is greater than that of the material of the second passivation layer.

2. The single event effect resistant high electron mobility transistor according to claim 1, characterized in that: The material of the enhanced passivation layer includes one of HfO2, TiO2, ZrO2, Y2O3, La2O3, Ta2O5, SiO2, and Si3N4.

3. The single event effect resistant high electron mobility transistor according to claim 1, wherein: Along the direction from the gate to the nitride layer, the height of the enhanced passivation layer is 90 nm to 400 nm.

4. The single event effect resistant high electron mobility transistor according to claim 1, wherein: The material of the nitride layer includes P-type gallium nitride or P-type aluminum nitride.

5. The single event effect resistant high electron mobility transistor according to claim 1, wherein: The material of the first passivation layer includes one of SiO2, Al2O3, and Si3N4; and / or the material of the second passivation layer includes one of SiO2, Al2O3, and Si3N4.

6. The single event effect resistant high electron mobility transistor according to claim 1, wherein: Along the direction from the gate to the nitride layer, the height of the enhanced passivation layer is greater than or equal to the height of the first passivation layer; and / or along the direction from the gate to the nitride layer, the height of the enhanced passivation layer is greater than or equal to the height of the second passivation layer.

7. A method for preparing a high electron mobility transistor resistant to single event effects, characterized in that: include: Providing a substrate, and forming a nucleation layer, a buffer layer, a channel layer, and a barrier layer stacked in sequence on the substrate; forming an epitaxial layer on a side of the barrier layer away from the channel layer; etching the epitaxial layer to form a nitride layer; forming a source electrode and a drain electrode on the barrier layer; forming an enhanced passivation material layer on the source electrode and the side of the nitride layer close to the source electrode, and on the drain electrode and the side of the nitride layer close to the drain electrode; Etching the enhanced passivation material layer to form an enhanced passivation layer; The enhanced passivation layer covers the sidewalls and at least a portion of the top wall of the nitride layer; When etching the enhanced passivation material layer, a portion of the surface of the barrier layer is exposed; forming a gate on the nitride layer; forming a passivation material layer over the barrier layer, the source electrode, the drain electrode, the enhanced passivation layer, and the gate electrode; Etching the passivation material layer to form a first passivation layer and a second passivation layer; The critical breakdown electric field strength of the material of the enhanced passivation layer is greater than the critical breakdown electric field strength of the material of the first passivation layer, and the critical breakdown electric field strength of the material of the enhanced passivation layer is greater than the critical breakdown electric field strength of the material of the second passivation layer; Electrodes are drawn out above the gate, the source, and the drain.

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