Data processing method, device and system, system-level SOC chip and computer device

Abstract

Embodiments of the present application provide a data processing method, device and system, a system-level SOC chip and a computer device. The method is applied to a system-level cache unit, the system-level cache unit comprising a first cache space and a second cache space; wherein the first cache space comprises a plurality of cache blocks and a plurality of storage data directory table entries; the second cache space comprises a plurality of page table directory table entries, the page table directory table entries being used to indicate a mapping relationship between a virtual address and a physical address of a data block in the storage unit; the method comprising: determining a target physical address indicated by a read-write access request sent by a host device; determining a target cache block in the first cache space or a target data block in the storage unit according to the target physical address; and performing a data read-write operation on the target cache block or the target data block.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, more particularly, to a data processing method, device and system, system-level SOC chip and computer equipment. BACKGROUND

[0002] In the current large-scale system on chip (SOC) or processor, a system-level cache unit (SLC) module shared by multiple master devices is arranged to cache data in a memory, thereby optimizing the read-write performance of the master devices in the SOC when accessing the memory.

[0003] In the above system, the cache spaces of the MMU module and the SLC module for performing virtual address and physical address conversion are independent of each other, which occupies more chip area, thereby increasing the hardware cost of the SOC. Moreover, the physical positions of the MMU module and the SLC module are possibly far apart, thereby causing additional time delay when addressing and reading and writing data, thereby affecting the running speed of the SOC. SUMMARY

[0004] The present application provides a data processing method, device and system, system-level SOC chip and computer equipment. The following introduces each aspect of the embodiments of the present application.

[0005] In a first aspect, a data processing method is provided, which is applied to a system-level cache unit arranged between at least one master device and a storage unit to perform address conversion and cache data in the storage unit, and the system-level cache unit includes a first cache space and a second cache space. The first cache space includes a plurality of cache blocks and a plurality of storage data directory table entries, the plurality of cache blocks are used to cache data in the storage unit, and the plurality of storage data directory table entries are used to indicate the mapping relationship between the cache blocks and the physical addresses of data blocks in the storage unit. The second cache space includes a plurality of page table directory table entries, and the page table directory table entries are used to indicate the mapping relationship between virtual addresses and the physical addresses of data blocks in the storage unit. The method includes determining a target physical address indicated by a read-write access request sent by the master device, determining a target cache block in the first cache space or a target data block in the storage unit according to the target physical address, and performing a data read-write operation on the target cache block or the target data block. The target cache block is one or more of the plurality of cache blocks, and the target data block is one or more of the plurality of data blocks.

[0006] In a second aspect, a data processing apparatus is provided, which is applied to a system-level cache unit arranged between at least one host device and a storage unit to perform address translation and cache data in the storage unit. The system-level cache unit includes a first cache space and a second cache space. The first cache space includes a plurality of cache blocks and a plurality of storage data directory table entries. The plurality of cache blocks are used to cache data in the storage unit, and the plurality of storage data directory table entries are used to indicate a mapping relationship between the cache blocks and physical addresses of data blocks in the storage unit. The second cache space includes a plurality of page table directory table entries, which are used to indicate a mapping relationship between a virtual address and physical addresses of data blocks in the storage unit. The apparatus includes a first determining unit configured to determine a target physical address indicated by a read / write access request sent by the host device, a second determining unit configured to determine a target cache block in the first cache space or a target data block in the storage unit according to the target physical address, and an executing unit configured to perform a data read / write operation on the target cache block or the target data block. The target cache block is one or more of the plurality of cache blocks, and the target data block is one or more of the plurality of data blocks.

[0007] In a third aspect, a data processing system is provided, which includes at least one host device, a storage unit, and a system-level cache unit. The system-level cache unit is arranged between the at least one host device and the storage unit to perform address translation and cache data in the storage unit. The system-level cache unit includes a first cache space and a second cache space. The first cache space includes a plurality of cache blocks and a plurality of storage data directory table entries. The plurality of cache blocks are used to cache data in the storage unit, and the plurality of storage data directory table entries are used to indicate a mapping relationship between the cache blocks and physical addresses of data blocks in the storage unit. The second cache space includes a plurality of page table directory table entries, which are used to indicate a mapping relationship between a virtual address and physical addresses of data blocks in the storage unit. The system-level cache unit is configured to determine a target physical address indicated by a read / write access request sent by the host device, determine a target cache block in the first cache space or a target data block in the storage unit according to the target physical address, and perform a data read / write operation on the target cache block or the target data block. The target cache block is one or more of the plurality of cache blocks, and the target data block is one or more of the plurality of data blocks.

[0008] Fourthly, a system-level SoC chip is provided, the SoC chip comprising: at least one master device and a system-level cache unit, wherein the at least one master device is connected to the system-level cache unit via a bus; the system-level cache or the master device is used to execute the data processing method as described in the first aspect.

[0009] Fifthly, a computer device is provided, the computer device comprising: a chip and a storage unit, the chip and the storage unit being connected together; the chip comprising a SOC chip as described in the fourth aspect.

[0010] According to the data read / write method provided in the embodiments of this application, by storing page table directory entries in the cache space of the system-level cache unit, it is equivalent to merging the memory management unit and the system-level cache unit, thereby shortening the access latency during addressing; at the same time, by reusing and optimizing the storage space of the system-level cache unit and optimizing the addressing logic, chip area is saved. Attached Figure Description

[0011] Figure 1 This is a schematic structural diagram of a System-on-a-Chip (SOC) in related technologies.

[0012] Figure 2 Yes Figure 1 The diagram shows a simplified partial view of the SOC.

[0013] Figure 3 This is a schematic diagram of another type of System-on-a-Chip (SoC) in related technologies.

[0014] Figure 4 Yes Figure 3 A simplified partial schematic diagram of the SOC in the diagram.

[0015] Figure 5 This is a schematic structural diagram of the system-level cache unit 50 provided in the embodiments of this application.

[0016] Figure 6 This is a schematic flowchart of the data processing method provided in the embodiments of this application.

[0017] Figure 7 This is a flowchart of data processing using the system-level cache unit provided in the embodiments of this application.

[0018] Figure 8 This is a schematic structural diagram of the data processing apparatus provided in the embodiments of this application.

[0019] Figure 9 This is a schematic structural diagram of the data processing system provided in the embodiments of this application.

[0020] Figure 10is a schematic structural diagram of a system-level SOC chip provided by an embodiment of the present application.

[0021] Figure 11 is a schematic structural diagram of a computer device of an embodiment of the present application. DETAILED DESCRIPTION

[0022] The embodiments of the present application will be described below with reference to the drawings.

[0023] The terms "first", "second", "third", and "fourth" and the like in the description and in the claims of the present application and the drawings herein are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of use in either order. Furthermore, the term "comprising" or "containing" and variations thereof as used herein is used generically and inclusively, that is, in the sense of "including", and is intended to cover the situation where one or more features, functions, or elements can be present, or able to be present, or one or more features are optional. The terms "comprise", "comprising", "containing" and "including" as used herein are used in their broadest sense and are intended to mean that the statement, whether in independent or dependent claim form, or in the application, encompasses the components or steps, but not to the exclusion of anything that the statement, in independent or dependent claim form, or in the application, might also describe. The terms "comprise", "comprising", "containing" and "including" as used herein are used in their broadest sense and are intended to mean that the statement, whether in independent or dependent claim form, or in the application, encompasses the components or steps, but not to the exclusion of anything that the statement, in independent or dependent claim form, or in the application, might also describe.

[0024] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily all directed to the same embodiment, or to a single alternative embodiment. It is expressly understood that any of the features, functionality, compositions, and steps described herein and in the claims can be included in a plurality of embodiments.

[0025] As used in this description, the terms "component," "module," "system", and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and / or thread of execution and a component can be localized, co-resident, and / or distributed amongst one or more computer(s). Also, these components can execute from various computer readable media having various data structures stored thereon. The components can communicate by way of local and / or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and / or across a network such as the Internet with other systems via the signal).

[0026] Before introducing the embodiments of the present application, the terms involved in the embodiments of the present application are explained and described, so as to facilitate the understanding of those skilled in the art.

[0027] Central Processing Unit (CPU)

[0028] The central processing unit is responsible for reading instructions, decoding instructions and executing instructions in the computer. The central processing unit mainly includes two parts, namely the controller and the arithmetic unit, and further includes the cache memory and the bus realizing the connection between them.

[0029] System on Chip (SOC)

[0030] System on Chip (SOC) is the core chip integration of information system, which is to integrate the key components of the system on a chip. SOC is a system or product formed by combining multiple integrated circuits with specific functions on a chip, which contains a complete hardware system and the embedded software carried thereby. In the current mobile terminal, the central processing unit (CPU), neural network processing unit (NPU) and graphics processing unit (GPU) and the like have increasingly adopted the design concept of SOC, so as to further improve the performance.

[0031] Processor core

[0032] The core of SOC or CPU is used to complete all calculations, accept / store commands, process data and the like. The core of various processors has a fixed logic structure, involving the layout of logic units such as level one cache, level two cache, execution unit, instruction level unit and bus interface.

[0033] Master device

[0034] The master device is a device that obtains the control right of the bus in the computer system, such as CPU, GPU or NPU in SOC and the like. The master device can exchange data with the slave device addressed by it through the bus, such as writing data to the memory by the CPU or GPU, or reading data from the memory by the CPU and the like. In the embodiments of the present application, the master device can be CPU, GPU, NPU and the like, and can also be a multimedia device, such as a video playing device, an audio playing device and the like.

[0035] Memory

[0036] A physical structure inside a computer device for storing information. According to the different purposes, the memory can be divided into main memory (also known as internal memory, or simply memory / main memory) and auxiliary memory (also known as external memory, or simply auxiliary / external storage). The main memory is used to store instruction information and / or data information represented by data signals, such as for storing data provided by the processor, and can also be used to realize information exchange between the processor and the external memory. The memory mentioned in this paper generally refers to the main memory.

[0037] Cache

[0038] The cache, also known as cache, is located between the CPU and the main memory DRAM, and is a small-capacity but high-speed memory, usually composed of static memory (Static Random Access Memory, SRAM). Among them, as long as the SRAM is powered on, the data stored can be constantly maintained. SRAM can generally be divided into the following five parts: memory cell array, row / column address decoder, sensitive amplifier, control circuit and drive circuit. Specifically, cache can save a part of data that has just been used or recycled by CPU, and if CPU needs to use this part of data again, it can be directly called from cache, speeding up the speed of data access and reducing the waiting time of CPU. Cache is generally divided into level 1 cache (L1 cache), level 2 cache (L2 cache) and level 3 cache (L3 cache), etc.; among them, L1 cache is mainly integrated in the CPU, L2 cache is integrated on the motherboard or in the CPU, and L3 cache is integrated on the motherboard or in the CPU. When in the CPU, the L3 cache is shared by multiple processor cores.

[0039] Physical Address (PA)

[0040] Also called real address, binary address, it is in electronic form on the address bus, so that the data bus can access a certain memory address of the main memory. The address is numbered from 0, sequentially adding 1 each time, so the physical address space of the memory is linearly increasing. Physical address can also be called actual address, real address or absolute address.

[0041] Virtual address

[0042] A virtual address is an abstract address used by software or programs running on a processor or external device (e.g., input / output device). A virtual address space can be larger than a physical address space, and a virtual address can be mapped to a corresponding physical address. For example, an abstract address used by software or programs running on a processor is a first virtual address, and an abstract address used by software or programs running on an external device (e.g., input / output device) is a second virtual address.

[0043] Paging management mechanism

[0044] A virtual address space is divided into multiple parts, each part being a virtual page, and a physical address space is divided into multiple parts, each part being a physical page. A physical page is also referred to as a physical address block or a physical address frame. A virtual physical address space is divided into multiple parts, each part being a virtual physical page.

[0045] Memory Management Unit (MMU)

[0046] Sometimes referred to as a paged memory management unit (PMMU), or a memory management unit (MMU), is a computer hardware responsible for handling memory access requests of a main device. Its functions include virtual address to physical address translation (i.e., virtual memory management), memory protection, control of caches in the system; in simpler computer architectures, it is responsible for bus arbitration and memory bank switching.

[0047] Translation Lookaside Buffer (TLB)

[0048] Also referred to as a page table cache, translation lookaside buffer, or translation lookaside cache, can be provided in an MMU to improve the speed of virtual address to physical address translation. All current desktop and server processors (e.g., x86) use a TLB. A TLB has a fixed number of space slots for storing tag page table entries that map virtual addresses to physical addresses. Its search key is a virtual memory address, and its search result is a physical address. If a requested virtual address exists in the TLB, a very fast matching result is given, and the resulting physical address can then be used to access memory. If a requested virtual address does not exist in the TLB, a tag page table is used for virtual to physical address translation, which is much slower than a TLB. Some systems allow tag page tables to be swapped to secondary storage, and virtual to physical address translation can then take a very long time.

[0049] After the definitions of the above-mentioned multiple terms are introduced, the data storage method in the related art and problems existing in the data storage method will be first illustrated in detail in combination with the accompanying drawings.

[0050] Figure 1 A schematic structure diagram of a typical system on chip (SOC) in the related art. Figure 1 The SOC 10 in the figure includes a plurality of processor cores 11A, …, 11N, each of which includes at least two levels of caches and a memory management unit (MMU). Taking the processor core 11A as an example, the processor core 11A includes a processing circuit 111A, a level-1 cache 112A, a level-2 cache 113A, and an MMU 114A. The processing circuit 111A is configured to process data or instructions, the level-1 cache 112A is configured to cache part of the data in the level-2 cache 113A, the level-2 cache 113 is configured to cache part of the data in a storage unit (e.g., a memory) outside the SOC, and the MMU 114A is configured to perform address translation when the processing circuit 111A initiates a data read / write operation.

[0051] For example, the processing circuit 111A issues an access instruction including a virtual address of a storage unit, and the MMU 114A determines a physical address corresponding to the virtual address. Then, the physical address is searched in the level-1 cache 112A. When the level-1 cache 112A includes a target cache line corresponding to the physical address, data is read / written on the cache line, otherwise, the level-2 cache 113A is searched. In the level-2 cache 113A, the same operation as the level-1 cache 112A is performed. When the search does not hit, data is read / written in a data block corresponding to the storage unit according to the physical address, and the data is cached in the upper level cache (i.e., the level-2 cache 113A). Thanks to the multi-level cache technology described above, the processor core has high efficiency when performing data read / write, thereby meeting the requirement of high-speed operation.

[0052] Continuing to refer to Figure 1 The SOC 10 further includes a GPU 12, an APU 13, an ISP 14, and the like. As described above, the above components can be referred to as master devices. In the SOC 10, the plurality of master devices are connected through a system bus 15, thereby being connected to a storage unit outside the SOC, and thereby realizing data interaction with the storage unit.

[0053] As described above, in a memory management mechanism based on page management, a storage management unit (MMU) is needed to realize conversion between a virtual address and a physical address. Therefore, in order to support data interaction between the plurality of master devices and the storage unit, the SOC 10 further includes a plurality of MMUs 16A, …, 16N arranged between the plurality of master devices and the storage unit. The plurality of storage management units can correspond to the plurality of master devices one by one, or only one storage management unit can be arranged in the system to be shared by the plurality of master devices, which is not limited here.

[0054] The GPU in the following example is used to illustrate the data read-write mode of the GPU and the storage unit. Please refer to Figure 2 , Figure 2 is a simplified structure diagram of Figure 1 . Figure 2 In the figure, only the GPU 21, the MMU 22 and the storage unit 23 are shown.

[0055] The GPU is usually used for video decoding and image rendering, and needs to interact with the storage unit 23 during operation. When reading and writing data, the GPU 21 sends an access instruction to the MMU 22; the MMU 22 receives and parses the access request to obtain a virtual address, and converts the virtual address to a physical address of a data block in the storage unit 23.

[0056] The working process of the MMU 22 is briefly described below. After receiving the access request of the host device, the MMU 22 parses it to determine the virtual address contained in the access request; according to the virtual address, the MMU 22 accesses the page table in the memory to find the page table entry matching the virtual address, thereby determining the physical address corresponding to the virtual address, and returning the physical address to the access instruction. The host device performs read-write operation on the data block indicated by the physical address in the memory according to the physical address returned by the MMU 22.

[0057] In the above process, the memory needs to be accessed twice. In the related art, in order to speed up the process, a translation lookaside buffer TLB 221 can also be provided in the MMU 22 to cache part of the page table in the memory. The page table cached in the TLB 221 can be part of the page table entries in the memory determined by the system logic based on the operating system, for example, it can be the page table entry of the data block accessed by the host device last time, so that in the next access, the corresponding page table entry can be directly found in the page table cached in the TLB 221 according to the virtual address of the access instruction, and the corresponding physical address can be directly obtained without querying the page table in the memory. That is, in this case, only one memory access is needed, which can speed up the memory access efficiency.

[0058] After receiving the physical address returned by the MMU 22, the GPU 21 performs read-write operation on the target data block in the storage unit 23 according to the physical address.

[0059] With the improvement of the hardware configuration of mobile phones and other devices, the screen resolution and frame rate of mobile phones have been greatly improved. In some scenarios, such as frame-by-frame rendering of game pictures, the increase in resolution and frame rate increases the data throughput of the GPU, thereby putting forward higher requirements for the data interaction rate between the GPU and the storage device.

[0060] It should also be noted here that in the existing SOC, in order to meet the demand for basic operation, a cache is set in the processor core; and in the main devices such as GPU and NPU, due to the limitation of chip area and cost considerations, no cache mechanism is set, but direct data interaction is carried out between these devices and the storage device. Therefore, in the case of a large number of frequent data interactions as described above, the processing mechanism in the prior art cannot meet the demand.

[0061] In view of the above problems, in some related technologies, as shown in Figure 3 A system level cache unit 35 is provided in the SOC 30, which is a shared cache resource high-speed memory for different main devices (such as Figure 3 processor cores 31A,…31N, GPU 32, APU 33 and ISP 34 in the SOC 30). The system level cache is provided between the above-mentioned multiple main devices and the storage device outside the SOC 30, as the last level cache in the cache system, or the cache for the external storage device. When the main device needs to perform read / write operation, it can read from or write data directly into the system level cache 32, so that the subsequent main device can quickly access the data, thereby improving the data processing efficiency of the main device.

[0062] The addressing and data read / write method when the main device reads / writes data to the system level cache and the storage device will be described in detail below. Please refer to Figure 4 Figure 4 , Figure 4 is a simplified structure diagram of Figure 3 , only the transmission path between the main device and the storage unit is shown, and it should be understood that Figure 4 The main device in the SOC can be any main device, which is not limited here.

[0063] The addressing and data read / write process of the main device 41 in Figure 4 will be described in detail below.

[0064] First, the main device 41 sends an access instruction to the MMU 42 according to the current business demand; the MMU 42 receives the access request and parses it to obtain a virtual address. According to the virtual address, the MMU 42 converts the virtual address into a physical address by looking up the page table entry in the TLB 421 or directly reading the page table entry stored in the storage unit. The process is basically the same as described above, which will not be repeated here.

[0065] After the physical address is determined, in​Figure 4 In the system shown, the host device also needs to determine, according to the physical address, whether the read-write operation of the data needs to be performed in the cache block of the SLC 43 or in the data block of the memory.

[0066] Specifically, the SLC 43 further includes a storage data directory table item, which is used to indicate the mapping relationship between the plurality of cache blocks of the SLC 43 and the physical addresses of the data blocks in the memory. The host device can perform a lookup in the storage data directory table item of the SLC 43 according to the physical address converted by the MMU 42; when the lookup hits, it indicates that the SLC 43 currently has the cache block of the data block of the memory corresponding to the physical address, and at this time, the data read-write can be performed on the cache block. When the above lookup does not hit, the data read-write is performed on the data block corresponding to the physical address in the memory according to the physical address, and part of the cache block in the SLC 43 is allocated to cache the data in the data block, so that the subsequent access to the physical address can be performed in the SLC 43, thereby improving the speed of data read-write.

[0067] Figure 4 The system shown in the above embodiment improves the speed of data interaction between the host device and the memory by setting the SLC cache between the host device and the memory, and improves the addressing speed by using the MMU module and the TLB cache in the MMU module, so that the speed of data interaction between the host device and the memory can be significantly improved, and the read-write performance of the host device accessing the memory can be optimized.

[0068] However, the above system still has some problems. First, in the system, in order to improve the efficiency of address conversion, it is necessary to increase the cache space of the TLB as much as possible in order to store more page table items. The TLB cache space in the MMU is independent of the SLC, and the two cannot share. This will result in occupying more chip area, thereby increasing the hardware cost of the SOC.

[0069] Secondly, in the system, the positions of the MMU and the SLC can be far away, and there is a physical connection between the MMU and the SLC. The path of the MMU accessing the SLC in the system is not necessarily optimal in terms of delay, and if the SLC contains the MMU page table, additional delay can be introduced.

[0070] Finally, the system includes a plurality of host devices, and an MMU can be provided between each host device and the SLC cache. In this case, even if the page table shared by the plurality of host devices needs to be obtained and stored in each MMU, the load of the system is increased, and additional power consumption is introduced. In addition, the paths of the MMU and the SLC in accessing the memory are independent of each other, which easily causes the system to increase additional load due to the access of the MMU.

[0071] In view of the above problems, the embodiments of the present application provide a data read-write method, device and system, a system-level SOC chip and a computer device.

[0072] The method provided by the embodiments of the present application will be described in detail below with reference to the accompanying drawings. The data read-write method provided by the embodiments of the present application is applied to a system-level cache unit. Therefore, before introducing the method embodiments of the present application, the system-level cache unit provided by the embodiments of the present application will be described in detail.

[0073] Figure 5 A schematic structural diagram of a system-level cache unit 50 provided by the embodiments of the present application is shown. The system-level cache unit can be arranged between at least one host device and a storage unit, and is used for address translation and caching data in the storage unit.

[0074] For the convenience of the description hereinafter, Figure 5 The host device and the storage unit connected with the system-level cache unit 50 are also shown in the figure.

[0075] In some embodiments, Figure 5 The host device in the figure can be any host device mentioned above, for example, can be a component in an SOC such as CPU, GPU, NPU, APU and ISP, or can also be a multimedia device arranged outside the SOC, for example, a video playing device, an audio playing device, etc. The type of the host device is not limited in the embodiments of the present application.

[0076] It should also be understood that Figure 5 The figure only shows an example. The number of the host devices is not limited in the embodiments of the present application. For example, the system-level cache unit can only be applied to one host device; or in some embodiments, the system-level cache unit 50 can also be connected with multiple host devices, i.e., the system-level cache unit 50 is shared by the multiple host devices. When multiple host devices are included, the multiple host devices can be the same or different, which is not limited in the embodiments of the present application.

[0077] The storage unit can be, for example, a memory of an electronic device such as a mobile phone, a cache of an external device such as a hard disk, etc. The memory can be used to store data generated during the operation of the CPU, or cache data in the hard disk for use by the CPU.

[0078] In some embodiments, the storage unit can also be an intermediate cache with a capacity and a read-write speed between the system-level cache unit 50 and the memory. Through the intermediate cache, the efficiency of the data read-write of the host device in the memory can be further improved.

[0079] Please continue to refer to Figure 5 , Figure 5The system-level cache unit 50 in the system includes a first cache space 51 and a second cache space 52.

[0080] The first cache space includes a plurality of cache blocks and a plurality of storage data directory table entries. The plurality of cache blocks are used to cache data in the storage unit, and the plurality of storage data directory table entries are used to indicate a mapping relationship between the cache blocks and the physical addresses of the data blocks in the memory. The plurality of cache blocks can also be referred to as cache lines. The cache blocks in the system-level cache unit 50 correspond to the data blocks in the memory. The correspondence can be embodied by a mapping relationship between the line numbers of the cache lines and the physical addresses of the data blocks in the memory. The storage data directory table entries mentioned above are table entries that store the mapping relationship. According to a target physical address that needs to be accessed by the host device, a query is performed in the storage data directory table entries, so that the target cache block that needs to be cached or the target data block in the memory can be determined.

[0081] The second cache space includes a plurality of page table directory table entries, which are used to indicate a mapping relationship between a virtual address and a physical address of a data block in the memory. It can be understood that the page table directory table entries are similar to the page table entries stored in the TLB cache mentioned above. By analyzing an access request of the host device, a query is performed in the page table directory table entries of the second cache space according to a virtual address in the access request, so that the virtual address can be converted into the physical address of the data block when a hit occurs.

[0082] It should be further noted that the first cache space and the second cache space in the embodiments of the present application are not two completely independent storage spaces, but only two virtual cache spaces in the system-level cache unit. In actual applications, the sizes of the two virtual cache spaces can be divided according to actual conditions. For example, in some scenarios, more page table entries need to be stored, at which time the capacity of the second cache space can be increased, and the size of the first cache space can be reduced. For another example, when the data throughput is large, the size of the first cache space can be increased accordingly, so that more cache blocks can be used to cache data in the storage unit. In other words, the first cache space and the second cache space share the storage space of the system-level cache unit, and can be flexibly adjusted according to actual conditions.

[0083] The method shown in Figure 6 The data processing method provided in the embodiments of the present application will be described in detail, Figure 6 The method shown in Figure 5 The system-level cache unit 50 shown in the system includes steps S61-S63.

[0084] In step S61, a target physical address indicated by a read-write access request sent by the host device is determined.

[0085] In some embodiments, the determination of the target physical address can be made according to the address indication in the read-write access request. Specifically, the system-level cache unit receives the read-write access request of the host device, and parses the read-write access request to determine the address indication in the read-write access request. When the address indication in the read-write access request is the physical address of the storage unit, the physical address is directly taken as the target physical address. When the address indication in the read-write access request is a virtual address, the system-level cache unit 50 is used to convert (also referred to as translate) the virtual address into the target physical address.

[0086] In step S62, the target cache block in the first cache space or the target data block in the memory is determined according to the target physical address.

[0087] It should be understood that the target cache block mentioned herein can be one or more of a plurality of cache blocks in the first cache space 51, and the target data block can be one or more of a plurality of data blocks in the storage unit.

[0088] In some embodiments, the determination of the target cache block or the target data block can be: according to the target physical address, searching in a plurality of storage data directory table items in the first cache space, when there is a target storage data table item (or there is a target storage data table item hit) in the plurality of storage data directory table items that matches the target physical address, determining that the cache block of the target storage data table item is the target cache block, at this time, the target cache block is the cache of the target data block in the storage unit that matches the target physical address, and the data read-write of the target data block can be directly performed in the target cache block, at this time, the data read-write efficiency is the highest.

[0089] When none of the above searches hits, that is, there is no cache block of the data block indicated by the target physical address in the current first cache space, the data read-write needs to be performed in the data block of the storage unit.

[0090] In step S63, the data read-write operation is performed on the target cache block or the target data block.

[0091] In the embodiments of the present application, the specific mode of the data read-write operation on the target cache block or the target data block is the same as that in the related art, which will not be described herein.

[0092] According to the data read-write method provided in the embodiments of the present application, by storing the page table directory table item in the cache space of the system-level cache unit, the memory management unit and the system-level cache unit are combined, the access time delay in addressing is shortened; at the same time, by multiplexing and optimizing the storage space of the system-level cache unit and optimizing the logic of addressing, the chip area is saved.

[0093] In some embodiments, as described above, the second cache space includes page table directory table items for indicating the mapping relationship between the virtual address and the physical address of the data block in the memory. Therefore, in step S61, the conversion of the virtual address to the target physical address can be: searching the plurality of page table directory table items in the second cache space according to the virtual address in the access request of the host device, and when the search hits, taking the physical address of the target data block indicated by the target page table directory table item as the target physical address.

[0094] In some embodiments, when the search in the plurality of page table directory table items in the second cache space does not hit, the plurality of page table items in the storage unit can be read, and a target page table item matching the virtual address is determined, and the physical address indicated by the target page table item is taken as the target physical address.

[0095] In some embodiments, when the search in the plurality of page table directory table items in the second cache space does not hit, the target physical address is determined by reading the page table item in the storage unit, and at this time, the mapping relationship between the target physical address and the aforementioned virtual address can be written as a new page table directory table item into the second cache space, so that in the subsequent process, if the address is indicated as the aforementioned virtual address, the corresponding target physical address can be directly obtained by querying the page table directory table item, thereby saving the addressing time and improving the data read / write efficiency.

[0096] In some embodiments, after the data read / write is performed in the target data block, the method provided by the embodiments of the present application further includes: allocating a first cache block in the plurality of cache blocks to the target data block to store the data in the target data block; and writing the mapping relationship between the first cache block and the target physical address as a new storage data directory table item into the plurality of storage data directory table items in the first cache space.

[0097] The processing flow of the system-level cache unit provided by the embodiments of the present application will be described in detail below. Figure 7

[0098] In step S70, the host device sends the read / write access and the address indication to the system-level cache unit SLC.

[0099] In step S71, the SLC receives the read / write access and the address indication, and judges the address indication to determine whether it is a physical address.

[0100] When the SLC analyzes that the address indication is a physical address, the physical address is taken as the target physical address, and the process goes to step S72, and when the SLC analyzes that the address indication is a virtual address, step S76 is performed.

[0101] ​At step S72, according to the target physical address determined in the foregoing steps, a search is performed in the plurality of storage data directory table items in the first cache space of the SLC.

[0102] At step S73, it is determined whether the search in the plurality of storage data directory table items hits. When it hits, step S74 is executed, otherwise step S75 is executed.

[0103] In the foregoing steps, when the search in the plurality of storage data directory table items hits, it means that there is a cache block corresponding to the data block indicated by the target physical address in the first cache space of the SLC, and at this time, the data read / write can be performed in the target cache block of the SLC. Therefore, at step S74, the data read / write is performed in the target cache block in the first cache space of the SLC in the granularity of the cache block.

[0104] When the search in step S73 does not hit, it means that there is no cache block corresponding to the data block indicated by the target address in the first cache space at this time, and the data read / write needs to be performed in the storage unit. Therefore, at step S75, the data read / write is performed in the target data block of the storage unit, and the first cache block is allocated to the target data block to cache the data.

[0105] When the search in the foregoing step S71 does not hit, it means that the address indicated by the host device is a virtual address, which needs to be converted into a target physical address.

[0106] At step S76, according to the foregoing virtual address, a search is performed in the plurality of page table directory table items in the second cache space of the SLC.

[0107] At step S77, it is determined whether the search in step S76 hits, and when it hits, step S78 is executed, otherwise step S79 is executed.

[0108] At step S78, the data read / write is performed in the second cache data space of the SLC in the granularity of the page table, and the physical address of the target data block indicated by the target page table directory table item is determined as the target physical address.

[0109] When the search does not hit, it means that the mapping relationship between the virtual address and the physical address is not stored in the second cache space at this time, and at this time, a search needs to be performed in the page table item of the storage unit to obtain the corresponding physical address.

[0110] At step S79, the read / write is performed in the page table item of the storage unit, a target page table item matched with the virtual address is determined, and the physical address indicated by the target page table item is taken as the target physical address. Meanwhile, the mapping relationship between the target physical address and the virtual address is written into the second cache space as a new page table directory table item.

[0111] The above describes the method embodiments of the present application Figures 1-7 The device embodiments of the present application are described in detail below with reference to the drawings. It should be understood that the description of the device embodiments corresponds to the method embodiments, and thus the parts not described in detail can be described in the description of the method embodiments.

[0112] Figure 8 is a schematic structural diagram of a data processing device provided by an embodiment of the present application, Figure 8 The device in the above embodiment can be applied to a system-level cache unit, which can be the system-level cache unit described in any of the above embodiments. Figure 8 The device 80 in the above embodiment comprises:

[0113] A first determining unit 81, configured to determine a target physical address indicated by a read-write access request sent by the host device.

[0114] A second determining unit 82, configured to determine a target cache block in the first cache space or a target data block in the storage unit according to the target physical address; wherein the target cache block is one or more of the plurality of cache blocks, and the target data block is one or more of the plurality of data blocks.

[0115] An executing unit 83, configured to perform a data read-write operation on the target cache block or the target data block.

[0116] Optionally, the first determining unit is configured to: parse the read-write access request; when an address indication in the read-write access request is a physical address of the storage unit, take the physical address as the target physical address; or when the address indication in the read-write access request is a virtual address, convert the virtual address into the target physical address.

[0117] Optionally, the conversion of the virtual address into the target physical address comprises: querying the plurality of page table directory table items in the second cache space according to the virtual address; when a target page table directory table item in the plurality of table directory table items hits, taking a physical address indicated by the target page table directory table item as the target physical address; or when none of the plurality of table directory table items hits, reading a page table of the storage unit to obtain a target physical address corresponding to the virtual address.

[0118] Optionally, the device further comprises a first writing unit, configured to write a mapping relationship between the virtual address and the target physical address as a new page table directory table item into the second cache space.

[0119] Optionally, the second determining unit is configured to: query the plurality of storage data directory table items in the first cache space according to the target physical address; when a target storage data table item in the plurality of storage data directory table items is hit, determine a cache block indicated by the target storage data table item as the target cache block; when none of the plurality of storage data directory table items is hit, determine a data block in the storage unit indicated by the target physical address as the target data block.

[0120] Optionally, the apparatus further comprises: an allocating unit configured to allocate a first cache block in the plurality of cache blocks to the target data block to store data in the target data block; and a second writing unit configured to write a mapping relationship between the first cache block and the target physical address as a new storage data directory table item into the plurality of storage data directory table items in the first cache space.

[0121] Figure 9 is a schematic structural diagram of a data processing system 90 provided by an embodiment of the present application, which comprises:

[0122] at least one host device 91, a storage unit 92, and a system-level cache unit 93. The system-level cache unit 93 is arranged between the at least one host device 91 and the storage unit 92, and is configured to perform address translation and cache data in the storage unit.

[0123] The system-level cache unit 93 comprises a first cache space 931 and a second cache space 932.

[0124] The first cache space 931 comprises a plurality of cache blocks and a plurality of storage data directory table items. The plurality of cache blocks are configured to cache data in the storage unit, and the plurality of storage data directory table items are configured to indicate mapping relationships between the cache blocks and physical addresses of data blocks in the storage unit.

[0125] The second cache space 932 comprises a plurality of page table directory table items, which are configured to indicate mapping relationships between virtual addresses and physical addresses of data blocks in the storage unit.

[0126] The system-level cache unit 93 is configured to:

[0127] determine a target physical address indicated by a read-write access request sent by the host device 91;

[0128] According to the target physical address, a target cache block in the first cache space 931 or a target data block in the storage unit 92 is determined; wherein the target cache block is one or more of the plurality of cache blocks, and the target data block is one or more of the plurality of data blocks.

[0129] A data read-write operation is performed on the target cache block or the target data block.

[0130] Optionally, the target physical address indicated by the read-write access request sent by the host device is determined by: parsing the read-write access request; when the address indication in the read-write access request is a physical address of the storage unit, the physical address is taken as the target physical address; or when the address indication in the read-write access request is a virtual address, the virtual address is converted into the target physical address.

[0131] Optionally, the conversion of the virtual address into the target physical address includes: according to the virtual address, querying the plurality of page table directory table items in the second cache space; when a target page table directory table item in the plurality of table directory table items hits, a physical address indicated by the target page table directory table item is taken as the target physical address; or when none of the plurality of table directory table items hits, a page table of the storage unit is read to obtain a target physical address corresponding to the virtual address.

[0132] Optionally, the system-level cache unit is further configured to: write a mapping relationship between the virtual address and the target physical address as a new page table directory table item into the second cache space.

[0133] Optionally, the determination of the target cache block in the first cache space or the target data block in the storage unit according to the target physical address includes: according to the target physical address, querying the plurality of storage data directory table items in the first cache space; when a target storage data table item in the plurality of storage data directory table items hits, determining a cache block indicated by the target storage data table item as the target cache block; when none of the plurality of storage data directory table items hits, taking a data block in the storage unit indicated by the target physical address as the target data block.

[0134] Optionally, the system-level cache unit is further configured to: allocate a first cache block in the plurality of cache blocks to the target data block to store data in the target data block; and write a mapping relationship between the first cache block and the target physical address as a new storage data directory table item into the plurality of storage data directory table items in the first cache space.

[0135] Figure 10is a schematic structural diagram of a system-level SOC chip 100 provided by an embodiment of the present application. Figure 10 The SOC chip in the system 1000 includes at least one master device 1001A,..., 1001N and a system-level cache unit 1002.

[0136] The master device can be the master device described in any of the preceding embodiments, for example, can be a component in an SOC such as a CPU, GPU, NPU, APU, ISP, or can also be a multimedia device arranged outside the SOC, for example, a video playing device, an audio playing device, etc.

[0137] The system-level cache unit 1002 or the master device 1001A,..., 1001N is configured to perform the data processing method described in any of the preceding embodiments.

[0138] Figure 11 is a schematic structural diagram of a computer device 110 provided by an embodiment of the present application. The computer device can be a smartphone, a tablet computer, a notebook computer, a desktop computer, a smart speaker, a smart watch, etc.

[0139] Figure 11 The computer device 110 in the system 1100 includes a chip 1101 and a storage unit 1102. The chip 1101 is connected to the storage unit 1102 through a bus. The chip 1101 can be the SOC chip described in any of the preceding embodiments, and the chip is configured to implement the data processing method described in the preceding embodiments when running.

[0140] An embodiment of the present application further provides a computer readable storage medium for storing a program. The computer readable storage medium can be applied to the terminal device or the network device provided by the embodiments of the present application, and the program causes the computer to execute the method performed by the terminal device or the network device in the embodiments of the present application.

[0141] An embodiment of the present application further provides a computer program product. The computer program product includes a program. The computer program product can be applied to the terminal device or the network device provided by the embodiments of the present application, and the program causes the computer to execute the method performed by the terminal device or the network device in the embodiments of the present application.

[0142] An embodiment of the present application further provides a computer program. The computer program can be applied to the terminal device or the network device provided by the embodiments of the present application, and the computer program causes the computer to execute the method performed by the terminal device or the network device in the embodiments of the present application.

[0143] In the embodiments described above, all or some of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or some of the embodiments can be implemented in the form of a computer program product storing computer program instructions. When the computer program instructions are loaded into and executed by a computer, all or some of the procedures or functions according to the embodiments of the present disclosure are generated. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer program instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer program instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) manner. The computer readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media. The available media can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a digital video disc (DVD)), or a semiconductor medium (such as a solid state disk (SSD)), etc.

[0144] Those skilled in the art can realize that the units and algorithm steps of each example described in connection with the embodiments of the present disclosure can be realized by electronic hardware, or a combination of computer software and electronic hardware. Whether the functions are performed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present disclosure.

[0145] In several embodiments provided by the present disclosure, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the device embodiments described above are merely schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units or components shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0146] The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may also be distributed to multiple network units. Part or all of the units can be selected to achieve the purpose of the embodiment of the present application according to actual needs.

[0147] In addition, each functional unit in various embodiments of the present disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0148] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A data processing method, the method being applied to a system-level cache unit, the system-level cache unit being disposed between at least one host device and a storage unit for address translation and caching of data in the storage unit, characterized in that, The system-level cache unit includes a first cache space and a second cache space; The first cache space includes multiple cache blocks and multiple storage data directory entries. The multiple cache blocks are used to cache data in the storage unit, and the multiple storage data directory entries are used to indicate the mapping relationship between the physical addresses of the cache blocks and the data blocks in the storage unit. The second cache space includes multiple page table directory entries, which are used to indicate the mapping relationship between virtual addresses and the physical addresses of data blocks in the storage unit; The method includes: Determine the target physical address indicated by the read / write access request sent by the master device; Based on the target physical address, determine the target cache block in the first cache space or the target data block in the storage unit; Perform data read / write operations on the target cache block or the target data block; Wherein, the target cache block is one or more of the plurality of cache blocks, and the target data block is one or more of the plurality of data blocks.

2. The method according to claim 1, characterized in that, Determining the target physical address indicated by the read / write access request sent by the master device includes: Parse the read / write access request; When the address in the read / write access request indicates the physical address of the storage unit, the physical address is used as the target physical address; or, When the address indicated in the read / write access request is a virtual address, the virtual address is converted to the target physical address.

3. The method according to claim 2, characterized in that, The step of converting the virtual address into a target physical address includes: Based on the virtual address, query the plurality of page table directory entries in the second cache space; When a target page table directory entry is matched among the plurality of page table directory entries, the physical address indicated by the target page table directory entry is used as the target physical address; or, When none of the multiple page table directory entries are matched, the page table of the storage unit is read to obtain the target physical address corresponding to the virtual address.

4. The method according to claim 3, characterized in that, After reading the page table of the storage unit and obtaining the target physical address corresponding to the virtual address, the method further includes: writing the mapping relationship between the virtual address and the target physical address as a new page table directory entry into the second cache space.

5. The method according to claim 1, characterized in that, The step of determining the target cache block in the first cache space or the target data block in the storage unit based on the target physical address includes: Based on the target physical address, query the plurality of storage data directory entries in the first cache space; When a target storage data entry is matched among the plurality of storage data directory entries, the cache block indicated by the target storage data entry is determined as the target cache block. When none of the multiple storage data directory entries are matched, the data block in the storage unit indicated by the target physical address is used as the target data block.

6. The method according to claim 1, characterized in that, After performing data read / write operations in the target data block, the method further includes: The first cache block among the plurality of cache blocks is allocated to the target data block to store the data in the target data block; The mapping relationship between the first cache block and the target physical address is written as a new storage data directory entry into multiple storage data directory entries of the first cache space.

7. A data processing apparatus, the apparatus being applied to a system-level cache unit, the system-level cache unit being disposed between at least one main device and a storage unit for address translation and caching of data in the storage unit, characterized in that, The system-level cache unit includes a first cache space and a second cache space; The first cache space includes multiple cache blocks and multiple storage data directory entries. The multiple cache blocks are used to cache data in the storage unit, and the multiple storage data directory entries are used to indicate the mapping relationship between the physical addresses of the cache blocks and the data blocks in the storage unit. The second cache space includes multiple page table directory entries, which are used to indicate the mapping relationship between virtual addresses and the physical addresses of data blocks in the storage unit; The device includes: The first determining unit is configured to determine the target physical address indicated by the read / write access request sent by the master device; The second determining unit is configured to determine a target cache block in the first cache space or a target data block in the storage unit based on the target physical address. The execution unit is configured to perform data read / write operations on the target cache block or the target data block. Wherein, the target cache block is one or more of the plurality of cache blocks, and the target data block is one or more of the plurality of data blocks.

8. The apparatus according to claim 7, characterized in that, The first determining unit is used for: Parse the read / write access request; When the address in the read / write access request indicates the physical address of the storage unit, the physical address is used as the target physical address; or, When the address indicated in the read / write access request is a virtual address, the virtual address is converted to the target physical address.

9. The apparatus according to claim 8, characterized in that, The step of converting the virtual address into a target physical address includes: Based on the virtual address, query the plurality of page table directory entries in the second cache space; When a target page table directory entry is matched among the plurality of page table directory entries, the physical address indicated by the target page table directory entry is used as the target physical address; or, When none of the multiple page table directory entries are matched, the page table of the storage unit is read to obtain the target physical address corresponding to the virtual address.

10. The apparatus according to claim 9, characterized in that, The device further includes: The first writing unit is configured to write the mapping relationship between the virtual address and the target physical address into the second cache space as a new page table directory entry.

11. The apparatus according to claim 7, characterized in that, The second determining unit is used for: Based on the target physical address, query the plurality of storage data directory entries in the first cache space; When a target storage data entry is matched among the plurality of storage data directory entries, the cache block indicated by the target storage data entry is determined as the target cache block. When none of the multiple storage data directory entries are matched, the data block in the storage unit indicated by the target physical address is used as the target data block.

12. The apparatus according to claim 7, characterized in that, The device further includes: The allocation unit is configured to allocate a first cache block among the plurality of cache blocks to the target data block to store the data in the target data block; The second writing unit is configured to write the mapping relationship between the first cache block and the target physical address as a new storage data directory entry into multiple storage data directory entries of the first cache space.

13. A data processing system, characterized in that, The system includes: At least one main device, storage unit, and system-level cache unit; The system-level cache unit is located between the at least one master device and the storage unit, and is used for address translation and caching of data in the storage unit; The system-level cache unit includes a first cache space and a second cache space. The first cache space includes multiple cache blocks and multiple storage data directory entries. The multiple cache blocks are used to cache data in the storage unit, and the multiple storage data directory entries are used to indicate the mapping relationship between the physical addresses of the cache blocks and the data blocks in the storage unit. The second cache space includes multiple page table directory entries, and the page table directory entries are used to indicate the mapping relationship between virtual addresses and the physical addresses of the data blocks in the storage unit. The system-level cache unit is used for: Determine the target physical address indicated by the read / write access request sent by the master device; Based on the target physical address, determine the target cache block in the first cache space or the target data block in the storage unit; Perform data read / write operations on the target cache block or the target data block; Wherein, the target cache block is one or more of the plurality of cache blocks, and the target data block is one or more of the plurality of data blocks.

14. The system according to claim 13, characterized in that, Determining the target physical address indicated by the read / write access request sent by the master device includes: Parse the read / write access request; When the address in the read / write access request indicates the physical address of the storage unit, the physical address is used as the target physical address; or, When the address indicated in the read / write access request is a virtual address, the virtual address is converted to the target physical address.

15. The system according to claim 14, characterized in that, The step of converting the virtual address into a target physical address includes: Based on the virtual address, query the plurality of page table directory entries in the second cache space; When a target page table directory entry is matched among the plurality of page table directory entries, the physical address indicated by the target page table directory entry is used as the target physical address; or, When none of the multiple page table directory entries are matched, the page table of the storage unit is read to obtain the target physical address corresponding to the virtual address.

16. The system according to claim 15, characterized in that, The system-level cache unit is also used for: The mapping relationship between the virtual address and the target physical address is written into the second cache space as a new page table directory entry.

17. The system according to claim 13, characterized in that, The step of determining the target cache block in the first cache space or the target data block in the storage unit based on the target physical address includes: Based on the target physical address, query the plurality of storage data directory entries in the first cache space; When a target storage data entry is matched among the plurality of storage data directory entries, the cache block indicated by the target storage data entry is determined as the target cache block. When none of the multiple storage data directory entries are matched, the data block in the storage unit indicated by the target physical address is used as the target data block.

18. The system according to claim 13, characterized in that, The system-level cache unit is also used for: The first cache block among the plurality of cache blocks is allocated to the target data block to store the data in the target data block; The mapping relationship between the first cache block and the target physical address is written as a new storage data directory entry into multiple storage data directory entries of the first cache space.

19. A system-on-a-chip (SoC), characterized in that, The SOC chip includes: at least one master device and a system-level cache unit, wherein the at least one master device is connected to the system-level cache unit via a bus; The system-level cache or the master device is used to execute the data processing method as described in any one of claims 1 to 6.

20. A computer device, characterized in that, The computer device includes: a chip and a storage unit, wherein the chip and the storage unit are connected together; The chip includes the SOC chip as described in claim 19.

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