Memory atomic operation instruction execution method, device, access module and system

Abstract

The present disclosure provides a method, device, access module and system for executing memory atomic operation instructions, which relate to the field of computer technology, and in particular to the field of chips. The specific implementation scheme is: obtaining the target memory atomic operation instruction sent by the target computing core; sending a mutually exclusive read instruction for the read and write address through the target protocol bus; in response to the read data fed back by the target protocol bus, calculating the instruction calculation result according to the target memory atomic operation instruction; sending a mutually exclusive write instruction for the read and write address through the target protocol bus, and writing the instruction calculation result to the read and write address; in response to the write success response fed back by the target protocol bus, feeding back the instruction calculation result to the target computing core. The present disclosure achieves the effect of low running overhead, high execution efficiency and low implementation complexity of the memory atomic operation instruction.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, in particular to the field of chips, and specifically to a method, device, access module and system for executing memory atomic operation instructions. Background Art

[0002] Modern multi-core processors generally support atomic operations to achieve mutually exclusive access to shared variables, avoid data contention, and ensure correct program execution. Atomic operations are atomic read-modify-write sequences of operations performed on shared variables in memory, and their execution cannot be interrupted by other operations. Implementing these atomic operations requires the processor to support corresponding atomic instructions, such as Intel's CMPXCHG atomic instruction, IBM's CAS atomic instruction (a Java instruction), ARM's SWP, LDADD, LDREX, or STREX instructions, MIPS's LL or SC instructions, and RISC-V's LR, SC, or AMO instructions.

[0003] Existing processors have high complexity and high implementation overhead when implementing AMO (Atomic Memory Operation) instructions. At the same time, they are generally implemented in on-chip cache (Local Memory) or data cache. Implementing AMO instructions in GM (Global Memory) is less common. Summary of the Invention

[0004] The present disclosure provides a method, device, access module and system for executing memory atomic operation instructions.

[0005] According to one aspect of the present disclosure, a method for executing a memory atomic operation instruction is provided, which is executed by a direct memory access module in a system on chip, comprising:

[0006] Obtaining a target memory atomic operation instruction sent by a target computing core, wherein the read and write addresses in the target memory atomic operation instruction are addresses on a global memory;

[0007] Sending a mutually exclusive read instruction for a read / write address via a target protocol bus to read data from the read / write address, wherein the target protocol bus has a mutually exclusive read / write control function;

[0008] In response to the read data fed back by the target protocol bus, calculating an instruction calculation result matching the read data according to the target memory atomic operation instruction;

[0009] Sending a mutually exclusive write instruction for the read / write address via the target protocol bus to write the instruction calculation result to the read / write address;

[0010] In response to the write success response fed back by the target protocol bus, the instruction calculation result is fed back to the target computing core.

[0011] According to another aspect of the present disclosure, a device for executing a memory atomic operation instruction is provided, which is configured on a direct memory access module in a system on chip, comprising:

[0012] an instruction acquisition module configured to acquire a target memory atomic operation instruction sent by a target computing core, wherein the read and write addresses in the target memory atomic operation instruction are addresses on a global memory;

[0013] a data reading module configured to send mutually exclusive read instructions for a read / write address via a target protocol bus to read data from the read / write address, wherein the target protocol bus has a mutually exclusive read / write control function;

[0014] a data calculation module configured to respond to the read data fed back by the target protocol bus and calculate an instruction calculation result matching the read data according to the target memory atomic operation instruction;

[0015] a data writing module configured to send mutually exclusive write instructions for the read and write addresses through the target protocol bus to write the instruction calculation results to the read and write addresses;

[0016] The data feedback module is configured to feed back the instruction calculation result to the target computing core in response to the write success response fed back by the target protocol bus.

[0017] According to another aspect of the present disclosure, a direct memory access module is provided, comprising:

[0018] at least one processor; and

[0019] a memory communicatively connected to at least one processor; wherein,

[0020] The memory stores instructions that can be executed by at least one processor, and the instructions are executed by at least one processor so that the at least one processor can execute the execution method of the memory atomic operation instruction in any embodiment of the present disclosure.

[0021] According to another aspect of the present disclosure, a system on chip is provided, comprising: a global memory and at least one cluster structure, wherein the at least one cluster structure establishes a communication connection with the global memory via an on-chip network module;

[0022] Each cluster structure includes a direct memory access module and multiple computing cores. Each direct memory access module and global memory are connected to the on-chip network module through a target protocol bus.

[0023] Each direct memory access module is used to execute the execution method of the memory atomic operation instruction in any embodiment of the present disclosure;

[0024] an on-chip network module, configured to, in response to a mutually exclusive read instruction for a first read / write address sent by the first direct memory access module, perform a recording operation on the first direct memory access module and the data item of the first read / write address; if the recording is successful, obtain read data matching the first read / write address from a global memory, and feed the read data back to the first direct memory access module; and

[0025] In response to a mutually exclusive write instruction for a second read-write address sent by a second direct memory access module, a query is made as to whether a target data item matching the second direct memory access module and the second read-write address is stored; if so, a calculation result of the instruction matching the mutually exclusive write operation is written to the second read-write address in the global memory; the target data item is cleared, and a write success response is fed back to the second direct memory access module.

[0026] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable a computer to execute the execution method of the memory atomic operation instruction in any embodiment of the present disclosure.

[0027] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, which implements the steps of the method for executing the memory atomic operation instruction in any embodiment of the present disclosure when the computer program is executed by a processor.

[0028] The technical solution of the embodiment of the present disclosure achieves the effects of low running overhead, high execution efficiency and low implementation complexity of memory atomic operation instructions.

[0029] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are provided to facilitate a better understanding of the present invention and do not constitute a limitation of the present disclosure.

[0031] Figure 1a This is a flowchart of a method for executing a memory atomic operation instruction provided by an embodiment of the present disclosure;

[0032] Figure 1bThis is a schematic diagram of the execution flow of a memory atomic operation instruction in a direct memory access module provided by an embodiment of the present disclosure;

[0033] Figure 2a This is a flowchart of another method for executing a memory atomic operation instruction provided by an embodiment of the present disclosure;

[0034] Figure 2b This is a flowchart of another method for executing a memory atomic operation instruction provided by an embodiment of the present disclosure;

[0035] Figure 3 It is a memory atomic operation instruction execution device provided by an embodiment of the present disclosure;

[0036] Figure 4 is a schematic diagram of a system on a chip provided by an embodiment of the present disclosure;

[0037] Figure 5 A schematic block diagram of an example direct memory access module that can be used to implement embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0038] The following description of exemplary embodiments of the present disclosure is made in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding. These details should be considered as merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0039] In one example, Figure 1a This is a flow chart of a method for executing a memory atomic operation instruction provided by an embodiment of the present disclosure. This embodiment is applicable to the case of implementing the read and write operations of memory atomic operation instructions on a global memory. This method can be executed by a direct memory access module in an on-chip chip. Figure 1a As shown, the method includes the following operations:

[0040] Step 110: Obtain the target memory atomic operation instruction sent by the target computing core.

[0041] The target computing core may be a computing core currently capable of performing data read and write operations based on addresses in global memory. The target memory atomic operation instruction may be a memory atomic operation instruction sent by the target computing core to perform a memory atomic operation by the target computing core. The read and write addresses in the target memory atomic operation instruction are addresses in global memory. The read and write addresses may be data storage addresses for which data is read and written back based on the target memory atomic operation instruction.

[0042] Generally speaking, the operation of reading data at storage address A of an operation object and writing the data processing result of the read data back to storage address A can be understood as an atomic operation, that is, first read the data stored in the read-write address, and after completing data processing on the data stored in the read-write address, write the data processing result back to the read-write address, which is equivalent to completing a memory atomic operation instruction.

[0043] For example, the format of a memory atomic operation instruction can be defined as "amoXXX rd, rt, rs" (the R-type encoding of the commonly used reduced instruction set computer style instruction set). Among them, XXX represents the operation type supported by the memory atomic operation instruction, such as signed integer addition and subtraction, signed integer comparison, exchange, logical AND or XOR operations, and integer maximum and minimum values. rt represents the storage address of the source data to be calculated, rd represents the write-back address of the data read result, and rs represents the specified read and write address. Because memory atomic operation instructions usually only support word-granularity data operations, the read and write addresses corresponding to rs are usually aligned to 4 bytes. The memory atomic operation instruction atomically executes a "read-modify-write" operation, that is, the instruction atomically reads the data value t from rs, writes the value t to rd, and performs a binary operation on the value t and the data stored in rt according to the instruction operation type, and then writes the binary data result back to rs.

[0044] Taking the instruction "amoadd r5, r2, r1" as an example, this instruction uses the data corresponding to the read-write address r1 as the read-write address, reads the data value from the read-write address in an atomic manner, puts the read data value into r5, and adds the read data value and the value stored in r2, and then writes the sum back to the read-write address r1.

[0045] Figure 1b This is a schematic diagram of the execution flow of a memory atomic operation instruction in a direct memory access module provided by an embodiment of the present disclosure. Figure 1b As shown, a memory atomic operation instruction, known as an instruction fetch, can be retrieved from the instruction cache. It is then decoded based on its instruction type and function, and the decoded result is transferred to the reservation station for issuance. Once the operands required for the memory atomic operation instruction are ready, it can be issued from the reservation station and begin execution. Memory access is performed during execution, and upon successful execution, data can be written back to the register.

[0046] In an embodiment of the present disclosure, the direct memory access module can receive memory atomic operation instructions sent by at least one computing core, and then determine the target computing core that can currently perform data read and write operations based on the address on the global memory from the computing core that sends the memory atomic operation instruction, thereby obtaining the target memory atomic operation instruction sent by the target computing core.

[0047] Step 120: Send a mutually exclusive read instruction for the read / write address via the target protocol bus to read data from the read / write address.

[0048] The target protocol bus has a mutually exclusive read and write control function. The mutually exclusive read instruction can be an instruction that only allows one object to have data read permission.

[0049] In an embodiment of the present disclosure, the direct memory access module can send mutually exclusive read instructions for the data stored in the read and write addresses to the global memory based on the target protocol bus, thereby realizing the reading of the data stored at the read and write addresses, and can prevent other computing cores other than the target computing core from initiating read operations on the data stored in the read and write addresses through the direct memory access module and the target protocol bus.

[0050] Step 130 : In response to the read data fed back by the target protocol bus, an instruction calculation result matching the read data is calculated according to the target memory atomic operation instruction.

[0051] The read data may be data read from the read / write address according to the mutually exclusive read instruction, and the instruction calculation result may be a data processing result after the read data is processed according to the target memory atomic operation instruction.

[0052] In an embodiment of the present disclosure, after the target protocol bus successfully reads the data stored in the read / write address, the read data is fed back to the direct memory access module. The direct memory access module performs corresponding data calculations on the read data according to the target memory atomic operation instruction to obtain an instruction calculation result that matches the read data.

[0053] Step 140: Send a mutually exclusive write instruction for the read / write address via the target protocol bus to write the instruction calculation result to the read / write address.

[0054] The mutually exclusive write instruction may be an instruction that only enables one object to have data write permission.

[0055] In an embodiment of the present disclosure, after calculating the instruction calculation result that matches the read data, the direct memory access module can further send a mutually exclusive write instruction through the target protocol bus to write the instruction calculation result to the read and write address, so as to prevent other computing cores except the target computing core from initiating write operations on the read and write addresses through the direct memory access module and the target protocol bus.

[0056] Step 150 : In response to the write success response fed back by the target protocol bus, the instruction calculation result is fed back to the target computing core.

[0057] The write success response may be a signal sent by the target protocol bus to the direct memory access module, reflecting that the instruction calculation result is successfully written into the read / write address.

[0058] In the disclosed embodiment, after the instruction calculation result is written to the read / write address of the global memory, the target protocol bus sends a write success response to the direct memory access module. After receiving the write success response fed back by the target protocol bus, the direct memory access module further sends the instruction calculation result to the target computing core, so that the target computing core can use the instruction calculation result for subsequent data processing.

[0059] The technical solution of the embodiment of the present disclosure obtains the target memory atomic operation instruction sent by the target computing core, thereby sending a mutually exclusive read instruction for the read and write address through the target protocol bus to read data from the read and write address, and responding to the read data fed back by the target protocol bus, calculating the instruction calculation result that matches the read data according to the target memory atomic operation instruction, and then sending a mutually exclusive write instruction for the read and write address through the target protocol bus to write the instruction calculation result to the read and write address, and further responding to the write success response fed back by the target protocol bus, feeding back the instruction calculation result to the target computing core. This solution can implement memory atomic operation instruction operations on the global memory, making the use and expansion range of memory atomic operation instructions wider, and the target protocol bus has a mutually exclusive read and write control function. When the direct memory access module executes the memory atomic operation instruction, the implementation complexity and related implementation overhead of the memory atomic operation instruction can be reduced, thereby improving the system execution efficiency, solving the problems of high complexity and high overhead in the existing processor implementation of memory atomic operation instructions, and achieving the effect of low running overhead, high execution efficiency and low implementation complexity of the memory atomic operation instruction.

[0060] In one example, Figure 2a This is a flowchart of another method for executing a memory atomic operation instruction provided by an embodiment of the present disclosure. This embodiment provides an optional implementation method. Figure 2a As shown, the method includes the following operations:

[0061] Step 210 : Whenever a beat time point is reached, the pending memory atomic operation instructions of multiple computing cores in the target cluster structure are obtained, and arbitration selection is performed among the pending memory atomic operation instructions.

[0062] Among them, the beat time point can be used to trigger the direct memory access module to obtain the memory atomic operation instruction sent by the computing core. Optionally, the beat time point can be set according to the clock cycle of the direct memory access module. At a beat time point, multiple computing cores can send memory atomic operation instructions to the direct memory access module. The target cluster structure can be a multi-core structure where the target computing core is located. The target cluster structure may include a target computing core, a direct memory access module, multiple memories, and other computing cores belonging to the same multi-core structure as the target computing core. The memory atomic operation instruction to be processed may be a memory atomic operation instruction sent by the computing core managed by the direct memory access module at the beat time point.

[0063] In the embodiment of the present disclosure, whenever the beat time point is reached, the direct memory access module of the target cluster structure obtains the pending memory atomic operation instructions sent by multiple computing cores in the cluster structure, and then arbitrates and selects the pending memory atomic operation instructions to determine the target memory atomic operation instructions sent by the target computing core.

[0064] Step 220: If a memory atomic operation instruction is arbitrated, the arbitrated memory atomic operation instruction is obtained as a target memory atomic operation instruction.

[0065] In an embodiment of the present disclosure, if at a beat time point, the direct memory access module arbitrates a memory atomic operation instruction sent by the target computing core, the arbitrated memory atomic operation instruction sent by the target computing core is used as the target memory atomic operation instruction.

[0066] Step 230: If no memory atomic operation instruction is arbitrated, wait for the next beat time point to continue arbitration until the target memory atomic operation instruction is obtained.

[0067] In the disclosed embodiment, if the direct memory access module does not obtain the memory atomic operation instruction sent by the target computing core at the beat time point, indicating that the direct memory access module has not arbitrated any memory atomic operation instruction, the direct memory access module waits for the next beat time point to continue arbitration until the target memory atomic operation instruction is obtained. Through steps 210-230, it is possible to automatically arbitrate the pending memory atomic operation instructions at the beat time point and obtain the target memory atomic operation instruction.

[0068] In an optional embodiment of the present disclosure, arbitration selection is performed among the memory atomic operation instructions to be processed, which may include: obtaining a target time slot that matches the current beat time point, and obtaining a target computing core assigned to the target time slot; determining whether the target computing core has a memory atomic operation instruction to be processed; if so, determining that a memory atomic operation instruction has been arbitrated; otherwise, determining that no memory atomic operation instruction has been arbitrated.

[0069] Among them, the target time slot can be a pre-set time interval. Optionally, the target time slot has a corresponding relationship with the target computing core. Under one target time slot, only one computing core is allocated as the target computing core, and different computing cores correspond to different target time slots. For example, assuming that the time slot interval of the pre-set target time slot is 5ms, the target time slot 1 is 11:22:49:993ms-11:22:49:998ms, and the target time slot 2 is 11:22:49:998ms-11:22:50:3ms. If the current beat time point is 11:22:50, the target time slot that matches the current beat time point is target time slot 2.

[0070] In the embodiment of the present disclosure, the direct memory access module can first obtain the target time slot that matches the current beat time point, and then determine the target computing core that matches the target time slot that matches the current beat time point based on the corresponding relationship between the target time slot and the computing core, and then determine whether the memory atomic operation instruction to be processed sent by the target computing core is received in the target time slot. If the memory atomic operation instruction to be processed sent by the target computing core is received in the target time slot, it is determined that the memory atomic operation instruction is arbitrated. If the memory atomic operation instruction to be processed sent by the target computing core is not received in the target time slot, it is determined that no memory atomic operation instruction is arbitrated. Since the target time slot and the computing core have a corresponding matching relationship, the target computing core can be quickly and accurately determined from multiple computing cores based on the target time slot to accurately obtain the memory atomic operation instruction to be processed.

[0071] Step 240: Send a mutually exclusive read instruction for the read / write address via the target protocol bus to read data from the read / write address.

[0072] In an optional embodiment of the present disclosure, after sending mutually exclusive read instructions for the read and write addresses through the target protocol bus, it may also include: in response to a read failure response fed back by the target protocol bus, re-sending mutually exclusive read instructions for the read and write addresses through the target protocol bus until read data from the target protocol bus is received.

[0073] The read failure response may be a signal fed back by the target protocol bus to the direct memory access module indicating a failure in reading the data stored in the read / write address.

[0074] In an embodiment of the present disclosure, after the direct memory access module sends a mutually exclusive read instruction for a read / write address through a target protocol bus, if the target protocol bus fails to successfully read the data in the read / write address, a read failure response is sent to the direct memory access module. The direct memory access module receives the read failure response fed back by the target protocol bus and further sends a mutually exclusive read instruction for the read / write address through the target protocol bus again until it receives the read data fed back by the target protocol bus after a successful read. This can avoid data read conflicts and ensure that the direct memory access module can reliably read and write addresses on the global memory.

[0075] Step 250: In response to the read data fed back by the target protocol bus, calculate an instruction calculation result that matches the read data according to the target memory atomic operation instruction.

[0076] Step 260: Send a mutually exclusive write instruction for the read / write address via the target protocol bus to write the instruction calculation result to the read / write address.

[0077] In an optional embodiment of the present disclosure, after sending mutually exclusive write instructions for the read and write addresses through the target protocol bus, it may also include: in response to a write failure response fed back by the target protocol bus, returning to execute the operation of sending mutually exclusive read instructions for the read and write addresses through the target protocol bus until a write success response fed back by the target protocol bus is received.

[0078] The write failure response may be a signal fed back by the target protocol bus to the direct memory access module, reflecting that writing of data in the read / write address has failed.

[0079] In an embodiment of the present disclosure, after the direct memory access module sends a mutually exclusive write instruction to write the instruction calculation result to the read-write address through the target protocol bus, if the instruction calculation result is not successfully written into the read-write address, a write failure response can be sent to the direct memory access module through the target protocol bus. After the direct memory access module receives the write failure response fed back by the target protocol bus, it returns to execute the operation of sending the mutually exclusive read instruction for the read-write address through the target protocol bus until it receives the write success response fed back by the target protocol bus. This can avoid data write operation conflicts, thereby ensuring that the instruction calculation result is successfully written into the read-write address.

[0080] Step 270: In response to the write success response fed back by the target protocol bus, the instruction calculation result is fed back to the target computing core.

[0081] In an optional embodiment of the present disclosure, the target protocol bus may be an advanced extensible interface bus, and sending a mutually exclusive read instruction for a read / write address through the target protocol bus may specifically include: sending a high-level read lock signal through the advanced extensible interface bus; and determining that the mutually exclusive read instruction has been successfully sent in response to a high-level read lock ready signal fed back by the advanced extensible interface bus; and sending a mutually exclusive write instruction for a read / write address through the target protocol bus may include: sending a high-level write lock signal through the advanced extensible interface bus; and determining that the mutually exclusive write instruction has been successfully sent in response to a high-level write lock ready signal fed back by the advanced extensible interface bus.

[0082] Among them, the advanced extensible interface bus is a multi-channel transmission bus. The read lock signal can be a signal sent by the advanced extensible interface bus to lock the reading of data stored in the read-write address, and is used for mutually exclusive reading of data stored in the read-write address. The read lock preparation signal can be a signal fed back by the advanced extensible interface bus to the direct memory access module after the advanced extensible interface bus sends a high-level read lock signal, which is used to indicate that the direct memory access module has the authority to lock the reading of data stored in the read-write address. The write lock signal can be used to enable the object that reads the data stored in the read-write address to write data in the read-write address exclusively. The write lock preparation signal can be a signal fed back by the advanced extensible interface bus to the direct memory access module after the advanced extensible interface bus sends a high-level write lock signal, which is used to enable the object that reads the data stored in the read-write address to have the authority to write data in the read-write address.

[0083] In the embodiment of the present disclosure, a high-level read lock signal can be sent through the advanced extensible interface bus. After the direct memory access module receives the high-level read lock ready signal fed back by the advanced extensible interface bus, it can be determined that the mutually exclusive read instruction has been successfully sent, thereby realizing the reading of the data stored in the read-write address. Furthermore, a high-level write lock signal can also be sent through the advanced extensible interface bus. After the direct memory access module receives the high-level write lock ready signal fed back by the advanced extensible interface bus, it can be determined that the mutually exclusive write instruction has been successfully sent. At this time, the direct memory access module that reads the data stored in the read-write address can write data to the read-write address. The advanced extensible interface bus has a bus interface feature that can enable memory atomic operation instructions to be executed on the global memory, thereby making the memory atomic operation instructions more usable and extensible.

[0084] The technical solution of the embodiment of the present disclosure is to obtain the pending memory atomic operation instructions of multiple computing cores in the target cluster structure every time a beat time point is reached, and arbitrate and select among the pending memory atomic operation instructions. If a memory atomic operation instruction is arbitrated, the arbitrated memory atomic operation instruction is obtained as the target memory atomic operation instruction. If no memory atomic operation instruction is arbitrated, the arbitration is continued at the next beat time point until the target memory atomic operation instruction is obtained, and then a mutually exclusive read instruction for the read and write address is sent through the target protocol bus to read data from the read and write address, and in response to the read data fed back by the target protocol bus, an instruction calculation result that matches the read data is calculated according to the target memory atomic operation instruction, and further a mutually exclusive write instruction for the read and write address is sent through the target protocol bus to write the instruction calculation result to the read and write address, and in response to the write success response fed back by the target protocol bus, the instruction calculation result is fed back to the target computing core. This solution can implement memory atomic operation instruction operations on the global memory, making the use and expansion scope of memory atomic operation instructions wider, and the target protocol bus has exclusive read and write control functions. When the direct memory access module executes the memory atomic operation instruction, the implementation complexity and related implementation overhead of the memory atomic operation instruction can be reduced, thereby improving the system execution efficiency, solving the problems of high complexity and high overhead in the implementation of memory atomic operation instructions by existing processors, and achieving the effect of low running overhead, high execution efficiency and low implementation complexity of memory atomic operation instructions.

[0085] In one example, Figure 2b is a flowchart of another method for executing a memory atomic operation instruction provided by an embodiment of the present disclosure, such as Figure 2b As shown, the method includes:

[0086] Step 2100: Whenever a beat time point is reached, obtain the pending memory atomic operation instructions of multiple computing cores in the target cluster structure, and obtain the target time slot matching the current beat time point and the target computing core allocated to the target time slot.

[0087] Step 2200, determine whether the target computing core has a memory atomic operation instruction to be processed; if so, determine that a memory atomic operation instruction is arbitrated, and obtain the arbitrated memory atomic operation instruction as the target memory atomic operation instruction; otherwise, determine that no memory atomic operation instruction is arbitrated, wait for the next beat time point to continue arbitration until the target memory atomic operation instruction is obtained.

[0088] Step 2300: Send a high-level read lock signal via the AEIB bus, and in response to a high-level read lock ready signal fed back by the AEIB bus, determine that the mutually exclusive read instruction is successfully sent.

[0089] Step 2400: In response to the read data fed back by the target protocol bus, or in response to the read failure response fed back by the target protocol bus, if in response to the read data fed back by the target protocol bus, the instruction calculation result that matches the read data is calculated according to the target memory atomic operation instruction; if in response to the read failure response fed back by the target protocol bus, the mutually exclusive read instruction for the read and write addresses is resent through the target protocol bus until the read data fed back by the target protocol bus is received.

[0090] Step 2500: Send a high-level write lock signal via the AEIB bus; and in response to a high-level write lock ready signal fed back by the AEIB bus, determine that the mutually exclusive write instruction is successfully sent.

[0091] Step 2600: In response to a write success response fed back by the target protocol bus, or in response to a write failure response fed back by the target protocol bus, if in response to a write success response fed back by the target protocol bus, the instruction calculation result is fed back to the target computing core; if in response to a write failure response fed back by the target protocol bus, the operation of sending mutually exclusive read instructions for the read and write addresses through the target protocol bus is returned to execution until a write success response fed back by the target protocol bus is received.

[0092] The technical solution of the embodiment of the present disclosure is to obtain the pending memory atomic operation instructions of multiple computing cores in the target cluster structure whenever a beat time point is reached, and obtain the target time slot matching the current beat time point, as well as the target computing core assigned to the target time slot, so as to determine whether the target computing core has a pending memory atomic operation instruction; if so, it is determined that a memory atomic operation instruction has been arbitrated, and the arbitrated memory atomic operation instruction is obtained as the target memory atomic operation instruction; otherwise, it is determined that no memory atomic operation instruction has been arbitrated, and the arbitration is continued at the next beat time point until the target memory atomic operation instruction is obtained, and then a high-level read lock signal is sent through the advanced extensible interface bus, and in response to the high-level read lock ready signal fed back by the advanced extensible interface bus, it is determined that the mutually exclusive read instruction has been successfully sent. In response to read data fed back by the target protocol bus, or in response to a read failure response fed back by the target protocol bus, if in response to the read data fed back by the target protocol bus, an instruction calculation result matching the read data is calculated according to the target memory atomic operation instruction; if in response to a read failure response fed back by the target protocol bus, mutually exclusive read instructions for the read and write addresses are resent via the target protocol bus until the read data fed back by the target protocol bus is received, and a high-level write lock signal is further sent via the advanced extensible interface bus; in response to a high-level write lock ready signal fed back by the advanced extensible interface bus, it is determined that the mutually exclusive write instruction has been successfully sent; in response to a write success response fed back by the target protocol bus, or in response to a write failure response fed back by the target protocol bus, if in response to a write success response fed back by the target protocol bus, the instruction calculation result is fed back to the target computing core; if in response to a write failure response fed back by the target protocol bus, execution of the operation of sending mutually exclusive read instructions for the read and write addresses via the target protocol bus is returned to until a write success response fed back by the target protocol bus is received. This solution can implement memory atomic operation instruction operations on the global memory, making the use and expansion scope of memory atomic operation instructions wider, and the target protocol bus has exclusive read and write control functions. When the direct memory access module executes the memory atomic operation instruction, the implementation complexity and related implementation overhead of the memory atomic operation instruction can be reduced, thereby improving the system execution efficiency, solving the problems of high complexity and high overhead in the implementation of memory atomic operation instructions by existing processors, and achieving the effect of low running overhead, high execution efficiency and low implementation complexity of memory atomic operation instructions.

[0093] Figure 3 The embodiment of the present disclosure provides an execution device for a memory atomic operation instruction, which is configured on a direct memory access module in a system on chip and includes an instruction acquisition module 310, a data reading module 320, a data calculation module 330, a data writing module 340, and a data feedback module 350, wherein:

[0094] The instruction acquisition module 310 is configured to acquire a target memory atomic operation instruction sent by a target computing core, wherein the read and write addresses in the target memory atomic operation instruction are addresses on a global memory;

[0095] The data reading module 320 is configured to send a mutually exclusive read instruction for a read / write address via a target protocol bus to read data from the read / write address, wherein the target protocol bus has a mutually exclusive read / write control function;

[0096] The data calculation module 330 is configured to respond to the read data fed back by the target protocol bus and calculate the instruction calculation result matching the read data according to the target memory atomic operation instruction;

[0097] The data writing module 340 is configured to send a mutually exclusive write instruction for the read / write address via the target protocol bus to write the instruction calculation result to the read / write address;

[0098] The data feedback module 350 is configured to feed back the instruction calculation result to the target computing core in response to the write success response fed back by the target protocol bus.

[0099] The technical solution of the embodiment of the present disclosure obtains the target memory atomic operation instruction sent by the target computing core, thereby sending a mutually exclusive read instruction for the read and write address through the target protocol bus to read data from the read and write address, and responding to the read data fed back by the target protocol bus, calculating the instruction calculation result that matches the read data according to the target memory atomic operation instruction, and then sending a mutually exclusive write instruction for the read and write address through the target protocol bus to write the instruction calculation result to the read and write address, and further responding to the write success response fed back by the target protocol bus, feeding back the instruction calculation result to the target computing core. This solution can implement memory atomic operation instruction operations on the global memory, making the use and expansion range of memory atomic operation instructions wider, and the target protocol bus has a mutually exclusive read and write control function. When the direct memory access module executes the memory atomic operation instruction, the implementation complexity and related implementation overhead of the memory atomic operation instruction can be reduced, thereby improving the system execution efficiency, solving the problems of high complexity and high overhead in the existing processor implementation of memory atomic operation instructions, and achieving the effect of low running overhead, high execution efficiency and low implementation complexity of the memory atomic operation instruction.

[0100] Optionally, the instruction acquisition module 310 includes an arbitration selection unit and an arbitration processing unit, wherein the arbitration selection unit is configured to obtain the pending memory atomic operation instructions of multiple computing cores in the target cluster structure whenever a beat time point is reached, and to arbitrate and select among the pending memory atomic operation instructions; the arbitration processing unit is configured to obtain the arbitrated memory atomic operation instruction as the target memory atomic operation instruction if a memory atomic operation instruction is arbitrated; if no memory atomic operation instruction is arbitrated, wait for the next beat time point to continue arbitration until the target memory atomic operation instruction is obtained.

[0101] Optionally, the arbitration selection unit includes a target computing core acquisition subunit and an arbitration result judgment subunit. The target computing core acquisition subunit is configured to obtain a target time slot that matches the current beat time point and obtain the target computing core allocated to the target time slot; the arbitration result judgment subunit is configured to judge whether the target computing core has a memory atomic operation instruction to be processed; if so, it is determined that a memory atomic operation instruction has been arbitrated; otherwise, it is determined that no memory atomic operation instruction has been arbitrated.

[0102] Optionally, the execution device of the memory atomic operation instruction also includes a mutually exclusive read instruction retransmission module, which is configured to respond to the read failure response fed back by the target protocol bus and resend the mutually exclusive read instruction for the read and write address through the target protocol bus until the read result fed back by the target protocol bus is received.

[0103] Optionally, the execution device of the memory atomic operation instruction also includes a mutually exclusive write instruction retransmission module, which is configured to respond to the write failure response fed back by the target protocol bus and return to execute the operation of sending the mutually exclusive read instruction for the read and write address through the target protocol bus until a write success response fed back by the target protocol bus is received.

[0104] Optionally, the target protocol bus is an advanced extensible interface bus; the data reading module 320 is configured to send a high-level read lock signal through the advanced extensible interface bus; in response to the high-level read lock ready signal fed back by the advanced extensible interface bus, it is determined that the mutually exclusive read instruction has been successfully sent; the data feedback module 350 is configured to send a high-level write lock signal through the advanced extensible interface bus; in response to the high-level write lock ready signal fed back by the advanced extensible interface bus, it is determined that the mutually exclusive write instruction has been successfully sent.

[0105] Figure 4 is a schematic diagram of a system on a chip provided by an embodiment of the present disclosure, such as Figure 4As shown, the on-chip system may include: a global memory and at least one cluster structure, at least one cluster structure establishing a communication connection with the global memory through an on-chip network module; each cluster structure may include a direct memory access module and multiple computing cores, each direct memory access module and the global memory are connected to the on-chip network module through a target protocol bus; each direct memory access module is used to execute the execution method of the memory atomic operation instruction provided by any embodiment of the present disclosure; the on-chip network module is used to respond to a mutually exclusive read instruction for a first read-write address sent by a first direct memory access module, perform a recording operation on the first direct memory access module and the data item of the first read-write address; if the recording is successful, obtain the read data matching the first read-write address in the global memory, and feed the read data back to the first direct memory access module; and respond to a mutually exclusive write instruction for a second read-write address sent by a second direct memory access module, query whether a target data item matching the second direct memory access module and the second read-write address is stored; if so, write the instruction calculation result matching the mutually exclusive write operation to the second read-write address in the global memory; clear the target data item, and feed back a write success response to the second direct memory access module.

[0106] In which, the cluster structure can be a multi-core structure in a system on chip. The first direct memory access module can be a direct memory access module that sends a mutually exclusive read instruction for a first read / write address. The first read / write address can be an address at which the first direct memory access module needs to read and write data. The data item recording operation can be an operation that records the read behavior of the direct memory access module for the data in the read / write address. The target data item can be the data item recorded by the data item recording operation. The target data item may include the device identifier of the direct memory access module that sends the mutually exclusive read instruction, and the read / write address that matches the mutually exclusive read instruction. The second direct memory access module can be a direct memory access module that sends a mutually exclusive write instruction to write the instruction calculation result to the second read / write address. The second read / write address can be an address at which the second direct memory access module needs to read and write data.

[0107] In an embodiment of the present disclosure, a system-on-chip (SoC) may be composed of a global memory and at least one cluster structure, each of which may include a direct memory access (DMA) module and multiple computing cores. Each cluster structure in the SoC is communicatively connected to the global memory via an on-chip (NOC) module. Each DMA module is connected to the NOC module via a target protocol bus to execute the method for executing atomic memory operation instructions provided in any embodiment of the present disclosure.

[0108] Specifically, when a direct memory access module executes a memory atomic operation instruction, the on-chip network can receive a mutually exclusive read instruction for a first read / write address sent by a first direct memory access module via a target protocol bus, and perform a record operation on the first direct memory access module and the data item at the first read / write address. If the record operation is successful, read data matching the first read / write address is retrieved from a global memory and fed back to the first direct memory access module.

[0109] The on-chip network module can also receive a mutually exclusive write instruction for the second read-write address sent by the second direct memory access module, and then query whether a target data item matching the second direct memory access module and the second read-write address is stored. If it is determined that a target data item matching the second direct memory access module and the second read-write address is stored, it is determined that the same direct memory access module reads and writes data to the second read-write address, and writes the instruction calculation result matching the mutually exclusive write operation to the second read-write address in the global memory, thereby clearing the target data item and feeding back a write success response to the second direct memory access module to promptly clean up the data space occupied by the target data item and reduce the occurrence rate of recording failure.

[0110] In an optional embodiment of the present disclosure, the on-chip network module may also be configured to: after performing a data item recording operation on the first direct memory access module and the first read / write address, if the recording fails, feed back a read failure response to the first direct memory access module.

[0111] In an embodiment of the present disclosure, after the on-chip network module records the operation on the first direct memory access module and the data item of the first read-write address, if the recording fails, a read failure response can be fed back to the first direct memory access module, and the first direct memory access module resends the mutually exclusive read instruction for the first read-write address to the on-chip network module through the target protocol bus until the read data fed back by the target protocol bus is received.

[0112] In an optional embodiment of the present disclosure, the on-chip network module can also be used to: after querying whether the target data item matching the second direct memory access module and the second read / write address is stored, if not, feed back a write failure response to the second direct memory access module.

[0113] In an embodiment of the present disclosure, after querying whether a target data item matching the second direct memory access module and the second read-write address is stored, if the on-chip network module does not find a target data item matching the second direct memory access module and the second read-write address, it is determined that the operation of the second direct memory access module to write the instruction calculation result at the second read-write address has failed, and then a write failure response is fed back to the second direct memory access module. The second direct memory access module returns to execute the operation of sending a mutually exclusive read instruction for the second read-write address through the target protocol bus until a write success response fed back by the target protocol bus is received.

[0114] Optionally, each cluster structure of the system on chip can include 64 identical computing cores. The computing cores in a cluster structure can share global memory. Each computing core in the cluster structure can access its own exclusive LM (local memory), shared SM (shared memory) within a single cluster structure, and global memory. Memory atomic operation instructions operate on the address space on the global memory and are used for synchronization between multiple cluster structures. Each cluster structure accesses the on-chip network module on the Soc (System on Chip) through the target protocol bus (such as the AXI bus, etc.) interface, and then accesses the on-chip global memory.

[0115] Optionally, each cluster structure includes a direct memory access module (DMA) that centrally handles global memory access for each compute core. The DMA module accesses the SoC's global memory via the AXI bus. To implement atomic memory operations on global memory, a memory atomic operation module can be added to the DMA module to support the execution of atomic memory operations.

[0116] Exemplarily, each computing core sends the memory atomic operation instruction with data ready in the reservation station to the memory atomic operation module of the direct memory access module. The memory atomic operation module selects the target memory atomic operation instruction from the pending memory atomic operation instructions sent by each computing core through polling arbitration for execution, and will not arbitrate to select the next memory atomic operation instruction before the target memory atomic operation instruction is executed. According to the usage scenario of the memory atomic operation instruction, in most cases, each computing core or cluster structure operates on the same global memory address. In order to reduce invalid competition for memory atomic operation instructions with the same address within the cluster structure, the memory atomic operation module in the direct memory access module will only start executing the next memory atomic operation instruction after successfully executing a memory atomic operation instruction. The execution of the memory atomic operation instruction in the memory atomic operation module can be divided into processes such as "mutually exclusive read-calculation-mutually exclusive write". The specific execution process of a memory atomic operation instruction is described as follows:

[0117] Step 1: After the system is reset, the memory atomic operation module enters the idle state, and then enters step 2, that is, the req_arb state.

[0118] Step 2, req_arb state: Enable the arbiter to arbitrate and select pending memory atomic operation instructions sent by each computing core. If the arbitration result is arb_vld is valid (arbitration valid response), the target memory atomic operation instruction is selected for execution, and the state machine enters the send_rd state. If arb_vld is invalid, it remains in the req_arb state and arbitration selection is made at the next tick time point. The arbiter is only enabled in the req_arb state; memory atomic operation instructions not selected for execution by arbitration remain in a waiting state.

[0119] Step 3, send_rd state: Receive memory atomic operation instructions from three directions: 1) instructions newly arbitrated and selected from the req_arb state; 2) instructions sent from the wait_rd state that need to be re-executed; 3) instructions sent from the wait_wr state that need to be re-executed. In this state, the received memory atomic operation instructions are parsed and, based on the instruction content, a mutually exclusive read instruction is initiated, where araddr is the read / write address stored in rs. Arlock (read lock signal) is pulled high to indicate a mutually exclusive read. If arready (read lock ready signal) is pulled high, the process jumps to the wait_rd state; otherwise, the process remains in the send_rd state.

[0120] Step 4, wait_rd state: Wait for the read result (rdata) and read operation feedback (rresp). If rresp is exokey, indicating a successful read, the state machine enters the amo_exe state. If resp is okey, indicating a read failure, the state machine enters the send_rd state and re-executes the target memory atomic operation instruction. The state machine remains in the wait_rd state until rresp is received.

[0121] Step 5, amo_exe state: According to the function of the target memory atomic operation instruction, the value stored in rt in the instruction is calculated accordingly with rdata to obtain the instruction calculation result (amo_res), and then enter the send_wr state.

[0122] Step 6, send_wr state: Parse the target memory atomic operation instruction and, based on the instruction content, initiate a mutually exclusive write instruction. awaddr is the read / write address stored in rs in the instruction; awlock (write lock signal) must be high to indicate mutually exclusive write; wdata is amo_res calculated in step 5. If wready (write lock ready signal) is high, jump to the wait_wr state; otherwise, remain in the send_wr state.

[0123] Step 7: Wait for the return of the write operation response (bresp). If the bresp is exokey, indicating a successful write, the mutually exclusive write is complete. rdata is returned to the corresponding target compute core, and the state enters the req_arb state, enabling amo_arb for the next arbitration selection. If the bresp is okey, indicating a write failure, the mutually exclusive write fails, requiring the state to enter the send_rd state and re-execute the target memory atomic operation instruction. Until the bresp is received, the state machine remains in the wait_wr state.

[0124] To support the execution of atomic memory operation instructions, it is also necessary to add monitor logic to the on-chip network module. When receiving a mutually exclusive read instruction sent by the AXI bus, the on-chip network module will occupy a monitor to record arid (device identifier of the direct memory access module) and araddr, return rresp as exokey(1), and return rdata based on the data read at the address. If the record item of the monitor is full (rarely), rresp is returned as okey(0). After receiving a mutually exclusive write instruction sent by the AXI bus, the on-chip network module will check the write address awaddr and awid in the monitor. If they match, the mutually exclusive write is successful, bresp returns exokey, the instruction calculation result is written to the global memory, and the monitor clears the target data item; if there is no match, the mutually exclusive write fails, bresp returns okey, and the instruction calculation result is not written to the global memory.

[0125] Among them, the arlock or awlock signal selects mutually exclusive access (for AXI4, 0 is normal access and 1 is mutually exclusive access), and rresp and bresp indicate the success and failure of mutually exclusive access read or write (0—okey—normal access success or mutually exclusive access failure, 1—exokey—mutually exclusive access success, 2—SLVERR—slave error, 3—DECERR—address decoding error).

[0126] The above system can execute the method provided by any embodiment of the present disclosure, and has the corresponding functional modules and beneficial effects of the execution method.

[0127] According to an embodiment of the present disclosure, the present disclosure also provides a direct memory access module, a readable storage medium, and a computer program product.

[0128] Figure 5 A schematic block diagram of an example direct memory access module that can be used to implement an embodiment of the present disclosure is shown. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0129] like Figure 5As shown, the direct memory access module 500 includes a processor 501, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 502 or a computer program loaded from a storage unit 508 into a random access memory (RAM) 503. Various programs and data required for the operation of the direct memory access module 500 can also be stored in the RAM 503. The processor 501, the ROM 502, and the RAM 503 are connected to each other via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0130] Multiple components in the direct memory access module 500 are connected to the I / O interface 505, including: an input unit 506, such as a keyboard, a mouse, etc.; an output unit 507, such as various types of displays, speakers, etc.; a storage unit 508, such as a magnetic disk, an optical disk, etc.; and a communication unit 509, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 509 allows the direct memory access module 500 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0131] The processor 501 can be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 501 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The processor 501 performs the various methods and processes described above, such as the execution method of the memory atomic operation instruction. For example, in some embodiments, the execution method of the memory atomic operation instruction can be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 508. In some embodiments, part or all of the computer program can be loaded and / or installed on the direct memory access module 500 via the ROM 502 and / or the communication unit 509. When the computer program is loaded into the RAM 503 and executed by the processor 501, one or more steps of the execution method of the memory atomic operation instruction described above can be performed. Alternatively, in other embodiments, the processor 501 may be configured to execute the memory atomic operation instruction execution method in any other appropriate manner (for example, by means of firmware).

[0132] Various embodiments of the systems and techniques described above can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0133] The program code for implementing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0134] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0135] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0136] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0137] A computer system may include a client and a server. The client and server are typically remote from each other and typically interact via a communication network. This client-server relationship arises through computer programs running on the respective computers, creating a client-server relationship. The server may be a cloud server, also known as a cloud computing server or cloud host, a hosting product within the cloud computing service ecosystem that addresses the management difficulties and limited scalability of traditional physical hosting and VPS services. The server may also be a server in a distributed system or a server integrated with blockchain.

[0138] Artificial intelligence (AI) is the study of how computers can simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, and planning). It encompasses both hardware and software technologies. AI hardware technologies generally include sensors, specialized AI chips, cloud computing, distributed storage, and big data processing. AI software technologies primarily encompass computer vision, speech recognition, natural language processing, machine learning / deep learning, big data processing, and knowledge graphs.

[0139] Cloud computing refers to a technology system that provides network access to elastically scalable shared pools of physical or virtual resources. These resources can include servers, operating systems, networks, software, applications, and storage devices, and can be deployed and managed on-demand in a self-service manner. Cloud computing technology provides efficient and powerful data processing capabilities for the application of technologies such as artificial intelligence and blockchain, as well as for model training.

[0140] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions provided by this disclosure can be achieved. This is not limited herein.

[0141] The above specific embodiments do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure shall be included within the scope of protection of this disclosure.

Claims

1. A method for executing a memory atomic operation instruction, executed by a direct memory access module in a system on chip, comprising: Obtaining a target memory atomic operation instruction sent by a target computing core, wherein the read and write addresses in the target memory atomic operation instruction are addresses on a global memory; Sending a mutually exclusive read instruction for the read / write address via a target protocol bus to read data from the read / write address, wherein the target protocol bus has a mutually exclusive read / write control function; In response to the read data fed back by the target protocol bus, calculating an instruction calculation result matching the read data according to the target memory atomic operation instruction; Sending a mutually exclusive write instruction for the read / write address via the target protocol bus to write the instruction calculation result to the read / write address; In response to a write success response fed back by the target protocol bus, the instruction calculation result is fed back to the target computing core.

2. The method according to claim 1, wherein The obtaining of the target memory atomic operation instruction sent by the target computing core includes: Whenever a beat time point is reached, the pending memory atomic operation instructions of multiple computing cores in the target cluster structure are obtained, and arbitration selection is performed among the pending memory atomic operation instructions; If a memory atomic operation instruction is arbitrated, the arbitrated memory atomic operation instruction is obtained as the target memory atomic operation instruction; If no memory atomic operation instruction is arbitrated, the arbitration is continued at the next beat time point until the target memory atomic operation instruction is obtained.

3. The method according to claim 2, wherein: The performing arbitration selection in the memory atomic operation instruction to be processed includes: Obtain a target time slot that matches the current beat time point, and obtain a target computing core allocated to the target time slot; Determining whether the target computing core has a memory atomic operation instruction to be processed; If so, it is determined that a memory atomic operation instruction is arbitrated; otherwise, it is determined that no memory atomic operation instruction is arbitrated.

4. The method according to claim 1, wherein After sending the mutually exclusive read instruction for the read and write address through the target protocol bus, the method further includes: In response to a read failure response fed back by the target protocol bus, the mutually exclusive read instruction for the read / write address is resent through the target protocol bus until read data fed back by the target protocol bus is received.

5. The method according to claim 1, wherein After sending the mutually exclusive write instruction for the read and write address through the target protocol bus, the method further includes: In response to a write failure response fed back by the target protocol bus, returning to executing the operation of sending the mutually exclusive read instruction for the read / write address through the target protocol bus until a write success response fed back by the target protocol bus is received.

6. The method according to claim 5, wherein: The target protocol bus is an advanced extensible interface bus; The sending of a mutually exclusive read instruction for the read and write address through the target protocol bus includes: Sending a high-level read lock signal via the Advanced Extensible Interface bus; In response to a high-level read lock ready signal fed back by the advanced extensible interface bus, determining that the mutually exclusive read instruction is successfully sent; Sending a mutually exclusive write instruction for the read and write address through the target protocol bus includes: Sending a high-level write lock signal via the Advanced Extensible Interface bus; In response to a high-level write lock preparation signal fed back by the advanced extensible interface bus, it is determined that the mutually exclusive write instruction is successfully sent.

7. A device for executing a memory atomic operation instruction, configured on a direct memory access module in a system on chip, comprising: an instruction acquisition module configured to acquire a target memory atomic operation instruction sent by a target computing core, wherein the read and write addresses in the target memory atomic operation instruction are addresses on a global memory; a data reading module configured to send a mutually exclusive read instruction for the read / write address via a target protocol bus to read data from the read / write address, wherein the target protocol bus has a mutually exclusive read / write control function; a data calculation module configured to, in response to the read data fed back by the target protocol bus, calculate an instruction calculation result matching the read data according to the target memory atomic operation instruction; a data writing module configured to send a mutually exclusive write instruction for the read / write address via the target protocol bus to write the instruction calculation result to the read / write address; The data feedback module is configured to feed back the instruction calculation result to the target computing core in response to a write success response fed back by the target protocol bus.

8. The device according to claim 7, wherein The instruction acquisition module includes an arbitration selection unit and an arbitration processing unit, wherein: an arbitration selection unit configured to obtain pending memory atomic operation instructions of a plurality of computing cores in a target cluster structure and perform arbitration selection among the pending memory atomic operation instructions whenever a beat time point is reached; The arbitration processing unit is configured to obtain the arbitrated memory atomic operation instruction as the target memory atomic operation instruction if a memory atomic operation instruction is arbitrated; if no memory atomic operation instruction is arbitrated, wait for the next beat time point to continue arbitration until the target memory atomic operation instruction is obtained.

9. The device according to claim 8, wherein The arbitration selection unit includes a target computing core acquisition subunit and an arbitration result judgment subunit. a target computing core acquisition subunit, configured to determine whether the target computing core has a memory atomic operation instruction to be processed; an arbitration result determination subunit, configured to determine whether the target computing core has a memory atomic operation instruction to be processed; If so, determine to arbitrate a memory atomic operation instruction; Otherwise, it is determined that no memory atomic operation instruction has been arbitrated.

10. The apparatus according to claim 7 further comprises a mutually exclusive read instruction resending module, wherein the mutually exclusive read instruction resending module is configured to, in response to a read failure response fed back by the target protocol bus, resend the mutually exclusive read instruction for the read / write address through the target protocol bus until a read result fed back by the target protocol bus is received.

11. A direct memory access module, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 6.

12. A system on chip, comprising: A global memory and at least one cluster structure, wherein the at least one cluster structure establishes a communication connection with the global memory via an on-chip network module; Each cluster structure includes a direct memory access module and multiple computing cores. Each direct memory access module and global memory are connected to the on-chip network module through a target protocol bus. Each direct memory access module is used to execute the method according to any one of claims 1 to 6; an on-chip network module, configured to, in response to a mutually exclusive read instruction for a first read / write address sent by a first direct memory access module, perform a recording operation on the first direct memory access module and a data item of the first read / write address; if the recording is successful, obtain read data matching the first read / write address from the global memory, and feed the read data back to the first direct memory access module; as well as In response to a mutually exclusive write instruction for a second read-write address sent by a second direct memory access module, query whether a target data item matching the second direct memory access module and the second read-write address is stored; if so, write an instruction calculation result matching the mutually exclusive write instruction to the second read-write address in the global memory; clear the target data item, and feed back a write success response to the second direct memory access module.

13. The system on chip according to claim 12, wherein: The on-chip network module is further used for: After performing the data item recording operation on the first direct memory access module and the first read / write address, if the recording fails, a read failure response is fed back to the first direct memory access module.

14. The system on chip according to claim 12, wherein: The on-chip network module is further used for: After querying whether a target data item matching the second direct memory access module and the second read / write address is stored, if not, a write failure response is fed back to the second direct memory access module.

15. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instruction is used to enable a computer to execute the execution method of the memory atomic operation instruction according to any one of claims 1-6.

16. A computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements the steps of the method for executing the memory atomic operation instruction according to any one of claims 1 to 6.

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