Memory structure and memory layout

Abstract

The embodiment of the present application provides a memory structure and a memory layout, comprising: a memory array, and each memory array contains a plurality of memory cells; a read-write conversion circuit arranged between two adjacent memory arrays in a first direction, the read-write conversion circuit is arranged in a second direction and has an axis of symmetry in the second direction, and is used for writing external data into the memory cells or reading out data of the memory cells, the first direction and the second direction are perpendicular to each other; a sense amplifier circuit symmetrically arranged between the two adjacent memory arrays according to the axis of symmetry and coupled with the memory cells of the adjacent memory arrays, and used for sensing a voltage of the memory cell and outputting logic 1 or 0 corresponding to the voltage of the memory cell; the extending direction of the gate structure of a MOS transistor in the sense amplifier circuit is the same as the extending direction of the gate structure of a MOS transistor in the read-write conversion circuit; and the device characteristics of the corresponding MOS transistors in different sense amplifiers arranged between the memory arrays are balanced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor memory structure design, in particular to a memory structure and a memory layout. BACKGROUND

[0002] Dynamic random access memory (DRAM) completes data write operation of the memory by storing electric charge into the capacitor of the memory cell, and completes data read operation of the memory by reading the electric charge in the capacitor of the memory cell.

[0003] In the DRAM, the memory cell is connected to the bit line BL and the complementary bit line BLB, and in the process of performing the data read operation, the sense amplifier is used to read the voltage of the bit line BL and the voltage of the complementary bit line BLB, and amplify the voltage difference between the bit line BL and the complementary bit line BLB.

[0004] However, the applicant finds that due to the inconsistent device environment around the corresponding MOS tube in different sense amplifiers, the corresponding MOS tube in different sense amplifiers has different device characteristics, and the device characteristics of the corresponding MOS tube in different sense amplifiers need to be matched with each other, that is, the different device characteristics of the corresponding MOS tube in different sense amplifiers will affect the amplification capability of the whole sense amplifier, and further reduce the performance of the DRAM. SUMMARY

[0005] The embodiments of the present application provide a memory structure and a memory layout to balance the device characteristics of the corresponding MOS tube in different sense amplifiers arranged between the memory arrays, and further improve the stability of the DRAM.

[0006] To solve the above technical problems, the embodiments of the present application provide a memory structure, comprising: a memory array, and each memory array contains a plurality of memory cells; a read-write conversion circuit arranged between two adjacent memory arrays in a first direction, the read-write conversion circuit is arranged in a second direction, and has a symmetry axis in the second direction, and is used to write external data into the memory cell or read out the data of the memory cell, the first direction and the second direction are perpendicular to each other; a sense amplification circuit symmetrically arranged between the two adjacent memory arrays according to the symmetry axis, and coupled to the memory cells of the adjacent memory columns, used to sense the voltage of the memory cell and output logic 1 or 0 corresponding to the voltage of the memory cell; wherein the extension direction of the gate structure of the MOS tube in the sense amplification circuit is the same as the extension direction of the gate structure of the MOS tube in the read-write conversion circuit.

[0007] Compared with the related art, the gate structure of the read-write conversion circuit in the application extends in the first direction, and the read-write conversion circuit has an axis of symmetry in the second direction; the sensing amplifier circuit is symmetrically arranged based on the axis of symmetry of the read-write conversion circuit, that is, the MOS transistors in different sensing amplifier circuits are symmetrically arranged based on the axis of symmetry of the read-write conversion circuit, so as to ensure that the environments of the corresponding MOS transistors in different sensing amplifier circuits arranged on both sides of the read-write conversion circuit are consistent; in addition, by arranging the extension direction of the gate structure of the MOS transistor in the read-write conversion circuit to be consistent with the extension direction of the gate structure of the MOS transistor in the sensing amplifier circuit, the distance between the gate structure of the corresponding MOS transistor in different sensing amplifier circuits located on both sides of the read-write conversion circuit and the gate structure of the MOS transistor in the read-write conversion circuit is further ensured to be equal, so as to balance the device characteristics of the corresponding MOS transistors in different sensing amplifiers, and thus improve the stability of the DRAM.

[0008] In addition, the MOS transistor structure in the read-write conversion circuit comprises: an active region arranged in a well region of a semiconductor substrate and extending in the second direction; gate structures arranged on the active region at intervals and extending in the first direction; and a conductive contact structure arranged on the active region in the gap between adjacent two gate structures, the top surface of the conductive contact structure being higher than the top surface of the gate structure.

[0009] In addition, the intervals between the adjacent gate structures arranged at intervals are the same.

[0010] In addition, the MOS transistor structure in the read-write conversion circuit further comprises: a gate extension structure arranged at the edge of the gate structure on the active region and extending in the second direction, the gate extension structure and the gate structure forming a ring-shaped gate structure; and in the first direction, the distance between the gate structure of the MOS transistor in the sensing amplifier circuit adjacent to the gate extension structure and the gate extension structure is equal. By forming the gate extension structure at the edge of the gate structure, the gate extension structure and the gate structure jointly form a ring-shaped gate structure, and the gate extension structure extends in the second direction, that is, the gate extension structure is arranged in parallel with the adjacent sensing amplifier circuit, so as to ensure that the distance between the gate structure of the MOS transistor in the sensing amplifier circuit at any position adjacent to the gate extension structure is equal.

[0011] In addition, in the first direction, the distance between the active regions of the MOS transistors in the sensing amplifier circuits adjacent to the read-write conversion circuit is equal. By arranging the distance between the active regions of the MOS transistors in the sensing amplifier circuits adjacent to the MOS transistor structure in the read-write conversion circuit to be equal, the environments of the MOS transistors in the sensing amplifier circuits arranged on both sides of the read-write conversion circuit are further ensured to be consistent.

[0012] In addition, the material of the gate extension structure is consistent with the material of the gate structure, and the height of the top surface of the gate extension structure is consistent with the height of the top surface of the gate structure, and the thickness of the gate extension structure is consistent with the thickness of the gate structure. By ensuring that the material, thickness and height of the gate extension structure and the gate structure are consistent, the gate extension structure and the gate structure can be formed in the same process step.

[0013] In addition, the conductive contact structure extends in the first direction, and the conductive contact structure is not in contact with the annular gate structure.

[0014] In addition, the read-write conversion circuit further comprises: an isolation structure located on the inner wall of the ring of the annular gate structure; and the conductive contact structure fills the remaining gap of the annular gate structure.

[0015] In addition, the sensing amplification circuit comprises: a first NMOS region circuit coupled to the storage cells in the adjacent storage array; a second NMOS region circuit coupled to the storage cells in the adjacent storage array; a first PMOS region circuit coupled to the storage cells in the adjacent storage array; and a second PMOS region circuit coupled to the storage cells in the adjacent storage array.

[0016] In addition, the memory structure further comprises: an equalization circuit symmetrically arranged between the two adjacent storage arrays according to the symmetry axis, and electrically connected to the sensing amplification circuit, for equalizing the voltage of the sensing amplification circuit coupled to the storage cell line; and an input / output circuit symmetrically arranged between the two adjacent storage arrays according to the symmetry axis, and electrically connected to the storage cells of the adjacent storage array, for selecting the storage cells in the storage array.

[0017] The embodiments of the present application also provide a memory layout, comprising: a storage array layout; a read-write conversion circuit layout arranged between the two adjacent storage array layouts in a first direction, the read-write conversion circuit layout being arranged in a second direction and having a symmetry axis in the second direction, the first direction being perpendicular to the second direction; and a sensing amplification circuit layout symmetrically arranged between the two adjacent storage array layouts based on the symmetry axis; wherein the extension direction of the gate pattern in the sensing amplification circuit layout is the same as the extension direction of the gate pattern in the read-write conversion circuit layout.

[0018] In addition, the read-write conversion circuit layout comprises: an active pattern arranged in the well region of the semiconductor substrate and extending in the second direction; a gate pattern arranged on the active pattern at intervals and extending in the first direction; and a conductive contact pattern arranged on the active pattern in the gap between the two adjacent gate patterns.

[0019] In addition, the intervals between the adjacent and spaced gate patterns are the same.

[0020] In addition, the read-write conversion circuit layout further comprises: a gate extension pattern, arranged at the edge of the gate pattern on the active pattern and extending in the second direction, the gate extension pattern and the gate pattern forming a closed loop; and in the first direction, the distance between the gate pattern in the sensing amplifier circuit layout adjacent to the gate extension pattern and the gate extension pattern is equal.

[0021] In addition, in the first direction, the distance between the active pattern in the sensing amplifier circuit layout adjacent to the active pattern and the active pattern is equal.

[0022] In addition, the conductive contact pattern extends in the first direction, and the conductive contact pattern is not in contact with the closed loop.

[0023] In addition, the sensing amplifier circuit layout comprises: a first NMOS region layout, a second NMOS region layout, a first PMOS region layout, and a second PMOS region layout.

[0024] In addition, the memory layout further comprises: an equalization circuit layout, symmetrically arranged between two adjacent memory array layouts based on the axis of symmetry; and an input / output circuit layout, symmetrically arranged between two adjacent memory array layouts based on the axis of symmetry.

[0025] Compared with the related art, in the present application, the gate pattern of the read-write conversion circuit layout extends in the first direction, and the read-write conversion circuit layout has an axis of symmetry in the second direction; the sensing amplifier circuit layout is symmetrically arranged based on the axis of symmetry of the read-write conversion circuit layout, that is, the MOS tubes in different sensing amplifier circuit layouts are symmetrically arranged based on the axis of symmetry of the read-write conversion circuit layout, so as to ensure that the environments of the corresponding MOS tubes in different sensing amplifier circuit layouts arranged on both sides of the read-write conversion circuit layout are consistent; in addition, by arranging the extension direction of the gate pattern of the MOS tube in the read-write conversion circuit layout to be consistent with the extension direction of the gate pattern of the MOS tube in the sensing amplifier circuit layout, the distance between the gate pattern of the corresponding MOS tube in different sensing amplifier circuit layouts located on both sides of the read-write conversion circuit layout and the gate pattern of the MOS tube in the read-write conversion circuit layout is further ensured to be equal, so as to balance the device characteristics of the corresponding MOS tubes in different sensing amplifiers, and further improve the stability of the DRAM. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 The structure schematic diagram of the memory provided in the present application is shown;

[0027] Figure 2 The structure schematic diagram of the memory structure provided in an embodiment of the present application is shown;

[0028] Figures 3-5 The structure schematic diagram of the read-write conversion circuit provided in an embodiment of the present application is shown;

[0029] Figure 6 This is a schematic diagram of the layout of a memory structure provided in an embodiment of this application;

[0030] Figure 7 A schematic diagram of the layout of a read / write conversion circuit provided in an embodiment of this application;

[0031] Figure 8 and Figure 9 This is a schematic diagram of the memory layout provided in another embodiment of this application. Detailed Implementation

[0032] refer to Figure 1 In the memory structure, each memory array 101 contains multiple memory cells 111. Each memory cell 111 is a 1T1C (1 transistor 1 capacitor) structure consisting of a transistor and a capacitor. The read / write conversion circuit 200, the sensing amplifier circuit 300, the equalization circuit 400, and the input / output circuit 500 are arranged between adjacent memory arrays.

[0033] In this unit transistor, one terminal of the source and drain is connected to the unit capacitor, and the other terminal is connected to the bit line BL / complementary bit line BLB. The word line WL is connected to the gate of the unit transistor and is used to select and turn on the gate of the corresponding unit transistor, so that the unit capacitor is connected to the bit line BL / complementary bit line BLB, thereby realizing the writing of the electrical signal in the bit line BL / complementary bit line BLB into the unit capacitor, or realizing the reading of the electrical signal in the unit capacitor out to the bit line BL / complementary bit line BLB.

[0034] The equalization circuit 400 connects bit line BL and complementary bit line BLB to equalize the voltage between bit line BL and complementary bit line BLB during the pre-charging phase.

[0035] The input / output circuit 500 includes an input / output transistor. One terminal of the input / output transistor's source / drain is connected to the bit line BL / complementary bit line BLB, and the other terminal is connected to the local data line Local I / O. The gate is used to receive a selection signal and, according to the selection signal, selects to turn on the bit line BL / complementary bit line BLB corresponding to the selection signal, so that the bit line BL / complementary bit line BLB is connected to the local data line Local I / O, thereby realizing data transfer between the bit line BL / complementary bit line BLB and the local data line Local I / O.

[0036] The local data line Local I / O is connected to the global data line Global I / O through the read-write conversion circuit 200, so as to realize transmission of external data or data in the local sense amplifier (placed in the read-write conversion circuit 200) to the local data line Local I / O, or output of data in the local data line Local I / O to the global data line Global I / O.

[0037] The sense amplifier circuit 300 is connected between the bit line BL and the complementary bit line BLB, and when an electrical signal in the cell capacitor is read out to the bit line BL / complementary bit line BLB, the voltage of the bit line BL / complementary bit line BLB is increased or decreased by a voltage change amount ΔV from the pre-charge voltage due to charge sharing of the cell capacitor and the bit line BL / complementary bit line BLB, and the sense amplifier circuit 300 is used to read and amplify the voltage change amount ΔV between the bit line BL and the complementary bit line BLB in response to the first control signal PCS and the second control signal NCS.

[0038] In the process of the sense amplifier circuit 300 performing the amplification operation, due to inconsistent device environments around the corresponding MOS tubes in different sense amplifiers, the corresponding MOS tubes in different sense amplifiers have different device characteristics, and the device characteristics of the corresponding MOS tubes in different sense amplifiers need to be matched with each other, that is, the different device characteristics of the corresponding MOS tubes in different sense amplifiers will affect the amplification capability of the whole sense amplifier, and further reduce the DRAM performance.

[0039] To solve the above problems, an embodiment of the present application provides a memory structure, comprising: a memory array, and each memory array contains a plurality of memory cells; a read-write conversion circuit, arranged between two adjacent memory arrays in a first direction, the read-write conversion circuit is arranged in a second direction, and has a symmetry axis in the second direction, and is used for writing external data into the memory cells or reading out data of the memory cells, the first direction and the second direction are perpendicular to each other; a sense amplifier circuit, symmetrically arranged between the two adjacent memory arrays according to the symmetry axis, and coupled to the memory cells of the adjacent memory arrays, and used for sensing the voltage of the memory cells and outputting logic 1 or 0 corresponding to the voltage of the memory cells; wherein the extension direction of the gate structure of the MOS tube in the sense amplifier circuit is the same as the extension direction of the gate structure of the MOS tube in the read-write conversion circuit.

[0040] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present application, many technical details are proposed in order to make the readers better understand the present application. However, the technical solutions claimed by the present application can be implemented even if there are no such technical details and various changes and modifications based on the following embodiments. The division of the following embodiments is for the convenience of description, and should not constitute any limitation on the specific implementation modes of the present application. The embodiments can be combined with each other and mutually referenced without contradiction.

[0041] Figure 2 A structural schematic diagram of the memory structure provided by the present embodiment is shown in the following figure, Figures 3-5 A structural schematic diagram of the read-write conversion circuit provided by the present embodiment is shown in the following figure, Figure 6 A layout mode schematic diagram of the memory structure provided by the present embodiment is shown in the following figure, Figure 7 A layout mode schematic diagram of the read-write conversion circuit provided by the present embodiment is shown in the following figure. The memory structure provided by the present embodiment will be described in further detail below with reference to the drawings, and specifically as follows:

[0042] Reference Figure 2 , the memory structure comprises:

[0043] The memory array 101, and each memory array 101 comprises a plurality of memory cells 111 (refer to Figure 1 );

[0044] The read-write conversion circuit 200 is arranged between the two adjacent memory arrays 101 in the first direction X, and the read-write conversion circuit is arranged in the second direction Y and has a symmetry axis AA1 in the second direction Y, for writing external data into the memory cells 111 (refer to Figure 1 ) or reading out the data of the memory cells 111, wherein the first direction X and the second direction Y are perpendicular to each other.

[0045] It should be noted that, in the present embodiment, the "external data" includes but is not limited to the global data line Global I / O (refer to Figure 1 ) and the data in the local sense amplifier (refer to Figure 1 , which is placed in the read-write conversion circuit 200).

[0046] The sense amplifier circuit 300 is symmetrically arranged between the two adjacent memory arrays 101 according to the symmetry axis AA1, and is coupled to the memory cells 111 (refer to Figure 1 ) of the adjacent memory arrays 101, for sensing the voltage of the memory cells 111 (refer to Figure 1 ) and outputting a corresponding voltage of the memory cells 111 (refer to Figure 1logic 1 or logic 0 of the read / write conversion circuit 200; wherein the extending direction of the gate structure of the MOS transistor in the sensing amplification circuit 300 is the same as the extending direction of the gate structure of the MOS transistor in the read / write conversion circuit 200; the sensing amplification circuit 300 is arranged based on the symmetry axis AA1 of the read / write conversion circuit 200, i.e. the corresponding MOS transistors in different sensing amplifiers are arranged based on the symmetry axis AA1 of the read / write conversion circuit 200, so as to ensure that the environments of the corresponding MOS transistors in the sensing amplification circuit 300 arranged on both sides of the read / write conversion circuit 200 are consistent, thereby ensuring the consistency of the characteristics of different sensing amplifiers.

[0047] It should be noted that in the gap between the adjacent memory arrays 101, the structures of the read / write conversion circuit 200 and the sensing amplification circuit 300 are arranged in the second direction Y, i.e. in the second direction Y, a plurality of read / write conversion circuits 200 and sensing amplification circuits 300 are arranged.

[0048] The embodiment takes the MOS transistor in the read / write conversion circuit 200 as an N-type MOS transistor for specific description, and does not constitute a limitation to the embodiment, and in other embodiments, the MOS transistor in the read / write conversion circuit can be a P-type MOS transistor.

[0049] Specifically, referring to Figure 3 , the MOS transistor structure in the read / write conversion circuit 200 includes:

[0050] The active region 202 is arranged in the well region 201 of the semiconductor substrate and extends in the second direction Y.

[0051] Specifically, in the first direction X, the distance between the active region of the MOS transistor in the sensing amplification circuit 300 adjacent to the MOS transistor structure in the read / write conversion circuit 200 and the active region 202 is equal. Specifically, the distance between the active region 202 and the active regions of the sensing amplification circuits 300 on both sides is d1, and the distance between the active region 202 and the active regions of the sensing amplification circuits 300 on both sides at any edge position is equal.

[0052] The gate structure 203 is arranged on the active region 202 in a spaced manner and extends in the first direction X.

[0053] Specifically, the distance between the gate structure 203 and the gate structures of the sensing amplification circuits 300 on both sides is d0, and in the first direction X,

[0054] The distance between the upper edge of the gate structure 203 and the lower edge of the gate structure in the upper sensing amplifier circuit 300 is equal, and the distance between the lower edge of the gate structure 203 and the upper edge of the gate structure in the lower sensing amplifier circuit 300 is equal. The interval s1 between the adjacent gate structures 203 is the same, and the gate structures 203 are arranged on the active area 202 at the same interval to ensure that the environments of the sensing amplifier circuits on both sides of the read-write conversion circuit are consistent. It should be noted that in this embodiment, the "consistent environment" refers to the same features such as the size, distance, and arrangement of the semiconductor structure composed of the same material.

[0055] The gate structure 203 of the read-write conversion circuit 200 extends in the first direction, and the read-write conversion circuit 200 has an axis of symmetry AA1 in the second direction Y. By arranging the extension direction of the gate structure 203 of the MOS transistor in the read-write conversion circuit 200 to be consistent with the extension direction of the gate structure of the MOS transistor in the sensing amplifier circuit 300, the distance between the gate structure of the corresponding MOS transistor in the sensing amplifier circuit 300 and the gate structure 203 of the MOS transistor in the read-write conversion circuit 200 is further ensured to be equal, thereby balancing the device characteristics of the sensing amplifiers on both sides of the read-write conversion circuit 200, and further improving the yield of the DRAM.

[0056] The conductive contact structure 205 is arranged on the active area 202 between the adjacent two gate structures 203, the height of the top surface of the conductive contact structure 205 is higher than the height of the top surface of the gate structure 203, the active areas 202 at both ends of the gate structure 203 are respectively used as the source and drain of the MOS transistor, one end of the conductive contact structure 205 is electrically connected to the active areas 202 on both sides of the gate structure 203, and the other end is used to guide the signal of the active area 202 out.

[0057] Further, with reference to Figure 4 and Figure 5 In this embodiment, the MOS transistor structure in the read-write conversion circuit 200 further includes:

[0058] The gate extension structure 204 is arranged at the edge of the gate structure 203 on the active region 202 and extends in the second direction Y, and the gate extension structure 204 and the gate structure 203 form a ring-shaped gate structure 206, and the distance d0 between the gate structure of the MOS transistor in the sense amplification circuit 300 adjacent to the gate extension structure 204 in the first direction X is equal to the distance between the gate extension structure 204; by forming the gate extension structure 204 at the edge of the gate structure 203, the gate extension structure 204 and the gate structure 203 form a ring-shaped gate structure 206, and the gate extension structure 204 extends in the second direction Y, that is, the gate extension structure 204 is arranged in parallel with the adjacent sense amplification circuit 300, so as to ensure that the distance between the gate structure of the MOS transistor in the sense amplification circuit 300 at any position and the gate extension structure 204 is equal.

[0059] In the embodiment, the material of the gate extension structure 204 is consistent with the material of the gate structure 203, and the height of the top surface of the gate extension structure 204 is consistent with the height of the top surface of the gate structure 203, and the thickness of the gate extension structure 204 is consistent with the thickness of the gate structure 203, so that the gate extension structure 204 and the gate structure 203 can be formed in the same process step by ensuring that the material, the thickness and the height of the gate extension structure 204 and the gate structure 203 are consistent.

[0060] In the embodiment, the conductive contact structure 205 is arranged in insulation with the gate extension structure 204.

[0061] In one example, referring to Figure 4 , the conductive contact structure 205 extends in the first direction X, and the conductive contact structure 205 is not in contact with the ring-shaped gate structure 206, so that the conductive contact structure 205 and the gate extension structure 204 are insulated from each other by being arranged separately.

[0062] In another example, referring to Figure 5 , the read-write conversion circuit 200 further comprises an isolation structure 207 located on the inner wall of the ring of the ring-shaped gate structure 206, and the conductive contact structure 205 fills the remaining gap of the ring-shaped gate structure 206, so that the conductive contact structure 205 and the gate extension structure 204 are insulated from each other by the isolation structure 207.

[0063] Referring to Figure 6 , in the embodiment, the sense amplification circuit 300 comprises:

[0064] The first NMOS region 310 circuit is coupled to the memory cell 111 in the adjacent memory array 101 (referring to Figure 1), the second NMOS region 320 circuit coupled to the memory cell 111 in the adjacent memory array 101, the first PMOS region 301 circuit coupled to the memory cell 111 in the adjacent memory array 101, the second PMOS region 302 circuit coupled to the memory cell 111 in the adjacent memory array 101; wherein the first NMOS region 310 circuit in the sense amplifier circuit 300 on both sides of the read-write conversion circuit 200 is symmetrically arranged based on the symmetry axis AA1, the second NMOS region 320 circuit in the sense amplifier circuit 300 on both sides of the read-write conversion circuit 200 is symmetrically arranged based on the symmetry axis AA1, the first PMOS region 301 circuit in the sense amplifier circuit 300 on both sides of the read-write conversion circuit 200 is symmetrically arranged based on the symmetry axis AA1, and the second PMOS region 302 circuit in the sense amplifier circuit 300 on both sides of the read-write conversion circuit 200 is symmetrically arranged based on the symmetry axis AA1.

[0065] The sense amplifier circuit 300 further comprises: an equalization circuit 400 symmetrically arranged between the two adjacent memory arrays 101 based on the symmetry axis AA1 and electrically connected to the sense amplifier circuit 300, for equalizing the voltage of the line coupled to the memory cell 111 by the sense amplifier circuit 300 (refer to Figure 1 ) The input / output circuit 500 is symmetrically arranged between the two adjacent memory arrays 101 based on the symmetry axis AA1 and electrically connected to the memory cell 111 of the adjacent memory array 101, for selecting the memory cell 111 in the memory array 101, transmitting the data on the local data line Local I / O to the bit line BL when the memory performs a write operation, and then writing the data into the memory cell 111; transmitting the data on the bit line BL to the local data line Local I / O when the memory performs a read operation, and then reading out the memory.

[0066] For the arrangement of the sense amplifier circuit 300, the equalization circuit 400, the input / output circuit 500 and the read-write conversion circuit 200, the read-write conversion circuit 200 is arranged at the middle part of the gap between the two adjacent memory arrays 101, and the read-write conversion circuit 200 has a symmetry axis AA1, the first NMOS region 310 circuit, the second NMOS region 320 circuit, the first PMOS region 301 circuit, the second PMOS region 302 circuit, the equalization circuit 400 and the input / output circuit 500 in the sense amplifier circuit on both sides of the read-write conversion circuit 200 are symmetrically arranged on both sides of the read-write conversion circuit 200 based on the symmetry axis AA1.

[0067] Specifically, in one arrangement, referring to Figure 6As shown in P1 and P2, the first NMOS region 310 circuit, the second NMOS region 320 circuit, the first PMOS region 301 circuit, and the second PMOS region 302 circuit are alternately arranged on one side of the read / write conversion circuit 200. The equalization circuit 400 and the input / output circuit 500 can be located at any position between the first NMOS region 310 circuit, the second NMOS region 320 circuit, the first PMOS region 301 circuit, and the second PMOS region 302 circuit. The equalization circuit 400 located on the same side serves as the equalization circuit 400 of the sensing amplifier circuit 300 (see reference). Figure 1 ).

[0068] In one layout, refer to Figure 6 The arrangement shown in P3 and P4 indicates that the first NMOS region 310 circuit and the second NMOS region 320 circuit are located between the first PMOS region 301 circuit and the second PMOS region 302 circuit, or the first PMOS region 301 circuit and the second PMOS region 302 circuit are located between the first NMOS region 310 circuit and the second NMOS region 320 circuit. The equalization circuit 400 and the input / output circuit 500 can be located at any position between the first NMOS region 310 circuit, the second NMOS region 320 circuit, the first PMOS region 301 circuit, and the second PMOS region 302 circuit. The equalization circuit 400 located on the same side serves as an equalization circuit 400 of a sensing amplifier circuit 300 (see reference). Figure 1 ).

[0069] It should be noted that, in Figure 6 In the arrangement shown, only the arrangement diagram of the sensing amplifier circuit 300 on one side of the read / write conversion circuit 200 is given. The sensing amplifier circuit on the other side of the read / write conversion circuit 200 is arranged symmetrically with the arrangement of the sensing amplifier circuit 300 shown based on the axis of symmetry AA1.

[0070] Additionally, refer to Figure 7 Read / write conversion circuit 200 (reference) Figure 2 It includes a first read / write conversion circuit 2001 and a second read / write conversion circuit 2002, which are located close to the storage array 101 and are arranged symmetrically.

[0071] Specifically, the first read / write conversion circuit 2001 is disposed between the sensing amplification circuit 300 and the storage array 101, and the second read / write conversion circuit 2002 is disposed between the sensing amplification circuit 300 and the storage array 101. The first read / write conversion circuit 2001 and the second read / write conversion circuit 2002 are symmetrically arranged based on the axis of symmetry AA1, that is, the read / write conversion circuit composed of the first read / write conversion circuit 2001 and the second read / write conversion circuit 2002 (see reference). Figure 2 It has an axis of symmetry AA1.

[0072] It should be noted that, in Figure 7 In the given example, the first read / write conversion circuit 2001 and the second read / write conversion circuit 2002 are disposed between the sensing amplification circuit 300 and the storage array 101. In other embodiments, the first read / write conversion circuit and the second read / write conversion circuit may be disposed in the sensing amplification circuit 300 and symmetrically arranged based on the axis of symmetry AA1.

[0073] Compared with related technologies, the gate structure of the read / write conversion circuit in this application extends in a first direction, and the read / write conversion circuit has a symmetry axis in a second direction; the sensing amplifier circuit is symmetrically arranged based on the symmetry axis of the read / write conversion circuit, that is, the MOS transistors in different sensing amplifier circuits are symmetrically arranged based on the symmetry axis of the read / write conversion circuit, thereby ensuring that the environment of the corresponding MOS transistors in different sensing amplifier circuits on both sides of the read / write conversion circuit is consistent; in addition, by setting the extension direction of the gate structure of the MOS transistor in the read / write conversion circuit to be consistent with the extension direction of the gate structure of the MOS transistor in the sensing amplifier circuit, it is further ensured that the distance between the gate structure of the corresponding MOS transistor in different sensing amplifier circuits on both sides of the read / write conversion circuit and the gate structure of the MOS transistor in the read / write conversion circuit is equal, thereby balancing the device characteristics of the corresponding MOS transistors in different sensing amplifiers, and thus improving the stability of DRAM.

[0074] Another embodiment of this application provides a memory layout, including: a memory array layout; a read / write conversion circuit layout disposed between two adjacent memory array layouts in a first direction, the read / write conversion circuit layouts being arranged in a second direction and having an axis of symmetry in the second direction, the first direction and the second direction being perpendicular; and a sensing amplifier circuit layout symmetrically disposed between two adjacent memory array layouts based on the axis of symmetry; wherein the extension direction of the gate pattern in the sensing amplifier circuit layout is the same as the extension direction of the gate pattern in the read / write conversion circuit layout.

[0075] Figure 8 and Figure 9 This is a schematic diagram of the memory layout provided in this embodiment. The memory layout provided in this embodiment will be further described in detail below with reference to the accompanying drawings:

[0076] refer toFigure 8 and Figure 9 , the memory layout comprises:

[0077] a storage array layout 601 extending in a second direction Y, the storage array layout 601 being configured to form the storage array 101 (refer to Figure 1 ).

[0078] a read-write conversion circuit layout 700 disposed between two adjacent storage array layouts 601 in a first direction X, the read-write conversion circuit layout 700 being arranged in the second direction Y and having an axis of symmetry AA1 in the second direction Y, the first direction X being perpendicular to the second direction Y, the read-write conversion circuit layout 700 being configured to form the read-write conversion circuit 200 (refer to Figure 1 ).

[0079] a sense amplification circuit layout 800 symmetrically disposed between the two adjacent storage array layouts 601 based on the axis of symmetry AA1, wherein an extension direction of a gate pattern 802 in the sense amplification circuit layout 800 is the same as an extension direction of a gate pattern 702 in the read-write conversion circuit layout 700.

[0080] It should be noted that, Figure 8 and Figure 9 the structures of the equalization circuit layout and the input / output circuit layout are not embodied, and based on the above description of the embodiments, it should be understood by those skilled in the art that in the present embodiment, the memory layout further comprises: an equalization circuit layout symmetrically disposed between two adjacent storage array layouts 601 based on the axis of symmetry AA1, configured to form the equalization circuit 400 (refer to Figure 1 ), and an input / output circuit layout symmetrically disposed between two adjacent storage array layouts 601 based on the axis of symmetry AA1, configured to form the input / output circuit 500 (refer to Figure 1 ).

[0081] With reference to Figure 8 , the read-write conversion circuit layout 700 comprises:

[0082] an active pattern 701 disposed in a well region 201 (refer to Figure 3 ) of the semiconductor substrate and extending in the second direction Y, configured to form an active region 202 (refer to Figure 3 ).

[0083] Specifically, in the first direction X, the active pattern 801 of the MOS transistor in the sense amplifier circuit layout 800 adjacent to the MOS transistor structure in the read-write conversion circuit layout 700 is equal to the distance of the active pattern 701. Specifically, the distance of the active pattern 701 to the active pattern 801 in the sense amplifier circuit layout 800 on both sides is d1, and the distance of the active pattern 701 to the active pattern 801 in the sense amplifier circuit layout 800 at any edge position is equal.

[0084] The gate pattern 702 is arranged on the active pattern 701 with a spacing and extends in the first direction X, and is used to form the gate structure 203 (refer to Figure 3 ).

[0085] Specifically, the distance of the gate pattern 702 to the gate pattern 802 in the sense amplifier circuit layout 800 on both sides is d0, and

[0086] The distance of the upper edge position of the gate pattern 702 to the lower edge position of the gate pattern 802 in the sense amplifier circuit layout 800 on both sides is equal, and the distance of the lower edge position of the gate pattern 702 to the upper edge position of the gate pattern 802 in the sense amplifier circuit layout 800 on both sides is equal, and the spacing s1 between the adjacent gate patterns 702 is the same. The conductive contact pattern 703 is arranged on the active pattern 701 between the adjacent two gate patterns 702, and is used to form the conductive contact structure 205 (refer to Figure 3 ).

[0087] Further, referring to Figure 9 , in the embodiment, the MOS transistor structure in the read-write conversion circuit layout 700 further comprises:

[0088] The gate extension pattern 704 is arranged on the edge of the gate pattern 702 on the active pattern 701 and extends in the second direction Y, and is used to form the gate extension structure 204 (refer to Figure 4 and Figure 5 ), and the gate extension pattern 704 and the gate pattern 702 form a closed loop 705, and the distance of the gate pattern of the MOS transistor in the sense amplifier circuit layout 800 adjacent to the gate extension pattern 704 in the first direction X is equal to the distance of the gate extension pattern 704.

[0089] In the embodiment, the material of the gate extension pattern 704 is consistent with the material of the gate pattern 702, and by ensuring that the material of the gate extension pattern 704 and the material of the gate pattern 702 are consistent, the gate extension pattern 704 and the gate pattern 702 can be formed in the same process step.

[0090] In the embodiment, the conductive contact pattern 703 and the gate extension pattern 704 are further insulated from each other.

[0091] In one example, referring to Figure 9 , the conductive contact pattern 703 extends in the first direction X, and the conductive contact pattern 703 is not in contact with the closed ring 705, and the conductive contact pattern 703 and the closed ring 705 are separately arranged, so that the conductive contact structure 205 (referring to Figure 3 ) formed by the conductive contact pattern 703 and the gate expansion structure 204 (referring to Figure 4 and Figure 5 ) formed by the gate expansion pattern 704 are insulated from each other.

[0092] In another example, the read-write conversion circuit pattern further includes an isolation pattern located on the inner wall of the ring of the closed ring, and the conductive contact pattern fills the remaining gap of the closed ring, so that the conductive contact pattern 703 and the gate expansion pattern 704 are insulated from each other by the isolation pattern, to form the read-write conversion circuit 200 (referring to Figure 5 ) as shown in Figure 1 .

[0093] In addition, in the present embodiment, the sense amplifier circuit layout 800 includes a first NMOS region layout, a second NMOS region layout, a first PMOS region layout, and a second PMOS region layout; wherein the first NMOS region layout and the second NMOS region layout are arranged between two adjacent storage array layouts 601 according to the symmetry axis AA1, and the first PMOS region layout and the second PMOS region layout are arranged between two adjacent storage array layouts 601 according to the symmetry axis AA1; wherein the first NMOS region layout is used to form the first NMOS region 310 circuit (referring to Figure 6 ), the second NMOS region layout is used to form the second NMOS region 320 circuit (referring to Figure 6 ), the first PMOS region layout is used to form the first PMOS region 301 circuit (referring to Figure 6 ), and the second PMOS region layout is used to form the second PMOS region 302 circuit (referring to Figure 6 ), so as to realize the formation of the memory structure as shown in Figure 6 by the corresponding layout arrangement of the memory.

[0094] Compared with the related art, the gate pattern of the read-write conversion circuit layout extends in the first direction, and the read-write conversion circuit layout has an axis of symmetry in the second direction; the sense amplifier circuit layout is symmetrically arranged based on the axis of symmetry of the read-write conversion circuit layout, that is, the MOS tubes in different sense amplifier circuit layouts are symmetrically arranged based on the axis of symmetry of the read-write conversion circuit layout, so as to ensure that the environments of the corresponding MOS tubes in different sense amplifier circuit layouts arranged on both sides of the read-write conversion circuit layout are consistent; in addition, by arranging the extension direction of the gate pattern of the MOS tube in the read-write conversion circuit layout to be consistent with the extension direction of the gate pattern of the MOS tube in the sense amplifier circuit layout, the distance between the gate pattern of the corresponding MOS tube in different sense amplifier circuit layouts located on both sides of the read-write conversion circuit layout and the gate pattern of the MOS tube in the read-write conversion circuit layout is further ensured to be equal, so as to balance the device characteristics of the corresponding MOS tubes in different sense amplifiers, and thus improve the stability of the DRAM.

[0095] Since the above embodiments correspond to the present embodiment, the present embodiment can be implemented in cooperation with the above embodiments. The related technical details mentioned in the above embodiments are still valid in the present embodiment, and the technical effects achieved in the above embodiments can also be achieved in the present embodiment. In order to reduce repetition, they will not be described here. Accordingly, the related technical details mentioned in the present embodiment can also be applied in the above embodiments.

[0096] Those skilled in the art can understand that the above embodiments are specific embodiments for implementing the present application, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present application.

Claims

1. A memory structure, comprising: The application relates to a memory array, and each memory array comprises a plurality of memory cells. A read-write conversion circuit is arranged between two adjacent memory arrays in a first direction, the read-write conversion circuit is arranged in a second direction, and has an axis of symmetry in the second direction, and is used for writing external data into the memory cells or reading out data of the memory cells, the first direction and the second direction are perpendicular to each other. A sense amplifier circuit is symmetrically arranged between two adjacent memory arrays according to the axis of symmetry, and is coupled with the memory cells of the adjacent memory arrays, and is used for sensing the voltage of the memory cells and outputting logic 1 or 0 corresponding to the voltage of the memory cells. The extending direction of the gate structure of the MOS tube in the sense amplifier circuit is the same as the extending direction of the gate structure of the MOS tube in the read-write conversion circuit. The sense amplifier circuit comprises: A first NMOS region circuit is coupled with the memory cells in the adjacent memory arrays, and is symmetrically arranged on both sides of the read-write conversion circuit based on the axis of symmetry. A second NMOS region circuit is coupled with the memory cells in the adjacent memory arrays, and is symmetrically arranged on both sides of the read-write conversion circuit based on the axis of symmetry. A first PMOS region circuit is coupled with the memory cells in the adjacent memory arrays, and is symmetrically arranged on both sides of the read-write conversion circuit based on the axis of symmetry. A second PMOS region circuit is coupled with the memory cells in the adjacent memory arrays, and is symmetrically arranged on both sides of the read-write conversion circuit based on the axis of symmetry. The MOS tube structure in the read-write conversion circuit comprises:

2. The memory structure of claim 1, wherein, An active region is arranged in a well region of a semiconductor substrate, and extends in the second direction. The gate structure is arranged on the active region in a spaced mode, and extends in the first direction. A conductive contact structure is arranged on the active region in the gap between two adjacent gate structures, and the height of the top surface of the conductive contact structure is higher than the height of the top surface of the gate structure. The interval between the adjacent gate structures is the same.

3. The memory structure of claim 2, wherein, The MOS tube structure in the read-write conversion circuit further comprises:

4. The memory structure of claim 2, wherein, A gate extension structure is arranged on the edge of the gate structure on the active region, and extends in the second direction, and the gate extension structure and the gate structure form a ring-shaped gate structure. In the first direction, the distance between the gate structure of the MOS tube in the sense amplifier circuit adjacent to the gate extension structure and the gate extension structure is equal. In the first direction, the distance between the active region of the MOS tube in the sense amplifier circuit adjacent to the read-write conversion circuit and the active region is equal.

5. The memory structure of claim 2 or 4, wherein, The material of the gate extension structure is consistent with the material of the gate structure, the height of the top surface of the gate extension structure is consistent with the height of the top surface of the gate structure, and the thickness of the gate extension structure is consistent with the thickness of the gate structure.

6. The memory structure of claim 4, wherein, The conductive contact structure extends in the first direction, and the conductive contact structure is not in contact with the ring-shaped gate structure.

7. The memory structure of claim 4, wherein, The read-write conversion circuit further comprises:

8. The memory structure of claim 4, wherein, ​ An isolation structure is located on the inner sidewall of the ring-shaped gate structure; The conductive contact structure fills the remaining gap of the ring-shaped gate structure.

9. The memory structure of claim 1, wherein, Further comprising: An equalization circuit is symmetrically arranged between two adjacent storage arrays according to the symmetry axis, and is electrically connected to the sense amplifier circuit, for equalizing the voltage coupled by the sense amplifier circuit to the storage cell line; An input / output circuit is symmetrically arranged between two adjacent storage arrays according to the symmetry axis, and is electrically connected to the storage cells of adjacent storage arrays, for selecting the storage cells in the storage array.

10. A memory layout, comprising: Comprise: A storage array layout; A read-write conversion circuit layout is arranged between two adjacent storage array layouts in a first direction, the read-write conversion circuit layout is arranged in a second direction, and has a symmetry axis in the second direction, and the first direction and the second direction are perpendicular; A sense amplifier circuit layout is symmetrically arranged between two adjacent storage array layouts based on the symmetry axis; The extension direction of the gate pattern in the sense amplifier circuit layout is the same as the extension direction of the gate pattern in the read-write conversion circuit layout; The sense amplifier circuit layout comprises: a first NMOS region layout, a second NMOS region layout, a first PMOS region layout and a second PMOS region layout; wherein the first NMOS region layout is symmetrically arranged on both sides of the read-write conversion circuit layout based on the symmetry axis, the second NMOS region layout is symmetrically arranged on both sides of the read-write conversion circuit layout based on the symmetry axis, the first PMOS region layout is symmetrically arranged on both sides of the read-write conversion circuit layout based on the symmetry axis, and the second PMOS region layout is symmetrically arranged on both sides of the read-write conversion circuit layout based on the symmetry axis.

11. The memory layout of claim 10, wherein, The read-write conversion circuit layout comprises: An active pattern is arranged in the well region of the semiconductor substrate and extends in the second direction; The gate pattern is arranged on the active pattern with a spacing and extends in the first direction; A conductive contact pattern is arranged on the active pattern between the gaps of two adjacent gate patterns.

12. The memory layout of claim 11, wherein, The spacing between the adjacent gate patterns is the same.

13. The memory layout of claim 11, wherein, The read-write conversion circuit layout further comprises: A gate extension pattern is arranged at the edge of the gate pattern on the active pattern and extends in the second direction, and the gate extension pattern and the gate pattern form a closed ring; In the first direction, the distance between the gate pattern in the sense amplifier circuit layout adjacent to the gate extension pattern and the gate extension pattern is equal.

14. The memory layout according to claim 11 or 13, wherein, In the first direction, the distance between the active pattern in the sense amplifier circuit layout adjacent to the active pattern and the active pattern is equal.

15. The memory layout of claim 13, wherein, The conductive contact pattern extends in the first direction, and the conductive contact pattern is not in contact with the closed ring.

16. The memory floorplan of claim 10, wherein, Further comprising: An equalization circuit layout is symmetrically arranged between two adjacent storage array layouts based on the symmetry axis; An input / output circuit layout is symmetrically arranged between two adjacent storage array layouts based on the symmetry axis.

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