Array substrate, method for preparing same, display panel and display device

Abstract

The present disclosure relates to the field of display technologies, and discloses an array substrate, a method for manufacturing the same, a display panel, and a display device; the array substrate includes a plurality of first transistors, a plurality of second transistors, and a plurality of storage capacitors; the first transistor includes a first channel portion, and the first channel portion includes a first semiconductor region and a first conductor region that are connected to each other; the second transistor includes a second channel portion, and the second channel portion includes a second semiconductor region and a second conductor region that are connected to each other; the storage capacitor includes a first electrode and a second electrode, the first electrode is provided on the same layer and made of the same material as the first conductor region, and the second electrode is provided on the same layer and made of the same material as the second conductor region. The structure and manufacturing process of the array substrate are relatively simple.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to an array substrate, a method for manufacturing the array substrate, a display panel including the array substrate, and a display device including the display panel. Background Art

[0002] AMOLED (Active-matrix organic light-emitting diode) display panels have advantages such as mature manufacturing processes, high luminous efficiency, low power consumption, high color saturation, and wide viewing angles.

[0003] However, currently, the structures and manufacturing processes of the array substrates of AMOLED display panels are relatively complex.

[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] The purpose of the present disclosure is to overcome the deficiencies of the relatively complex structures and manufacturing processes of the above-mentioned prior art, and to provide an array substrate with a relatively simple structure and manufacturing process, a method for manufacturing the same, a display panel including the array substrate, and a display device including the display panel.

[0006] According to one aspect of the present disclosure, there is provided an array substrate, comprising:

[0007] A plurality of first transistors, each of the first transistors including a first channel portion, and the first channel portion including a first semiconductor region and a first conductor region connected to each other;

[0008] A plurality of second transistors, each of the second transistors including a second channel portion, and the second channel portion including a second semiconductor region and a second conductor region connected to each other;

[0009] A plurality of storage capacitors, each of the storage capacitors including a first electrode and a second electrode, the first electrode being provided on the same layer and made of the same material as the first conductor region, and the second electrode being provided on the same layer and made of the same material as the second conductor region.

[0010] In an exemplary embodiment of the present disclosure, each of the first transistors further includes a first gate, a first source, and a first drain, each of the second transistors further includes a second gate, a second source, and a second drain, and the second gate, the second source, the second drain, the first source, and the first drain are provided on the same layer and made of the same material.

[0011] In an exemplary embodiment of the present disclosure, the array substrate further includes:

[0012] The light-shielding layer is provided on the same layer and made of the same material as the first gate.

[0013] In an exemplary embodiment of the present disclosure, the array substrate includes:

[0014] A substrate;

[0015] A first active layer provided on one side of the substrate, the first active layer including a first connection portion, a second connection portion, the first channel portion, and the first electrode which are arranged at intervals;

[0016] A first insulating layer provided on the side of the first active layer facing away from the substrate;

[0017] A first gate layer provided on the side of the first insulating layer facing away from the substrate, the first gate layer including the first gate and the light-shielding layer which are arranged at intervals, and a positive projection of the first semiconductor region on the substrate is located within a positive projection of the first gate on the substrate;

[0018] A second insulating layer provided on the side of the first gate layer facing away from the substrate.

[0019] In an exemplary embodiment of the present disclosure, the array substrate further includes:

[0020] A second active layer provided on the side of the second insulating layer facing away from the substrate, the second active layer including the second channel portion and the second electrode which are arranged at intervals, a positive projection of the second channel portion on the substrate is located within a positive projection of the light-shielding layer on the substrate, and a positive projection of the second electrode on the substrate at least partially overlaps with a positive projection of the first electrode on the substrate;

[0021] A third insulating layer provided on the side of the second active layer facing away from the substrate;

[0022] A conductor layer provided on the side of the third insulating layer facing away from the substrate, the conductor layer including the second gate, the second source, the second drain, the first source, the first drain, a first connection line, a second connection line, a third connection line, a power line, a data line, a scanning line, a first source lead, and a second source lead;

[0023] Wherein, the positive projection of the second semiconductor region on the substrate is located within the positive projection of the second gate on the substrate. The second source electrode and the second drain electrode are correspondingly connected to two of the second conductor regions, and the second source electrode lead connects the second source electrode and the first connection portion. The first drain electrode and the first source electrode are correspondingly connected to two of the first conductor regions, and the first source electrode lead connects the first source electrode and the second connection portion. The first connection line connects the first gate and the first connection portion, the second connection line connects the first connection portion and the first electrode, the third connection line connects the second connection portion and the second electrode, the power supply line is connected to the first source electrode, the data line is connected to the first drain electrode, and the scan line is connected to the second gate.

[0024] In an exemplary embodiment of the present disclosure, the third insulating layer is disposed on a side of the second channel portion facing away from the substrate. The positive projection of the third insulating layer on the substrate covers and is larger than the positive projection of the second semiconductor region on the substrate, and the positive projection of the third insulating layer on the substrate overlaps with the positive projection of the second conductor region on the substrate to form a first overlapping portion. The second source electrode and the second drain electrode are disposed on opposite sides of the third insulating layer, and a first gap is provided between them and the third insulating layer. The positive projection of the second source electrode on the substrate overlaps with the positive projection of the second conductor region on the substrate to form a second overlapping portion. The positive projection of the second drain electrode on the substrate overlaps with the positive projection of the second conductor region on the substrate to form a third overlapping portion.

[0025] In an exemplary embodiment of the present disclosure, the width of the first overlapping portion is greater than or equal to 0.5 micrometers and less than or equal to 1 micrometer, the width of the second overlapping portion is greater than or equal to 0.5 micrometers and less than or equal to 1 micrometer, and the width of the third overlapping portion is greater than or equal to 0.5 micrometers and less than or equal to 1 micrometer.

[0026] In an exemplary embodiment of the present disclosure, the first connection portion and the second connection portion extend along a first direction. The first channel portion and the first electrode are arranged along the first direction, and the first channel portion and the first electrode are located between the first connection portion and the second connection portion. The first direction is parallel to the substrate.

[0027] In an exemplary embodiment of the present disclosure, the first connection line, the second connection line, and the third connection line extend along a second direction. The first source electrode lead and the second source electrode lead extend along the second direction. The second direction is parallel to the substrate, and the second direction intersects the first direction.

[0028] In an exemplary embodiment of the present disclosure, the orthographic projection of the second electrode on the substrate is located within the orthographic projection of the first electrode on the substrate.

[0029] In an exemplary embodiment of the present disclosure, the material of the first semiconductor region is low-temperature polysilicon, and the material of the second semiconductor region is an oxide active layer.

[0030] According to another aspect of the present disclosure, according to still another aspect of the present disclosure, a method for manufacturing an array substrate includes:

[0031] Forming a plurality of first transistors, the first transistors including first channel portions, the first channel portions including a first semiconductor region and a first conductor region connected to each other, and forming a first electrode while forming the first conductor region;

[0032] Forming a plurality of second transistors, the second transistors including second channel portions, the second channel portions including a second semiconductor region and a second conductor region connected to each other, and forming a second electrode while forming the second conductor region, the second electrode and the first electrode forming a storage capacitor.

[0033] In an exemplary embodiment of the present disclosure, the first transistors further include first gates, first sources, and first drains, and the second transistors further include second gates, second sources, and second drains, and forming the second sources, the second drains, the first sources, and the first drains while forming the second gates.

[0034] In an exemplary embodiment of the present disclosure, the array substrate further includes a light-shielding layer, and forming the first gates while forming the light-shielding layer.

[0035] In an exemplary embodiment of the present disclosure, forming the first transistors includes:

[0036] Providing a substrate;

[0037] Forming a first active pattern layer on one side of the substrate;

[0038] Forming a first insulating layer on a side of the first active pattern layer facing away from the substrate;

[0039] Forming a first gate layer on a side of the first insulating layer facing away from the substrate, the first gate layer including the first gates and the light-shielding layer disposed at intervals, and the orthographic projection of the first semiconductor region on the substrate being located within the orthographic projection of the first gates on the substrate;

[0040] Using the first gate layer as a mask, a part of the first active pattern layer is conductorized to form a first connection portion, a second connection portion, the first conductor region, and the first electrode;

[0041] A second insulating layer is formed on a side of the first gate layer facing away from the substrate.

[0042] In an exemplary embodiment of the present disclosure, forming the first transistor and the second transistor includes:

[0043] A second active pattern layer is formed on a side of the second insulating layer facing away from the substrate.

[0044] A third insulating layer is formed on a side of the second active pattern layer facing away from the substrate.

[0045] A conductor layer is formed on a side of the third insulating layer facing away from the substrate. The conductor layer includes the second gate, the second source, the second drain, the first source, the first drain, a first connection line, a second connection line, a third connection line, a power supply line, a data line, a scanning line, a first source lead, and a second source lead.

[0046] Using the second gate as a mask, a part of the second active pattern layer is conductorized to form the second conductor region and the second electrode.

[0047] According to another aspect of the present disclosure, a display panel is provided, including: the array substrate according to any one of the above.

[0048] According to still another aspect of the present disclosure, a display device is provided, including: the display panel according to the above.

[0049] In the array substrate and its manufacturing method of the present disclosure, the first electrode and the first conductor region are provided on the same layer and made of the same material, that is, the first electrode and the first conductor region are formed through the same patterning process; the second electrode and the second conductor region are provided on the same layer and made of the same material, that is, the second electrode and the second conductor region are formed through the same patterning process; thereby, the structure of at least two insulating layers can be reduced, and at least two patterning process steps can be reduced, further making the structure and manufacturing process of the array substrate relatively simple; and when the array substrate is used for a flexible display panel, the bending stress is small, which is beneficial to the bending of the flexible display panel.

[0050] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. Description of the Drawings

[0051] The accompanying drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other accompanying drawings based on these drawings without creative efforts.

[0052] Figure 1 It is a schematic structural diagram of an exemplary embodiment of the array substrate of the present disclosure.

[0053] Figure 2 It is Figure 1 a top view schematic diagram of.

[0054] Figure 3 It is a schematic structural diagram of forming a first active pattern layer on a substrate substrate.

[0055] Figure 4 It is Figure 3 a top view schematic diagram of.

[0056] Figure 5 It is for forming Figure 3 a schematic structural diagram of a first insulating layer and a first gate layer on the basis of.

[0057] Figure 6 It is Figure 5 a top view schematic diagram of.

[0058] Figure 7 It is for forming Figure 5 a schematic structural diagram of a second insulating layer and a second active pattern layer on the basis of.

[0059] Figure 8 It is Figure 7 a top view schematic diagram of.

[0060] Figure 9 It is for forming Figure 7 a schematic structural diagram of a third insulating layer on the basis of.

[0061] Figure 10 It is Figure 9 a top view schematic diagram of.

[0062] Figure 11 It is for forming Figure 9 a schematic structural diagram of a conductor layer on the basis of.

[0063] Figure 12 It is Figure 11 a top view schematic diagram of.

[0064] Figure 13 It is a schematic flow chart of an exemplary embodiment of the method for preparing the array substrate of the present disclosure.

[0065] Description of reference numerals:

[0066] 1. Substrate;

[0067] 2a, first active pattern layer; 21a, first connection pattern; 22a, second connection pattern; 23a, first channel pattern; 24, first electrode pattern;

[0068] 2. First active layer; 21. First connecting portion; 22. Second connecting portion; 23. First channel portion; 231. First semiconductor region; 232. First conductor region; 24. First electrode;

[0069] 3. First insulating layer; 31. First via hole;

[0070] 4. First gate layer; 41. First gate; 42. Light shielding layer;

[0071] 5. Second insulating layer; 51. Second via hole;

[0072] 6a, second active pattern layer; 61a, second channel pattern; 62a, second electrode pattern;

[0073] 6. Second active layer; 61. Second channel portion; 611. Second semiconductor region; 612. Second conductor region; 62. Second electrode;

[0074] 7. The third insulation layer;

[0075] 8. Conductor layer; 81. Second gate; 811. Scan line; 82. Second source; 821. Second source lead; 83. Second drain; 831. Data line; 84. First source; 841. First source lead; 85. First drain; 851. Power line; 86. First connecting line; 87. Second connecting line; 88. Third connecting line; 89. First gap;

[0076] 91, first overlapping portion; 92, second overlapping portion; 93, third overlapping portion; 94, fourth overlapping portion;

[0077] T1, first transistor; T2, second transistor; C, storage capacitor;

[0078] X, first direction; Y, second direction. DETAILED DESCRIPTION

[0079] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their detailed description will be omitted. Further, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0080] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the directions of the examples described in the drawings. It can be understood that if the device of the icon is turned upside down, the component described as "upper" will become the component described as "lower". When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.

[0081] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first", "second", "third", etc. are used only as labels and are not a limitation on the quantity of their objects.

[0082] In this application, unless otherwise clearly defined and limited, the term "connected" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or integrated; it can be directly connected, or indirectly connected through an intermediate medium. "And / or" is merely a description of the associated relationship of the associated objects and indicates that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after.

[0083] The example embodiments of the present disclosure provide an array substrate. Refer to Figures 1 - 12As shown, the array substrate may include a plurality of first transistors T1, a plurality of second transistors T2, and a plurality of storage capacitors C; the first transistor T1 may include a first channel portion 23, and the first channel portion 23 may include a first semiconductor region 231 and a first conductor region 232 connected to each other; the second transistor T2 may include a second channel portion 61, and the second channel portion 61 may include a second semiconductor region 611 and a second conductor region 612 connected to each other; the storage capacitor C may include a first electrode 24 and a second electrode 62, the first electrode 24 is provided on the same layer and made of the same material as the first conductor region 232, and the second electrode 62 is provided on the same layer and made of the same material as the second conductor region 612.

[0084] For the array substrate and its manufacturing method of the present disclosure, the first electrode 24 is provided on the same layer and made of the same material as the first conductor region 232, that is, the first electrode 24 and the first conductor region 232 are formed by the same patterning process; the second electrode 62 is provided on the same layer and made of the same material as the second conductor region 612, that is, the second electrode 62 and the second conductor region 612 are formed by the same patterning process; thereby, the structure of at least two insulating layers can be reduced, and at least two patterning process steps can be reduced, and further, the structure and manufacturing process of the array substrate are relatively simple; and when the array substrate is used for a flexible display panel, the bending stress is small, which is beneficial to the bending of the flexible display panel.

[0085] It should be noted that both the first direction X and the second direction Y are parallel to the substrate 1, and the first direction X intersects the second direction Y. For example, the first direction X is perpendicular to the second direction Y. Moreover, Figure 2 、 Figure 4 、 Figure 6 、 Figure 8 、 Figure 10 and Figure 12 are all top views. To avoid the figure being too complex, therefore, the first insulating layer 3 and the second insulating layer 5 are not shown. In addition, Figure 1 is formed by cutting along A-A in Figure 2 , Figure 3 is formed by cutting along B-B in Figure 4 , Figure 5 is formed by cutting along C-C in Figure 6 , Figure 7 is formed by cutting along D-D in Figure 8 , Figure 9 is formed by cutting along E-E in Figure 10 , Figure 11 is formed by cutting along F-F in Figure 12 .

[0086] The material of the first semiconductor region 231 is low-temperature polysilicon, that is, the first transistor T1 is a low-temperature polysilicon (LTPS) thin-film transistor. The material of the second semiconductor region 611 is an oxide active layer. For example, it can be one of indium gallium zinc oxide, indium tin zinc oxide, or indium gallium zinc tin oxide, or a combination of two or three of them; that is, the second transistor T2 is an oxide (Oxide) thin-film transistor. The oxide thin-film transistor has a relatively low leakage current, while the low-temperature polysilicon thin-film transistor has a relatively high mobility. Combining the advantages of both can save 5%-15% of the power for the display panel, thereby making the power consumption of the display panel lower. However, due to the different structures and process flows of the oxide thin-film transistor and the low-temperature polysilicon thin-film transistor, the low-temperature poly-oxide (LTPO) array substrate with these two types of thin-film transistors has more film layers, a complex process, and a larger number of photomasks used.

[0087] In the present exemplary embodiment, referring to Figure 1 As shown, the array substrate may include a substrate 1. The material of the substrate 1 may include inorganic materials. For example, the inorganic material may be glass, quartz, or metal, etc. The material of the substrate 1 may also include organic materials. For example, the organic material may be resin materials such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. The substrate 1 may be formed by multiple material layers. For example, the substrate 1 may include multiple base layers, and the material of the base layer may be any of the above materials. Of course, the substrate 1 may also be provided as a single layer, which may be any of the above materials.

[0088] Referring to Figure 5 and Figure 6 As shown, a first active layer 2 is provided on one side of the array substrate. The first active layer 2 may include a first connection portion 21, a second connection portion 22, a first channel portion 23, and a first electrode 24 arranged at intervals. Both the first connection portion 21 and the second connection portion 22 are arranged as strips extending along the first direction X, that is, the first connection portion 21 and the second connection portion 22 are arranged substantially parallel to each other, and there is an interval space between the first connection portion 21 and the second connection portion 22. The first channel portion 23 and the first electrode 24 are arranged along the first direction X, and the first channel portion 23 and the first electrode 24 are located between the first connection portion 21 and the second connection portion 22, that is, the first channel portion 23 and the first electrode 24 are located in the interval space between the first connection portion 21 and the second connection portion 22. Moreover, the area of the first electrode 24 is larger than the area of the first channel portion 23. The first channel portion 23 may include a first semiconductor region 231 and a first conductor region 232. The first conductor region 232 is provided in two, and the two first conductor regions 232 are arranged on opposite sides of the first semiconductor region 231 in the first direction X.

[0089] The distance between the first channel portion 23 and the first connection portion 21 is K1, and K1 is greater than or equal to 3 micrometers; the distance between the first channel portion 23 and the second connection portion 22 is K2, and K2 is greater than or equal to 3 micrometers; the distance between the first electrode 24 and the first connection portion 21 is K3, and K3 is greater than or equal to 3 micrometers; the distance between the first electrode 24 and the second connection portion 22 is K4, and K4 is greater than or equal to 3 micrometers. Such settings can avoid short circuits caused by connections between adjacent two. Of course, when the accuracy of the exposure machine is higher and the process conditions permit, the values of K1, K2, K3, and K4 can be smaller. Moreover, K1 can be equal to K2, so that the first channel portion 23 is centered, and the coupling effect between the first channel portion 23 and the first connection portion 21 and the second connection portion 22 is minimized; K3 can be equal to K4, so that the first electrode 24 is centered, and the coupling effect between the first electrode 24 and the first connection portion 21 and the second connection portion 22 is minimized. The distance between the first channel portion 23 and the first electrode 24 is K5, and K5 is greater than or equal to 5 micrometers. Such settings can avoid the coupling effect between the first channel portion 23 and the first electrode 24. The thickness of the first active layer 2 is greater than or equal to 300 Å and less than or equal to 1000 Å.

[0090] Refer to Figure 1 、 Figure 9 and Figure 10 as shown, Figure 10 The dashed square frames in [[ ]] represent the first vias 31 and the second vias 51. A first insulating layer 3 is provided on the side of the first active layer 2 away from the substrate 1. Eight first vias 31 are provided on the first insulating layer 3. Two of the first vias 31 are respectively connected to two first conductor regions 232 in a one-to-one correspondence, so that at least part of the first conductor region 232 is exposed. Another first via 31 is connected to the first electrode 24, so that at least part of the first electrode 24 is exposed. Three first vias 31 are connected to the first connection portion 21, so that three isolated parts of the first connection portion 21 are exposed; two first vias 31 are connected to the second connection portion 22, so that two isolated parts of the second connection portion 22 are exposed.

[0091] The material of the first insulating layer 3 can be silicon oxide, silicon oxynitride, or a combination of both, and its thickness is greater than or equal to 1000 Å and less than or equal to 3000 Å. The diameter or side length of the first via 31 is greater than or equal to 4 μm and less than or equal to 6 μm.

[0092] Refer to Figure 1 、 Figure 5 and Figure 6As shown, a first gate layer 4 is disposed on a side of the first insulating layer 3 away from the substrate 1. The first gate layer 4 may include a first gate 41 and a light-shielding layer 42 disposed at intervals. The material of the first gate layer 4 may be an alloy of one or more of molybdenum, aluminum, copper, and titanium, and its thickness is greater than or equal to 2000 Å and less than or equal to 6000 Å.

[0093] The distance between the first gate 41 and the first connection portion 21 is equal to the distance between the first gate 41 and the second connection portion 22, so that the first gate 41 is centered, and the first gate 41 is also centered with respect to the first channel portion 23. That is, in the first direction X, the distance between the first gate 41 and one edge of the first channel portion 23 is equal to the distance between the first gate 41 and the other edge of the first channel portion 23. Try to avoid the coupling effect between the first gate 41 and the first connection portion 21 and the second connection portion 22.

[0094] The distance between the light-shielding layer 42 and the first connection portion 21 is equal to the distance between the light-shielding layer 42 and the second connection portion 22, so that the light-shielding layer 42 is centered. The distance between the first gate 41 and the light-shielding layer 42 is basically equal to the distance between the first gate 41 and the first electrode 24. The position of the light-shielding layer 42 determines the position of the second transistor T2. With such a setting, the interference between the second transistor T2 and the first transistor T1 is minimized.

[0095] The orthographic projection of the first semiconductor region 231 on the substrate 1 is located within the orthographic projection of the first gate 41 on the substrate 1. For example, the orthographic projection of the first gate 41 on the substrate 1 covers and is larger than the orthographic projection of the first semiconductor region 231 on the substrate 1, or the edge lines of the orthographic projection of the first gate 41 on the substrate 1 coincide with the edge lines of the orthographic projection of the first semiconductor region 231 on the substrate 1. Applying an appropriate voltage to the first gate 41 can cause the first semiconductor region 231 to form a conductor to conduct two first conductor regions 232 on opposite sides of the first semiconductor region 231. Therefore, the area of the first gate 41 is large enough to ensure the conduction of the first semiconductor region 231.

[0096] The light-shielding layer 42 is located on a side of the first gate 41 away from the first electrode 24. The light incident from the substrate 1 into the second semiconductor region 611 will generate photo-generated carriers in the second semiconductor region 611, which will have a huge impact on the characteristics of the thin-film transistor and ultimately affect the display quality of the display panel. The light-shielding layer 42 can block the light incident from the substrate 1, thereby avoiding affecting the characteristics of the thin-film transistor and the display quality of the display panel.

[0097] Refer to Figure 1 、 Figure 9 and Figure 10As shown, a second insulating layer 5 is provided on the side of the first gate layer 4 facing away from the substrate 1. Nine second vias 51 are provided on the second insulating layer 5. Two of the second vias 51 are correspondingly connected to the first vias 31 one by one and finally connected to two first conductor regions 232, so that at least part of the first conductor region 232 is exposed. Another first via 31 is connected to the first via 31 and finally connected to the first electrode 24, so that at least part of the first electrode 24 is exposed. There is also a second via 51 connected to the first gate 41, so that at least part of the first gate 41 is exposed; among them, there are also three second vias 51 correspondingly connected to the first vias 31 one by one and finally connected to the first connection part 21, so that three isolated parts of the first connection part 21 are exposed; among them, there are also two second vias 51 correspondingly connected to the first vias 31 one by one and finally connected to the second connection part 22, so that two isolated parts of the second connection part 22 are exposed.

[0098] The material of the second insulating layer 5 can be silicon oxide, silicon oxynitride, silicon nitride or a combination of two or three of them, and its thickness is greater than or equal to 1000 Å and less than or equal to 3000 Å. The diameter or side length of the second via 51 is greater than or equal to 4 μm and less than or equal to 6 μm.

[0099] Refer to Figure 1 and Figure 2 As shown, a second active layer 6 is provided on the side of the second insulating layer 5 facing away from the substrate 1. The second active layer 6 may include a second channel portion 61 and a second electrode 62 arranged at intervals. The thickness of the second active layer 6 is greater than or equal to 100 Å and less than or equal to 1000 Å. The width of the second channel portion 61 is greater than or equal to 6 μm and less than or equal to 10 μm, and the length is greater than or equal to 20 μm and less than or equal to 30 μm. The width of the second electrode 62 is greater than or equal to 25 μm and less than or equal to 40 μm.

[0100] The second channel portion 61 is centered relative to the light-shielding layer 42, that is, in the first direction X, the distance between the second channel portion 61 and one edge of the light-shielding layer 42 is equal to the distance between the second channel portion 61 and the other edge of the light-shielding layer 42; in the second direction Y, the distance between the second channel portion 61 and one edge of the light-shielding layer 42 is equal to the distance between the second channel portion 61 and the other edge of the light-shielding layer 42. So that the light-shielding layer 42 can achieve a good light-shielding effect on the second channel portion 61.

[0101] In the second direction Y, the second electrode 62 is centered relative to the first electrode 24, that is, in the second direction Y, the distance between the second electrode 62 and one edge of the first electrode 24 is equal to the distance between the second electrode 62 and the other edge of the first electrode 24. In the first direction X, since a contact position between the first electrode 24 and the second connection wire 87 needs to be reserved, the second electrode 62 is eccentrically arranged relative to the first electrode 24. For example, in the first direction X, the distance between the second electrode 62 and one edge of the first electrode 24 is greater than the distance between the second electrode 62 and the other edge of the first electrode 24.

[0102] The orthographic projection of the second channel portion 61 on the substrate 1 is located within the orthographic projection of the light-shielding layer 42 on the substrate 1. For example, the orthographic projection of the light-shielding layer 42 on the substrate 1 covers and is larger than the orthographic projection of the second channel portion 61 on the substrate 1, or the edge lines of the orthographic projection of the second channel portion 61 on the substrate 1 coincide with the edge lines of the orthographic projection of the light-shielding layer 42 on the substrate 1, so that the light-shielding layer 42 can achieve a good light-shielding effect on the second channel portion 61, avoiding light from hitting the second channel portion 61 and affecting the performance of the second transistor T2.

[0103] The orthographic projection of the second electrode 62 on the substrate 1 is located within the orthographic projection of the first electrode 24 on the substrate 1; for example, the edge lines of the orthographic projection of the second electrode 62 on the substrate 1 coincide with the edge lines of the orthographic projection of the first electrode 24 on the substrate 1; or, the orthographic projection of the first electrode 24 on the substrate 1 covers and is larger than the orthographic projection of the second electrode 62 on the substrate 1. In the present exemplary embodiment, since the first electrode 24 is disposed below the second electrode 62 and the first electrode 24 needs to leave a certain space for arranging connection vias, the area of the second electrode 62 is smaller than the area of the first electrode 24; the larger the overlapping area between the first electrode 24 and the second electrode 62, the larger the capacitance of the formed capacitor, ensuring the effect of storing electrical energy in the storage capacitor C.

[0104] Referring to Figure 1 、 Figure 9 、 Figure 10 and Figure 11 As shown in, a third insulating layer 7 is disposed on the side of the second active layer 6 away from the substrate 1. The material of the third insulating layer 7 can be silicon oxide, silicon oxynitride or a combination of both; its thickness is greater than or equal to 1000 Å and less than or equal to 3000 Å.

[0105] Specifically, the third insulating layer 7 is disposed on a side of the second channel portion 61 away from the substrate 1; moreover, a positive projection of the third insulating layer 7 on the substrate 1 covers and is larger than a positive projection of the second semiconductor region 611 on the substrate 1, such that a positive projection of the third insulating layer 7 on the substrate 1 overlaps a positive projection of the second conductor region 612 on the substrate 1 to form a first overlapping portion 91, and a width of the first overlapping portion 91 is greater than or equal to 0.5 micrometers and less than or equal to 1 micrometer. For example, the width of the first overlapping portion 91 may be 0.65 micrometers, 0.7 micrometers, 0.78 micrometers, 0.83 micrometers, 0.9 micrometers, 0.95 micrometers, and so on.

[0106] Referring Figure 1 , Figure 2 , Figure 11 and Figure 12 As shown in, a conductor layer 8 is disposed on a side of the third insulating layer 7 and the second active layer 6 away from the substrate 1. The conductor layer 8 may include a second gate 81, a second source 82, a second drain 83, a first source 84, a first drain 85, a first connection line 86, a second connection line 87, and a third connection line 88 that are spaced apart. The conductor layer 8 may further include a second source lead 821 and a first source lead 841. The material of the conductor layer 8 may be an alloy of one or more of molybdenum, aluminum, copper, and titanium, and its thickness is greater than or equal to 2000 Å and less than or equal to 6000 Å.

[0107] The first source 84 is disposed in a first via 31 on the first insulating layer 3 and a second via 51 on the second insulating layer 5. The first drain 85 is disposed in a first via 31 on the first insulating layer 3 and a second via 51 on the second insulating layer 5.

[0108] It should be noted that the so-called "spaced apart" means that there is a spaced space between two parts and they are not connected as a whole. For example, A and B are spaced apart means that there is a spaced space between A and B, and A and B are not connected as a whole; A, B, and C are spaced apart means that there are spaced spaces between A and B, B and C, and A and C, and A, B, and C are not connected to each other.

[0109] Specifically, the second gate 81 is disposed on the side of the third insulating layer 7 away from the substrate 1, and the second gate 81 can be insulated from the second active layer 6 through the third insulating layer 7. Moreover, the orthographic projection of the second semiconductor region 611 on the substrate 1 is located within the orthographic projection of the second gate 81 on the substrate 1. For example, the edge line of the orthographic projection of the second semiconductor region 611 on the substrate 1 coincides with the edge line of the orthographic projection of the second gate 81 on the substrate 1, or the orthographic projection of the second gate 81 on the substrate 1 covers and is larger than the orthographic projection of the second semiconductor region 611 on the substrate 1. Applying an appropriate voltage to the second gate 81 can cause the second semiconductor region 611 to form a conductor to conduct two second conductor regions 612 on opposite sides of the second semiconductor region 611. Therefore, the area of the second gate 81 is large enough to ensure the conduction of the second semiconductor region 611.

[0110] The second source 82 and the second drain 83 are correspondingly connected to the two second conductor regions 612. A part of the second source 82 is disposed on the side of one second conductor region 612 away from the substrate 1, so that the second source 82 is connected to one second conductor region 612. A part of the second drain 83 is disposed on the side of the other second conductor region 612 away from the substrate 1, so that the second drain 83 is connected to one second conductor region 612. Moreover, the second source 82 is connected to one end of the second source lead 821. The second source lead 821 extends along the second direction Y, and the other end is connected to the first connection portion 21 through the first via 31 on the first insulating layer 3 and the second via 51 on the second insulating layer 5. The second drain 83 is connected to the data line 831; the second gate 81 is connected to the scan line 811. The data line 831 and the scan line 811 both extend along the second direction Y.

[0111] Furthermore, the second source 82 and the second drain 83 are disposed on opposite sides of the third insulating layer 7, and a first gap 89 is provided between them and the third insulating layer 7, so that a gap is also provided between the second source 82 and the second drain 83 and the second gate 81, avoiding contact between the second source 82 and the second drain 83 and the second gate 81. The orthographic projection of the first gap 89 on the substrate 1 is located within the orthographic projection of the conductor region on the substrate 1. The orthographic projection of the first gap 89 on the substrate 1 is adjacent to the first overlapping portion 91, and the edge lines close to each other are collinear.

[0112] The distance between the second source 82 and the third insulating layer 7 is equal to the distance between the second drain 83 and the third insulating layer 7, or the distance between the second source 82 and the second gate 81 is equal to the distance between the second drain 83 and the second gate 81, that is, the second gate 81 is centrally disposed between the second source 82 and the second drain 83, which is convenient for design calculation and process operation.

[0113] Moreover, the positive projection of the second source electrode 82 on the substrate 1 overlaps with the positive projection of the second conductor region 612 on the substrate 1 to form a second overlapping portion 92, and the width of the second overlapping portion 92 is substantially the same as the width of the first overlapping portion 91; specifically, the width of the second overlapping portion 92 is greater than or equal to 0.5 μm and less than or equal to 1 μm. For example, the width of the second overlapping portion 92 can be 0.65 μm, 0.7 μm, 0.78 μm, 0.83 μm, 0.9 μm, 0.95 μm, etc. Thereby, the second source electrode 82 is conductively connected to a second conductor region 612. The positive projection of the first gap 89 on the substrate 1 is adjacent to the second overlapping portion 92, and the adjacent edges are collinear.

[0114] The positive projection of the second drain electrode 83 on the substrate 1 overlaps with the positive projection of the second conductor region 612 on the substrate 1 to form a third overlapping portion 93, and the width of the third overlapping portion 93 is substantially the same as the width of the second overlapping portion 92; specifically, the width of the third overlapping portion 93 is greater than or equal to 0.5 μm and less than or equal to 1 μm. For example, the width of the third overlapping portion 93 can be 0.65 μm, 0.7 μm, 0.78 μm, 0.83 μm, 0.9 μm, 0.95 μm, etc. Thereby, the second drain electrode 83 is conductively connected to another second conductor region 612. After applying an appropriate voltage to the second gate electrode 81, current can sequentially pass through the second source electrode 82, a second conductor region 612, the second semiconductor region 611, another second conductor region 612, and the second drain electrode 83. The positive projection of the first gap 89 on the substrate 1 is adjacent to the third overlapping portion 93, and the adjacent edges are collinear.

[0115] Please continue to refer to Figure 1 and Figure 2 As shown, the first drain electrode 85 and the first source electrode 84 are correspondingly connected to two first conductor regions 232. Specifically, the first drain electrode 85 is connected to a first conductor region 232 through a first via 31 on the first insulating layer 3 and a second via 51 on the second insulating layer 5, and the first source electrode 84 is connected to another first conductor region 232 through the first via 31 on the first insulating layer 3 and the second via 51 on the second insulating layer 5. Moreover, the first drain electrode 85 is connected to the Vdd signal terminal (power supply line 851), and the power supply line 851 extends in the second direction Y. The first source electrode 84 is connected to the first source lead 821, and the first source lead 821 also extends in the second direction Y. The first source lead 821 is connected to the second connection portion 22 through the first via 31 on the first insulating layer 3 and the second via 51 on the second insulating layer 5. Moreover, the first source electrode 84 is connected to the anode of the light-emitting substrate (not shown in the figure), and current is provided for the anode and the light-emitting layer group through the first source electrode 84.

[0116] Please continue to refer toFigure 1 and Figure 2 As shown, the first connection line 86, the second connection line 87, and the third connection line 88 all extend along the second direction Y. The first connection line 86 is connected between the first gate 41 and the first connection portion 21. One end of the first connection line 86 is connected to the first gate 41 through the second via 51 on the second insulating layer 5, and the other end of the first connection line 86 is connected to the first connection portion 21 through the first via 31 on the first insulating layer 3 and the second via 51 on the second insulating layer 5.

[0117] The second connection line 87 is connected between the first connection portion 21 and the first electrode 24. One end of the second connection line 87 is connected to the first connection portion 21 through the first via 31 on the first insulating layer 3 and the second via 51 on the second insulating layer 5, and the other end of the second connection line 87 is connected to the first electrode 24 through the first via 31 on the first insulating layer 3 and the second via 51 on the second insulating layer 5.

[0118] The third connection line 88 is connected between the second connection portion 22 and the second electrode 62. One end portion of the third connection line 88 is located on the side of the second electrode 62 away from the substrate 1, such that one end portion of the third connection line 88 is directly connected to the second electrode 62, and the other end of the third connection line 88 is connected to the second connection portion 22 through the first via 31 on the first insulating layer 3 and the second via 51 on the second insulating layer 5.

[0119] Moreover, the orthographic projection of the second electrode 62 on the substrate 1 and the orthographic projection of the third connection line 88 on the substrate 1 overlap to form a fourth overlapping portion 94, and the width of the fourth overlapping portion 94 is substantially the same as the width of the third overlapping portion 93; specifically, the width of the fourth overlapping portion 94 is greater than or equal to 0.5 micrometers and less than or equal to 1 micrometer. For example, the width of the fourth overlapping portion 94 can be 0.65 micrometers, 0.7 micrometers, 0.78 micrometers, 0.83 micrometers, 0.9 micrometers, 0.95 micrometers, etc. Thereby enabling the second electrode 62 and the third connection line 88 to be conductively connected.

[0120] Based on the same inventive concept, the exemplary embodiments of the present disclosure provide a method for manufacturing an array substrate. Referring to Figure 13 as shown, the method for manufacturing the array substrate may include the following steps:

[0121] Step S10, forming a plurality of first transistors, the first transistors including first channel portions, the first channel portions including a first semiconductor region and a first conductor region connected to each other, and forming a first electrode while forming the first conductor region.

[0122] Step S20: Form a plurality of second transistors. The second transistors include second channel portions, and each second channel portion includes a second semiconductor region and a second conductor region that are connected to each other. A second electrode is formed while forming the second conductor region, and the second electrode and the first electrode form a storage capacitor.

[0123] Further, the first transistor T1 may further include a first gate 41, a first source 84, and a first drain 85. The second transistor T2 further includes a second gate 81, a second source 82, and a second drain 83. The second source 82, the second drain 83, the first source 84, and the first drain 85 are formed while forming the second gate 81.

[0124] Further, the array substrate may further include a light-shielding layer 42, and the first gate 41 is formed while forming the light-shielding layer 42.

[0125] Specifically, referring to Figure 3 and Figure 4 As shown, a substrate 1 is provided. The specific structure of the substrate 1 has been described in detail above, so it will not be elaborated here. A first active material layer is formed on one side of the substrate 1, and the first active material layer is patterned to form a first active pattern layer 2a. The first active pattern layer 2a may include a first connection pattern 21a, a second connection pattern 22a, a first electrode pattern 24a, and a first channel pattern 23a. The structure of the first connection pattern 21a is the same as that of the first connection portion 21, the structure of the second connection pattern 22a is the same as that of the second connection portion 22, the structure of the first channel pattern 23a is the same as that of the first channel portion 23, and the structure of the first electrode pattern 24a is the same as that of the first electrode, so it will not be elaborated here.

[0126] Referring to Figure 5 and Figure 6 As shown, a first insulating layer 3 is formed on the side of the first active pattern layer 2a away from the substrate 1. A first gate material layer is formed on the side of the first insulating layer 3 away from the substrate 1, and the first gate material layer is patterned to form a first gate layer 4. The first gate layer 4 may include a first gate 41 and a light-shielding layer 42. The orthographic projection of the first gate 41 on the substrate 1 overlaps with the orthographic projection of the first channel pattern 23a on the substrate 1. The specific structure of the first gate layer 4 has been described in detail above, so it will not be elaborated here.

[0127] Then, using the first gate layer 4 as a mask, an ion implantation process is performed on the first active pattern layer 2a. The implanted ions may include boron or phosphorus. The ion implantation process causes the first active pattern layer 2a that is not masked by the first gate layer 4 to form a conductor, that is, the first active pattern layer 2a forms the first active layer 2. The first active layer 2 may include a first connection portion 21, a second connection portion 22, a first channel portion 23, and a first electrode 24. The first channel portion 23 may include a first semiconductor region 231 and a first conductor region 232. Since the first semiconductor region 231 is masked by the first gate layer 4 and no ion implantation process is performed, the material of the first semiconductor region 231 is still polysilicon, which is a semiconductor. Moreover, the orthographic projection of the formed first semiconductor region 231 on the substrate 1 is located within the orthographic projection of the first gate 41 on the substrate 1. Since the first connection portion 21, the second connection portion 22, the first conductor region 232, and the first electrode 24 are not masked by the first gate layer 4, they become conductors after the ion implantation process is completed.

[0128] Using the first gate layer 4 as a mask can reduce the use of one photomask, making the process flow relatively simple.

[0129] Refer to Figure 7 and Figure 8 As shown, a second insulating layer 5 is formed on the side of the first gate layer 4 facing away from the substrate 1. A second active material layer is formed on the side of the second insulating layer 5 facing away from the substrate 1, and the second active material layer is patterned to form a second active pattern layer 6a. The second active pattern layer 6a may include a second channel pattern 61a and a second electrode pattern 62a. The structure of the second channel pattern 61a is the same as that of the second channel portion 61, and the structure of the second electrode pattern 62a is the same as that of the second electrode, which will not be elaborated here.

[0130] Refer to Figure 9 and Figure 10 As shown, Figure 10 To avoid the pattern being too complex, the first insulating layer 3 and the second insulating layer 5 are not shown. Therefore, Figure 10The second via 51 in it is represented by a dotted-line square. A third insulating material layer is formed on the side of the second active pattern layer 6a facing away from the substrate 1. A mask is placed on the side of the third insulating material layer facing away from the substrate 1. The mask is a half-tone mask, that is, the mask includes a light-transmitting portion, a light-blocking portion, and a semi-light-transmitting portion. The light-blocking portion is disposed opposite to the portion where the third insulating layer 7 needs to be formed, and the light-transmitting portion is disposed opposite to the portion where the second via 51 needs to be formed. Then, the third insulating material layer is irradiated and exposed, so that the third insulating material layer disposed opposite to the light-blocking portion remains to form the third insulating layer 7; the third insulating material layer disposed opposite to the light-transmitting portion is completely etched, and moreover, the second insulating layer 5 under the third insulating material layer is also etched to form the second via 51, and the first insulating layer 3 under the second insulating material layer is also etched to form the first via 31. The third insulating material layer disposed opposite to the semi-light-transmitting portion is completely etched, but the first insulating layer 3 and the second insulating layer 5 are basically not etched.

[0131] Refer to Figure 11 and Figure 12 As shown, a conductor material layer is formed on the side of the third insulating layer 7 facing away from the substrate 1, and the conductor material layer is patterned to form a conductor layer 8. The conductor layer 8 may include a second gate 81, a second source 82, a second drain 83, a first source 84, a first drain 85, a first connection line 86, a second connection line 87, and a third connection line 88. That is, the second gate 81, the second source 82, the second drain 83, the first source 84, the first drain 85, the first connection line 86, the second connection line 87, and the third connection line 88 are formed by the same lithography process; the process flow is saved, and moreover, the structure of the formed array substrate is simple; the specific structure of the conductor layer 8 has been described in detail above, so it will not be elaborated here.

[0132] Refer to Figure 1 and Figure 2 As shown, a part of the second active pattern layer 6a is conductorized with the second gate 81 as a shield to form a second conductor region 612 and a second electrode 62. That is, the exposed second active pattern layer 6a is conductorized to form the second conductor region 612 and the second electrode 62, and the second active pattern shielded by the second gate 81 is not conductorized and remains a semiconductor to form a second semiconductor region 611.

[0133] Moreover, since the lateral conductivity depth of the conductivity process is greater than or equal to 0.5 μm and less than or equal to 1 μm, the second source electrode 82 can form a second overlapping portion 9292 with the second conductor region 612, so that the second source electrode 82 can be conductively connected to the second conductor region 612. Similarly, the second drain electrode 83 can form a third overlapping portion 9393 with the second conductor region 612, so that the second drain electrode 83 can be conductively connected to the second conductor region 612. Moreover, the third connection line 88 can form a fourth overlapping portion 9494 with the second electrode 62, so that the third connection line 88 can be conductively connected to the second electrode 62.

[0134] Using the second gate electrode 81 as a shield can reduce the use of a photomask, making the process flow relatively simple.

[0135] It should be noted that although the steps of the method of the array substrate in the present disclosure are described in a specific order in the drawings, this does not require or imply that these steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired result. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step for execution, and / or one step may be decomposed into multiple steps for execution, etc.

[0136] Based on the same inventive concept, the exemplary embodiments of the present disclosure provide a display panel. The display panel may include the array substrate described in any one of the above. On one side of the array substrate, a light-emitting substrate is provided. The light-emitting substrate may include an anode, a pixel definition layer, a light-emitting layer group, and a cathode that are sequentially stacked. The main working principle is: when appropriate voltages are applied to the cathode and the anode, electrons and holes are respectively injected from the cathode and the anode into the organic material functional layer, and the holes and electrons recombine to emit light in the organic light-emitting layer. The specific structure of the array substrate has been described in detail above, and therefore, it will not be elaborated here.

[0137] Compared with the prior art, the beneficial effects of the display panel provided by the exemplary embodiments of the present invention are the same as those of the array substrate provided by the above exemplary embodiments, and will not be elaborated here.

[0138] Based on the same inventive concept, the exemplary embodiments of the present disclosure provide a display device. The display device may include the display panel described above.

[0139] The specific type of the display device is not particularly limited, and any common display device type in the art can be used, such as mobile devices such as mobile phones, wearable devices such as watches, VR devices, etc. Those skilled in the art can make corresponding selections according to the specific use of the display device, and will not be elaborated here.

[0140] It should be noted that, in addition to the display panel, the display device further includes other necessary components and compositions. Taking a display as an example, specifically, such as a housing, a circuit board, a power cord, and so on. Those skilled in the art can make corresponding supplements according to the specific usage requirements of the display device, which will not be elaborated here.

[0141] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily conceive of other embodiments of the present disclosure. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and examples are only to be considered as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. An array substrate, characterized in that, Including: A plurality of first transistors, the first transistors including first channel portions, the first channel portions including a first semiconductor region and a first conductor region connected to each other; A plurality of second transistors, the second transistors including second channel portions, the second channel portions including a second semiconductor region and a second conductor region connected to each other; A plurality of storage capacitors, the storage capacitors including a first electrode and a second electrode, the first electrode being provided on the same layer and made of the same material as the first conductor region, and the second electrode being provided on the same layer and made of the same material as the second conductor region; The array substrate includes: A substrate; A first active layer provided on one side of the substrate, the first active layer including the spaced-apart first channel portions and the first electrode; A first insulating layer provided on the side of the first active layer facing away from the substrate; A first gate layer provided on the side of the first insulating layer facing away from the substrate, the first gate layer including spaced-apart first gates and a light-shielding layer, and a positive projection of the first semiconductor region on the substrate being located within a positive projection of the first gate on the substrate; A second insulating layer provided on the side of the first gate layer facing away from the substrate; A second active layer provided on the side of the second insulating layer facing away from the substrate, the second active layer including the spaced-apart second channel portions and the second electrode, a positive projection of the second channel portion on the substrate being located within a positive projection of the light-shielding layer on the substrate, and a positive projection of the second electrode on the substrate overlapping at least partially with a positive projection of the first electrode on the substrate; A third insulating layer provided on the side of the second active layer facing away from the substrate; A conductor layer provided on the side of the third insulating layer facing away from the substrate, the conductor layer including a second gate, a second source, a second drain, a first source, and a first drain; Wherein, a positive projection of the second semiconductor region on the substrate is located within a positive projection of the second gate on the substrate, the second source and the second drain are correspondingly connected to two of the second conductor regions, and the first drain and the first source are correspondingly connected to two of the first conductor regions.

2. The array substrate according to claim 1, wherein The first active layer further includes spaced-apart first connection portions and second connection portions, and there are spaces between the first connection portions, the second connection portions, the first channel portions, and the first electrode.

3. The array substrate according to claim 2, wherein, The conductor layer further includes a first connection line, a second connection line, a third connection line, a power line, a data line, a scan line, a first source lead, and a second source lead; the second source lead connects the second source and the first connection portion; the first source lead connects the first source and the second connection portion; the first connection line connects the first gate and the first connection portion, the second connection line connects the first connection portion and the first electrode, the third connection line connects the second connection portion and the second electrode, the power line is connected to the first drain, the data line is connected to the second drain, and the scan line is connected to the second gate.

4. The array substrate according to claim 3, wherein The third insulating layer is disposed on a side of the second channel portion away from the substrate. A positive projection of the third insulating layer on the substrate covers and is larger than a positive projection of the second semiconductor region on the substrate, and the positive projection of the third insulating layer on the substrate overlaps with a positive projection of the second conductor region on the substrate to form a first overlapping portion. The second source electrode and the second drain electrode are disposed on opposite sides of the third insulating layer, and a first gap is provided between the second source electrode and the second drain electrode and the third insulating layer. A positive projection of the second source electrode on the substrate overlaps with a positive projection of the second conductor region on the substrate to form a second overlapping portion. A positive projection of the second drain electrode on the substrate overlaps with a positive projection of the second conductor region on the substrate to form a third overlapping portion.

5. The array substrate according to claim 4, wherein The width of the first overlapping portion is greater than or equal to 0.5 micrometers and less than or equal to 1 micrometer. The width of the second overlapping portion is greater than or equal to 0.5 micrometers and less than or equal to 1 micrometer. The width of the third overlapping portion is greater than or equal to 0.5 micrometers and less than or equal to 1 micrometer.

6. The array substrate according to claim 3, wherein The first connecting portion and the second connecting portion extend along a first direction. The first channel portion and the first electrode are arranged along the first direction, and the first channel portion and the first electrode are located between the first connecting portion and the second connecting portion. The first direction is parallel to the substrate.

7. The array substrate according to claim 6, wherein The first connecting line, the second connecting line, and the third connecting line extend along a second direction. The first source electrode lead and the second source electrode lead extend along the second direction. The second direction is parallel to the substrate, and the second direction intersects the first direction.

8. The array substrate according to claim 3, wherein A positive projection of the second electrode on the substrate is located within a positive projection of the first electrode on the substrate.

9. The array substrate according to claim 1, wherein The material of the first semiconductor region is low-temperature polysilicon, and the material of the second semiconductor region is an oxide active layer.

10. A method for preparing an array substrate, characterized in that, Including: Forming a plurality of first transistors, the first transistors including first channel portions, the first channel portions including a first semiconductor region and a first conductor region connected to each other, and forming a first electrode while forming the first conductor region; Forming a plurality of second transistors, the second transistors including second channel portions, the second channel portions including a second semiconductor region and a second conductor region connected to each other, and forming a second electrode while forming the second conductor region, the second electrode and the first electrode forming a storage capacitor; Forming the first transistors and the second transistors includes: Providing a substrate; Forming a first active pattern layer on one side of the substrate; Forming a first insulating layer on a side of the first active pattern layer away from the substrate; Forming a first gate layer on a side of the first insulating layer away from the substrate, the first gate layer including a first gate and a light-shielding layer disposed at intervals, and a positive projection of the first semiconductor region on the substrate is located within a positive projection of the first gate on the substrate; Using the first gate layer as a mask, a part of the first active pattern layer is conductively processed to form the first conductor region and the first electrode; A second insulating layer is formed on a side of the first gate layer facing away from the substrate; A second active pattern layer is formed on a side of the second insulating layer facing away from the substrate; A third insulating layer is formed on a side of the second active pattern layer facing away from the substrate; A conductor layer is formed on a side of the third insulating layer facing away from the substrate, the conductor layer including a second gate, a second source, a second drain, a first source, and a first drain; Using the second gate as a mask, a part of the second active pattern layer is conductively processed to form the second conductor region and the second electrode.

11. The method for manufacturing an array substrate according to claim 10, wherein Using the first gate layer as a mask, a part of the first active pattern layer is conductively processed to form the first conductor region and the first electrode, and at the same time, a first connection part and a second connection part are formed.

12. The method for preparing an array substrate according to claim 11, wherein, The conductor layer further includes a first connection line, a second connection line, a third connection line, a power line, a data line, a scan line, a first source lead, and a second source lead.

13. A display panel, characterized in that, Comprising: The array substrate according to any one of claims 1 to 9.

14. A display device, characterized in that, Comprising: The display panel according to claim 13.

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