A method, system, device and medium for collecting information from non-perceptual network cables

Abstract

The present invention provides a method, system, device and medium for collecting information from a non-perceptual network cable, which collects and acquires the initial signal of a network device; performs signal level coupling on the initial signal to obtain an enhanced signal; the transmission channel of the enhanced signal is isolated from the physical layer device chip by an isolation circuit; the enhanced signal is collected by differential transmission to obtain a target differential signal; information is parsed according to the target differential signal, and the signal obtained after the analysis is repackaged after adding a time mark according to the timing situation to obtain a target signal; equipment configuration and / or information collection management are performed according to the target signal; the solution performs AC coupling access through an isolation circuit, has no interference with network signals, and realizes non-perceptual access by only receiving but not sending, realizes synchronous restoration of received and sent data through the time mark of an FPGA, and realizes non-perceptual information collection, which can be widely used in the field of signal processing technology.

Description

Technical Field

[0001] The present invention relates to the field of signal processing technology, and in particular to a method, system, device and medium for collecting network cable information without perception. Background Art

[0002] Ethernet access is currently one of the main ways to access wired networks. Sometimes, according to special needs, it is necessary to obtain information transmitted by Ethernet and obtain the required content based on the information. The current methods are mainly through Ethernet packet capture tools for analysis or through traffic monitoring equipment for analysis. However, these methods require access to MAC devices, and a network device will be identified in the network topology, making it impossible to obtain relevant information without perception. Summary of the invention

[0003] In view of this, in order to at least partially solve the above-mentioned technical problems or one of the defects, the purpose of an embodiment of the present invention is to use FPGA and PHY chip technology to provide a fast and relatively simple method for collecting network cable information without perception; in addition, the embodiment also provides a system, device and storage medium that can implement this method.

[0004] On the one hand, the technical solution of the present application provides a method for collecting network cable information without perception, comprising the following steps:

[0005] Collect and obtain the initial signal of network equipment;

[0006] Performing signal level coupling on the initial signal to obtain an enhanced signal; a transmission channel of the enhanced signal is isolated from a physical layer device chip by an isolation circuit;

[0007] The enhanced signal is collected by differential transmission to obtain a target differential signal;

[0008] Performing information parsing according to the target differential signal, adding a time stamp to the signal obtained after parsing according to the timing situation, and then repackaging to obtain the target signal;

[0009] Device configuration and / or information collection management are performed according to the target signal.

[0010] In a feasible embodiment of the solution of the present application, the step of acquiring the enhanced signal by differential transmission to obtain the target differential signal includes:

[0011] Acquiring an initial differential signal obtained by the differential transmission;

[0012] The filter signal is obtained by coupling filtering through the differential mode coupling coil at the transformer end;

[0013] The filtered signal generates an electromagnetic field after passing through the coil. According to the change of the electromagnetic field, the filtered signal is converted and coupled to the opposite coil of the transformer, and the target differential signal is obtained through the output of the opposite coil.

[0014] In a feasible embodiment of the solution of the present application, the step of performing information parsing according to the target differential signal, adding a time mark to the signal obtained after parsing according to the timing situation, and then repackaging to obtain the target signal includes:

[0015] Acquire a clock signal, and perform phase adjustment on the clock signal according to the target differential signal to obtain a first data signal; the first data signal is aligned with the target differential signal;

[0016] Determine the operating parameters of the Ethernet link, check the MAC frame length and cyclic redundancy check code of the target differential signal according to the operating parameters and the first data signal, and obtain the data packet of the target signal according to the test result output;

[0017] A cyclic redundancy check code is double-checked during the transmission of the data packet through a preset control bit, and / or a pause frame is added during the transmission of the data packet.

[0018] In a feasible embodiment of the solution of the present application, the step of performing information parsing according to the target differential signal, adding a time mark to the signal obtained after the parsing according to the timing situation, and then repackaging to obtain the target signal also includes:

[0019] Eliminate the frame check sequence signal in the data packet, perform frame structure analysis on the data packet after the elimination process, and obtain source MAC address information, source IP information and Ethernet packet protocol type;

[0020] The time marker is added to the target signal in the data packet.

[0021] In a feasible embodiment of the solution of the present application, before the step of performing device configuration and / or information collection management according to the target signal, the method further includes:

[0022] The data packet and the interface signal during the sending process are adjusted, and a frame header sop signal, a frame tail eop signal, a frame data valid indication dval signal and the target signal are generated according to the adjustment result.

[0023] On the other hand, the technical solution of the present application also provides a non-perceptual network cable information collection system, which includes:

[0024] An isolation circuit unit is used to obtain an initial signal of a network device; perform signal level coupling on the initial signal to obtain an enhanced signal; and isolate the enhanced signal from a PHY chip;

[0025] A PHY processing unit, configured to collect the enhanced signal by differential transmission to obtain a target differential signal;

[0026] The FPGA processing unit is used to perform information analysis according to the target differential signal, add a time mark to the signal obtained after the analysis according to the timing situation, and then re-encapsulate it to obtain the target signal;

[0027] The CPU processing unit is used to perform device configuration and / or information collection management according to the target signal.

[0028] In a feasible embodiment of the solution of the present application, the FPGA processing unit includes:

[0029] An RGMII interface module is used to obtain a clock signal, and perform phase adjustment on the target differential signal according to the clock signal to obtain a first data signal; the first data signal is aligned with the clock signal;

[0030] a MAC receiving module, determining working parameters of the Ethernet link, receiving the first data signal according to the working parameters, checking the MAC frame length and cyclic redundancy check code of the first data signal, and outputting a data packet of the target signal according to the checking result;

[0031] The MAC sending module performs a secondary check on the cyclic redundancy check code in the process of sending the data packet through a preset control bit, and / or adds a pause frame in the process of sending the data packet.

[0032] In a feasible embodiment of the solution of the present application, the FPGA processing unit further includes:

[0033] An FCS signal removal module, used to remove the frame check sequence signal in the data packet;

[0034] The Ethernet packet header parsing module is used to parse the frame structure of the data packet after the elimination process, obtain the source MAC address information, source IP information and Ethernet packet protocol type; and add the time mark to the target signal in the data packet.

[0035] On the other hand, the technical solution of the present application also provides a non-perceptual network cable information collection device, the device comprising:

[0036] at least one processor;

[0037] at least one memory for storing at least one program;

[0038] When the at least one program is executed by the at least one processor, the at least one processor runs a method for collecting network cable information without perception as described in any one of the first aspects.

[0039] On the other hand, the technical solution of the present application also provides a storage medium, which stores a program executable by a processor. When the program executable by the processor is executed by the processor, it is used to execute a method for collecting network cable information without perception as described in any one of the first aspects.

[0040] The advantages and beneficial effects of the present invention will be partially given in the following description, and the other parts can be understood through the specific embodiments of the present invention:

[0041] The technical solution of this application provides a method, system, device and medium for collecting information from a non-perceptual network cable. The solution mainly adopts FPGA and PHY chip technology, and receives the information sent from both ends of the network cable through two PHYs, and then transmits the received information to the FPGA for interpretation and adds a time stamp to upload to the CPU platform for analysis and restoration. The solution uses an isolation circuit for AC coupling access, which does not interfere with the network signal, and only receives but does not send to achieve non-perceptual access. The time stamp of the FPGA is used to achieve synchronous restoration of the sent and received data, thereby achieving non-perceptual information collection. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 This is a flowchart of a method for collecting network cable information without perception provided in the technical solution of this application;

[0044] Figure 2 This is a schematic diagram of the transmission process of non-aware network cable information in the technical solution of this application;

[0045] Figure 3 This is a structural diagram of a non-perceptual network cable information collection system provided in the technical solution of this application;

[0046] Figure 4 This is a schematic diagram of the modules inside the FPGA processing unit in the technical solution of this application. DETAILED DESCRIPTION

[0047] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and are not to be construed as limitations of the present invention. For the step numbers in the following embodiments, they are only provided for the convenience of explanation, and the order between the steps is not limited in any way. The execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0048] First, some technical terms in the technical solution of this application are explained:

[0049] Port Physical (PHY) is a common abbreviation for the physical layer of the OSI model. Ethernet is a device that operates the physical layer of the OSI model. An Ethernet PHY is a chip that can send and receive Ethernet data frames.

[0050] Field Programmable Gate Array (FPGA) is a product further developed on the basis of programmable devices such as PAL (Programmable Array Logic) and GAL (General Array Logic). It appears as a semi-custom circuit in the field of Application Specific Integrated Circuit (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices.

[0051] In the related technical solutions, the methods used are mainly to analyze through Ethernet packet capture tools or through traffic monitoring equipment, but these methods require access to MAC devices, and a network device will be identified in the network topology, and it is impossible to obtain relevant information without perception. Therefore, the technical solution of this application specifically solves two deficiencies or defects in the related technical solutions: first, it realizes non-perceptual data collection, which not only does not interfere with the network signal, but also is not monitored and identified by related network equipment; second, it can collect two-way data separately to achieve synchronous restoration.

[0052] In the first aspect, Figure 1 As shown, the technical solution of the present application provides a method for collecting network cable information without perception; the method includes steps S100-S500:

[0053] S100, collecting and obtaining the initial signal of the network device;

[0054] Specifically in the embodiment, the initial signal may refer to a signal sent by any network device and having a clear transmission object. In the embodiment, after the network device sends a signal, it is first transmitted to the isolation circuit.

[0055] S200, performing signal level coupling on the initial signal to obtain an enhanced signal; wherein the transmission channel of the enhanced signal is isolated from the physical layer device chip through an isolation circuit;

[0056] Specifically in the embodiment, the collected initial signal is first transmitted to the isolation circuit in the embodiment. The isolation circuit in the embodiment is mainly composed of an Ethernet transformer and a TVS device. The network transformer is mainly used for signal level coupling to enhance the signal and increase the transmission distance. The isolation circuit in the embodiment can achieve isolation between the network cable and the PHY chip to prevent signal or different level interference between devices; in addition, the TVS device in the isolation circuit mainly plays an overvoltage and overcurrent protection role.

[0057] S300, collecting the enhanced signal by differential transmission to obtain a target differential signal;

[0058] Specifically in the embodiment, the signal sent by the network device is transmitted to the PHY processing unit after passing through the isolation circuit. The PHY unit in the embodiment is mainly used to realize data reception. The receiving ends of the two PHY processing units are respectively connected to the sending signal line of the Ethernet cable, and data is collected for the signals sent by the two network devices respectively, and no signal is sent by itself.

[0059] S400, performing information parsing according to the target differential signal, adding a time stamp to the signal obtained after the parsing according to the timing situation, and then repackaging to obtain the target signal;

[0060] Specifically in the embodiment, the PHY processing unit forwards the signal to the FPGA processing unit after signal recognition and processing, and the FPGA unit interprets the signal, adds a time mark according to the timing, repackages it, and sends it to the CPU processing unit. The FPGA processing unit in the embodiment mainly completes the information analysis transmitted by the PHY, adds a time mark according to the timing situation, and repackages it and transmits it to the CPU for analysis.

[0061] S500, performing device configuration and / or information collection management according to the target signal;

[0062] Specifically in the embodiment, the signal is interpreted by the FPGA processing unit, and the repackaged signal or data packet with a time stamp is sent to the CPU processing unit in the embodiment, which analyzes and restores the information, and simultaneously configures the network device and manages the collection of signal data.

[0063] In some feasible implementations, the embodiment method collects the enhanced signal by differential transmission to obtain the target differential signal in step S300, which may include steps S310-S330:

[0064] S310, collecting and acquiring an initial differential signal obtained by differential transmission;

[0065] Specifically in the embodiment, during the signal transmission process, differential transmission can be adopted, that is, the transmitting end, such as a network device, transmits an electrical signal with equal amplitude and opposite phase on two signal lines, and the receiving end, such as the PHY processing unit in the embodiment, performs a subtraction operation on the received two line signals, thereby obtaining a signal with doubled amplitude.

[0066] S320, performing coupling filtering through the differential mode coupling coil at the local end of the transformer to obtain a filtered signal;

[0067] S330, the filtered signal generates an electromagnetic field after passing through the coil, and according to the change of the electromagnetic field, the filtered signal is converted and coupled to the opposite coil of the transformer, and the target differential signal is obtained through the output of the opposite coil;

[0068] Specifically in the embodiment, when the PHY processing unit transmits the signal to the FPGA processing unit, the differential signal sent by the PHY chip is coupled and filtered through the differential mode coupling coil at the transformer end. At the same time, the differential signal generates an electromagnetic field after passing through the coil, and the signal is converted and coupled to the opposite coil of the transformer through the change of the magnetic field. Through the transformer isolation coupling mode, not only the AC signal is not physically connected between the network cable and the PHY chip, but also the DC component is cut off, supporting data transmission in devices with different 0V levels. The TVS tube is connected to the line side, and the lightning current induced by the line is introduced into the ground through the TVS tube, completing the rapid release of lightning energy and realizing the lightning protection function.

[0069] In some feasible implementations, the step S400 of performing information parsing according to the target differential signal, adding a time stamp to the signal obtained after parsing according to the timing situation, and then repackaging the signal to obtain the target signal may include steps S410-S430:

[0070] S410, acquiring a clock signal, and performing phase adjustment on the clock signal according to a target differential signal to obtain a first data signal; wherein the first data signal is aligned with the target differential signal;

[0071] Specifically in the embodiment, the first data signal refers to the clock signal after phase adjustment. In the embodiment, the interface signal processing of the physical layer PHY chip can be completed through the RGMII interface, and the clock signal of the interface is aligned with the data signal by phase adjustment of the clock signal of the GMII interface to ensure the stability of Ethernet data reception. There are four RGMII interfaces in total to complete data reception and data upload in two directions.

[0072] S420, determining the working parameters of the Ethernet link, receiving the first data signal according to the working parameters, checking the MAC frame length and the cyclic redundancy check code of the first data signal, and outputting a data packet of the target signal according to the test result;

[0073] S430, performing a secondary check on a cyclic redundancy check code during the transmission of a data packet through a preset control bit, and / or adding a pause frame during the transmission of a data packet;

[0074] In the embodiment, at least one MAP_TOP module is provided in the FPGA processing unit, and the MAP_TOP module may include a sending submodule and a receiving submodule. Specifically, in the embodiment, the MAP_TOP module may implement a 10 / 100 / 1000M clock byte adaptation function, and in the embodiment, the MAP_TOP module may set the working parameters of the Ethernet link, such as duplex half-duplex, thresholds for sending and receiving FTO, interframe gap, insertion of pause frames, insertion of error CRC, etc.

[0075] More specifically, the transmitting submodule (MAC_Tx) and receiving submodule (MAC_Rx) in the embodiment, wherein MAC_Tx implements MAC data transmission and generates CRC, detects CRS and col in half-duplex working mode to implement half-duplex flow control protocol; when in full-duplex working mode, it can send a pause frame. There is a 1-bit control bit in MAC_Tx to control whether to insert an erroneous CRC check when sending a data packet, and there is also a 1-bit control bit in MAC_Tx to control whether the transmitting module sends a pause frame. MAC_Rx mainly receives and detects the MAC frame length, whether the CRC checksum is correct, and outputs the status of the corresponding data packet.

[0076] In some feasible implementations, the step S400 of performing information parsing according to the target differential signal, adding a time stamp to the signal obtained after parsing according to the timing situation, and then repackaging the signal to obtain the target signal may also include steps S440-S450:

[0077] S440, removing the frame check sequence signal in the data packet, parsing the frame structure of the data packet after the removal process, and obtaining source MAC address information, source IP information and Ethernet packet protocol type;

[0078] S450, adding a time mark to the target signal in the data packet;

[0079] In the embodiment, the FPGA processing unit is provided with a cut_crc32 module for removing the frame check sequence (FCS) signal in the data message to prevent the FCS data from being mistakenly regarded as business data when the data is cached, thereby affecting the business analysis function. After that, the Ethernet packet header parsing module in the FPGA processing unit parses the source MAC address information, source IP information and Ethernet packet protocol type of the Ethernet packet according to the Ethernet frame structure, and adds time stamp information to the received data for the software to collect, integrate and analyze the data of the transceiver link.

[0080] In some feasible implementations, before step S500 of performing device configuration and / or information collection management according to the target signal, the method of the embodiment may further include step S460:

[0081] S460, adjusting the data packet and the interface signal during the sending process, and generating a frame header sop signal, a frame tail eop signal, a frame data valid indication dval signal and a target signal according to the adjustment result;

[0082] In the embodiment, a PKT_SD_CTRL module is also provided in the FPGA processing unit, which mainly processes the sending of data packets, adjusts the interface signal between the data packets and the MAC_TX module, and generates the frame header sop signal, frame tail eop signal, frame data valid indication dval signal, and data signal of the sending module.

[0083] Refer to the instruction manual Figure 2 The specific implementation process of the method for collecting network cable information without perception in the technical solution of this application is fully described as follows:

[0084] The signal sent by the network device is transmitted to the PHY unit after passing through the isolation circuit. The PHY unit forwards it to the FPGA unit after signal recognition and processing. The FPGA unit interprets the signal, adds a time stamp according to the timing, re-encapsulates it and sends it to the CPU unit. The CPU restores the Ethernet information delivery process based on the time stamp.

[0085] On the other hand, Figure 3 As shown, the technical solution of the present application also provides a non-perceptual network cable information collection system, which includes:

[0086] The isolation circuit unit is used to obtain the initial signal of the network device; perform signal level coupling on the initial signal to obtain an enhanced signal; and isolate the enhanced signal from the PHY chip;

[0087] The PHY processing unit is used to collect the enhanced signal by differential transmission to obtain a target differential signal;

[0088] The FPGA processing unit is used to perform information analysis according to the target differential signal, add a time mark to the signal obtained after the analysis according to the timing situation, and then re-encapsulate it to obtain the target signal;

[0089] The CPU processing unit is used to perform device configuration and / or information collection management according to the target signal.

[0090] like Figure 4 As shown, in some feasible implementation manners, the FPGA processing unit in the embodiment may further include the following modules:

[0091] The RGMII interface module is used to complete the interface signal processing of the physical layer PHY chip. By adjusting the phase of the clock signal of the GMII interface, the clock signal of the interface is aligned with the data signal to ensure the stability of Ethernet data reception. There are four RGMII interfaces in total to complete data reception and data upload in two directions.

[0092] The MAP_TOP module includes a MAC receiving submodule and a MAC sending submodule. Its main functions include:

[0093] (1) 10 / 100 / 1000M clock byte adaptation function;

[0094] (2) Set the working parameters of the Ethernet link, such as duplex and half-duplex, thresholds for sending and receiving FTO, interframe spacing, insertion of pause frames, insertion of error CRC, etc.

[0095] (3) MAC sending submodule and MAC receiving submodule: The MAC sending submodule implements MAC data transmission and generates CRC. It detects CRS and col to implement half-duplex flow control protocol in half-duplex mode, and can send pause frames in full-duplex mode. There is a control bit in the MAC sending submodule to control whether to insert an incorrect CRC check when sending a data packet, and another control bit to control whether the sending module sends a pause frame. The MAC data submodule detects the MAC frame length, whether the CRC checksum is correct, and outputs the status of the corresponding packet. The MAC receiving module can also detect the pause frame in full-duplex mode and send a request to the MAC sending module to respond to the pause frame.

[0096] (4) Functions of inserting FCS errors and inserting pause frames.

[0097] The cut_crc32 module is used to remove the FCS signal in the data message to prevent the FCS data from being mistakenly regarded as business data when caching data, thereby affecting the business analysis function.

[0098] The RX_PROC module (Ethernet packet header parsing module) is used to parse the source MAC address information, source IP information and Ethernet packet protocol type of the Ethernet packet according to the Ethernet frame structure, and add time stamp information to the received data for the software to collect, integrate and analyze the data of the transceiver link.

[0099] The rx_statis module is a traffic statistics module. It mainly counts the total messages, broadcast messages, and error messages. It can count the number of packets and the number of bytes in the packets, and monitor the data traffic of the entire link for the software to make corresponding analysis.

[0100] The rx_pkt_data module is the packet capture module. The CPU can capture the data packets of the specified IP address for analysis by configuring the IP address parameters. The captured data will not affect the data collection of the link.

[0101] The PKT_SD_CTRL module mainly processes the sending of data packets, adjusts the interface signals between the data packets and the MAC_TX module, and generates the frame header sop signal, frame tail eop signal, frame data valid indication dval signal, and data signal of the sending module.

[0102] The phy_config module mainly implements the initialization function of the PHY chip configuration and obtains the link status of the interface, such as interface rate, interface mode and other information, and uploads it to the CPU for port monitoring display.

[0103] The gpmc_to_localbus template converts the GPMC interface signals connected to the CPU into localbus signals, which is mainly used for communication between the main control CPU and FPGA.

[0104] The reg_mapper module maps the register addresses inside the FPGA. Through address mapping, the operation addresses of various functional modules are divided. It is mainly used for the communication address management function between the main control CPU and the FPGA.

[0105] On the other hand, the technical solution of the present application also provides a non-perceptual network cable information collection device; which includes:

[0106] At least one processor; at least one memory, the memory being used to store at least one program; when the at least one program is executed by the at least one processor, the at least one processor runs a method for collecting network cable information without perception as in the first aspect.

[0107] An embodiment of the present invention further provides a storage medium storing a corresponding execution program, which is executed by a processor to implement a method for collecting network cable information without perception in the first aspect.

[0108] From the above specific implementation process, it can be concluded that the technical solution provided by the present invention has the following advantages or strengths compared with the prior art:

[0109] The technical solution of this application proposes a non-perceptual network cable information collection device and method, which mainly adopts FPGA and PHY chip technology, receives the information sent from both ends of the network cable through two PHYs, and then transmits the received information to the FPGA for interpretation and adds a time mark to upload to the CPU platform for analysis and restoration. AC coupling access is performed through an isolation circuit, which does not interfere with the network signal, and non-perceptual access is achieved by only receiving but not sending. The time mark of the FPGA is used to achieve synchronous restoration of the sent and received data, thereby realizing non-perceptual information collection.

[0110] The solution mainly solves the following two difficulties:

[0111] a) Non-perceptual data collection, firstly, no interference with network signals, and secondly, no detection and identification by related network equipment;

[0112] b) Bidirectional data is collected separately and restored synchronously.

[0113] In some selectable embodiments, the function / operation mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the function / operation involved, the two boxes shown in succession can actually be executed substantially simultaneously or the boxes can sometimes be executed in reverse order. In addition, the embodiment presented and described in the flow chart of the present invention is provided by way of example, for the purpose of providing a more comprehensive understanding of technology. The disclosed method is not limited to the operation and logic flow presented herein. Selectable embodiments are expected, wherein the order of various operations is changed and the sub-operation of a part for which is described as a larger operation is performed independently.

[0114] In addition, although the present invention is described in the context of functional modules, it should be understood that, unless otherwise specified, one or more of the functions and / or features can be integrated into a single physical device and / or software module, or one or more functions and / or features can be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the present invention. More specifically, in view of the properties, functions and internal relationships of the various functional modules in the device disclosed herein, the actual implementation of the module will be understood within the conventional skills of the engineer. Therefore, those skilled in the art can implement the present invention set forth in the claims without excessive experimentation using ordinary techniques. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present invention, which is determined by the full scope of the appended claims and their equivalents.

[0115] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, which can be embodied in any computer-readable medium for use by an instruction execution system, apparatus or device (such as a computer-based system, a system including a processor or other system that can fetch instructions from an instruction execution system, apparatus or device and execute instructions), or used in combination with these instruction execution systems, apparatuses or devices.

[0116] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0117] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

[0118] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A method for collecting network cable information without perception. It is characterized in that The following steps are involved: Collect and obtain the initial signal of network equipment; The initial signal is subjected to signal level coupling to obtain an enhanced signal; the transmission channel of the enhanced signal is isolated from the physical layer device chip by an isolation circuit; the isolation circuit includes an Ethernet transformer and a TVS device; The enhanced signal is collected by differential transmission to obtain a target differential signal; the physical layer device chip is used to receive the enhanced signal and collect data from the network device; Performing information parsing according to the target differential signal, adding a time stamp to the signal obtained after parsing according to the timing situation, and then repackaging to obtain the target signal; Performing equipment configuration and / or information collection management according to the target signal; The step of collecting the enhanced signal by differential transmission to obtain a target differential signal includes: Acquiring the initial differential signal obtained by differential transmission; The filter signal is obtained by coupling filtering through the differential mode coupling coil at the transformer end; The filtered signal generates an electromagnetic field after passing through the coil. According to the change of the electromagnetic field, the filtered signal is converted and coupled to the opposite coil of the transformer, and the target differential signal is obtained through the output of the opposite coil.

2. According to the method for collecting network cable information without perception in claim 1, It is characterized in that The step of performing information parsing according to the target differential signal, adding a time stamp to the signal obtained after the parsing according to the timing situation, and then repackaging the signal to obtain the target signal includes: Acquire a clock signal, and perform phase adjustment on the clock signal according to the target differential signal to obtain a first data signal; the first data signal is aligned with the target differential signal; Determine the operating parameters of the Ethernet link, check the MAC frame length and cyclic redundancy check code of the target differential signal according to the operating parameters and the first data signal, and obtain the data packet of the target signal according to the test result output; A cyclic redundancy check code is double-checked during the transmission of the data packet through a preset control bit, and / or a pause frame is added during the transmission of the data packet.

3. According to the method for collecting network cable information without perception in claim 2, It is characterized in that The step of performing information parsing according to the target differential signal, adding a time mark to the signal obtained after the parsing according to the timing situation, and then repackaging to obtain the target signal also includes: Eliminate the frame check sequence signal in the data packet, perform frame structure analysis on the data packet after the elimination process, and obtain source MAC address information, source IP information and Ethernet packet protocol type; The time marker is added to the target signal in the data packet.

4. According to the method for collecting network cable information without perception in claim 2, It is characterized in that Before the step of performing device configuration and / or information collection management according to the target signal, the method further includes: The data packet and the interface signal during the sending process are adjusted, and a frame header sop signal, a frame tail eop signal, a frame data valid indication dval signal and the target signal are generated according to the adjustment result.

5. A non-perceptual network cable information collection system, It is characterized in that The system comprises: An isolation circuit unit is used to obtain an initial signal of a network device; perform signal level coupling on the initial signal to obtain an enhanced signal; and isolate the enhanced signal from the PHY chip; the isolation circuit unit includes an Ethernet transformer and a TVS device; A PHY processing unit is used to collect the enhanced signal by differential transmission to obtain a target differential signal; the PHY processing unit is used to receive the enhanced signal and collect data from the network device; The FPGA processing unit is used to perform information analysis according to the target differential signal, add a time mark to the signal obtained after the analysis according to the timing situation, and then re-encapsulate it to obtain the target signal; A CPU processing unit, used for performing device configuration and / or information collection management according to the target signal; The PHY processing unit is used to collect the enhanced signal by differential transmission to obtain a target differential signal, including: The PHY processing unit collects and obtains an initial differential signal obtained by differential transmission; The filter signal is obtained by coupling filtering through the differential mode coupling coil at the transformer end; The filtered signal generates an electromagnetic field after passing through the coil. According to the change of the electromagnetic field, the filtered signal is converted and coupled to the opposite coil of the transformer, and the target differential signal is obtained through the output of the opposite coil.

6. According to the non-perceptual network cable information collection system of claim 5, It is characterized in that The FPGA processing unit comprises: An RGMII interface module, configured to obtain a clock signal, and perform phase adjustment on the clock signal according to the target differential signal to obtain a first data signal; the first data signal is aligned with the target differential signal; A MAC receiving module, used to determine the working parameters of the Ethernet link, check the MAC frame length and cyclic redundancy check code of the target differential signal according to the working parameters and the first data signal, and obtain the data packet of the target signal according to the check result output; The MAC sending module is used to perform a secondary check on the cyclic redundancy check code during the sending process of the data packet through a preset control bit, and / or add a pause frame during the sending process of the data packet.

7. The non-perceptual network cable information collection system according to claim 6, It is characterized in that The FPGA processing unit also includes: An FCS signal removal module, used to remove the frame check sequence signal in the data packet; The Ethernet packet header parsing module is used to parse the frame structure of the data packet after the elimination process, obtain the source MAC address information, source IP information and Ethernet packet protocol type; and add the time mark to the target signal in the data packet.

8. A non-sensing network cable information collection device, It is characterized in that include: at least one processor; at least one memory for storing at least one program; When the at least one program is executed by the at least one processor, the at least one processor runs the method for collecting network cable information without perception as described in any one of claims 1 to 4.

9. A storage medium storing a program executable by a processor, It is characterized in that The program executable by the processor is used to run a method for collecting network cable information without perception as described in any one of claims 1 to 4 when executed by the processor.

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