Band tilt correction using combined signal and image passive mixers

Abstract

Certain aspects provide a circuit for frequency translation. The circuit includes first mixer circuitry coupled to a load circuit and having a first mixer configured to generate, based on a first differential input signal and a second differential input signal, a first portion of a frequency translated differential signal to be provided to the load circuit, and a second mixer configured to generate, based on a third differential input signal and a fourth differential input signal, a second portion of the frequency translated differential signal. The circuit also includes second mixer circuitry coupled to another load circuit and having a third mixer configured to generate, based on the first differential input signal and the fourth differential input signal, a first portion of another frequency translated differential signal, and a fourth mixer configured to generate, based on the third differential input signal and the second differential input signal, a second portion of the another frequency translated differential signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit and priority of U.S. nonprovisional application No. 16 / 869,898, filed May 8, 2020, which has been assigned to its assignee and is expressly incorporated herein by reference in its entirety, as fully set forth below, and for all applicable purposes. Technical Field

[0003] Some aspects of this disclosure generally relate to electronic circuits, and more specifically to a circuit system for frequency conversion. Background Technology

[0004] A wireless communication network may include multiple base stations, which can support communication with multiple mobile stations. A mobile station (MS) can communicate with a base station (BS) via downlink and uplink. A downlink (or forward link) refers to the communication link from the base station to the mobile station, and an uplink (or reverse link) refers to the communication link from the mobile station to the base station. The base station can transmit data and control information to the mobile station on the downlink, and / or can receive data and control messages from the mobile station on the uplink. The base station and / or mobile station may include one or more mixers for generating frequency-converted signals. For example, a baseband signal can be up-converted to a radio frequency (RF) signal for transmission, and a received RF signal can be down-converted back to baseband for processing. Summary of the Invention

[0005] Some aspects provide a circuit for frequency conversion. The circuit includes: a first mixer circuit system coupled to a load circuit and having: a first mixer configured to generate a first portion of a frequency-converted differential signal to be provided to the load circuit based on a first differential input signal and a second differential input signal; and a second mixer configured to generate a second portion of the frequency-converted differential signal based on a third differential input signal and a fourth differential input signal. The circuit also includes: a second mixer circuit system coupled to another load circuit and having: a third mixer configured to generate a first portion of another frequency-converted differential signal based on the first differential input signal and the fourth differential input signal; and a fourth mixer configured to generate a second portion of another frequency-converted differential signal based on the third differential input signal and the second differential input signal.

[0006] Some aspects provide a method for frequency conversion. The method typically includes: generating a first portion of a frequency-converted differential signal based on a first differential input signal and a second differential input signal via a first mixer of a first mixer circuit system; generating a second portion of the frequency-converted differential signal based on a third differential input signal and a fourth differential input signal via a second mixer of the first mixer circuit system; and providing the first and second portions of the frequency-converted differential signal to a load circuit. The method may further include: generating a first portion of another frequency-converted differential signal based on the first and fourth differential input signals via a third mixer of a second mixer circuit system; generating a second portion of another frequency-converted differential signal based on the third and second differential input signals via a fourth mixer of the second mixer circuit system; and providing the first and second portions of the other frequency-converted differential signal to another load circuit.

[0007] Some aspects provide an apparatus for frequency conversion. The method typically includes: components for generating a first portion of a frequency-converted differential signal based on a first differential input signal and a second differential input signal; components for generating a second portion of the frequency-converted differential signal based on a third differential input signal and a fourth differential input signal; and components for combining the first and second portions of the frequency-converted differential signal and providing the frequency-converted differential signal to a load circuit. The apparatus may further include: components for generating a first portion of another frequency-converted differential signal based on the first and fourth differential input signals; components for generating a second portion of another frequency-converted differential signal based on the third and second differential input signals; and components for combining the first and second portions of the other frequency-converted differential signal and providing the other frequency-converted differential signal to another load circuit. Attached Figure Description

[0008] To enable a detailed understanding of the foregoing features of this disclosure, a more specific description, briefly summarized above, can be obtained by referring to various aspects, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only certain typical aspects of this disclosure and should not be considered as limiting its scope, as the description may acknowledge other equally valid aspects.

[0009] Figure 1 This is a diagram of an exemplary wireless communication network according to certain aspects of this disclosure.

[0010] Figure 2 This is a block diagram of an exemplary access point (AP) and an exemplary user terminal according to certain aspects of this disclosure.

[0011] Figure 3This is a block diagram of an exemplary transceiver front end according to certain aspects of this disclosure.

[0012] Figure 4 An exemplary upconversion circuit system according to certain aspects of this disclosure is illustrated.

[0013] Figure 5 It is a graph illustrating the impedance band tilt associated with baseband (BB) and radio frequency (RF) signals.

[0014] Figure 6 The diagram illustrates an upconversion circuit system that uses a signal mixer and an image mixer in parallel according to certain aspects of this disclosure.

[0015] Figure 7 The illustration shows a main mixer and a picture mixer according to certain aspects of this disclosure.

[0016] Figure 8 The diagram illustrates the impedances of the BB and RF signals associated with the main mixer and the image mixer according to certain aspects of this disclosure.

[0017] Figure 9 This is a table illustrating various design options for the BB signal input to the image mixer according to certain aspects of this disclosure.

[0018] Figure 10 The illustration shows an upconversion circuit system according to certain aspects of this disclosure, which includes a signal mixer and an image mixer that receive local oscillator (LO) signals in different sequences.

[0019] Figure 11 The illustration shows an upconversion circuit system coupled to a drive amplifier (DA) and a dummy load, according to certain aspects of this disclosure.

[0020] Figure 12 The illustration shows an upconversion circuit system coupled to a capacitor element associated with a DA, according to certain aspects of this disclosure.

[0021] Figure 13 This is a flowchart illustrating an exemplary operation for frequency conversion according to certain aspects of this disclosure. Detailed Implementation

[0022] Various aspects of this disclosure are described more fully below with reference to the accompanying drawings. However, this disclosure may be implemented in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure is comprehensive and complete, and will fully communicate the scope of this disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art should understand that the scope of this disclosure is intended to cover any aspect of this disclosure disclosed herein, whether implemented independently of or in combination with any other aspect of this disclosure. For example, an apparatus may be implemented, or a method may be practiced, using any number of aspects set forth herein. Furthermore, the scope of this disclosure is intended to cover such apparatus or methods practiced using other structures, functionalities, or structures and functionalities that are additional to or different from the aspects of this disclosure set forth herein. It should be understood that any aspect of this disclosure disclosed herein may be implemented by one or more elements of the claims.

[0023] The word “exemplary” is used in this document to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” should not be construed as preferred or advantageous over other aspects.

[0024] As used herein, the term "connected with" in various tenses of the verb "connect" can mean that element A is directly connected to element B, or that other elements can be connected between element A and B (i.e., element A is indirectly connected to element B). In the case of electrical components, the term "connected with" can also be used herein to indicate that wires, traces, or other conductive materials are used to electrically connect element A and B (and any component is electrically connected therebetween).

[0025] Exemplary wireless system

[0026] Figure 1 The illustration shows a wireless communication system 100 with access point 110 and user terminal 120, which can be implemented according to various aspects of this disclosure. For simplicity, only one access point 110 is shown. Figure 1 As shown in the diagram. An access point (AP) is typically a fixed station that communicates with a user terminal and may also be referred to as a base station (BS), evolved Node B (eNB), or other terms. A user terminal (UT) can be fixed or mobile and may also be referred to as a mobile station (MS), access terminal, user equipment (UE), station (STA), client, wireless device, or other terms. A user terminal can be a wireless device such as a cellular phone, personal digital assistant (PDA), handheld device, wireless modem, laptop computer, tablet computer, personal computer, etc.

[0027] Access point 110 can communicate with one or more user terminals 120 on both the downlink and uplink at any given time. The downlink (i.e., the forward link) is the communication link from the access point to the user terminal, and the uplink (i.e., the reverse link) is the communication link from the user terminal to the access point. User terminals can also communicate point-to-point with other user terminals. System controller 130 is coupled to the access point and provides coordination and control for it.

[0028] System 100 uses multiple transmit antennas and multiple receive antennas to transmit data on the downlink and uplink. Access point 110 can be equipped with a number N ap One antenna is used to achieve transmit diversity for downlink transmission and / or receive diversity for uplink transmission. The selected set N of user terminals 120... u It can receive downlink transmissions and transmit uplink transmissions. Each selected user terminal transmits user-specific data to and / or receives user-specific data from the access point. Typically, each selected user terminal can be equipped with one or more antennas (i.e., N). ut ≥1). N u Each selected user terminal can have the same or different number of antennas.

[0029] Wireless system 100 can be a time-division duplex (TDD) system or a frequency-division duplex (FDD) system. For a TDD system, the downlink and uplink share the same frequency band. For an FDD system, the downlink and uplink use different frequency bands. System 100 can also use single-carrier or multi-carrier transmission. Each user terminal 120 can be equipped with a single antenna (e.g., to reduce cost) or multiple antennas (e.g., where additional costs can be supported). In some aspects of this disclosure, access point 110 and / or user terminal 120 may include one or more mixers configured to provide a symmetrical frequency response, as described in more detail herein.

[0030] Figure 2 A block diagram of an access point 110 and two user terminals 120m and 120x in a wireless system 100 is shown. Access point 110 is equipped with N... ap Each antenna is 224a to 224ap. The user terminal 120m is equipped with N... ut,m Each antenna is 252 mA to 252 mA, and the user terminal 120x is equipped with N ut,xEach antenna ranges from 252xa to 252xu. Access point 110 is a transmitting entity for the downlink and a receiving entity for the uplink. Each user terminal 120 is a transmitting entity for the uplink and a receiving entity for the downlink. As used herein, a “transmitting entity” is an independently operating device or apparatus capable of transmitting data via a frequency channel, and a “receiving entity” is an independently operating device or apparatus capable of receiving data via a frequency channel. In the following description, the subscript “dn” denotes the downlink, the subscript “up” denotes the uplink, and N... up N user terminals are selected to transmit simultaneously on the uplink. dn N user terminals are selected to transmit simultaneously on the downlink. up It can be equal to or not equal to N dn And N up and N dn These values ​​can be static or can be changed for each scheduling interval. Beam control or other spatial processing techniques can be used at the access point and user terminal.

[0031] On the uplink, at each user terminal 120 selected for uplink transmission, the TX data processor 288 receives traffic data from the data source 286 and control data from the controller 280. The TX data processor 288 processes (e.g., encoding, interleaving, and modulation) the traffic data {d} for the user terminal based on the coding and modulation scheme associated with the rate selected for the user terminal. up}, and is N ut,m One of the antennas provides a data symbol stream {s} up The transceiver front-end (TX / RX) 254 (also known as the radio frequency front-end (RFFE)) receives and processes (e.g., converts to analog, amplifies, filters, and up-converts) the corresponding symbol stream to generate an uplink signal. For example, the transceiver front-end 254 can also route the uplink signal to N... ut,m One of the antennas is used for transmit diversity via a radio frequency (RF) switch. Controller 280 can control routing within transceiver front end 254. Memory 282 can store data and program code for user terminal 120 and can interface with controller 280.

[0032] Quantity N up One user terminal 120 can be scheduled to transmit simultaneously on the uplink. Each of these user terminals transmits its processed set of symbol streams to the access point on the uplink.

[0033] At access point 110, N ap Each antenna 224a to 224ap transmits N data from the uplink. upEach user terminal receives uplink signals. For receive diversity, transceiver front-end 222 can select signals received from one of antennas 224 for processing. Signals received from multiple antennas 224 can be combined for enhanced receive diversity. The transceiver front-end 222 of the access point also performs processing complementary to that performed by the transceiver front-end 254 of the user terminal and provides a recovered uplink data symbol stream. The recovered uplink data symbol stream is the data symbol stream {s} transmitted by the user terminal. up The RX data processor 242 processes (e.g., demodulates, deinterlaces, and decodes) the recovered uplink data symbol stream according to the rate used to obtain decoded data from the stream. Decoded data from each user terminal can be provided to the data sink 244 for storage and / or to the controller 230 for further processing. In some aspects, the transceiver front-end (TX / RX) 222 of access point 110 and / or the transceiver front-end 254 of user terminal 120 may include one or more mixers configured to provide a symmetrical frequency response, as described in more detail herein.

[0034] On the downlink, at access point 110, TX data processor 210 receives service data from data source 208 for scheduling for downlink transmission. dn Each user terminal receives control data from controller 230 and other possible data from scheduler 234. Various types of data can be transmitted on different transport channels. TX data processor 210 processes (e.g., encoding, interleaving, and modulation) the service data of each user terminal based on the rate selected for that user terminal. TX data processor 210 can process the service data to be transmitted from N... ap One of the antennas transmits N. dn One or more user terminals among the user terminals provide a downlink data symbol stream. Transceiver front-end 222 receives and processes (e.g., converts to analog, amplifies, filters, and up-converts the symbol stream) to generate a downlink signal. For example, transceiver front-end 222 can also route the downlink signal to N ap One or more antennas of antenna 224 are used for transmit diversity via an RF switch. Controller 230 can control routing within transceiver front end 222. Memory 232 can store data and program code of access point 110 and can interface with controller 230.

[0035] At each user terminal 120, N ut,mAntenna 252 receives downlink signals from access point 110. For receive diversity at user terminal 120, transceiver front-end 254 can selectively process signals received from one of the antennas 252. Signals received from multiple antennas 252 can be combined for enhanced receive diversity. The transceiver front-end 254 of the user terminal also performs processing complementary to that performed by the transceiver front-end 222 of the access point and provides a recovered downlink data symbol stream. RX data processor 270 processes (e.g., demodulation, deinterlacing, and decoding) the recovered downlink data symbol stream to obtain decoded data for the user terminal.

[0036] Figure 3 This is a block diagram of an exemplary transceiver front-end 300 that can be practiced in various aspects of this disclosure, such as... Figure 2 The transceiver front-ends 222 and 254 are described in the text. The transceiver front-end 300 includes a transmit (TX) path 302 (also referred to as a transmit chain) for transmitting signals via one or more antennas and a receive (RX) path 304 (also referred to as a receive chain) for receiving signals via antennas. When the TX path 302 and RX path 304 share antenna 303, the paths can be connected to the antenna via interface 306, which can include any of a variety of suitable RF devices, such as a duplexer, switch, or combiner.

[0037] Receiving in-phase (I) or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC) 308, the TX path 302 may include a baseband filter (BBF) 310, a mixer 312, a driver amplifier (DA) 314, and a power amplifier (PA) 316. The BBF 310, mixer 312, and DA 314 may be included in a radio frequency integrated circuit (RFIC), while the PA 316 may be located outside the RFIC. The BBF 310 filters the baseband signal received from the DAC 308, and the mixer 312 mixes the filtered baseband signal with a transmission local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., up-conversion from baseband to RF). This frequency conversion process produces the sum and difference frequencies of the LO frequency and the signal frequency of interest. The sum and difference frequencies are referred to as the beat frequencies. The beat frequency is typically in the RF range, so the signal output from mixer 312 is usually an RF signal, which can be amplified by DA 314 and / or PA 316 before being transmitted by antenna 303. In some respects, mixer 312 can be configured to provide a symmetrical frequency response, as described in more detail herein.

[0038] The RX path 304 includes a low-noise amplifier (LNA) 322, a mixer 324, and a baseband filter (BBF) 326. The LNA 322, mixer 324, and BBF 326 may or may not be included in a radio frequency integrated circuit (RFIC), which may or may not be the same RFIC that includes the TX path components. The RF signal received via antenna 303 can be amplified by the LNA 322, and the mixer 324 mixes the amplified RF signal with a received local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (i.e., down-conversion). The baseband signal output from the mixer 324 can be filtered by the BBF 326 before being converted into digital I or Q signals by an analog-to-digital converter (ADC) 328 for digital signal processing.

[0039] While it is desirable for the LO output to remain stable in frequency, tuning the LO to different frequencies typically requires the use of a frequency converter oscillator, which may involve a trade-off between stability and tunability. Modern systems may use a frequency synthesizer with a voltage-controlled oscillator (VCO) to generate a stable, tunable LO with a specific tuning range. Therefore, the transmit LO frequency can be generated by the TX frequency synthesizer 318, and this transmit LO frequency can be buffered or amplified by the amplifier 320 before being mixed with the baseband signal in the mixer 312. Similarly, the receive LO frequency can be generated by the RX frequency synthesizer 330, and this receive LO frequency can be buffered or amplified by the amplifier 332 before being mixed with the RF signal in the mixer 324.

[0040] although Figures 1 to 3 A wireless communication system is provided as an exemplary application to facilitate understanding, in which certain aspects of this disclosure may be implemented, but certain aspects described herein may be used in up-conversion and down-conversion in any of a variety of other suitable systems.

[0041] Exemplary techniques for frequency band tilt correction

[0042] Certain aspects of this disclosure generally relate to frequency-converting passive mixers (e.g., for up-conversion or down-conversion) configured to reduce bandtilt associated with the mixer's radio frequency (RF) output. The transmitter uses an up-conversion mixer to convert a baseband (BB) signal to RF. Voltage-mode passive mixers provide a linear response. In some embodiments, harmonic suppression mixers can be used to reduce spurious tone by implementing BB or LO signals with different phases (e.g., lag or lead). For example, the BB signal and the local oscillator (LO) signal can be input to a mixer with a combined output. In some cases, the delay between the LO phases may be fixed (or lag), and the delay between the BB phases may vary (e.g., lag or lead), thus providing the transceiver with upper sideband (USB) or lower sideband (LSB) operation as described in more detail herein. The BB signal provided to a mixer with a lagging phase can provide USB, and the BB signal provided to a mixer with a leading phase can provide LSB.

[0043] Figure 4 An exemplary upconversion circuit system 400 according to certain aspects of this disclosure is illustrated. As illustrated, the upconversion circuit system 400 includes mixers 402, 404, 406, and 408 that receive BB frequency signals BBF0, BBF1, BBF2, BBF3, BBF4, BBF5, BBF6, and BBF7, and LO signals LO0, LO1, LO2, LO3, LO4, LO5, LO6, and LO7. For example, mixer 402 may receive LO0 and LO4 and BBF0 and BBF4, mixer 404 may receive LO1 and LO5 and BBF1 and BBF5, mixer 406 may receive LO2 and LO6 and BBF2 and BBF6, and mixer 408 may receive LO3 and LO7 and BBF7 and BBF3. The first outputs (e.g., positive outputs) of mixers 402, 404, 406, and 408 can be coupled to input node 410 of DA 314, and the second outputs (e.g., negative outputs) of mixers 402, 404, 406, and 408 can be coupled to input node 412 of DA 314. Input nodes 410 and 412 can form a differential input pair of DA 314. Although the exemplary upconversion circuit system 400 illustrates four mixers for upconversion for ease of understanding, the aspects described herein are applicable to upconversion or downconversion using two or more mixers.

[0044] In some cases, the BB frequency signals BBF0, BBF1, BBF2, BBF3, BBF4, BBF5, BBF6, and BBF7 may have a lagging phase. For example, the phase of BBF0 may lag behind the phase of BBF1, the phase of BBF1 may lag behind the phase of BBF2, and so on. In some cases, the LO signals LO0, LO1, LO2, LO3, LO4, LO5, LO6, and LO7 may have a leading phase. For example, the phase of LO0 may lead the phase of LO1, and the phase of LO1 may lead the phase of LO2, and so on. In this way, glitches associated with the upconverter circuit system can be reduced. However, as described in more detail herein, a passive mixer implemented in this way may experience band tilt in the operating frequency band.

[0045] Figure 5 This is graph 500, which illustrates the impedance band tilt associated with the BB and RF signals. Line 502 represents the impedance (Z) associated with the BB signal. BB ), and line 504 represents the impedance (Z) associated with the RF signal. RF The RF signal is generated by up-converting the BB signal.

[0046] From a frequency domain perspective, the mixer input impedance Z BB It is the RF impedance (Z) RF The frequency conversion version of ) . RF load capacitance (e.g., the gate-to-source capacitance of the transistor in the DA 314) may cause Z BB The presence of complex capacitance introduces an asymmetric transfer function around the RF frequency, resulting in a frequency band tilt, as illustrated. In other words, for a capacitive load, with the LO signals lagging behind each other in phase, the LSB impedance amplitude is greater than the USB impedance amplitude, as described in the example above. Without Z... BB In the case of associated complex impedance, the BB transfer function can correspond to a low-pass filter (LPF), and the BB signal can be up-converted to a frequency around ω. LO Symmetric bandpass filter (BPF), ω LO It is the angular frequency associated with the LO frequency.

[0047] Certain aspects of this disclosure provide an architecture for reducing bandwidth tilt using a parallel combination of signal and image mixers. For example, the architecture described herein provides a circuit system for frequency conversion that can provide a more symmetrical frequency response compared to conventional implementations.

[0048] Figure 6An upconversion circuit system 600 using a signal mixer and an image mixer in parallel according to certain aspects of this disclosure is illustrated. For example, the upconversion circuit system 600 includes a main mixer 602 (also referred to herein as a "signal mixer") and an image mixer 604. (As opposed to...) Figure 4 The described main mixer 602 may include mixers 402, 404, 406, and 408. As illustrated, an LO signal 606 may be provided to the main mixer 602 and the image mixer 604. The main mixer 602 receives BB signals 608, and the image mixer 604 receives BB signals 610. Each BB signal in BB signals 610 may correspond to one BB signal in BB signals 608, but in a different order. For example, BB signals 608 may correspond sequentially to BBF0, BBF1, BBF2, BBF3, BBF4, BBF5, BBF6, and BBF7, and BB signals 610 may correspond sequentially to BBF7, BBF6, BBF5, BBF4, BBF3, BBF2, BBF1, and BBF0. As illustrated, the output of mixer 604 may be coupled to an RF dummy load 670 via input nodes 672 and 674. For example, the impedance of the RF dummy load 670 can be configured to match the impedance associated with the DA 314.

[0049] Figure 7 The diagram illustrates a main mixer 602 and a picture mixer 604 according to certain aspects of this disclosure. As illustrated, the picture mixer 604 may include mixers 702, 704, 706, and 708. As illustrated, two mixers 402 and 702 can receive LO0 and LO4, two mixers 404 and 704 can receive LO1 and LO5, two mixers 406 and 706 can receive LO2 and LO6, and two mixers 408 and 708 can receive LO3 and LO7. Mixer 402 of the main mixer 602 can receive BBF0 and BBF4, mixer 404 of the main mixer 602 can receive BBF1 and BBF5, mixer 406 of the main mixer 602 can receive BBF2 and BBF6, and mixer 408 of the main mixer 602 can receive BBF3 and BBF7.

[0050] As described, mixer 604 can receive the same BB signals as mixer 602, but in a different order. For example, while mixers 402 and 702 receive the same LO signals (LO0, LO4), mixer 402 receives BBF0 and BBF4, and mixer 702 receives BBF3 and BBF7. Furthermore, mixer 704 receives BBF2 and BBF6, mixer 706 receives BBF1 and BBF5, and mixer 708 receives BBF0 and BBF4.

[0051] Figure 8 The diagram illustrates the impedances of the BB and RF signals associated with the main mixer and the image mixer according to certain aspects of this disclosure. Line 502 represents the Z-axis of the main mixer 602. BB And line 504 indicates the Z-axis of the main mixer 602. RF The RF load of the main mixer 602 is converted to BB, thereby generating Z represented by line 502. BB As illustrated. Furthermore, line 802 represents the Z-axis of the image mixer 604. RF It can be converted to BB, thus causing the Z of the image mixer 604 represented by line 804 to be... BB As illustrated, the Z-axis of the image mixer 604... RF Compared to the increase in frequency, the Z-axis of the main mixer... RF The frequency decreases relative to the input frequency. Therefore, the Z-axis, generated by the combination of the RF impedance of the image mixer and the main mixer and converted to BB, is... BB This results in a symmetrical BB impedance of 806.

[0052] Figure 9 Table 900 illustrates various design options for the BB signal input to the image mixer 604 according to certain aspects of this disclosure. In Table 900, the number of different phases of the BB signal is N, where N is an integer equal to or greater than 4. For example, as illustrated in Table 900, if the BB signal provided to the main mixer and the image mixer has 8 different phases (N = 8), a first option may include providing the LO and BB signals in the order from LO0 to LO7 and BBF0 to BBF7, and providing the BB signal to the image mixer in reverse order from BB7 to BBF0. As a second option, the BB signal may be provided to the image mixer in the order of BBF6, BBF5, BBF4, BBF3, BBF2, BBF1, BBF0, and BBF7. As a third option, the BB signal may be provided to the image mixer in the order of BBF5, BBF4, BBF3, BBF2, BBF1, BBF0, BBF6, and BBF7. In some respects, the change in signal order can be applied to the LO signal of the image mixer while keeping the order of the BB signals supplied to the image mixer and the main mixer unchanged.

[0053] Figure 10 The illustration shows an upconversion circuit system 1000 for a signal mixer and an image mixer that receive LO signals in different orders, according to certain aspects of this disclosure. As illustrated, a main mixer 602 can receive LO signal 606, and an image mixer 604 can receive LO signal 1002. LO signal 1002 can correspond to LO signal 606, but in a different order. As illustrated, the BB signals provided to the main mixer 602 and the image mixer 604 can be in the same order.

[0054] Exemplary techniques for reducing common-mode spurs

[0055] The techniques described herein for providing a symmetrical frequency response may generate common-mode glitches, which can be fed into a DA 314 and converted at the output of the DA 314 into a differential-mode four-times-modulation-frequency (4FMOD) primary (4FMODP) signal. 4FMODP refers to a signal located at the LO frequency minus three times the BB frequency (LO-3BB). The differential-mode signal at 4FMODP may fall within a frequency band protected by specifications and should be reduced. Certain aspects of this disclosure relate to techniques for reducing common-mode glitches, thereby achieving a reduction in the 4FMODP signal.

[0056] Figure 11 An upconversion circuit system 600 coupled to a DA and a dummy load according to certain aspects of this disclosure is illustrated. As illustrated, the RF load may be a DA 314 implemented using only n-type metal-oxide-semiconductor (NMOS) transistors. NMOS DAs consume less power and area compared to other types of DAs (e.g., complementary metal-oxide-semiconductor (CMOS) DAs). For example, DA 314 may include an NMOS transistor 1102 (having a gate coupled to the output of mixer 602, e.g., via AC coupling capacitor element 1140) and an NMOS transistor 1104 (having a gate coupled to another output of mixer 602, e.g., via AC coupling capacitor element 1142).

[0057] As illustrated, the upconversion circuit system 600 may include filters 1120, each having a resistor-capacitor (RC) circuit, as shown. Each filter in 1120 can receive positive and negative differential input signals 1122 and a negative differential input signal 1124. The outputs of filters 1120 are coupled to the BB inputs of the main mixer 602 and the image mixer 640. As described herein, the BB signals can be provided to the main mixer 602 and the image mixer 604 in different orders to provide a symmetrical frequency response. For example, at the LSB of the BB (LSB... BB ) and BB's USB (USB) BB When operating on the main mixer 602 and the image mixer 604, the input impedances can be the same.

[0058] As described, certain aspects of this disclosure relate to techniques for reducing common-mode glitches, thereby achieving a reduction in 4FMODP signals. For example, the dummy load 670 can be implemented as a common-mode trap circuit to suppress common-mode glitches at the residual sideband (RSB) of the upconverter circuit system. Specifically, the dummy load 670 can include capacitor elements 1130 and 1132 coupled to corresponding output nodes of the image mixer 604. In some aspects, node 1136 between capacitor elements 1130 and 1132 can be floating. In other words, a first terminal of capacitor elements 1130 and 1132 can be coupled to a corresponding output node of the image mixer 604, while a second terminal of the capacitor elements can be coupled together at node 1136. In other aspects, the node between capacitor elements 1130 and 1132 can be coupled to a reference potential node (e.g., electrical ground) via an impedance element 1134 having a relatively large impedance. For example, impedance element 1134 can be implemented using a resistive element, an inductive element, or both a resistive element and an inductive element.

[0059] In some respects, each of the capacitor elements 1130, 1132 can be implemented via a transistor. The bulk of the transistor can be coupled to node 1136 and floated or coupled to electrical ground via impedance element 1134 to form a common-mode trap. Impedance element 1134 can facilitate the biasing of the transistor implementing capacitor elements 1130, 1132.

[0060] Figure 12 An upconversion circuit system 600, according to certain aspects of this disclosure, is illustrated, coupled to capacitor elements 1202, 1204 associated with DA 314. For example, capacitor element 1202 may correspond to the gate-to-source capacitance of transistor 1102, and capacitor element 1204 may correspond to the gate-to-source capacitance of transistor 1104. As illustrated, the output of the upconversion circuit system 600 is coupled to capacitor elements 1130, 1132 (labeled “Ctilt”). As described herein, the node between capacitor elements 1130, 1132 may be coupled to electrical ground via impedance element 1134.

[0061] Figure 13 This is a flowchart illustrating an exemplary operation 1300 for frequency conversion according to certain aspects of this disclosure. Operation 1300 can be performed by circuitry, such as an upconversion circuit system 600.

[0062] Operation 1300 begins at block 1302, where the circuit generates a first portion (e.g., at input node 410) of a frequency-converted differential signal based on a first differential input signal (e.g., LO0 and LO4) and second differential input information (e.g., BBF0 and BBF4) via a first mixer (e.g., mixer 402) of a first mixer circuit system (e.g., main mixer 602). At block 1304, the circuit can generate a second portion of the frequency-converted differential signal based on a third differential input signal (e.g., LO3 and LO7) and fourth differential input information (e.g., BBF3 and BBF7) via a second mixer (e.g., mixer 408) of the first mixer circuit system. At block 1306, the circuit combines the first and second portions of the frequency-converted differential signal and provides the frequency-converted differential signal to a load circuit (e.g., DA 314).

[0063] In some respects, the phase of the first input signal of the second differential input signal lags behind (or leads) the phase of the first input signal of the fourth differential input signal, and the phase of the second input signal of the second differential input signal lags behind (or leads) the phase of the second input signal of the fourth differential input signal.

[0064] At block 1308, the circuit can generate a first portion of another frequency-converted differential signal based on a first differential input signal (e.g., LO0 and LO4) and a fourth differential input information (e.g., BBF7 and BBF3) via a third mixer (e.g., mixer 702) of a second mixer circuit system (e.g., image mixer 604), and at block 1310, generate a second portion of another frequency-converted differential signal based on a third differential input signal (e.g., LO3 and LO7) and a second differential input information (e.g., BBF4 and BBF0) via a fourth mixer (e.g., mixer 708) of the second mixer circuit system. For example, the third mixer can be configured to generate the first portion of the other frequency-converted differential signal based on the inversion (e.g., in reverse order) of the fourth differential input signal of the second mixer, and the fourth mixer can be configured to generate the second portion of the other frequency-converted differential signal based on the inversion of the second differential input signal of the first mixer. At block 1312, the circuit combines the first and second portions of another frequency-converted differential signal and provides the other frequency-converted differential signal to another load circuit (e.g., dummy load 670).

[0065] In some aspects, a first differential input signal (e.g., BBF0 and BBF4) and a third differential input signal (e.g., BBF3 and BBF7) are frequency-transformed to generate a frequency-transformed differential signal, and a second differential input signal (e.g., LO0 and LO4) and a fourth differential input signal (e.g., LO3 and LO7) are differential LO signals. For example, the first and third differential input signals can be BB signals, and the second and fourth differential input signals can be differential LO signals. As another example, the second and fourth differential input signals can be BB signals, and the first and third differential input signals can be LO signals.

[0066] In some respects, the load circuit can be a primary load circuit, and the other load circuit can be a dummy load circuit. The primary load circuit can be a driver amplifier (DA).

[0067] In some aspects, the circuit may also generate a third portion of the frequency-converted differential signal based on a fifth differential input signal (e.g., LO1 and LO5) and a sixth differential input signal (e.g., BBF1 and BBF5) via a fifth mixer (e.g., mixer 404) of the first mixer circuit system, and a fourth portion of the frequency-converted differential signal based on a seventh differential input signal (e.g., LO2 and LO6) and an eighth differential input signal (e.g., BBF2 and BBF6) via a sixth mixer (e.g., mixer 406) of the first mixer circuit system. The circuit may combine the third and fourth portions with the first and second portions of the frequency-converted differential signal and provide the frequency-converted differential signal to the load circuit.

[0068] In some aspects, the circuit generates a third portion of another frequency-converted differential signal based on the fifth differential input signal (e.g., LO1 and LO5) and the eighth differential input signal (e.g., BBF6 and BBF2) via the seventh mixer (e.g., mixer 704) of the second mixer circuit system, and generates a fourth portion of the other frequency-converted differential signal based on the seventh differential input signal (e.g., LO2 and LO6) and the sixth differential input signal (e.g., BBF5 and BBF1) via the eighth mixer (e.g., mixer 706) of the second mixer circuit system. The circuit can combine the third and fourth portions with the first and second portions of the other frequency-converted differential signal before providing the other frequency-converted differential signal to another load circuit.

[0069] In some aspects, another load circuit may include a first capacitor element (e.g., capacitor element 1130) coupled to a first output of the second mixer circuit system and a second capacitor element (e.g., capacitor element 1132) coupled to a second output of the second mixer circuit system. In some cases, the node between the first and second capacitor elements is electrically floating. In some cases, the other load circuit may include an impedance element, wherein the node between the first and second capacitor elements is coupled to a reference potential node of the circuit (e.g., electrically grounded) through the impedance element.

[0070] In some aspects, the circuit may further amplify the frequency-converted differential signal via an amplifier (e.g., DA 314) having a first transistor (e.g., transistor 1102) coupled to a first output of the first mixer circuit system and a second transistor (e.g., transistor 1104) coupled to a second output of the first mixer circuit system. In some aspects, a first capacitor element has a first capacitance corresponding to the gate-to-source capacitance of the first transistor, and a second capacitor element has a second capacitance corresponding to the gate-to-source capacitance of the second transistor.

[0071] The various operations described above can be performed by any suitable component capable of performing the corresponding function. This component may include various hardware components (one or more) and / or modules (one or more), including but not limited to one or more circuits. Typically, in the presence of operations illustrated in the figures, these operations may have corresponding component plus functional components, which have similar numbering. For example, the component used for generation may include mixers such as mixers 402, 404, 406, 408, 702, 704, 706, and 708. Components used for combination (and provision) may include nodes with multiple branches (e.g., summing nodes), such as input nodes 410, 412, 672, and 674.

[0072] As used herein, the term "determine" encompasses a variety of actions. For example, "determine" can include calculating, computing, processing, deriving, investigating, searching (e.g., looking in a table, database, or other data structure), ascertaining, etc. Furthermore, "determine" can include receiving (e.g., receiving information), accessing (e.g., accessing data in memory), etc. Moreover, "determine" can include parsing, selecting, picking, building, etc.

[0073] As used herein, the phrase “at least one” in the list of referenced items refers to any combination of these items, including a single member. As an example, “at least one of the following: a, b, or c” is intended to cover: a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbb, cc, and ccc, or any other ordering of a, b, and c).

[0074] The various illustrative logic blocks, modules, and circuits described in this disclosure can be implemented or performed using discrete hardware components designed to perform the functions described herein.

[0075] The methods disclosed herein include one or more steps or actions for implementing the described methods. The method steps and / or actions may be interchanged without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0076] It should be understood that the claims are not limited to the precise configuration and components shown in the figures above. Various modifications, alterations, and variations may be made to the arrangement, operation, and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A circuit for frequency conversion, comprising: The first mixer circuit system is coupled to the load circuit and has the following characteristics: The first mixer is configured to generate a first portion of a frequency-converted differential signal to be provided to the load circuit based on a first differential input signal and a second differential input signal; as well as The second mixer is configured to generate a second portion of the frequency-converted differential signal to be provided to the load circuit based on the third differential input signal and the fourth differential input signal; as well as The second mixer circuit system is coupled to another load circuit and has the following characteristics: A third mixer is configured to generate a first portion of another frequency-converted differential signal to be provided to the other load circuit based on the first differential input signal and the fourth differential input signal, wherein the third mixer is configured to generate the first portion of the other frequency-converted differential signal based on the inversion of the fourth differential input signal of the second mixer; and A fourth mixer is configured to generate a second portion of the other frequency-converted differential signal to be provided to the other load circuit based on the third differential input signal and the second differential input signal, wherein the fourth mixer is configured to generate the second portion of the other frequency-converted differential signal based on the inversion of the second differential input signal of the first mixer.

2. The circuit according to claim 1, wherein: The phase of the first input signal of the second differential input signal is configured to lag behind the phase of the first input signal of the fourth differential input signal; and The phase of the second input signal of the second differential input signal is configured to lag behind the phase of the second input signal of the fourth differential input signal.

3. The circuit according to claim 1, wherein: The phase of the first input signal of the second differential input signal is configured to lead the phase of the first input signal of the fourth differential input signal; and The phase of the second input signal of the second differential input signal is configured to lead the phase of the second input signal of the fourth differential input signal.

4. The circuit of claim 1, wherein the first differential input signal and the third differential input signal are frequency-transformed to generate the frequency-transformed differential signal, and the second differential input signal and the fourth differential input signal include differential local oscillator (LO) signals.

5. The circuit of claim 1, wherein the second differential input signal and the fourth differential input signal are frequency-transformed to generate the frequency-transformed differential signal, and the first differential input signal and the third differential input signal include differential local oscillator (LO) signals.

6. The circuit according to claim 1, wherein: The first differential input signal and the third differential input signal include baseband (BB) signals, and the second differential input signal and the fourth differential input signal include differential local oscillator (LO) signals; or The second differential input signal and the fourth differential input signal include BB signals, and the first differential input signal and the third differential input signal include LO signals.

7. The circuit according to claim 1, wherein: The first mixer circuit system further includes: The fifth mixer is configured to generate a third portion of the frequency-converted differential signal to be provided to the load circuit based on the fifth and sixth differential input signals; and The sixth mixer is configured to generate the fourth portion of the frequency-converted differential signal based on the seventh and eighth differential input signals; and The second mixer circuit system also includes: A seventh mixer is configured to generate a third portion of the other frequency-converted differential signal to be provided to the other load circuit based on the fifth differential input signal and the eighth differential input signal; and The eighth mixer is configured to generate a fourth portion of the other frequency-converted differential signal based on the seventh differential input signal and the sixth differential input signal.

8. The circuit of claim 1, wherein the other load circuit comprises: The first capacitor element has a first terminal that is coupled to a first output of the second mixer circuit system; as well as The second capacitor element has a first terminal that is coupled to the second output of the second mixer circuit system.

9. The circuit of claim 8, wherein the node coupled to the second terminal of the first capacitor element and the second terminal of the second capacitor element is electrically floating.

10. The circuit of claim 8, wherein the other load circuit further comprises an impedance element coupled between a reference potential node and a node of the circuit, the node being coupled to a second terminal of the first capacitor element and a second terminal of the second capacitor element.

11. The circuit of claim 10, wherein the impedance element comprises at least one of a resistive element or an inductive element.

12. The circuit according to claim 8, wherein: The load circuit includes an amplifier having a first transistor and a second transistor, the first transistor being coupled to a first output of the first mixer circuit system, and the second transistor being coupled to a second output of the first mixer circuit system; The first capacitor element has a first capacitance corresponding to the gate-to-source capacitance of the first transistor; and The second capacitor element has a second capacitance corresponding to the gate-to-source capacitance of the second transistor.

13. A method for frequency conversion, comprising: The first mixer of the first mixer circuit system generates a first part of the frequency-converted differential signal based on the first differential input signal and the second differential input signal; The second part of the frequency-converted differential signal is generated by the second mixer of the first mixer circuit system based on the third differential input signal and the fourth differential input signal; The first and second portions of the frequency-converted differential signal are provided to the load circuit. A third mixer of the second mixer circuit system generates a first portion of another frequency-converted differential signal based on the first differential input signal and the fourth differential input signal, wherein generating the first portion of the other frequency-converted differential signal includes: generating the first portion of the other frequency-converted differential signal based on the inversion of the fourth differential input signal of the second mixer via the third mixer; A second portion of the other frequency-converted differential signal is generated via a fourth mixer of the second mixer circuit system, based on the third differential input signal and the second differential input signal. Generating the second portion of the other frequency-converted differential signal includes: generating the second portion of the other frequency-converted differential signal via the fourth mixer, based on the inversion of the second differential input signal of the first mixer; and The first and second portions of the other frequency-converted differential signal are provided to another load circuit.

14. The method of claim 13, wherein: The phase of the first input signal of the second differential input signal lags behind the phase of the first input signal of the fourth differential input signal; and The phase of the second input signal of the second differential input signal lags behind the phase of the second input signal of the fourth differential input signal.

15. The method according to claim 13, wherein: The phase of the first input signal of the second differential input signal leads the phase of the first input signal of the fourth differential input signal; and The phase of the second input signal of the second differential input signal leads the phase of the second input signal of the fourth differential input signal.

16. The method of claim 13, wherein the first differential input signal and the third differential input signal are frequency-transformed to generate the frequency-transformed differential signal, and the second differential input signal and the fourth differential input signal include differential local oscillator (LO) signals.

17. The method of claim 13, wherein the second differential input signal and the fourth differential input signal are frequency-transformed to generate the frequency-transformed differential signal, and the first differential input signal and the third differential input signal include differential local oscillator (LO) signals.

18. The method of claim 13, wherein: The first differential input signal and the third differential input signal include baseband (BB) signals, and the second differential input signal and the fourth differential input signal include differential local oscillator (LO) signals; or The second differential input signal and the fourth differential input signal include BB signals, and the first differential input signal and the third differential input signal include LO signals.

19. The method of claim 13, wherein the load circuit comprises a main load circuit, and wherein the other load circuit comprises a dummy load circuit.

20. The method of claim 19, wherein the main load circuit includes a driver amplifier (DA).

21. The method of claim 13, further comprising: The third part of the frequency-converted differential signal is generated by the fifth mixer of the first mixer circuit system based on the fifth differential input signal and the sixth differential input signal; The fourth part of the frequency-converted differential signal is generated by the sixth mixer of the first mixer circuit system based on the seventh and eighth differential input signals. The third and fourth portions of the frequency-converted differential signal are provided to the load circuit; The third part of the other frequency-converted differential signal is generated by the seventh mixer of the second mixer circuit system based on the fifth differential input signal and the eighth differential input signal; The fourth portion of the other frequency-converted differential signal is generated by the eighth mixer of the second mixer circuit system based on the seventh differential input signal and the sixth differential input signal; and The third and fourth portions of the other frequency-converted differential signal are provided to the other load circuit.

22. The method of claim 13, wherein the other load circuit comprises: The first capacitor element has a first terminal that is coupled to a first output of the second mixer circuit system; as well as The second capacitor element has a first terminal that is coupled to the second output of the second mixer circuit system.

23. The method of claim 22, wherein the node coupled to the second terminal of the first capacitor element and the second terminal of the second capacitor element is electrically floating.

24. The method of claim 22, wherein the other load circuit further comprises an impedance element coupled between a reference potential node and a node coupled to a second terminal of the first capacitor element and a second terminal of the impedance element.

25. The method according to claim 22, wherein: The method further includes: amplifying the frequency-converted differential signal via an amplifier having a first transistor and a second transistor, the first transistor being coupled to a first output of the first mixer circuit system, and the second transistor being coupled to a second output of the first mixer circuit system; The first capacitor element has a first capacitance corresponding to the gate-to-source capacitance of the first transistor; and The second capacitor element has a second capacitance corresponding to the gate-to-source capacitance of the second transistor.

26. An apparatus for frequency conversion, comprising: A component for generating a first portion of a frequency-converted differential signal based on a first differential input signal and a second differential input signal; A component for generating the second part of the frequency-converted differential signal based on the third differential input signal and the fourth differential input signal; A component for combining the first and second portions of the frequency-converted differential signal and providing the frequency-converted differential signal to a load circuit; A component for generating a first portion of another frequency-converted differential signal based on the first differential input signal and the fourth differential input signal, wherein the component for generating the first portion of the other frequency-converted differential signal includes a component for generating the first portion of the other frequency-converted differential signal based on the inversion of the fourth differential input signal. A component for generating a second portion of the other frequency-converted differential signal based on the third differential input signal and the second differential input signal, wherein the component for generating the second portion of the other frequency-converted differential signal includes a component for generating the second portion of the other frequency-converted differential signal based on the inversion of the second differential input signal; and A component for combining the first and second portions of the other frequency-converted differential signal and providing the other frequency-converted differential signal to another load circuit.

27. A circuit for frequency conversion, comprising: The first mixer circuit system is coupled to the load circuit and has the following characteristics: The first mixer is configured to generate a first portion of a frequency-converted differential signal to be provided to the load circuit based on a first differential input signal and a second differential input signal; as well as The second mixer is configured to generate a second portion of the frequency-converted differential signal based on the third differential input signal and the fourth differential input signal; as well as The second mixer circuit system is coupled to another load circuit and has the following characteristics: A third mixer is configured to generate a first portion of another frequency-converted differential signal based on the first differential input signal and the fourth differential input signal; as well as A fourth mixer is configured to generate a second portion of the other frequency-converted differential signal based on the third differential input signal and the second differential input signal, wherein the load circuit includes a main load circuit and wherein the other load circuit includes a dummy load circuit.

28. The circuit of claim 27, wherein the main load circuit includes a driver amplifier (DA).

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