A high linearity wideband input buffer

Abstract

The application discloses a high linearity wideband input buffer, which comprises a common-source and common-gate type source flip-flop configured as a pseudo differential structure, and comprises a positive end input transistor, a negative end input transistor, a positive end common-gate transistor and a negative end common-gate transistor, a positive end output transistor and a negative end output transistor; a cross-coupling input circuit is coupled between the drain of the positive end input transistor and the gate of the negative end common-gate transistor, and between the drain of the negative end input transistor and the gate of the positive end common-gate transistor; a mirror load circuit is connected between the gate of the positive end input transistor and the source of the positive end output transistor, and between the gate of the negative end input transistor and the source of the negative end output transistor; and a bias current source circuit is connected to the source ends of the positive end input transistor and the negative end input transistor. The buffer increases the loop gain of the common-source and common-gate type source flip-flop, reduces the output impedance, effectively improves the bandwidth of the input buffer, and ensures the linearity of the input buffer.

Description

Technical Field

[0001] This invention belongs to the field of analog-to-digital conversion technology, specifically relating to a high-linearity wideband input buffer. Background Technology

[0002] With the continuous development of artificial intelligence, wireless communication, and automotive electronics, the market has placed higher demands on high-frequency, high-quality signal transmission technologies. As the interface between analog front-end circuits and digital circuits, the accuracy and speed of the analog-to-digital converter (ADC) determine the final signal quality of the entire information acquisition system. Considering the influence of input impedance, designers generally choose between two types of high-speed ADCs: buffered and unbuffered. Although the power consumption of an unbuffered high-speed ADC is much lower than that of a buffered ADC, the sample-and-hold circuit directly connected to the external front-end in an unbuffered ADC introduces two problems: First, when the ADC switches between sample and hold modes, its input impedance changes with frequency and mode. Second, charge injection from internal sampling capacitors and networks can reflect a small amount of signal back to the front-end circuit and input signal, interfering with components connected to the ADC input. Therefore, to eliminate the adverse effects of these two problems on the overall performance of the ADC, an input buffer needs to be integrated into the ADC front-end. Considering the power consumption of the input buffer and the accuracy requirements of the ADC, the buffer design must have high linearity, large bandwidth, and low power consumption.

[0003] Currently, existing ADC front-end input buffers typically employ a Cascode architecture, using a multi-transistor stacking structure to ensure the linearity of the buffer transistors. However, multi-transistor stacking leads to a rise in the output common-mode voltage, making direct connection to the subsequent ADC impossible. Therefore, a negative voltage is usually introduced to reduce the output common-mode voltage. However, the introduction of a negative voltage introduces circuit stability issues and increases the complexity of circuit design. Furthermore, multi-transistor stacking increases the output resistance of the input buffer, reducing its bandwidth. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a high-linearity wideband input buffer. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] In a first aspect, this invention proposes a high-linearity wideband input buffer, comprising a cascode source-flipping follower, a cross-coupled input circuit, a mirror load circuit, and a bias current source circuit; wherein...

[0006] The common-source cascode source-flipping follower is configured as a pseudo-differential structure, including a positive input transistor, a negative input transistor, a positive common-gate transistor, a negative common-gate transistor, a positive output transistor, and a negative output transistor.

[0007] The cross-coupled input circuit is coupled between the drain of the positive input transistor and the gate of the negative common gate transistor, and between the drain of the negative input transistor and the gate of the positive common gate transistor.

[0008] The mirror load circuit is connected between the gate of the positive input transistor and the source of the positive output transistor, and between the gate of the negative input transistor and the source of the negative output transistor.

[0009] The bias current source circuit is connected to the drain of the positive input transistor and the negative input transistor.

[0010] In a second aspect, the present invention proposes a high-speed analog-to-digital converter, which includes a high-linearity wideband input buffer proposed in the first aspect of the present invention.

[0011] The beneficial effects of this invention are:

[0012] 1. The high linearity broadband input buffer proposed in this invention adds a common-source common-gate transistor to the traditional source-flipping follower circuit to form a common-source common-gate source-flipping follower. On the other hand, it designs an input cross-coupling circuit to increase the loop gain of the common-source common-gate source-flipping follower and reduce the output impedance, which effectively improves the bandwidth of the input buffer and ensures the linearity of the input buffer.

[0013] 2. The high linearity broadband input buffer proposed in this invention also features a mirrored load architecture, which reduces the current variation caused by changes in the input buffer load and further improves linearity.

[0014] 3. The bias current source designed in this invention adopts a low-voltage common-source common-gate architecture, which further ensures the current fluctuation caused by the load change of the input buffer and improves the linearity of the input buffer. In addition, the low-voltage common-source common-gate architecture also avoids the large burden of low power supply voltage, reduces power consumption, ensures output swing, and improves circuit stability.

[0015] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0016] Figure 1 A schematic diagram of a high linearity wideband input buffer provided in an embodiment of the present invention;

[0017] Figure 2 The circuit structure diagram of the common-source common-gate source-flipping follower provided in the embodiment of the present invention;

[0018] Figure 3A comparison diagram of a traditional source-flipping follower and a common-source, common-gate source-flipping follower;

[0019] Figure 4 This is a schematic diagram of the cross-coupled input circuit provided in an embodiment of the present invention;

[0020] Figure 5 This is a schematic diagram of the structure of the mirror load circuit provided in an embodiment of the present invention;

[0021] Figure 6 The circuit structure diagram of the bias current source provided in the embodiment of the present invention is shown. Detailed Implementation

[0022] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0023] Example 1

[0024] Please see Figure 1 , Figure 1 This is a schematic diagram of a high-linearity wideband input buffer provided in an embodiment of the present invention. The high-linearity wideband input buffer provided in this embodiment includes a common-source cascode source-flipping follower, a cross-coupled input circuit, a mirror load circuit, and a bias current source circuit; wherein,

[0025] The common-source cascode source-flip follower is configured as a pseudo-differential structure, including a positive input transistor, a negative input transistor, a positive common-gate transistor, a negative common-gate transistor, a positive output transistor, and a negative output transistor;

[0026] The cross-coupled input circuit is coupled between the drain of the positive input transistor and the gate of the negative common gate transistor, and between the drain of the negative input transistor and the gate of the positive common gate transistor.

[0027] The mirror load circuit is connected between the gate of the positive input transistor and the source of the positive output transistor, and between the gate of the negative input transistor and the source of the negative output transistor.

[0028] The bias current source circuit is connected to the drain of the positive input transistor and the negative input transistor.

[0029] Alternatively, as one implementation method, please refer to Figure 2 , Figure 2 This is a circuit diagram of a common-source cascode source-flipping follower provided in an embodiment of the present invention. In this embodiment, the common-source cascode source-flipping follower specifically includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6; wherein,

[0030] The first transistor M1 and the second transistor M2 serve as the positive and negative input transistors of a cascode source-flipping follower, respectively, with their gates being the signal input terminals.

[0031] The third transistor M3 and the fourth transistor M4 serve as the positive and negative output transistors of the cascode source-flipping follower, respectively, with their drains being the signal output terminals.

[0032] The fifth transistor M5 and the sixth transistor M6 serve as the positive and negative common gate transistors of a common-source flip-flop follower, respectively.

[0033] In this configuration, the source of the first transistor M1 is connected to the drain of the third transistor M3, and the source of the second transistor M2 is connected to the drain of the fourth transistor M4; the drain of the first transistor M1 is connected to the source of the fifth transistor M5, and the drain of the second transistor M2 is connected to the source of the sixth transistor M6; the gate of the third transistor M3 is connected to the drain of the fifth transistor M5, and the gate of the fourth transistor M4 is connected to the drain of the sixth transistor M6.

[0034] The present invention proposes a high-linearity broadband input buffer. On the one hand, a common-source cascode transistor is added to the traditional source-flipping follower circuit to form a common-source cascode source-flipping follower. On the other hand, an input cross-coupling circuit is designed to increase the loop gain of the common-source cascode source-flipping follower and reduce the output impedance, thereby effectively improving the bandwidth of the input buffer and ensuring the linearity of the input buffer.

[0035] Understandably, the pseudo-differential cascode source-flipping follower also includes a tail current source.

[0036] Optionally, as one implementation method, this embodiment uses two tail current transistors M. S1 and M S2 To implement a tail current source, such as Figure 1 Or as shown in Figure 2, where,

[0037] Tail current tube M S1 and M S2 The drains of the transistors are connected to the sources of the positive and negative output transistors, respectively, and the gates of both transistors are connected to the first bias voltage V. B The source electrode is grounded.

[0038] Specifically, in the common-source common-gate source-flipping follower structure provided in this embodiment, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 constitute the main circuit of the common-source common-gate source-flipping follower, and the fifth transistor M5 and the sixth transistor M6 are connected to the active feedback loop as common gate transistors, which effectively improves the loop gain.

[0039] The common-source cascode source-flipping follower of the present invention will be compared with a conventional source-flipping follower to illustrate in detail the advantages of the common-source cascode source-flipping follower designed in the present invention in improving loop gain.

[0040] Please see Figure 3 , Figure 3 The diagrams show a comparison between a traditional source-flipping follower and a common-source, common-gate source-flipping follower. The left diagram shows the structure of the traditional source-flipping follower, and the right diagram shows the common-source, common-gate source-flipping follower of this invention. Compared to the traditional source-flipping follower circuit shown in the left diagram, the circuit structure proposed in this invention adds transistor M6 as a common-source, common-gate transistor in the active feedback loop. If the loop is broken at the gate of transistor M4 in both circuit structures, and the corresponding loop gain is calculated, the following formula can be obtained:

[0041] ;

[0042] ;

[0043] In the formula, T conv This represents the loop gain of a traditional source-flipping follower circuit. g m4 This indicates the transconductance of transistor M4. g m2 This indicates the transconductance of transistor M2. r o2 This indicates the output resistance of transistor M2. r o4 This indicates the output resistance of transistor M4; T conv This indicates the loop gain of the common-source, common-gate source-flipping follower proposed in this invention. g m6 This indicates the transconductance of transistor M6. r o6 This indicates the output resistance of transistor M6.

[0044] As can be seen from the above equation, by adding common gate transistors M5 and M6, the loop gain of the cascode source-flipping follower increases. g m6 r o6 According to the feedback theorem, for the voltage-current negative feedback in this circuit structure, according to the formula... The output impedance of this common-source cascode source-flipping follower is correspondingly reduced. g m6 r o6This effectively increases the bandwidth of the input buffer. Simultaneously, the increased loop gain makes the source-drain voltages of buffer transistors M1 and M2 more stable, ensuring the linearity of the input buffer.

[0045] For further details, please see Figure 4 , Figure 4 This is a schematic diagram of a cross-coupled input circuit provided in an embodiment of the present invention. In this embodiment, the cross-coupled input circuit specifically includes a first coupling resistor R. B1 First coupling capacitor C X1 Second coupling resistor R B2 and the second coupling capacitor C X2 ;in,

[0046] First coupling resistor R B1 The first terminal is connected to the gate of the fifth transistor M5, and simultaneously connected to the second coupling capacitor C. X2 Connect the drain of the second transistor M2 to the source of the sixth transistor M6;

[0047] Second coupling resistor R B2 The first terminal is connected to the gate of the sixth transistor M6, and simultaneously connected to the first coupling capacitor C. X1 Connect the drain of the first transistor M1 to the source of the fifth transistor M5;

[0048] First coupling resistor R B1 Second coupling resistor R B2 The second terminal is connected to the second bias voltage V. b .

[0049] Specifically, this invention forms a cross-coupled input circuit using two coupling resistors and a capacitor, effectively improving the loop gain of the input buffer through a feedback loop. Simultaneously, it reduces the output impedance of the input buffer, effectively increasing its bandwidth. The increased loop gain also makes the source-drain voltages of buffer transistors M1 and M2 more stable, ensuring the linearity of the input buffer.

[0050] For further details, please see Figure 5 , Figure 5 This is a schematic diagram of the mirror load circuit provided in an embodiment of the present invention. The mirror load circuit designed in this embodiment includes a first load capacitor C. r1 Second load capacitor C r2 ;in,

[0051] First load capacitor C r1 Connected between the gate of the first transistor M1 and the source of the third transistor M3; the second load capacitor C r2 A mirrored load architecture is formed by connecting the gate of the second transistor M2 and the source of the fourth transistor M4.

[0052] The mirrored load architecture designed in this invention reduces the current variation caused by changes in the input buffer load, and further improves linearity.

[0053] Specifically, the first load capacitor C r1 Second load capacitor C r2 Both are the same value as the load capacitance of the input buffer. In practice, this means they are equal to the sampling capacitance of the subsequent analog-to-digital converter. Buffer transistors M1 and M2 are connected via a mirror image of the load capacitance C. r1 and C r2 It is connected to the source of transistors M3 and M4. Through this architecture, the mirrored load capacitor injects a current I equal to the current required by the output load of the buffer into the output point. L This reduces the current changes in buffer tubes M1 and M2 caused by changes in the input buffer load, thereby improving linearity.

[0054] For further details, please see Figure 6 , Figure 6 This is a circuit diagram of a bias current source provided in an embodiment of the present invention. The bias current source circuit designed in this embodiment includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, and a reference current source I. Q ;in,

[0055] The gate and drain of the seventh transistor M7 are shorted, and it is connected to the gate of the eighth transistor M8 and the source of the ninth transistor M9; the gate and drain of the ninth transistor M9 are shorted, and it is connected to the gate of the tenth transistor M10 and the reference current source I. Q Connected;

[0056] The drain of the eighth transistor M8 is connected to the source of the tenth transistor M10;

[0057] The drain of the tenth transistor M10 is connected to the drain of the eleventh transistor M11, the gate of the eleventh transistor M11, the drain of the twelfth transistor M12, and the gate of the fourteenth transistor M14.

[0058] The source of the eleventh transistor M11 is connected to the drain of the fourteenth transistor M14, and the source of the twelfth transistor M12 is connected to the drain of the thirteenth transistor M13.

[0059] The gate of the twelfth transistor M12 is connected to the gate of the thirteenth transistor M13, and serves as the output terminal of the bias current source circuit, outputting current I. B ;

[0060] The source of the seventh transistor M7 and the source of the eighth transistor M8 are grounded; the source of the thirteenth transistor M13 and the source of the fourteenth transistor M14 are connected to the power supply.

[0061] The bias current source designed in this invention adopts a low-voltage cascode architecture, which further ensures the current fluctuation caused by changes in the input buffer load and improves the linearity of the input buffer. In addition, the low-voltage cascode architecture also avoids the large burden of low supply voltage, reduces power consumption, ensures output swing, and improves circuit stability.

[0062] Specifically, such as Figure 6 As shown, transistors M11, M12, M13, and M14 form a current source through a low-voltage cascode architecture. This increases the output impedance of the current source and ensures that the current in the buffer transistors M1 and M2 does not fluctuate significantly with changes in the output load, thus improving the linearity of the input buffer. Simultaneously, the low-voltage cascode architecture avoids a large burden from low supply voltages, ensuring a smooth output swing.

[0063] The high-linearity broadband input buffer circuit provided by this invention achieves multiple negative feedbacks through source-flipping and cross-coupled input architecture. This reduces the output load of the input buffer while clamping the source-drain voltages of buffer transistors M1 and M2, thereby increasing the input buffer's bandwidth. The use of a mirrored load and a low-voltage cascode current source reduces the current fluctuations in buffer transistors M1 and M2 caused by changes in output load, further improving the input buffer's bandwidth. Combining these structures, a high-linearity broadband input buffer circuit is ultimately realized.

[0064] Another embodiment of the present invention provides a high-speed analog-to-digital converter, which includes the high-linearity wideband input buffer described above, and the repeated parts will not be described again here.

[0065] In the description of this specification, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0066] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high linearity wideband input buffer, characterized in that, This includes a common-source cascode source-flipping follower, a cross-coupled input circuit, a mirror load circuit, and a bias current source circuit; among which, The common-source cascode source-flipping follower is configured as a pseudo-differential structure, including a positive input transistor, a negative input transistor, a positive common-gate transistor, a negative common-gate transistor, a positive output transistor, and a negative output transistor. The cross-coupled input circuit is coupled between the drain of the positive input transistor and the gate of the negative common gate transistor, and between the drain of the negative input transistor and the gate of the positive common gate transistor. The mirror load circuit is connected between the gate of the positive input transistor and the source of the positive output transistor, and between the gate of the negative input transistor and the source of the negative output transistor. The bias current source circuit is connected to the drain of the positive input transistor and the negative input transistor; Specifically, the common-source cascode source-flipping follower includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. The first transistor M1 and the second transistor M2 serve as the positive and negative input transistors of the common-source cascode source-flipping follower, respectively, with their gates as signal input terminals. The third transistor M3 and the fourth transistor M4 serve as the positive and negative output transistors of the common-source cascode source-flipping follower, respectively, with their drains as signal output terminals. The fifth transistor... M5 and the sixth transistor M6 serve as the positive and negative common-gate transistors of a common-source flip-flop follower, respectively; wherein, the source of the first transistor M1 is connected to the drain of the third transistor M3, and the source of the second transistor M2 is connected to the drain of the fourth transistor M4; the drain of the first transistor M1 is connected to the source of the fifth transistor M5, and the drain of the second transistor M2 is connected to the source of the sixth transistor M6; the gate of the third transistor M3 is connected to the drain of the fifth transistor M5, and the gate of the fourth transistor M4 is connected to the drain of the sixth transistor M6; The cross-coupled input circuit specifically includes a first coupling resistor R. B1 First coupling capacitor C X1 Second coupling resistor R B2 and the second coupling capacitor C X2 Wherein, the first coupling resistor R B1 The first end is connected to the gate of the fifth transistor M5, and simultaneously connected through the second coupling capacitor C. X2 Connect the drain of the second transistor M2 and the source of the sixth transistor M6; the second coupling resistor R B2 The first end is connected to the gate of the sixth transistor M6, and simultaneously through the first coupling capacitor C X1 Connect the drain of the first transistor M1 and the source of the fifth transistor M5; the first coupling resistor R B1 and the second coupling resistor R B2 The second terminal is connected to the second bias voltage V. b ; The mirror load circuit includes a first load capacitor C. r1 Second load capacitor C r2 Wherein, the first load capacitor C r1 Connected between the gate of the first transistor M1 and the source of the third transistor M3; the second load capacitor C r2 A mirrored load architecture is formed by connecting the gate of the second transistor M2 and the source of the fourth transistor M4.

2. The high linearity wideband input buffer according to claim 1, characterized in that, The common-source common-gate source-flipping follower also includes a tail current source, which employs two tail current transistors M. S1 and M S2 To achieve; among which, The tail current tube M S1 and M S2 The drains of the transistors are connected to the sources of the positive and negative output transistors, respectively, and the gates of both transistors are connected to a first bias voltage V. B The source electrode is grounded.

3. The high linearity wideband input buffer according to claim 1, characterized in that, The first load capacitor C r1 and the second load capacitor C r2 All of them are the same size as the load capacitance of the input buffer.

4. A high linearity wideband input buffer according to claim 1, characterized in that, The bias current source circuit includes transistors M7 (seventh), M8 (eighth), M9 (ninth), M10 (tenth), M11 (eleventh), M12 (twelfth), M13 (thirteenth), M14 (fourteenth), and reference current source I. Q ;in, The gate and drain of the seventh transistor M7 are shorted together and connected to the gate of the eighth transistor M8 and the source of the ninth transistor M9; the gate and drain of the ninth transistor M9 are shorted together and connected to the gate of the tenth transistor M10 and the reference current source I. Q Connected; The drain of the eighth transistor M8 is connected to the source of the tenth transistor M10; The drain of the tenth transistor M10 is connected to the drain of the eleventh transistor M11, the gate of the eleventh transistor M11, the gate of the twelfth transistor M12, and the gate of the fourteenth transistor M14. The source of the eleventh transistor M11 is connected to the drain of the fourteenth transistor M14, and the source of the twelfth transistor M12 is connected to the drain of the thirteenth transistor M13. The drain of the twelfth transistor M12 is connected to the gate of the thirteenth transistor M13, and serves as the output terminal of the bias current source circuit, outputting current I. B ; The source of the seventh transistor M7 and the source of the eighth transistor M8 are grounded; the source of the thirteenth transistor M13 and the source of the fourteenth transistor M14 are connected to the power supply terminal.

5. A high-speed analog-to-digital converter, characterized in that, Includes a high linearity wideband input buffer as described in any one of claims 1-4.

Images