Measuring devices, measuring procedures and measuring methods

Abstract

An embodiment provides a measuring device, a measuring program, and a measuring method for improving the accuracy of calculating the positional offset of a pattern formed on an object. The measuring device of the embodiment is a measuring device for measuring the positional offset of a pattern formed on the surface of an object. The measuring device includes: a measuring unit for measuring a first two-dimensional intensity distribution of first diffracted light generated by irradiating the object with light after forming a first pattern and before forming a second pattern, and a second two-dimensional intensity distribution of second diffracted light generated by irradiating the object with light after forming the second pattern; a storage unit for storing first measurement data representing the first two-dimensional intensity distribution and second measurement data representing the second two-dimensional intensity distribution; and a calculation unit for performing calculation processing using the first measurement data and the second measurement data to obtain difference data between the first measurement data and the second measurement data, and calculating the positional offset of the difference pattern between the first pattern and the second pattern based on the difference data.

Description

[0001] References to related applications

[0002] This application claims priority based on Japanese Patent Application No. 2021-100743 (filing date: June 17, 2021), and the present application incorporates all the contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a measuring device, a measuring program, and a measuring method. Background Art

[0004] In order to further increase the capacity of memories, semiconductor devices such as memories having a three-dimensional structure have been developed. Summary of the Invention

[0005] An object of the present invention is to provide a measuring device and a measuring program that can improve the accuracy of calculating the positional deviation of a pattern formed on an object.

[0006] A measuring device according to an embodiment measures the positional offset of a pattern formed on the surface of an object. The measuring device includes: a measuring unit that measures a first two-dimensional intensity distribution of first diffracted light generated by irradiating the object with light after forming a first pattern and before forming a second pattern, and a second two-dimensional intensity distribution generated by irradiating the object with light after forming the second pattern; a storage unit that stores first measurement data representing the first two-dimensional intensity distribution and second measurement data representing the second two-dimensional intensity distribution; and a calculation unit that performs calculation processing using the first and second measurement data to obtain difference data between the first and second measurement data, and calculates the positional offset of the difference pattern between the first and second patterns based on the difference data. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a schematic plan view for explaining an example of a conventional method for measuring pattern position deviation.

[0008] Figure 2 It is a schematic plan view showing an example of pattern layout.

[0009] Figure 3 2 is a schematic diagram showing a configuration example of the measuring device 100 .

[0010] Figure 4 2 is a schematic diagram showing a configuration example of the measuring device 100 .

[0011] Figure 5 A block diagram showing the overall structure of a semiconductor memory device.

[0012] Figure 6 2 is a diagram showing an example of the circuit configuration of the memory cell array 10 .

[0013] Figure 7 A diagram showing an example of a cross-sectional structure of a semiconductor memory device.

[0014] Figure 8 It is a schematic diagram showing the state of the structure before the insulating layer 255 is formed.

[0015] Figure 9 It is a schematic diagram showing the state of the structure before the insulating layer 255 is formed.

[0016] Figure 10 FIG. 2 is a schematic diagram for explaining an example of forming the insulating layer 255 .

[0017] Figure 11 FIG. 2 is a schematic diagram for explaining an example of forming the insulating layer 255 .

[0018] Figure 12 This is a flowchart for explaining an example of a measurement method.

[0019] Figure 13 A diagram showing an example of the first two-dimensional intensity distribution.

[0020] Figure 14 A diagram showing an example of the first two-dimensional intensity distribution.

[0021] Figure 15 A diagram showing an example of the second two-dimensional intensity distribution.

[0022] Figure 16 A diagram showing an example of the second two-dimensional intensity distribution.

[0023] Figure 17 Schematic top view showing the area illuminated by light.

[0024] Figure 18 Graph showing an example of a two-dimensional intensity distribution based on difference data.

[0025] Figure 19 Schematic top view showing an example of a difference pattern corresponding to difference data.

[0026] Figure 20 1 is a schematic top view showing an example of pattern P1 of a comparative sample.

[0027] Figure 21 3 is a schematic top view showing an example of pattern P2 of a comparative sample.

[0028] Figure 22 3 is a schematic top view showing an example of pattern P3 of a comparative sample.

[0029] Figure 23 : is a two-dimensional intensity distribution diagram showing an example of intensity distribution based on the difference data of pattern P1.

[0030] Figure 24 2 is a two-dimensional intensity distribution diagram showing an example of intensity distribution based on the difference data of pattern P2.

[0031] Figure 25 : is a two-dimensional intensity distribution diagram showing an example of intensity distribution based on the difference data of pattern P3.

[0032] Figure 26 A schematic diagram of a two-dimensional intensity distribution for explaining the calculation method of the asymmetric component.

[0033] Figure 27 Schematic diagram showing an example of the model formula M. DETAILED DESCRIPTION

[0034] The following describes the embodiments with reference to the accompanying drawings. The relationships between the thickness and planar dimensions of the components, the ratio of the thicknesses of the components, and other details shown in the drawings may differ from those in actual components. In the embodiments, substantially identical components are denoted by the same reference numerals, and their descriptions are omitted as appropriate.

[0035] Semiconductor devices such as memories with three-dimensional structures are manufactured by processing multi-layer structures to form patterns such as circuit patterns or device patterns. These patterns can be formed using, for example, photolithography. When a lower-layer pattern is formed in a previous step and an upper-layer pattern is formed in a subsequent step, aligned with the lower-layer pattern, the resulting semiconductor device may not function properly if the alignment accuracy between the lower-layer pattern and the upper-layer pattern is low. Therefore, it is known that the positional deviation of the formed pattern is measured and the pattern position is adjusted.

[0036] Figure 1 It is a schematic plan view for explaining an example of a conventional method for measuring pattern position deviation. Figure 1 Indicates alignment mark ML of the lower pattern and alignment mark MU of the upper pattern. Conventional methods for measuring pattern position shifts form alignment mark ML of the lower pattern and alignment mark MU of the upper pattern. After forming the upper pattern, the center-to-center distance between alignment mark ML's center CL and alignment mark MU's center CU is optically measured to calculate pattern position shifts.

[0037] Such an alignment mark is difficult to form in the same area as a circuit pattern or a device pattern. Figure 2 It is a schematic plan view showing an example of pattern layout. Figure 2 Indicates alignment mark AM, device pattern DP and scribing pattern SP. Figure 2As shown, in the case where the alignment mark AM is formed in a region different from the device pattern DP, as shown in FIG. Figure 2 As shown by the arrows, the positional deviation direction of the alignment mark AM may differ from the positional deviation direction of the device pattern DP. Therefore, if the positional deviation amount of the device pattern DP is calculated using the alignment mark AM, the calculated positional deviation amount will differ from the actual deviation amount of the device pattern DP. Therefore, a measurement device that can measure the positional deviation amount of a desired pattern with high calculation accuracy is required.

[0038] Next, the measuring device according to the embodiment will be described. Figure 3 and Figure 4 This is a schematic diagram showing an example configuration of a measuring device 100. The measuring device 100 has a function of measuring the positional offset of a pattern formed on an object 110. The measuring device 100 includes a measuring unit comprising a measuring device 101, a storage unit comprising a storage device 121, a computing unit comprising a computing device 103, an output unit comprising an output device 104, and a control unit comprising a control device 108. The measuring unit, storage unit, computing unit, output unit, and control unit may be provided in a single device or in multiple separate devices to form a measurement system.

[0039] The measuring device 101 can measure the intensity distribution of diffracted light generated by irradiating light onto an object 110. The measuring device 101 includes a light source 111, a stage 112, an imaging device 113, and an optical system 114.

[0040] The light source 111 can emit light. Examples of the light source 111 include a xenon lamp and the like.

[0041] The stage 112 has a surface for placing the object 110. The stage 112 is movable, and the object 110 can be moved and measured by scanning the stage 112.

[0042] The imaging device 113 can measure the two-dimensional intensity distribution of diffracted light generated by irradiating the object 110 with light. Because diffracted light includes zero-order light, first-order light, and second-order light that are incident at different positions, the two-dimensional intensity distribution can be measured by using a two-dimensional detector in the imaging device 113. Examples of two-dimensional detectors include image sensors such as charge-coupled device (CCD) sensors and CMOS (Complementary Metal Oxide Semiconductor) sensors.

[0043] The optical system 114 has a function of guiding light from the light source 111 to the object 110 , or a function of guiding diffracted light generated by irradiating the object 110 with light to the imaging device 113 . Figure 3 and Figure 4 The optical system 114 shown in FIG. 1 includes a plurality of condensing lenses 141, a beam splitter 142, and an objective lens 143. However, the configuration of the optical system 114 is not limited to the configuration of FIG. Figure 3 and Figure 4 The composition shown.

[0044] The storage device 102 can store data (measurement data) representing the two-dimensional intensity distribution of diffracted light measured by the measurement device 101. The storage device 102 can also store a measurement program for the measurement device 101 to perform measurement operations, a calculation program for the calculation device 103 to perform calculations, and a control program for the control device 108 to control the various operations of the measurement device 101, the storage device 102, and the calculation device 108. Examples of the storage device 102 include a hard disk drive, a solid-state drive, and the like. The storage device 102 can be provided within the measurement device 101.

[0045] The calculation device 103 can perform calculation processing using a plurality of measurement data and calculate the positional shift amount of the pattern based on the calculation processing result. Examples of the calculation device 103 include computers such as personal computers. The calculation device 103 can be installed in the measurement device 101.

[0046] Output device 104 can output data representing the positional offset of the pattern calculated based on the results of the computational processing. Examples of output device 104 include a computer that reads a file-saving program and processes the data using a central processing unit (CPU). Output device 104 can be installed within measurement device 101.

[0047] The control device 108 controls the operations of the measurement device 101, the storage device 121, and the computing device 103. Examples of the control device 108 include computers such as personal computers. The control device 108 may be provided in the measurement device 101.

[0048] Figure 4 The illustrated measuring device 100 further includes a measuring device 105 and an external storage device 122 .

[0049] The configuration of the measuring device 105 can be the same as that of the measuring device 101. Therefore, the description of the measuring device 105 can refer to the description of the measuring device 101. The operation of the measuring device 105 can be controlled by, for example, the control device 108, but is not limited thereto and can also be controlled by another control device such as a computer.

[0050] The external storage device 122 is provided in the storage unit. The external storage device 122 can store data (measurement data) representing the two-dimensional intensity distribution of the diffracted light measured by the measuring device 105. Examples of the external storage device 122 are a hard disk drive, a solid state drive, and the like. The operation of the external storage device 122 can be controlled by, for example, the control device 108, but is not limited thereto and can also be controlled by a control device such as another computer. The external storage device 122 can be provided in the measuring device 105. The measurement data stored in the external storage device 122 can be sent to the storage device 121 via, for example, a data communication unit 123 provided in the storage unit. Examples of the data communication unit 123 include a local area network (LAN).

[0051] Next, an example of the object 110 will be described. The example of the object 110 is a structure formed during the manufacture of a semiconductor memory device.

[0052] First, an example of a semiconductor memory device will be described. Figure 5 This is a block diagram showing the overall structure of a semiconductor memory device. Semiconductor memory device 1 is controlled by, for example, a memory controller. Semiconductor memory device 1 includes a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0053] The memory cell array 10 includes a plurality of blocks BLK0 to BLK(L-1) (L is an integer greater than or equal to 2). Block BLK is a collection of multiple memory cell transistors (hereinafter referred to as "memory cells") that store data non-volatilely and is used, for example, as a unit for erasing data. The memory cell array 10 is provided with a plurality of bit lines and a plurality of word lines. Each memory cell transistor is associated with, for example, one bit line and one word line. The detailed structure of the memory cell array 10 will be described later.

[0054] The command register 11 can store commands CMD received by the semiconductor memory device 1 from the memory controller. Commands CMD include, for example, commands for causing the sequencer 13 to execute read, write, and erase operations. The address register 12 can store address information ADD received by the semiconductor memory device 1 from the memory controller. Address information ADD includes, for example, a block address BA, a page address PA, and a column address CA. For example, the block address BA, the page address PA, and the column address CA are used to select a block BLK, a word line, and a bit line, respectively.

[0055] The sequencer 13 controls the overall operation of the semiconductor memory device 1. For example, based on the command CMD stored in the command register 11, the sequencer 13 controls the driver module 14, the row decoder module 15, and the sense amplifier module 16 to execute read, write, and erase operations.

[0056] The driver module 14 generates voltages used in read operations, write operations, and erase operations, etc. The driver module 14 applies the generated voltages to signal lines corresponding to selected word lines based on, for example, the page address PA stored in the address register 12 .

[0057] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address BA stored in the address register 12. The row decoder module 15 then transfers, for example, a voltage applied to a signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0058] During a write operation, the sense amplifier module 16 applies a desired voltage to each bit line based on write data DAT received from the memory controller. Furthermore, during a read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage on the bit line or the current flowing through the bit line, and transmits the determination result as read data DAT to the memory controller.

[0059] The communication between the semiconductor memory device 1 and the memory controller supports, for example, a NAND interface. For example, the communication between the semiconductor memory device 1 and the memory controller uses a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, a ready busy signal RBn, and an input / output signal I / O.

[0060] The command latch enable signal CLE is a signal indicating that the input / output signal I / O received by the semiconductor memory device 1 is a command CMD. The address latch enable signal ALE is a signal indicating that the signal I / O received by the semiconductor memory device 1 is address information ADD. The write enable signal WEn is a signal for controlling the input of data from the input / output signal I / O. The read enable signal REn is a signal for controlling the output of data from the input / output signal I / O.

[0061] The ready busy signal RBn is a signal that notifies the memory controller whether the semiconductor storage device 1 is in a ready state to accept a command from the memory controller or a busy state to not accept a command.

[0062] The input / output signal I / O is, for example, an 8-bit wide signal and can include a command CMD, address information ADD, data DAT, and the like.

[0063] The combination of the semiconductor memory device 1 and the memory controller described above can constitute a semiconductor memory device. Examples of such semiconductor memory devices include memory cards such as SD (Secure Digital) cards and SSD (Solid State Drive).

[0064] Next, use Figure 6 The circuit configuration of the memory cell array 10 will be described. Figure 6 The example shows the block BLK0, but the circuit configuration of other blocks BLK is also the same. Figure 6 As shown, the block BLK0 includes, for example, four string sections SU0 to SU3. Each string section SU includes a plurality of NAND strings NS.

[0065] A plurality of NAND strings NS are associated with bit lines BL0 to BL(N-1), respectively (N is an integer greater than or equal to 2). Each NAND string NS includes, for example, memory cell transistors MC0 to MC7 and selection transistors ST1 and ST2.

[0066] Memory cell transistor MC includes a control gate and a charge storage layer, capable of non-volatile data storage. Hereinafter, when not specifying any of the memory cell transistors MC0-MC7, they will be referred to as memory cell transistor MC. Furthermore, memory cell transistor MC can be a MONOS (Metal Oxide Nitride Oxide Semiconductor) type, using an insulating film for the charge storage layer, or an FG (Floating Gate) type, using a conductive layer for the charge storage layer. The following embodiments use the MONOS type as an example.

[0067] Select transistor ST1 is used to select a string location SU during various operations. In each NAND string NS, the drain of select transistor ST1 is connected to the associated bit line BL. The source of select transistor ST1 is connected to one end of the series-connected memory cell transistors MC0-MC7. The other ends of the series-connected memory cell transistors MC0-MC7 are connected to the gate of select transistor ST2.

[0068] In the same block BLK, the sources of select transistors ST2 are commonly connected to source line SL. The gates of select transistors ST1 in string sections SU0 through SU3 are commonly connected to select gate lines SGD0 through SGD3, respectively. The control gates of memory cell transistors MC0 through MC7 are commonly connected to word lines WL0 through WL7, respectively. The gates of select transistors ST2 are commonly connected to select gate line SGS.

[0069] In the circuit configuration of the memory cell array 10 described above, a plurality of NAND strings NS assigned the same column address CA are connected to the same bit line BL in common among a plurality of blocks BLK. A source line SL is connected in common among a plurality of blocks BLK.

[0070] The circuit configuration of the memory cell array 10 included in the semiconductor device is not limited to the configuration described above. For example, the number of memory cell transistors MC and select transistors ST1 and ST2 included in each NAND string NS can be designed to be any number. The number of string units SU included in each block BLK can also be designed to be any number.

[0071] Next, use Figure 7 The cross-sectional structure of a semiconductor memory device will be described. Figure 7 This figure is used to illustrate a structural example of a semiconductor memory device, showing a YZ cross-section represented by an X-axis approximately parallel to the surface (upper surface) of a semiconductor substrate 200, a Y-axis approximately perpendicular to the X-axis, and a Z-axis approximately perpendicular to the X-axis and the Y-axis.

[0072] like Figure 7 As shown in FIG. 2 , an insulating layer 203 is formed on a semiconductor substrate 200. The insulating layer 203 is formed using silicon oxide, for example. A memory cell array 10 is provided on the insulating layer 203. Peripheral circuits are formed below the memory cell array 10. Figure 7 In the embodiment, a circuit region including a peripheral circuit is provided below a memory cell region including the memory cell array 10 . However, the present invention is not limited thereto, and the circuit region may be provided in parallel with the memory cell region.

[0073] First, the structure of the memory cell array 10 will be described. A conductive layer 220, which functions as a source line SL, is provided on the insulating layer 203. For example, the conductive layer 220 is formed in a plate shape extending along an XY plane substantially parallel to the surface (top surface) of the semiconductor substrate 200. The conductive layer 220 is formed using a conductive material such as a metal material or a semiconductor material.

[0074] Multiple conductive layers 221 and multiple insulating layers 222 are alternately stacked on the conductive layer 220. SiO is used, for example, for the insulating layer 222. The multiple conductive layers 221 function, for example, as the select gate line SGS, word lines WL0 to WL7, and select gate line SGD, in order from the bottom. For example, the conductive layers 221 are formed in a plate shape extending in the X-axis direction. The conductive layers 221 are formed using a conductive material, such as a metal.

[0075] Multiple memory pillars MP are provided, each extending through the conductive layers 221 in the Z-axis direction. Each memory pillar MP has its bottom surface reaching the conductive layers 220. Each memory pillar MP extends along the Z-axis. One memory pillar MP corresponds to one NAND string NS. Each memory pillar MP includes a block insulating film 231, a charge storage layer 232, a tunnel insulating film 233, a semiconductor layer 234, a core insulator 235, and a cap layer 236.

[0076] More specifically, holes corresponding to memory pillars MP are formed, penetrating multiple conductive layers 221 and with their bottom surfaces reaching conductive layer 220. A block insulating film 231, a charge storage layer 232, and a tunnel insulating film 233 are sequentially stacked on the sides of the holes. Furthermore, a semiconductor layer 234 is formed, with its sides in contact with tunnel insulating film 233 and its bottom surface in contact with conductive layer 220. Semiconductor layer 234 forms the region where the channels of memory cell transistor MC and select transistors ST1 and ST2 are formed. Therefore, semiconductor layer 234 functions as a signal line connecting the current paths of select transistor ST2, memory cell transistors MC0-MC7, and select transistor ST1. A core insulator 235 is provided within semiconductor layer 234. Furthermore, a cap layer 236 is formed on semiconductor layer 234 and core insulator 235, with its sides in contact with tunnel insulating film 233.

[0077] For example, SiO can be used for the block insulating film 231, the tunnel insulating film 233, and the core insulator 235. For example, silicon nitride (SiN) can be used for the charge storage layer 232. For example, polysilicon can be used for the semiconductor layer 234 and the cap layer 236.

[0078] The memory pillar MP is combined with multiple conductive layers 221 that function as word lines WL0 to WL7, respectively, to function as memory cell transistors MC0 to MC7. Similarly, the memory pillar MP is combined with multiple conductive layers 221 that function as select gate line SGD and select gate line SGS, respectively, to function as select transistors ST1 and ST2.

[0079] Contact plugs CP are formed on the cap layer 236. A conductive layer (not shown) functioning as the bit lines BL is formed on the contact plugs CP. The contact plugs CP are formed using a conductive material, such as a metal material.

[0080] In addition, Figure 7 In the example shown in FIG. 4 , the memory pillars MP are arranged along the Y-axis direction, but the memory pillars MP can be arranged arbitrarily.

[0081] The insulating layer 251 is provided on the laminate of the conductive layer 221 and the insulating layer 222. The insulating layer 251 is formed using, for example, tetraethyl orthosilicate.

[0082] The conductive layer 253 has the function of serving as a separator that electrically separates the word lines WL0 to WL7, the selection gate line SGD, and the selection gate line SGS in each group including a plurality of NAND strings NS. The group is also referred to as a finger. In addition, the conductive layer 253 has the function of serving as a wiring (also referred to as a local interconnect wiring) L1 connected to the source line SL. The conductive layer 253 penetrates the plurality of conductive layers 221 in the Z-axis direction to reach the conductive layer 220. The conductive layer 253 includes a conductive layer 253a provided on the conductive layer 220, and a conductive layer 253b provided on the conductive layer 253a. The conductive layer 253a is formed using, for example, a semiconductor material such as polysilicon. The conductive layer 253b is formed using, for example, a metal material such as tungsten.

[0083] The insulating layer 254 is provided between the conductive layer 253 and each of the plurality of conductive layers 221. The insulating layer 254 is formed using an insulating material such as silicon oxide.

[0084] Insulating layer 255 penetrates conductive layer 221 of select gate line SGD in the Z-axis direction, but does not penetrate conductive layer 221 of select gate line SGS in the Z-axis direction. Insulating layer 255 functions as a separator that electrically isolates select gate line SGD for each group of multiple NAND strings NS. Insulating layer 255 is formed using an insulating material such as silicon oxide, for example.

[0085] The circuit area has a field effect transistor TR N With electric field effect transistor TR P . Field Effect Transistor TR N and field effect transistor TR P For example, it can be used in peripheral circuits such as the command register 11, the address register 12, the sequencer 13, the driver module 14, the row decoder module 15, and the sense amplifier module 16. N and field effect transistor TR P The channel length direction is, for example, the Y-axis direction, and the channel width direction is, for example, the X-axis direction.

[0086] Field Effect Transistor TR N and field effect transistor TR P It is provided below the memory cell array 10. The field effect transistor TR N It is an N-channel transistor. Field effect transistor TR P It is a P-channel transistor.

[0087] Each of the plurality of conductive layers 201 constitutes a contact plug. The plurality of conductive layers 202 constitutes one wiring layer, and each conductive layer 202 constitutes each wiring of the wiring layer. Each conductive layer 202 is connected to the field effect transistor TR via the conductive layer 201, for example. N or electric field effect transistor TR P The conductive layer 201 and the conductive layer 202 include a metal material.

[0088] The insulating layer 203 separates the field effect transistor TR N With electric field effect transistor TR P The insulating layer 203 is made of silicon oxide, for example. N and field effect transistor TR P The device is not only connected to the conductive layer 201 and the conductive layer 202 but is also connected to the memory cell array 10 via other wiring layers or contact plugs, but these are omitted for convenience in this embodiment.

[0089] Next, an example of forming the insulating layer 255 will be described as an example of a method for manufacturing a semiconductor memory device. Figure 8 and Figure 9 It is a schematic diagram showing the state of the structure before the insulating layer 255 is formed. Figure 8 It is a schematic diagram of the XY plane. Figure 9 It is a schematic diagram of the YZ section. Figure 8 and Figure 9 As shown, before forming the insulating layer 255, the memory pillars MP and the conductive layer 253 are formed to penetrate the plurality of conductive layers 221. The memory pillars MP and the conductive layer 253 before forming the insulating layer 255 form a first pattern. The structure having the first pattern can be used in the object 110.

[0090] Figure 10 and Figure 11 FIG. 2 is a schematic diagram for explaining an example of forming the insulating layer 255 . Figure 10 It is a schematic diagram of the XY plane. Figure 11 It is a schematic diagram of the YZ section. Figure 10 and Figure 11 The parts shown are Figure 8 and Figure 9 The same part as shown. Figure 10 and Figure 11As shown, before forming the insulating layer 255, a slit SHE extending in the Z-axis direction is formed so as to penetrate the conductive layer 221 of the select gate line SGD among the multiple conductive layers 221 and not reach the conductive layer 221 of the select gate line SGS. The slit SHE can be formed, for example, by etching the conductive layer 221 and the insulating layer 222. Before forming the insulating layer 255, the memory pillars MP, the conductive layer 253, and the slit SHE form a second pattern. The structure having the second pattern can be used in the object 110. Thereafter, the insulating layer 255 is formed to fill the slit SHE. The insulating layer 255 can be formed, for example, using CVD (Chemical Vapor Deposition).

[0091] If the slit SHE's positional deviation is significant, overlapping the memory pillars MP when viewed from above, this can cause malfunction in the semiconductor memory device. Therefore, it is preferable to measure the extent to which the slit SHE's position has deviated from the designed position, using the positions of the memory pillars MP included in the first pattern as a reference. In other words, the positional deviation is measured. This allows feedback correction of the slit SHE's position during the semiconductor memory device manufacturing process.

[0092] Next, an example of a method of measuring the positional deviation amount of a pattern using the measuring device 100 will be described. Figure 12 This is a flowchart for explaining an example of a measurement method.

[0093] like Figure 12 As shown, the example measurement method includes a measurement step S1, a calculation step S2, and a data processing step S3. The example measurement method can be performed by the control device 108 reading a control program stored in a storage unit such as the storage device 121, and causing the measurement device 100, the storage device 121, and the calculation device 103 to execute the program including each step.

[0094] In measurement step S1, the measurement device 101 uses the imaging device 113 to measure: a first two-dimensional intensity distribution of first diffracted light, generated by irradiating the object 110 with light from the light source 111 via the optical system 114 after forming the first pattern including the memory pins MP and the conductive layer 253 and before forming the second pattern including the memory pins MP, the conductive layer 253, and the slits SHE; and a second two-dimensional intensity distribution of second diffracted light, generated by irradiating the object 110 with the light after forming the second pattern. The operations of the light source 111, the stage 112, and the imaging device 113 are controlled by the control device 118. The first measurement data representing the first two-dimensional intensity distribution and the second measurement data representing the second two-dimensional intensity distribution are stored in the storage device 121. The object 110 used for measuring the second two-dimensional intensity distribution can be the same as the object 110 after measuring the first two-dimensional intensity distribution, or another structure manufactured through the same manufacturing steps can be used as the object 110.

[0095] At Figure 4 In the case of the measurement device 100 shown, the measurement device 101 measures the first two-dimensional intensity distribution, and the measurement device 105 measures the second two-dimensional intensity distribution. First measurement data representing the first two-dimensional intensity distribution is stored in the storage device 121. Second measurement data representing the second two-dimensional intensity distribution is stored in the external storage device 122. Furthermore, the second measurement data is transmitted from the external storage device 122 to the storage device 121 via the data communication unit 123. By having each of the measurement devices 101 and 105 measure the two-dimensional intensity distribution of diffracted light, measurement step S1 can be performed efficiently.

[0096] Figure 13 and Figure 14 This is a diagram showing an example of the first two-dimensional intensity distribution. The two-dimensional intensity distribution can be obtained from the intensity distribution of each pixel detected in the two-dimensional imaging device 113 having multiple pixels, and represents the intensity in each XY plane coordinate of the diffracted light incident on the imaging device 113 in two dimensions. The horizontal axis of the two-dimensional intensity distribution diagram represents the wave number of the diffracted light in the X-axis direction. The vertical axis of the two-dimensional intensity distribution diagram represents the wave number of the diffracted light in the Y-axis direction. The light and dark colors of the two-dimensional intensity distribution diagram represent the intensity. When viewed from above, when the position of the conductive layer 253 is consistent with the design relative to the position of the memory column MP, the first two-dimensional intensity distribution is as shown. Figure 13 However, if the position of the conductive layer 253 is offset from the designed position due to manufacturing errors caused by photolithography or dry etching when forming the conductive layer 253, the first two-dimensional intensity distribution is as shown in FIG. Figure 14 As shown, the vertical asymmetry of the two-dimensional intensity distribution is lower, which means that the positional deviation of the conductive layer 253 is greater.

[0097] Figure 15 and Figure 16 A diagram showing an example of the second two-dimensional intensity distribution. Figure 15 and Figure 16 The horizontal axis represents the wave number of the diffracted light in the X-axis direction. Figure 15 and Figure 16 The vertical axis represents the wave number of the diffracted light in the Y-axis direction. When viewed from above, if the position of the conductive layer 253 relative to the position of the memory column MP and the position of the slit SHE relative to the position of the memory column MP are consistent with the design, the second two-dimensional intensity distribution is as follows: Figure 15 However, if the position of the conductive layer 253 and the slit SHE deviates from the designed position due to manufacturing errors caused by photolithography or dry etching when forming the conductive layer 253 and the slit SHE, the second two-dimensional intensity distribution may be as shown in FIG. Figure 16 As shown, the vertical asymmetry is shown. The lower the vertical symmetry of the two-dimensional intensity distribution, the greater the offset between the conductive layer 253 and the slit SHE relative to the memory pillar MP. The vertical symmetry of the second two-dimensional intensity distribution varies depending on the offset between the conductive layer 253 and the slit SHE. Furthermore, the area illuminated by light is larger than the device pattern. Figure 17 2 is a schematic plan view showing a light irradiation area, showing the memory pillar MP, the conductive layer 253, the slit SHE, and the light irradiation area BA. Figure 17 The light-irradiated area BA shown overlaps both the conductive layer 253 and the slit SHE. As the positional offset of the conductive layer 253 increases, the distance D1 between the conductive layer 253 and the memory pillar MP changes. As the positional offset of the slit SHE increases, the distance D2 between the slit SHE and the memory pillar MP changes. Therefore, it is difficult to distinguish the positional offset of the conductive layer 253 from that of the slit SHE based solely on the second two-dimensional intensity distribution.

[0098] In calculation step S2, the calculation device 103 reads the first measurement data and the second measurement data stored in the storage device 121 and performs calculation processing using the first measurement data and the second measurement data to obtain difference data between the first measurement data and the second measurement data. Examples of the calculation processing include subtraction processing between the first measurement data and the second measurement data.

[0099] As a pre-processing for subtracting the first and second measurement data, noise filtering may be performed on the first and second measurement data. For example, low-pass filtering that excludes frequency components above a cutoff frequency may be applied.

[0100] Furthermore, if the intensities of the first and second measurement data differ significantly, the subtraction process can be performed after normalizing the intensities as a pre-processing step. For example, the intensity distribution can be processed so that it falls within the range of -1 to 1, with an average value of 0. This normalization process can also be applied to differential data as needed for data processing.

[0101] Figure 18 is a two-dimensional intensity distribution diagram showing an example of intensity distribution based on difference data. Figure 18 The intensity distribution shown can be achieved, for example, by performing Figure 14 The first measurement data corresponding to the first two-dimensional intensity distribution shown in FIG. Figure 16 The second two-dimensional intensity distribution shown is obtained by subtracting the second measurement data corresponding to the second two-dimensional intensity distribution.

[0102] Figure 19 Schematic top view showing an example of a difference pattern corresponding to difference data. Figure 19 The difference pattern shown corresponds to a pattern including the memory pillars MP and the slits SHE, but without the conductive layer 253. Therefore, by obtaining a two-dimensional intensity distribution based on the difference data, changes in vertical symmetry caused by the positional offset of the conductive layer 253 relative to the memory pillars MP can be removed from the second two-dimensional intensity distribution.

[0103] In the data processing step S3, the calculation process 103 calculates the positional offset of the difference pattern based on the difference data. An example of a method for calculating the positional offset of the difference pattern is described below.

[0104] First, a comparative sample of a structure whose offset from the designed position of the slit SHE is determined in advance is prepared. The structure has a pattern having the same shape as the object. Figures 20 to 22 It is a schematic top view showing an example of a pattern of a comparative sample. Figure 20 The pattern P1 is shown in which the positional deviation in the Y-axis direction from the designed position (dashed line portion) of the slit SHE is +10 nm. Figure 21 The pattern P2 shows that the position shift amount is ±0 nm. Figure 22 The pattern P3 with the positional shift of -10 nm is shown. The comparative sample includes, for example, pattern P1, pattern P2, and pattern P3 on one semiconductor substrate.

[0105] As with the object 110 , the first two-dimensional intensity distribution and the second two-dimensional intensity distribution of the patterns P1 , P2 , and P3 are measured in advance, and difference data are obtained through calculation processing. Figure 23 : is a two-dimensional intensity distribution diagram showing an example of intensity distribution based on the difference data of pattern P1. Figure 242 is a two-dimensional intensity distribution diagram showing an example of intensity distribution based on the difference data of pattern P2. Figure 25 : is a two-dimensional intensity distribution diagram showing an example of intensity distribution based on the difference data of pattern P3. Figures 23 to 25 The horizontal axis represents the wave number of the diffracted light in the X-axis direction. Figures 23 to 25 The vertical axis represents the wave number of the diffracted light in the Y-axis direction.

[0106] Next, in the two-dimensional intensity distribution map based on each difference pattern, difference data between the upper intensity distribution and the lower intensity distribution is obtained to calculate the asymmetric component. Figure 26 This diagram illustrates a two-dimensional intensity distribution used to illustrate the calculation method for the asymmetric component. The asymmetric component divides the two-dimensional intensity distribution into the first, second, third, and fourth quadrants and is calculated by subtracting the average intensity of the third and fourth quadrants (the lower intensity distribution) from the average intensity of the first and second quadrants (the upper intensity distribution).

[0107] Next, a linear regression is performed using the positional offset in the Y-axis direction as a target variable and the asymmetric component as an explanatory variable, thereby creating a model equation M of the positional offset: Y=(X). Figure 27 This is a schematic diagram showing an example of model formula M. For example, when the asymmetric component of pattern P1 is -0.8, the asymmetric component of pattern P2 is 0.0, and the asymmetric component of pattern P3 is +0.8, model formula M is represented by Y = 12.5X. Furthermore, model formula M is not limited to a linear regression model; complex models such as a Partial Least Squares (PLS) model or a neural network can also be used.

[0108] The same method is then used to obtain the asymmetric component of the differential data for object 110. Substituting the obtained asymmetric component value into the Y of the model equation M:Y=12.5X, the positional offset in the Y-axis direction can be calculated. For example, if the asymmetric component is -0.6, the positional offset in the Y-axis direction is -7.5 nm. The calculated positional offset data can then be output to the outside of the measurement device.

[0109] As described above, the method for measuring the positional offset of a pattern using the measurement device of this embodiment measures the two-dimensional intensity distribution of diffracted light corresponding to the pattern formed on the object in each manufacturing step, and performs arithmetic processing using the measured data to obtain differential data. As a result, since only the two-dimensional intensity distribution of the pattern to be measured can be captured, the calculation accuracy of the positional offset of the desired pattern can be improved.

[0110] While various embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. The novel embodiments described above may be implemented in various other forms and may be omitted, replaced, or modified without departing from the spirit of the invention. These embodiments and modifications are intended to be within the scope and spirit of the invention and encompassed by the inventions described in the claims and their equivalents.

[0111] [Explanation of Symbols]

[0112] 1: Semiconductor devices

[0113] 2: Memory controller

[0114] 10: Memory cell array

[0115] 11: Command register

[0116] 12: Address register

[0117] 13: Sequencer

[0118] 14: Driver module

[0119] 15: Row decoder module

[0120] 16: Sense amplifier module

[0121] 100: Measuring device

[0122] 101: Measuring device

[0123] 102: Storage device

[0124] 103: Computing device

[0125] 104: Output device

[0126] 105: Measuring device

[0127] 108: Control device

[0128] 110: Object

[0129] 111: Light Source

[0130] 112: Carrier

[0131] 113: Camera

[0132] 114: Optical System

[0133] 121: Storage device

[0134] 122: External storage device

[0135] 123: Data Communications Department

[0136] 123: Ministry of Communications

[0137] 141: Focusing lens

[0138] 142: Beam splitter

[0139] 143:Objective lens

[0140] 200: semiconductor substrate

[0141] 201: conductive layer

[0142] 202: conductive layer

[0143] 203: Insulation layer

[0144] 220: conductive layer

[0145] 221: conductive layer

[0146] 222: Insulation layer

[0147] 231: Block insulation film

[0148] 232: Charge storage layer

[0149] 233: Tunnel insulating film

[0150] 234: semiconductor layer

[0151] 235: Core insulator

[0152] 236: Covering

[0153] 253: conductive layer

[0154] 253a: conductive layer

[0155] 253b: conductive layer

[0156] 254:Insulation layer

[0157] 255: Insulation layer.

Claims

1. A measuring and calculating device for measuring and calculating a positional deviation of a pattern on a surface of an object, the device comprising: A measuring unit includes at least one measuring device, the measuring device including: a light source for irradiating light; and an imaging device having an image sensor for receiving light, wherein the at least one measuring device is configured to: (I) control the light source to irradiate the object after forming a first pattern and before forming a second pattern to generate first diffracted light, receive the generated first diffracted light using the image sensor, and measure a first two-dimensional intensity distribution of the received first diffracted light; and (II) control the light source to irradiate the object after forming the first pattern and the second pattern to generate second diffracted light, receive the generated second diffracted light using the image sensor, and measure a second two-dimensional intensity distribution of the received second diffracted light, wherein the first pattern includes a first object pattern and a second object pattern, and the second pattern includes the first object pattern, the second object pattern, and a third object pattern; a storage unit comprising at least one storage device, the storage device comprising at least one of a hard disk drive and a solid-state drive, the at least one storage device being configured to store first measurement data and second measurement data, the first measurement data representing the first two-dimensional intensity distribution, the second measurement data representing second measurement data of the second two-dimensional intensity distribution; and The calculation unit includes a computer, which obtains difference data between the first measurement data and the second measurement data by performing calculation processing using the first measurement data and the second measurement data, and calculates a position offset of a difference pattern between the first pattern and the second pattern based on the difference data, wherein the difference pattern has the first object pattern and the third object pattern but does not have the second object pattern.

2. The device according to claim 1, wherein the at least one measuring device of the measuring unit comprises: a first measuring device comprising a first light source and a first imaging device having a first image sensor, the first measuring device being configured to measure the first two-dimensional intensity distribution of the first diffracted light, the first diffracted light being received by the first image sensor, the first diffracted light being generated by controlling the first light source to irradiate the object with the light after the first pattern is formed and before the second pattern is formed; and a second measuring device comprising a second light source and a second imaging device having a second image sensor, the second measuring device being configured to measure the second two-dimensional intensity distribution of the second diffracted light, the second diffracted light being received by the second image sensor, the second diffracted light being generated by controlling the second light source to irradiate the object after the first pattern and the second pattern are formed; and The storage unit includes: a first storage device comprising at least one of a first hard disk drive and a first solid state drive, the first storage device being configured to store the first measurement data; and The second storage device includes at least one of a second hard disk drive and a second solid state drive, and the second storage device is configured to store the second measurement data. 3 . The device according to claim 1 , wherein the calculation processing includes a subtraction process between the first measurement data and the second measurement data.

4. A non-transitory computer-readable storage medium storing a computer-executable program executable by a computer of a measuring and calculating device for measuring and calculating a positional offset of a pattern on a surface of an object, wherein: The measuring and calculating device includes a measuring unit, the measuring unit including at least one measuring device, the measuring device including: a light source for emitting light; and an imaging device including an image sensor for receiving light, and the program is executed by the computer to control the computer to perform the following functions: (I) controlling the light source to irradiate the object after forming the first pattern and before forming the second pattern with light to generate first diffracted light, receiving the generated first diffracted light using the image sensor, and measuring a first two-dimensional intensity distribution of the received first diffracted light; and (II) controlling the light source to irradiate the object after forming the first pattern and the second pattern with light to generate second diffracted light, receiving the generated second diffracted light using the image sensor, and measuring a second two-dimensional intensity distribution of the received second diffracted light, wherein the first pattern includes a first object pattern and a second object pattern, and the second pattern includes the first object pattern, the second object pattern, and a third object pattern; performing a calculation process using first measurement data and second measurement data to obtain difference data between the first measurement data and the second measurement data, the first measurement data representing the first two-dimensional intensity distribution and the second measurement data representing the second two-dimensional intensity distribution; and Based on the difference data, a positional offset of a difference pattern between the first pattern and the second pattern is calculated, the difference pattern including the first object pattern and the third object pattern but not the second object pattern. 5 . The non-transitory computer-readable storage medium according to claim 4 , wherein the arithmetic processing includes a subtraction process between the first measurement data and the second measurement data.

6. A measuring and calculating method for measuring and calculating a positional offset of a pattern on a surface of an object using a measuring and calculating device, wherein: The measuring and calculating device includes a measuring unit, the measuring unit includes at least one measuring device, the measuring device includes: a light source for irradiating light; and an imaging device including an image sensor for receiving light, and the measuring and calculating method includes the following steps: (I) controlling the light source to irradiate the object after forming the first pattern and before forming the second pattern with light to generate first diffracted light, receiving the generated first diffracted light using the image sensor, and measuring a first two-dimensional intensity distribution of the received first diffracted light; and (II) controlling the light source to irradiate the object after forming the first pattern and the second pattern with light to generate second diffracted light, receiving the generated second diffracted light using the image sensor, and measuring a second two-dimensional intensity distribution of the received second diffracted light, wherein the first pattern includes a first object pattern and a second object pattern, and the second pattern includes the first object pattern, the second object pattern, and a third object pattern; performing a calculation process using first measurement data and second measurement data to obtain difference data between the first measurement data and the second measurement data, the first measurement data representing the first two-dimensional intensity distribution and the second measurement data representing the second two-dimensional intensity distribution; and Based on the difference data, a positional offset of a difference pattern between the first pattern and the second pattern is calculated, the difference pattern including the first object pattern and the third object pattern but not the second object pattern. 7 . The method according to claim 6 , wherein the calculation processing includes a subtraction process between the first measurement data and the second measurement data.

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