An LDO circuit without external capacitor

Abstract

The present application discloses a low voltage drop linear regulator (LDO) circuit without external capacitors, comprising: a voltage stabilizing unit, a first NMOS tube, a PMOS tube, a first current branch, a second current branch and a capacitor. The output end of the voltage stabilizing unit is used to output a stable reference voltage. The gate of the first NMOS tube is used to input a stable reference voltage, and the gate of the PMOS tube is connected to the drain of the first NMOS tube. The drain of the PMOS tube is connected to one end of the capacitor, and the connection point is the second connection point. The voltage of the second connection point is the output stable voltage of the LDO circuit. The first current branch includes at least one upper current branch, and the second current branch includes at least one lower current branch. The number of upper current branches and lower current branches is the same. The first and second current branches increase the current passing through the first NMOS tube, and when the load increases, the current passing through the PMOS tube increases. The increase in the current of the first NMOS tube and the PMOS tube increases the loop bandwidth, enhances the slew rate, and improves the load transient response capability of the LDO circuit.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a LDO circuit without an external capacitor. Background Art

[0002] Low Dropout Regulator (LDO) has the functions of output voltage stability and noise resistance. It is widely used in chip circuits to provide a stable voltage source for other modules in the chip.

[0003] At present, LDO is divided into external capacitor type LDO and non-external capacitor LDO. External capacitor type LDO uses external capacitor to improve the load transient response capability of LDO. However, external capacitor type LDO needs to connect a capacitor to the board-level application system. This design will increase the area of ​​the printed circuit board. The existing non-external capacitor LDO has poor load transient response capability. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a LDO circuit without external capacitors, which is used to output a stable voltage and improve the load transient response capability of the LDO without external capacitors.

[0005] In order to achieve the above purpose, the technical solutions provided by the embodiments of the present application are as follows:

[0006] The embodiment of the present application provides a low-dropout linear regulator LDO circuit without an external capacitor, the LDO circuit without an external capacitor comprising: a voltage stabilizing unit, a first NMOS transistor, a PMOS transistor, a first current branch, a second current branch and an on-chip capacitor;

[0007] The output end of the voltage stabilizing unit is used to output a stable reference voltage;

[0008] The gate of the first NMOS tube is connected to the output end of the voltage stabilizing unit; the gate of the first NMOS tube is used to input the stable reference voltage;

[0009] The gate of the PMOS tube is connected to the drain of the first NMOS tube, and the connection point is a first connection point; the drain of the PMOS tube is connected to one end of the capacitor, and the connection point is a second connection point, and the second connection point is the output end of the LDO circuit without external capacitor; the output end of the LDO circuit without external capacitor is used to output a stable voltage; the source of the PMOS tube is connected to a power supply; the other end of the capacitor is grounded;

[0010] The first current branch includes a target number of upper current branches connected in parallel with each other; each of the upper current branches is provided with a switch; one end of the first current branch is connected to the power supply; the other end of the first current branch is connected to the first connection point;

[0011] The second current branch includes the target number of lower current branches connected in parallel with each other; each of the lower current branches is provided with a switch; one end of the second current branch is grounded; and the other end of the second current branch is connected to the second connection point.

[0012] Optionally, the voltage stabilizing unit includes: an operational amplifier, a second NMOS tube, a compensation capacitor, an adjustable resistor, a first feedback resistor and a second feedback resistor;

[0013] The operational amplifier comprises a positive input terminal, a reverse input terminal and an output terminal; the reverse input terminal is connected to an input reference voltage; the output terminal of the operational amplifier is the output terminal of the voltage stabilizing unit;

[0014] The gate of the second NMOS tube is connected to the output end of the operational amplifier; the drain of the second NMOS tube is connected to the power supply; the source of the second NMOS tube is connected to one end of the adjustable resistor, the other end of the adjustable resistor is connected to one end of the first feedback resistor, the other end of the first feedback resistor is connected to one end of the second feedback resistor, and the other end of the second feedback resistor is grounded; there is a third connection point between the first feedback resistor and the second feedback resistor; the third connection point is connected to the positive input end of the operational amplifier;

[0015] One end of the compensation capacitor is connected to the output end of the operational amplifier; the other end of the compensation capacitor is grounded.

[0016] Optionally, the voltage stabilization unit is a bandgap reference circuit.

[0017] Optionally, when the LDO circuit without off-chip capacitor is in standby mode, the switch of the target upper current branch is in a closed state, and the switch of the target lower current branch is in a closed state;

[0018] The target upper current branch is any current branch in the upper current branches; the target lower current branch is a current branch in the lower current branches corresponding to the target upper current branch.

[0019] Optionally, when the LDO circuit without off-chip capacitor is in working mode, the switch of the target upper current branch is in a closed state, and the switch of the target lower current branch is in a closed state;

[0020] The target upper current branch is at least one current branch in the upper current branch; the target lower current branch is at least one current branch in the lower current branch corresponding to the target upper current branch.

[0021] Optionally, when the LDO circuit without external capacitor is in working mode, the number of the target upper current branches is equal to the number of the target lower current branches, and both are determined according to an external load of the LDO circuit without external capacitor.

[0022] Optionally, the time when the switch of the target lower current branch is in the closed state is earlier than the time when the switch of the target upper current branch is in the closed state.

[0023] Optionally, when the LDO circuit without off-chip capacitor is in working mode, the resistance value of the adjustable resistor is a target resistance value;

[0024] When the resistance value of the adjustable resistor is the target resistance value, the output voltage of the output end of the LDO circuit without off-chip capacitor reaches the target voltage.

[0025] Optionally, the current of the upper current branch is smaller than the current of the corresponding lower current branch; and the total current of the first current branch is smaller than the total current of the second current branch.

[0026] An embodiment of the present application further provides an electronic device, wherein the electronic device includes the LDO circuit without external capacitor.

[0027] Through the above technical solution, it can be seen that the present application has the following beneficial effects:

[0028] The embodiment of the present application provides a low-dropout linear regulator LDO circuit without an external capacitor, and the LDO circuit without an external capacitor includes: a voltage stabilizing unit, a first NMOS tube, a PMOS tube, a first current branch, a second current branch and an on-chip capacitor. The output end of the voltage stabilizing unit is used to output a stable reference voltage. The gate of the first NMOS tube is connected to the output end of the voltage stabilizing unit; the gate of the first NMOS tube is used to input a stable reference voltage. The gate of the PMOS tube is connected to the drain of the first NMOS tube, and the connection point is the first connection point; the drain of the PMOS tube is connected to one end of the capacitor, and the connection point is the second connection point, and the second connection point is the output end of the LDO circuit without an external capacitor; the output end of the LDO circuit without an external capacitor is used to output a stable voltage; the source of the PMOS tube is connected to a power supply; the other end of the capacitor is grounded. The first current branch includes a target number of upper current branches connected in parallel with each other; a switch is provided in each upper current branch; one end of the first current branch is connected to the power supply; the other end of the first current branch is connected to the first connection point. The second current branch includes a target number of lower current branches connected in parallel with each other; each lower current branch is provided with a switch; one end of the second current branch is grounded; and the other end of the second current branch is connected to the second connection point.

[0029] In the LDO circuit without external capacitor, there is a loop 2 composed of a first NMOS tube and a PMOS tube. When the load of the LDO circuit without external capacitor increases, the current passing through the PMOS tube increases, so that the loop gain of loop 2 decreases, the loop bandwidth of loop 2 increases, and the load transient response capability of the LDO circuit without external capacitor is enhanced. In addition, by adding the first current branch and the second current branch to increase the current passing through the first NMOS tube, the loop gain of loop 2 can also be reduced, the loop bandwidth of loop 2 can be increased, and the load transient response capability of the LDO circuit without external capacitor is enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 A schematic diagram of the structure of a traditional external capacitor LDO circuit provided in an embodiment of the present application;

[0032] Figure 2 A schematic diagram of a structure of an LDO circuit without external capacitors provided in an embodiment of the present application;

[0033] Figure 3 A schematic diagram of the structure of another LDO circuit without external capacitors provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0035] In order to facilitate the understanding and explanation of the technical solution provided by the embodiments of the present application, the background technology of the embodiments of the present application is first described.

[0036] At present, LDO circuits are widely used in chip circuits due to their characteristics of stable output voltage and anti-noise ability, providing a stable voltage source for other modules in the chip.

[0037] LDO circuits can be divided into external capacitor LDO circuits and non-external capacitor LDO circuits. In external capacitor LDO circuits, there is generally an external capacitor, which has strong charging and discharging capabilities and can improve the load transient response capability of the LDO circuit.

[0038] Generally, the traditional LDO circuit structure can be found in Figure 1 , Figure 1 The schematic diagram of the structure of a conventional external capacitor LDO circuit provided in the embodiment of the present application is shown in FIG. Figure 1 As shown, the external capacitor LDO circuit includes an operational amplifier OP, an NMOS tube MN, and feedback resistors R0 and R1. The operational amplifier OP has a positive input terminal, a reverse input terminal, and an output terminal. The reverse input terminal inputs a reference voltage VREF, and the output terminal of the operational amplifier is connected to the gate of the NMOS tube MN. The source of MN is connected to one end of the feedback resistor R1, the other end of the feedback resistor R1 is connected to one end of the feedback resistor R0, and the other end of the feedback resistor R0 is grounded. The other end of the feedback resistor R1 is connected to the positive input terminal of the operational amplifier OP. The drain of the NMOS tube MN is connected to the power supply. The connection point between the source of MN and the feedback resistor R1 is point B, which is the output terminal of the LDO circuit. Point B is connected to one end of the external capacitor CL, and the other end of the external capacitor CL is grounded. Due to the existence of the external capacitor CL, the LDO circuit has a strong load transient response capability.

[0039] Traditional external capacitor LDO circuits require an extra pin on the chip circuit to connect the external capacitor, which will increase the design and volume of the circuit board and is not conducive to the miniaturization and miniaturization of the chip. When facing large current load transients, the output voltage of the current LDO circuit without external capacitor will overshoot or drop outside the reasonable range of LDO, resulting in poor load transient response capability of the LDO circuit without external capacitor.

[0040] Based on this, the embodiment of the present application provides a low-dropout linear regulator LDO circuit without external capacitors, including: a voltage stabilizing unit, a first NMOS tube, a PMOS tube, a first current branch, a second current branch and an on-chip capacitor. The output end of the voltage stabilizing unit is used to output a stable reference voltage. The gate of the first NMOS tube is connected to the output end of the voltage stabilizing unit, and the gate of the first NMOS tube is used to input a stable reference voltage. The gate of the PMOS tube is connected to the drain of the first NMOS tube, and the connection point is the first connection point. The drain of the PMOS tube is connected to one end of the capacitor, and the connection point is the second connection point, and the second connection point is the output end of the LDO circuit without external capacitors. The output end of the LDO circuit without external capacitors is used to output a stable voltage. The first current branch includes a target number of upper current branches connected in parallel to each other; a switch is provided in each upper current branch. The second current branch includes a target number of lower current branches connected in parallel to each other; a switch is provided in each lower current branch. Through this LDO structure, not only a stable voltage can be output, but also the load transient response capability of the LDO circuit can be improved.

[0041] See also Figure 2 , Figure 2 The schematic diagram of the structure of a LDO circuit without external capacitor provided in the embodiment of the present application is shown in FIG. Figure 2 As shown, the LDO circuit without external capacitor includes:

[0042] A voltage stabilizing unit, a first NMOS transistor MN0, a PMOS transistor MP, a first current branch IBPx, a second current branch IBNx and an on-chip capacitor CL.

[0043] The output end of the voltage stabilizing unit is used to output a stable reference voltage.

[0044] The gate of the first NMOS transistor MN0 is connected to the output end of the voltage stabilizing unit; the gate of the first NMOS transistor MN0 is used to input a stable reference voltage.

[0045] The gate of the PMOS tube MP is connected to the drain of the first NMOS tube MN0, and the connection point is the first connection point D; the drain of the PMOS tube MP is connected to one end of the capacitor CL, and the connection point is the second connection point C, and the second connection point C is the output end LDO_OUT of the LDO circuit without an external capacitor. The output end LDO_OUT of the LDO circuit without an external capacitor is used to output a stable voltage. The source of the PMOS tube MP is connected to the power supply VDD. The other end of the capacitor CL is grounded GND.

[0046] It should be noted that the structure of this embodiment enables the stable voltage outputted by the output terminal LDO_OUT of the LDO circuit without an external capacitor to be the set target voltage.

[0047] It should also be noted that the capacitor CL is used to enhance the load transient response capability of the LDO circuit without external capacitors. The capacitor CL includes parasitic capacitance. Generally speaking, due to the limited layout area of ​​the LDO circuit without external capacitors, the size of the capacitor CL is generally tens to hundreds of pF. If the layout area of ​​the LDO circuit without external capacitors allows, the larger the value of the capacitor CL, the better.

[0048] The first current branch IBPx includes a target number of lower current branches connected in parallel with each other; each lower current branch is provided with a switch. Figure 1 As shown, the switches provided in the first current branch IBPx are collectively referred to as KPx. One end of the first current branch IBPx is connected to the power supply VDD; the other end of the first current branch IBPx is connected to the first connection point D. As an example, the upper current branch is a current mirror. It should be noted that the target number can be determined according to the external load of the LDO circuit without external capacitor.

[0049] The second current branch IBNx includes a target number of lower current branches connected in parallel with each other; each lower current branch is provided with a switch. Figure 1 As shown, the switches provided in the second current branch IBNx are collectively referred to as KNx. One end of the second current branch IBNx is grounded GND, and the other end is connected to the second connection point C. As an example, the lower current branch is a current mirror.

[0050] It should be noted that the voltage stabilizing unit is used to Figure 2 The gate of the first NMOS transistor MN0 in the loop 2 (LOOP2) shown in FIG. 1 provides a stable reference voltage. As an example, the voltage stabilizing unit is a bandgap reference circuit. As another example, the voltage stabilizing unit is Figure 3 The voltage stabilizing unit shown in the figure can be found in the following Figure 3 It is understandable that the embodiment of the present application does not limit the specific structure of the voltage stabilizing unit, and it only needs to provide a stable reference voltage for the gate of the first NMOS transistor MN0.

[0051] In the embodiment of the present application, the first NMOS transistor MN0 and the PMOS transistor MP form a common-source common-gate negative feedback loop 2 (LOOP2). For LOOP2, the loop gain A of LOOP2 is V =A V0 *A VP *β. Among them, A V0 A represents the loop gain of the common-gate amplifier passing through the first NMOS tube MN0. Usually, a common-gate amplifier is a forward amplifier, and its gain is its transconductance multiplied by the impedance to ground. VP It represents the gain of the common-source inverting amplifier through the PMOS tube MP, and the gain is the impedance from the MP tube transconductance to the ground. β is the voltage division coefficient of the resistor branch. The bandwidth of LOOP2 can be very large, so that the LDO circuit without external capacitor has high load transient response capability, which can be reflected in the following two points.

[0052] First, by analyzing the load transient response of the LDO circuit without external capacitors, it can be found that when the current of the PMOS tube MP increases (that is, the load of the LDO circuit without external capacitors increases), the transconductance through the PMOS tube MP increases, and the slew rate increases (slew rate = gm / CL, gm is the transconductance of the MP tube). As the transconductance of the PMOS tube MP increases and the equivalent output impedance decreases, the loop gain A of LOOP2 V The loop gain bandwidth product of LOOP2 is constant. V When the value of LOOP2 is reduced, the loop bandwidth of LOOP2 increases. Because the loop bandwidth and slew rate of LOOP2 are increased, the load transient response capability of the LDO circuit without external capacitor is enhanced.

[0053] Second point, analysis of the loop stability of LOOP2 shows that the second connection point C has a capacitance of several hundred pF. Therefore, the second connection point C is the main pole, and the first connection point D is the secondary pole. When the output load of the LDO circuit without external capacitor is larger, the main pole will approach the secondary pole, which will cause the stability of LOOP2 to decrease. Increasing the current (i.e., the internal load current) passing through the first NMOS tube MN0 will push the secondary pole away from the main pole, thereby increasing the stability of LOOP2. In an embodiment of the present application, the current passing through the first NMOS tube MN0, i.e., the internal load current, is increased through the first current branch IBPx and the second current branch IBNx. When the current passing through the first NMOS tube MN0 increases, the on-resistance of IBPx is reduced, resulting in a loop gain A of LOOP2. V The LOOP2 bandwidth is increased, the slew rate is increased, and the load transient response capability of the LDO circuit without external capacitor is improved.

[0054] In summary, the circuit composed of the first NMOS transistor MN0, the PMOS transistor MP, the first current branch IBPx, the second current branch IBNx and the capacitor CL enables the LDO circuit without external capacitor to have a high load transient response capability.

[0055] In an embodiment of the present application, the LDO circuit without external capacitors is divided into a standby mode and an operating mode. When the LDO circuit without external capacitors is in standby mode, the switch of the target upper current branch is in a closed state, and the switch of the target lower current branch is in a closed state. Among them, the target upper current branch is any current branch in the upper current branch. The target lower current branch is a current branch in the lower current branch that corresponds to the target upper current branch. As an example, in standby mode, the switch KP0 corresponding to the upper current branch IBP0 in the first current branch IBPx is closed. The switch KN0 corresponding to the lower current branch IBN0 included in the second current branch IBNx is closed. In this way, the standby power consumption of the LDO circuit can be basically met, thereby realizing the standby low power consumption design of the LDO circuit.

[0056] It should be noted that in the standby mode, when the switch is closed, the switch of the lower current branch is closed first, and then the switch of the upper current branch is closed. When the LDO circuit without external capacitor is in the standby mode, the current of the target upper current branch is less than the current of the target lower current branch. For example, after closing the switches of the circuits where the upper current branch IBP0 and the lower current branch IBN0 are located, the current of the upper current branch IBP0 is less than the current of the lower current branch IBN0.

[0057] When the LDO circuit without off-chip capacitor is in working mode, the switch of the target upper current branch is in a closed state, and the switch of the target lower current branch is in a closed state. Wherein, the target upper current branch is at least one current branch in the upper current branch. The target lower current branch is at least one current branch in the lower current branch that corresponds to the target upper current branch. For example, the switches KP0, KP1 and KP2 corresponding to the upper current branches IBP0, IBP1 and IBP2 in the first current branch IBPx are closed. The switches KN0, KN1 and KN2 corresponding to the lower current branches IBN0, IBN1 and IBN2 in the second current branch IBNx are closed.

[0058] It is understandable that when the LDO circuit without external capacitor is converted from standby mode to working mode, according to the load requirement of the LDO circuit without external capacitor, it may be necessary to increase a certain number of upper current branches and the same number of lower current branches. At this time, it is necessary to close the switch in the upper current branch and the switch of the lower current branch to increase the current branch. During specific implementation, a certain number of switches of the lower current branch are closed first, and after a certain number of switches of the lower current branch are closed, the same number of switches of the upper current branch are closed. That is, the time when the switch of the target lower current branch is in a closed state is earlier than the time when the switch of the target upper current branch is in a closed state.

[0059] It should be noted that, whether the LDO circuit without external capacitor is in standby mode or working mode, when a lower current branch is added, that is, a switch of the lower current branch is closed, a corresponding upper current branch needs to be added, that is, a switch of the upper current branch is closed. For example, after closing the switch of the IBN0 branch, the switch of the IBP0 branch is closed.

[0060] That is to say, the upper current branch and the lower current branch are added in groups. When adding several lower current branches, several upper current branches must also be added. Moreover, it is necessary to add the lower current branch first, and then add the upper current branch. This is because if the upper current branch IBPx is connected first, the current cannot flow to the ground, and the current will charge the gate of the PMOS tube MP, causing the output of the LDO circuit to decrease. If the lower current branch IBNx is connected first, since the current of the upper current branch IBPx is not connected, the current will first flow to IBNx through the PMOS tube MP. Similarly, if the current of the upper current branch IBPx is greater than the current of the lower current branch IBNx, it will also cause the current to be unable to flow to the ground, and the current will charge the gate of the PMOS tube MP, resulting in a decrease in the output of the LDO circuit.

[0061] By adding a plurality of groups of upper current branches and lower current branches, the internal load current of the LDO circuit without external capacitor is increased and the load transient response characteristic is enhanced.

[0062] It should be noted that the larger the internal load current of the LDO circuit without external capacitors, the better the load transient response characteristics. In a specific application process, when the LDO circuit without external capacitors is in working mode, the number of target upper current branches and the number of target lower current branches are determined according to the external load of the LDO circuit without external capacitors. That is, in the working mode, the number of upper current branches working in the first current branch IBPx and the number of lower current branches working in the second current branch IBNx are determined according to the external load of the LDO circuit without external capacitors.

[0063] In addition, the current of the upper current branch is smaller than the current of the corresponding lower current branch. It can be obtained that the total current of the first current branch is smaller than the total current of the second current branch. For example, the current of the upper current branch IBP2 is smaller than the current of the corresponding lower current branch IBN2.

[0064] By the non-chip capacitor LDO circuit provided by the embodiment of the present application, a stable voltage can be output. And there is a loop 2 composed of a first NMOS tube and a PMOS tube in the non-chip capacitor LDO circuit provided by the embodiment of the present application. When the load of the non-chip capacitor LDO circuit increases, the current through the PMOS tube increases, so that the loop gain of loop 2 decreases, the loop bandwidth of loop 2 increases, and the load transient response capability of the non-chip capacitor LDO circuit is enhanced. In addition, by increasing the first current branch and the second current branch so that the current through the first NMOS tube increases, the loop gain of loop 2 can also be reduced, the loop bandwidth of loop 2 increases, and the load transient response capability of the non-chip capacitor LDO circuit is enhanced. The non-chip capacitor LDO circuit provided by the embodiment of the present application has a simple structure, a small circuit scale, and a high load transient response capability. In addition, the upper current branch in the first current branch and the lower current branch in the second current branch in the non-chip capacitor LDO circuit can be flexibly set according to the load of the LDO circuit, and very low standby power consumption can be achieved.

[0065] See also Figure 3 , Figure 3 This is a schematic diagram of another LDO circuit without external capacitors provided in an embodiment of the present application. Figure 3 As shown, the voltage stabilizing unit in the circuit specifically includes:

[0066] An operational amplifier OP, a second NMOS transistor MN1, a compensation capacitor Cm, an adjustable resistor Ract, a first feedback resistor R1 and a second feedback resistor R0.

[0067] The operational amplifier OP includes a positive input terminal, a negative input terminal and an output terminal. Among them, the negative input terminal is connected to the input reference voltage VREF, and the output terminal of the operational amplifier OP is the output terminal of the voltage stabilization unit, that is, Figure 3 Point A in the figure is the output end of the voltage stabilizing unit, and point A is connected to the gate of the first NMOS tube.

[0068] The gate of the second NMOS tube MN1 is connected to the output end of the operational amplifier OP, the drain of the second NMOS tube MN1 is connected to the power supply VDD, and the source of the second NMOS tube MN1 is connected to one end of the adjustable resistor Ract. The other end of the adjustable resistor Ract is connected to one end of the first feedback resistor R1, the other end of the first feedback resistor R1 is connected to one end of the second feedback resistor R0, and the other end of the second feedback resistor R0 is grounded GND. There is a third connection point B between the first feedback resistor R1 and the second feedback resistor R0; the third connection point B is connected to the positive input end of the operational amplifier. Among them, the adjustable resistor Ract, the first feedback resistor R1 and the second feedback resistor R0 form a resistor negative feedback network.

[0069] It should be noted that loop 1 (LOOP1) is composed of an operational amplifier OP, a second NMOS tube MN1 and a resistor negative feedback network. The structure of LOOP1 is basically the same as that of a traditional LDO circuit, and its function is to determine the stable output voltage at point E. LOOP1 is a negative feedback loop, and the voltage VE at point E is determined by the following formula:

[0070] VE=VREF*(Ract+R0+R1) / R0

[0071] because Figure 3 The second NMOS transistor MN1 and the first NMOS transistor MN0 are controlled by the same gate voltage, and the gate voltage VGS of the second NMOS transistor MN1 and the first NMOS transistor MN0 relative to the source is substantially equal. Therefore, the output voltage of the output terminal LDO_OUT of the LDO circuit without external capacitor in the embodiment of the present application is substantially equal to the stable output voltage at point E, which is also determined by the above formula.

[0072] In addition, for LOOP1, point A is the main pole of the loop, so a larger compensation capacitor Cm is connected to point A. The compensation capacitor Cm enables LOOP1 to maintain good stability. Specifically, one end of the compensation capacitor Cm is connected to the output end of the operational amplifier OP, and the other end of the compensation capacitor Cm is grounded GND.

[0073] As an example, Cm is the Miller compensation capacitor. In practical applications, it can be based on the following Figure 1 The stability of LOOP1 shown in FIG. 1 is determined by the selection of compensation capacitor Cm. Since LOOP1 is not affected by the output load, the stability of LOOP1 is also not affected by the output load.

[0074] It should be noted that, in the embodiment of the present application, the voltage stabilizing unit is Figure 3In the structure shown, when the LDO circuit without external capacitor is in working mode, it is necessary to adjust the adjustable resistor Ract until the target resistance value, at which time, the output voltage at the output end of the LDO circuit without external capacitor reaches the target voltage. It can be understood that the first feedback resistor R1 and the second feedback resistor R0 are resistors with fixed resistance values. The resistor negative feedback network can be used to adjust the output voltage, power consumption and other values ​​of the output end of the LDO circuit without external capacitor.

[0075] The non-off-chip capacitor LDO circuit provided by the embodiment of the present application provides a specific structure of a stabilizing unit, so that the non-off-chip capacitor LDO circuit can output a stable voltage. The loop 2 composed of the first NMOS tube and the PMOS tube in the non-off-chip capacitor LDO circuit, and the first current branch and the second current branch that can be flexibly set according to the load make the non-off-chip capacitor LDO circuit have a strong load transient response capability. The non-off-chip capacitor LDO circuit provided by the embodiment of the present application has a simple structure, a small circuit scale, and a high load transient response capability. In addition, the first current branch and the second current branch in the non-off-chip capacitor LDO circuit can be flexibly set according to the load of the LDO circuit, and can achieve very low standby power consumption.

[0076] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the system disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the system part description.

[0077] It should also be noted that, in this article, the term "includes", "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0078] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A LDO circuit without external capacitor, characterized in that: The LDO circuit without off-chip capacitors comprises: a voltage stabilizing unit, a first NMOS transistor, a PMOS transistor, a first current branch, a second current branch and an on-chip capacitor; The output end of the voltage stabilizing unit is used to output a stable reference voltage; The gate of the first NMOS tube is connected to the output end of the voltage stabilizing unit; the gate of the first NMOS tube is used to input the stable reference voltage; The gate of the PMOS tube is connected to the drain of the first NMOS tube, and the connection point is a first connection point; the drain of the PMOS tube is connected to one end of the capacitor, and the connection point is a second connection point, and the second connection point is the output end of the LDO circuit without external capacitor; the output end of the LDO circuit without external capacitor is used to output a stable voltage; the source of the PMOS tube is connected to a power supply; the other end of the capacitor is grounded; The first current branch includes a target number of upper current branches connected in parallel with each other; each of the upper current branches is provided with a switch; one end of the first current branch is connected to the power supply; the other end of the first current branch is connected to the first connection point; The second current branch includes the target number of lower current branches connected in parallel with each other; each of the lower current branches is provided with a switch; one end of the second current branch is grounded; and the other end of the second current branch is connected to the second connection point.

2. The LDO circuit without external capacitor according to claim 1, characterized in that: The voltage stabilizing unit includes: an operational amplifier, a second NMOS tube, a compensation capacitor, an adjustable resistor, a first feedback resistor and a second feedback resistor; The operational amplifier comprises a positive input terminal, a reverse input terminal and an output terminal; the reverse input terminal is connected to an input reference voltage; the output terminal of the operational amplifier is the output terminal of the voltage stabilizing unit; The gate of the second NMOS tube is connected to the output end of the operational amplifier; the drain of the second NMOS tube is connected to the power supply; the source of the second NMOS tube is connected to one end of the adjustable resistor, the other end of the adjustable resistor is connected to one end of the first feedback resistor, the other end of the first feedback resistor is connected to one end of the second feedback resistor, and the other end of the second feedback resistor is grounded; there is a third connection point between the first feedback resistor and the second feedback resistor; the third connection point is connected to the positive input end of the operational amplifier; One end of the compensation capacitor is connected to the output end of the operational amplifier; the other end of the compensation capacitor is grounded.

3. The LDO circuit without external capacitor according to claim 1, characterized in that: The voltage stabilizing unit is a bandgap reference circuit.

4. The LDO circuit without external capacitor according to any one of claims 1 to 3, characterized in that: When the LDO circuit without off-chip capacitor is in standby mode, the switch of the target upper current branch is in a closed state, and the switch of the target lower current branch is in a closed state; The target upper current branch is any current branch among the upper current branches; The target lower current branch is a current branch in the lower current branch corresponding to the target upper current branch.

5. The LDO circuit without external capacitor according to any one of claims 1 to 3, characterized in that: When the LDO circuit without off-chip capacitor is in working mode, the switch of the target upper current branch is in a closed state, and the switch of the target lower current branch is in a closed state; The target upper current branch is at least one current branch in the upper current branch; the target lower current branch is at least one current branch in the lower current branch corresponding to the target upper current branch.

6. The LDO circuit without external capacitor according to claim 5, characterized in that: When the LDO circuit without external capacitor is in working mode, the number of the target upper current branches is equal to the number of the target lower current branches, and both are determined according to the external load of the LDO circuit without external capacitor.

7. The LDO circuit without external capacitor according to claim 5, characterized in that: The time when the switch of the target lower current branch is in the closed state is earlier than the time when the switch of the target upper current branch is in the closed state.

8. The LDO circuit without external capacitor according to claim 2, characterized in that: When the LDO circuit without off-chip capacitor is in working mode, the resistance value of the adjustable resistor is a target resistance value; When the resistance value of the adjustable resistor is the target resistance value, the output voltage of the output end of the LDO circuit without off-chip capacitor reaches the target voltage.

9. The LDO circuit without external capacitor according to claim 4, characterized in that: The current of the upper current branch is smaller than the current of the corresponding lower current branch; the total current of the first current branch is smaller than the total current of the second current branch.

10. An electronic device, characterized in that: The electronic device comprises the LDO circuit without external capacitor according to any one of claims 1 to 9.

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