A dual-chip intercommunication method and device

Abstract

The application provides a kind of double-chip communication method and device, the method includes: the SPI single channel of initialization master controller and slave controller is established Synchronous communication between two controllers;When the master controller receives the predetermined signal of slave controller, start the SPI communication of master controller and slave controller;Wherein, the frame data of sending end is filled in buffer after pre-transmission, frame buffer is switched by pointer to carry out frame data transmission;Real-time detection whether there is communication abnormality between master controller and slave controller;If there is no communication abnormality, it is detected that master controller or slave controller grants trust completion, then the next frame data is processed.The scheme can avoid the problem of different step of SPI communication between chips, and guarantee normal and reliable communication between chips.

Description

Technical Field

[0001] This invention belongs to the field of communications, and particularly relates to a method and apparatus for communication between two chips. Background Technology

[0002] The rapid development of automotive technology has raised the bar for vehicle intelligence. To achieve intelligent in-vehicle products, factors such as cost and ease of function implementation need to be considered comprehensively. Multi-chip solutions are increasingly widely used in areas such as intelligent driving because they not only improve vehicle computing performance but also play an important role in vehicle redundancy control. However, efficient, reliable, and stable communication between multiple chips has become a major challenge in multi-chip solutions.

[0003] Inter-CPU communication can utilize various serial communication methods. Considering factors such as communication speed, scalability, compatibility, and quality, SPI communication is commonly used for inter-chip communication. However, due to limitations in the SPI hardware resources of different CPUs, it is often necessary to design software to conserve scarce port resources. Furthermore, because different CPUs may run different operating systems, precise synchronization between CPUs can occur, leading to issues with accurate and normal signal transmission in specific or extreme situations. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a method and apparatus for communication between two chips to solve the problem of possible anomalies in existing inter-chip SPI communication.

[0005] In a first aspect of the present invention, a method for communication between two chips is provided, comprising:

[0006] Initialize the SPI single channel of the master controller and slave controller, and establish synchronous communication between the two controllers;

[0007] When the master controller receives the predetermined signal from the slave controller, it initiates SPI communication between the master controller and the slave controller.

[0008] Both the master controller and the slave controller are configured with a sending authorization buffer space, a sending authorization lock state, a sending authorization update state, and a sending authorization frame type. After the sending end fills the pre-sent frame data in the buffer, it switches the frame buffer through a pointer to send the frame data.

[0009] Real-time detection of communication anomalies between the master controller and slave controller;

[0010] If there are no communication anomalies, and the master controller or slave controller has completed authorization, then the next frame of data will be processed.

[0011] In a second aspect of the present invention, a dual-chip inter-communication device is provided, comprising at least a master controller, a slave controller, and an SPI bus;

[0012] The master controller is used to initialize the SPI channel, establish synchronous communication with the slave controller, and start SPI communication with the slave controller after receiving a predetermined signal from the slave controller. It also detects in real time whether there is a communication abnormality with the slave controller. If there is no communication abnormality, it processes the next frame of data after detecting that the slave controller has completed the authorization.

[0013] The slave controller is used to initialize the SPI channel, establish synchronous communication with the master controller, send a predetermined signal to the master controller, start SPI communication with the master controller, and detect in real time whether there is a communication abnormality with the master controller. If there is no communication abnormality, after the master controller completes the authorization, the next frame of data is processed.

[0014] When the master controller and slave controller start SPI communication, they both set the send authorization buffer space, send authorization lock state, send authorization update state, and send authorization frame type. After the sending end fills the pre-send frame data in the buffer, it switches the frame buffer through the pointer to send the frame data.

[0015] In a third aspect of the present invention, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable by the processor, wherein the processor executes the computer program to implement the steps of the method as described in the first aspect of the present invention.

[0016] In a fourth aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the method provided in the first aspect of the present invention.

[0017] In this embodiment of the invention, a multi-buffer combination with a buffer locking mechanism is used to achieve inter-chip communication and to monitor communication anomalies in real time during the communication process. This enables both synchronous communication between CPUs of different systems and ensures normal and reliable SPI communication between chips. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1This is a schematic flowchart of a dual-chip communication method according to an embodiment of the present invention;

[0020] Figure 2 This is another schematic flowchart illustrating a method for communication between two chips according to an embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram of a dual-chip communication device provided in one embodiment of the present invention. Detailed Implementation

[0022] To make the objectives, features, and advantages of this invention more apparent and understandable, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0023] It should be understood that the terms "comprising" and other similar expressions in the specification, claims, and accompanying drawings of this invention are intended to cover a non-exclusive inclusion, such as a process, method, system, or apparatus that includes a series of steps or units and is not limited to the listed steps or units. Furthermore, "first" and "second" are used to distinguish different objects and are not intended to describe a specific order.

[0024] Please see Figure 1 A flowchart illustrating a dual-chip communication method provided in this embodiment of the invention includes:

[0025] S101. Initialize the SPI single channel of the master controller and slave controller, and establish synchronous communication between the two controllers;

[0026] The master controller and slave controller can be MCU (Microcontroller Unit) or SOC (System on Chip) chips, etc.

[0027] This includes initializing the hardware port of the SPI single channel, the on-chip peripheral clock system, the DMA module, and the drivers for associated peripheral functions.

[0028] SPI (Serial Peripheral Interface) single-channel initialization mainly refers to the initialization of hardware ports, on-chip peripheral clock system, DMA (Direct Memory Access) module, and driver initialization of associated peripheral functions.

[0029] Establishing synchronous communication involves the master and slave controllers initializing their respective SPI single channels. Once the slave controller has completed its initialization, it notifies the master controller that its initialization operation is ready via specific control signal lines. Specifically, when the slave controller completes its SPI signaling preparation, it notifies the master controller of its readiness by controlling specific communication enable signal lines, such as pulling them from high to low or from low to high, or by controlling the output of specific square wave pulse signals.

[0030] S102. When the master controller receives the predetermined signal from the slave controller, it starts the SPI communication between the master controller and the slave controller.

[0031] The predetermined signal is a ready signal from the controller side, which can be in the form of a square wave pulse, etc. When the main controller receives the signal, it can start the communication between the two controllers.

[0032] Specifically, the initiation of SPI communication between the master controller and the slave controller includes:

[0033] The master controller starts the SPI single-channel communication peripheral and associated DMA module, selects the slave controller and controls the output of MOSI and CLK signals;

[0034] The controller initiates the SPI single-channel communication peripheral and begins sending or receiving data.

[0035] Both the master controller and the slave controller are configured with a sending and granting buffer space, a sending and granting lock state, a sending and granting update state, and a sending and granting frame type. After the sending end fills the buffer with the pre-sent frame data, it switches the frame buffer through a pointer to send the frame data.

[0036] The send and receive buffer space refers to the buffer area used to store send and receive frame data; the send and receive lock state refers to the mutual exclusion lock state when the driver layer and the application layer use the send and receive buffer resources; the send and receive update state refers to the state when the application layer has finished filling the send and receive buffer or the receive and receive buffer area; the send and receive frame type refers to the data frames used to distinguish different types in a single-channel SPI.

[0037] In one embodiment, such as Figure 2 As shown, after the transmitting end (sender, i.e., the master controller) generates a transmission request task, it fills the task request data into the CAN frame. After the frame data is filled in the buffer, it feeds back the buffer address of the data frame to the driver layer. The driver layer then sends the data to the slave controller (authorizing end) via the SPI bus. The master controller switches the frame buffer through the address pointer to send different frame data.

[0038] Specifically, the address of the buffer filled with frame data points to the driver layer, and the driver layer sends the frame data through the SPI bus;

[0039] The driver layer is a software layer used to set the SPI module to work in a specific mode. The specific mode may include at least the communication frequency, baud rate, communication frame size, communication frame definition, and data validity verification method.

[0040] The application layer refers to the software layer that needs to use the specific data of each field in SPI communication.

[0041] The data validity verification includes, but is not limited to, defining a specific frame format, using specific frame headers, frame trailers, frame sequence numbers, summation verification methods, or CRC verification methods.

[0042] S103. Real-time detection of communication abnormalities between the master controller and the slave controller;

[0043] The communication anomaly refers to an anomaly in data communication between the master controller and the slave controller, i.e., an anomaly in frame data transmission.

[0044] Among them, communication anomaly detection includes at least detecting the validity of data frame headers, authorization data and verification, and determining the validity of anomaly flags in data frames.

[0045] If an anomaly is detected by any of the three detection methods, the current frame is discarded and the data from the previous frame is retained.

[0046] In one embodiment, if the master controller continuously detects an anomaly within a specific time period, it actively stops communication with the slave controller and cuts off the power supply to the slave controller before restarting it.

[0047] If an anomaly is continuously detected by the slave controller within a specific time period, communication with the master controller will be actively stopped. After the master and slave controllers restart the SPI module, the slave controller will initiate a communication request again.

[0048] For anomaly detection, if the master detects an anomaly for a specific period of time, it will proactively stop communication with the slave and cut off the slave's power supply (this requires hardware design coordination, i.e., the slave's power supply is controlled by the master through a specific monitoring mechanism), thereby restarting the slave system to restore communication. If the slave detects an anomaly for a specific period of time, it will request the master to stop communication. After both the master and slave restart the SPI communication module, the slave will re-initiate a request to resume communication, thus restoring communication.

[0049] The request from the controller to the main controller to stop communication mainly involves controlling the transmission of signals on specific communication permission signal lines, such as pulling from low level to high level or from high level to low level, i.e., controlling the output of specific square wave pulse signals.

[0050] S104. If there is no communication abnormality and the master controller or slave controller is detected to have completed authorization, then process the next frame of data.

[0051] Specifically, when data transmission is completed on the master controller and the chip select signal is set to invalid, a frame end interrupt is generated on the slave controller. After entering the interrupt, the next frame is processed.

[0052] Specifically, the trustee driver performs a checksum verification on the received frame data. If the verification passes, it determines the current frame type and saves it. If the application layer corresponding to the current frame type has already completed the frame data copy, it switches the trustee buffer pointer.

[0053] The sending end driver obtains the sending type of the previous frame and determines whether the frame data of the next frame has been filled into the sending buffer. If the frame data is filled and ready, the sending end switches the sending buffer pointer to send the next frame data.

[0054] The authorization side swaps the authorization buffer pointers of the driver layer and the current received frame with respect to the application layer, in order to receive the next frame data packet; the sending side driver swaps the sending buffer pointers of the driver layer and the application layer, and the next frame sent is a data packet with the swapped type.

[0055] The conditions for switching the buffer pointers of the authorization and transmission are including but not limited to: the authorization side data and verification are passed, the valid data in the authorization side application layer buffer (the driver side buffer of the previous frame) has been taken by the relevant application, and the transmission side application layer buffer has been filled by the relevant application.

[0056] Furthermore, just before the system is about to enter sleep mode, the slave end sends the sleep condition back to the master end via SPI. The master end confirms that the system needs to enter sleep mode through comprehensive logic. At this time, the power supply to the slave end system is cut off through power control, and the slave end stops working and synchronously stops SPI signaling processing.

[0057] In this embodiment, a multi-buffered locking mechanism is used to resolve the frame loss issue caused by the lack of strict alternation in data transmission and authorization between the master and slave devices due to system asynchrony. Through a synchronous communication control mechanism, combined with specific communication data packet definitions and an anomaly detection mechanism for specific communication data packets, rapid monitoring of communication anomalies is ensured, and fast and effective recovery measures are implemented. Even under CPU load fluctuations, the master and slave ends can still achieve ideal communication performance, thus guaranteeing normal and reliable SPI communication between chips.

[0058] Meanwhile, the communication method provided in this embodiment meets automotive-grade ASILB requirements, satisfying stringent automotive-grade functional safety requirements while fulfilling functional requirements. Effective communication of multiple types of frame data via a single channel is achieved through well-planned hardware and software design.

[0059] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0060] Figure 3 This is a schematic diagram of a dual-chip communication device provided in an embodiment of the present invention. The device includes a master controller, a slave controller, and an SPI bus.

[0061] The main controller 310 is used to initialize the SPI channel, establish synchronous communication with the slave controller, and start SPI communication with the slave controller after receiving a predetermined signal from the slave controller. It also detects in real time whether there is a communication abnormality with the slave controller. If there is no communication abnormality, it processes the next frame of data after detecting that the slave controller has completed the authorization.

[0062] The slave controller 320 is used to initialize the SPI channel, establish synchronous communication with the master controller, send a predetermined signal to the master controller, start SPI communication with the master controller, and detect in real time whether there is a communication abnormality with the master controller. If there is no communication abnormality, after the master controller completes the authorization, the next frame of data is processed.

[0063] When the master controller and slave controller start SPI communication, they both set the send authorization buffer space, send authorization lock state, send authorization update state, and send authorization frame type. After the sending end fills the pre-send frame data in the buffer, it switches the frame buffer through the pointer to send the frame data.

[0064] The initialization of the SPI single channel includes:

[0065] Initialize the hardware port of the SPI single channel, the on-chip peripheral clock system, the DMA module, and the drivers for associated peripheral functions.

[0066] The process of initiating SPI communication between the master controller and the slave controller includes:

[0067] The master controller starts the SPI single-channel communication peripheral and associated DMA module, selects the slave controller and controls the output of MOSI and CLK signals;

[0068] The controller initiates the SPI single-channel communication peripheral and begins sending or receiving data.

[0069] Specifically, the step of switching the frame buffer via pointer to send frame data includes:

[0070] The address of the buffer filled with frame data points to the driver layer, and the driver layer sends data through the SPI bus;

[0071] The driver layer is a software layer used to set the SPI module to work in a specific mode. The specific mode includes communication frequency, baud rate, communication frame size, communication frame definition, and data validity verification method.

[0072] Preferably, detecting communication anomalies between the master controller and the slave controller includes: at least detecting the validity of the data frame header, the authorization data and verification, and determining the validity of the anomaly flag in the data frame.

[0073] Preferably, the exception handling mechanisms for the master controller and slave controller include:

[0074] If the master controller continuously detects an anomaly within a specific time period, it will proactively stop communication with the slave controller and cut off the power supply to the slave controller before restarting it.

[0075] If an anomaly is continuously detected by the slave controller within a specific time period, communication with the master controller will be actively stopped. After the master and slave controllers restart the SPI module, the slave controller will initiate a communication request again.

[0076] In one embodiment, the authorization driver performs a verification on the received frame data. If the verification passes, it determines the current frame type and saves it. If the application layer corresponding to the current frame type has already completed the frame data copying, it switches the authorization buffer pointer.

[0077] The sending end driver obtains the sending type of the previous frame and determines whether the frame data of the next frame has been filled into the sending buffer. If the frame data is filled and ready, the sending end switches the sending buffer pointer to send the next frame data.

[0078] It should be understood that the aforementioned inter-chip communication device can be a vehicle control module, enabling specific control of the vehicle through the dual chips. The hardware components not shown in this embodiment can be referenced from existing vehicle controllers.

[0079] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0080] Those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium. When the program is executed, it implements part or all of the processes in steps S101 to S104. The storage medium includes, for example, ROM / RAM.

[0081] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0082] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for communication between two chips, characterized in that, include: Initialize the SPI single channel of the master controller and slave controller, and establish synchronous communication between the two controllers; When the master controller receives the predetermined signal from the slave controller, it initiates SPI communication between the master controller and the slave controller. Both the master controller and the slave controller are configured with a sending authorization buffer space, a sending authorization lock state, a sending authorization update state, and a sending authorization frame type. After the sending end fills the pre-sent frame data in the buffer, it switches the frame buffer through a pointer to send the frame data. The sending and receiving buffer space is a buffer area used to store sending and receiving frame data; the sending and receiving lock state refers to the mutual exclusion locking state when the driver layer and the application layer use the sending and receiving buffer resources; the sending and receiving update state refers to the state when the application layer has finished filling the sending and receiving buffer or receiving the receiving and receiving buffer; the sending and receiving frame type refers to the data frames used to distinguish different types in a single-channel SPI. The step of sending frame data by switching the frame buffer via a pointer includes: The address of the buffer filled with frame data points to the driver layer, and the driver layer sends data through the SPI bus; The driver layer is a software layer used to set the SPI module to work in a specific mode. The specific mode includes communication frequency, baud rate, communication frame size, communication frame definition and data validity verification method. Real-time detection of communication anomalies between the master controller and slave controller; If there are no communication anomalies, and the master controller or slave controller has completed authorization, then the next frame of data will be processed.

2. The method according to claim 1, characterized in that, The initialization of the master controller and slave controller's SPI single channel includes: Initialize the hardware port of the SPI single channel, the on-chip peripheral clock system, the DMA module, and the drivers for associated peripheral functions.

3. The method according to claim 1, characterized in that, The initiation of SPI communication between the master controller and the slave controller includes: The master controller starts the SPI single-channel communication peripheral and associated DMA module, selects the slave controller and controls the output of MOSI and CLK signals; The controller initiates the SPI single-channel communication peripheral and begins sending or receiving data.

4. The method according to claim 1, characterized in that, The real-time detection of communication anomalies between the master controller and the slave controller includes: At a minimum, the validity of the data frame header, the authorization data and verification, and the validity of the abnormal flags in the data frame should be checked.

5. The method according to claim 1, characterized in that, The real-time detection of communication anomalies between the master controller and the slave controller includes: If the master controller continuously detects an anomaly within a predetermined time period, it will actively stop communication with the slave controller and cut off the power supply to the slave controller before restarting it. If an anomaly is continuously detected by the slave controller within a predetermined time period, communication with the master controller will be actively stopped. After the master and slave controllers restart the SPI module, the slave controller will initiate a communication request again.

6. The method according to claim 1, characterized in that, The step of processing the next frame of data after detecting that the master controller or slave controller has completed authorization also includes: The trustee driver performs a checksum verification on the received frame data. If the verification passes, it determines the current frame type and saves it. If the application layer corresponding to the current frame type has already completed the frame data copy, it switches the trustee buffer pointer. The sending end driver obtains the sending type of the previous frame and determines whether the frame data of the next frame has been filled into the sending buffer. If the frame data is filled and ready, the sending end switches the sending buffer pointer to send the next frame data.

7. A dual-chip inter-communication device, characterized in that, It includes at least a master controller, a slave controller, and an SPI bus; The master controller is used to initialize the SPI channel, establish synchronous communication with the slave controller, and start SPI communication with the slave controller after receiving a predetermined signal from the slave controller. It also detects in real time whether there is a communication abnormality with the slave controller. If there is no communication abnormality, it processes the next frame of data after detecting that the slave controller has completed the authorization. The slave controller is used to initialize the SPI channel, establish synchronous communication with the master controller, send a predetermined signal to the master controller, start SPI communication with the master controller, and detect in real time whether there is a communication abnormality with the master controller. If there is no communication abnormality, after the master controller completes the authorization, the next frame of data is processed. When the master controller and slave controller start SPI communication, they both set the sending authorization buffer space, sending authorization lock state, sending authorization update state, and sending authorization frame type. After the sending end fills the pre-send frame data in the buffer, it switches the frame buffer through the pointer to send the frame data. The sending and receiving buffer space is a buffer area used to store sending and receiving frame data; the sending and receiving lock state refers to the mutual exclusion locking state when the driver layer and the application layer use the sending and receiving buffer resources; the sending and receiving update state refers to the state when the application layer has finished filling the sending and receiving buffer or receiving the receiving and receiving buffer; the sending and receiving frame type refers to the data frames used to distinguish different types in a single-channel SPI. The step of sending frame data by switching the frame buffer via a pointer includes: The address of the buffer filled with frame data points to the driver layer, and the driver layer sends data through the SPI bus; The driver layer is a software layer used to set the SPI module to work in a specific mode. The specific mode includes communication frequency, baud rate, communication frame size, communication frame definition, and data validity verification method.

8. The apparatus according to claim 7, characterized in that, At least the validity of the data frame header, the authorization data and verification, and the validity of the abnormal flags in the data frame should be checked to determine whether there is a communication abnormality between the master controller and the slave controller.

9. The apparatus according to claim 7, characterized in that, If the master controller continuously detects an anomaly within a predetermined time period, it will actively stop communication with the slave controller and cut off the power supply to the slave controller before restarting it. If an anomaly is continuously detected by the slave controller within a predetermined time period, communication with the master controller will be actively stopped. After the master and slave controllers restart the SPI module, the slave controller will initiate a communication request again.

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