Reconfigurable fractional order computing system with efficient use of fpga resources

Abstract

The application discloses a reconfigurable fractional order calculation system with high-efficiency FPGA resource utilization. After input data is normalized and converted into single-precision floating-point numbers by a data preprocessing module, a control module receives binomial coefficient theoretical calculation parameters and binomial coefficient segmented linear fitting parameters set by a user, controls a binomial coefficient fitting module to calculate binomial coefficients and perform segmented linear fitting, configures configuration parameters required by a fixed window length calculation module and a segmented linear function calculation module according to a fitting result, and starts the fixed window length calculation module and the segmented linear function calculation module to perform fractional order calculation after the configuration is completed, so that a fractional order calculation result of the input data is obtained. The application is based on a fixed window (FWL) with error compensation and a multi-segment linear function (PWL), realizes a real-time reconfigurable fractional order calculation system on an FPGA platform, improves the FPGA resource utilization efficiency, and guarantees the precision and efficiency of the fractional order calculation.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of digital signal processing, and more particularly relates to a reconfigurable fractional order calculation system with efficient FPGA resource utilization. BACKGROUND

[0002] Fractional order calculation (FC) is to generalize the integral and differential operation of integer order to non-integer, which can more accurately and truly describe physical, biological, chemical, electrical and other natural phenomena. At present, fractional calculus operation has been widely used in synovial membrane control, multi-dimensional chaotic system, weak signal detection, speech encryption, digital filtering, memristor, image recognition, neuron simulation and other technical fields.

[0003] At present, the main calculation methods of fractional calculus are Grunwald-Letnikov (GL), Caputo and Riemann-Liouville (RL). The most common hardware implementation methods of fractional order calculation are analog method (or continuous method) and digital method (or discrete method). In the analog method, commercial passive devices (resistor, capacitor) and active devices (operational amplifier, multiplier, CCII, analog switch) are used for circuit design, PCB manufacturing and debugging. Arbitrary waveform generator (AWG) and digital oscilloscope (DO) are used to generate excitation signal and display FC result. In the analog method, Valsa CPE and ASCI are usually used for fractional differential or integral operation. The digital method mainly realizes fractional order calculation through power series expansion (PSE), MacLaurin expansion, Taylor series and direct method. However, the finite memory method based on GL definition is the most direct and efficient method, which is also the method commonly used by most scholars. Any digital implementation method needs to consider the balance between calculation speed and accuracy. Larger memory space helps to improve the calculation accuracy of fractional order calculation, which also means longer calculation time. This makes it difficult to realize the hardware platform of fractional order system based on microprocessor. SUMMARY

[0004] The purpose of the present application is to overcome the shortcomings of the prior art and provide a reconfigurable fractional order calculation system with efficient FPGA resource utilization. Based on the fixed window with error compensation (FWL) and the piecewise linear function (PWL), a real-time reconfigurable fractional order calculation system is realized on the FPGA platform, which improves the efficiency of FPGA resource utilization while ensuring the accuracy and efficiency of fractional order calculation.

[0005] In order to achieve the above-mentioned purposes, the reconfigurable fractional order calculation system with FPGA resource high efficient utilization comprises a data preprocessing module, a control module, a binomial coefficient fitting module, a fixed window length calculation module and a segmented linear function calculation module, wherein the data preprocessing module, the fixed window length calculation module and the segmented linear function calculation module are realized in the FPGA, and wherein:

[0006] The data preprocessing module is used for normalizing the input data to the range [-1, 1] and converting the input data into single-precision floating-point numbers, and then sending the processed data x(n) to the fixed window length calculation module and the segmented linear function calculation module;

[0007] The control module is used for receiving the binomial coefficient theoretical calculation parameters set by a user, including a fractional order α and a total window length WL s , and the binomial coefficient segmented linear fitting parameters, including a fixed window length WL, a fitting segment number K and the number L of binomial coefficients in each fitting segment k , k = 1, 2, …, K, wherein The control module sends the binomial coefficient theoretical calculation parameters and the binomial coefficient segmented linear fitting parameters to the binomial coefficient fitting module; after the control module receives the WL binomial coefficients b(0):b(WL-1) and the slope β of each segmented linear function fed back by the binomial coefficient fitting module, k the control module calculates and configures the configuration parameters required by the fixed window length calculation module and the segmented linear function calculation module, and starts the fixed window length calculation module and the segmented linear function calculation module to perform fractional order calculation after the configuration is completed, and the parameter calculation and configuration method is as follows:

[0008] For the fixed window length calculation module, first, the number of the first calculation units in the fixed window length calculation module is configured as WL, and the coefficient of the multiplier in the dth first calculation unit CU1_d is set as d = 1, 2, …, WL, and the time delay lat1 of the variable depth shift register in the WL first calculation units CU1_d is set as lat1 = 2 × lat acc + level × lat add , wherein lat acc is the operation period of the accumulator in the segmented linear function calculation module, lat add is the operation period of each two-input adder in the tree adder in the segmented linear function calculation module, and level is the number of levels of the tree adder in the segmented linear function calculation module.

[0009] For the segmented linear function calculation module, first, the number of the third calculation units in the segmented linear function calculation module is configured as K+1, and then the number of levels level of the tree adder in the segmented linear function calculation module is determined by the following method:

[0010]

[0011] wherein, denotes the ceiling function;

[0012] Let the time delay lat 2,1 = 0, the coefficient in the second calculation unit CU2_1 in the piecewise linear function calculation module 2,2 = L k - 1, the coefficient

[0013] Let the time delay lat in the third calculation unit CU3_f the coefficient K+1 = 0;

[0014] The binomial coefficient fitting module is used to calculate the binomial coefficient theoretical value b(j), j = 0, 1, …, WL s - 1 according to the fractional order α and the total window length WL s after receiving the binomial coefficient theoretical calculation parameters and the binomial coefficient piecewise linear fitting parameters, and then perform piecewise linear fitting on the binomial coefficients according to the piecewise fitting parameters: set the piecewise linear function of each segment of the binomial coefficient as follows:

[0015] y k (j) = β k j + μ k

[0016] wherein n k = n k-1 + L k , n0= WL-1, 1≤l k ≤ L k , β k denotes the slope, and μ k denotes the intercept;

[0017] The binomial coefficient fitting module performs linear function fitting on the b(j) theoretical value sequence in each segment to obtain the slope β k of each segment of the piecewise linear function of the binomial coefficient, and then feeds back the WL binomial coefficients b(0):b(WL-1) and the slope β k of each segment of the piecewise linear function to the control module;

[0018] The fixed window length calculation module is used to calculate the non-linear convolution calculation part in the fractional order The first computing unit CU1_d includes a multiplier, a variable depth shift register and an adder, wherein d=1, 2, …, WL, and the first computing unit CU1_d includes a multiplier, a variable depth shift register and an adder, wherein:

[0019] The multiplier is used for multiplying the delayed input data x(n) and the coefficient coef 1,d , and sending the multiplication result a 1,d to the variable depth shift register; the operation period of the multiplier is configured as lat mul clock cycles, wherein the value of lat mul is determined according to the FPGA timing analysis result, and needs to meet the requirement of establishing the holding time;

[0020] The variable depth shift register is used for delaying the multiplication result a 1,d according to the time delay lat1 sent by the control module, and sending the delayed result a to the adder;

[0021] The adder is used for adding the delayed result a and the output out d+1 of the first computing unit CU1 1,d+1 , wherein out 1,WL+1 = out PWL , and outputting the addition result as the output out 1,d of the first computing unit CU1_d; wherein out 1,d′ is output to the first computing unit CU1_d′-1, d′=2, 3, …, WL, and out 1,1 is output as the fractional order calculation result D α x(n) of the input data x(n); the operation period of the adder is configured as 1 clock cycle;

[0022] The piecewise linear function computing module is used for calculating the linear convolution calculation part in the fractional order, and includes 2 second computing units CU2_e, K+1 third computing units CU3_f and a tree-shaped adder, e=1, 2, and f=1, 2, …, K+1;

[0023] The second computing unit includes a variable depth shift register, a multiplier, an accumulator and a D flip-flop group, wherein:

[0024] The variable depth shift register is used for delaying the input data x(n) according to the time delay lat 2,e sent by the control module, and sending the delayed input data x(n-lat 2,e ) to the multiplier;

[0025] The multiplier is used for multiplying the delayed input data x(n-lat 2,e ​) and coefficient coef 2,e The multiplication result a 2,e is sent to an accumulator; the operation period of the multiplier is configured as lat mul clock cycles;

[0026] The accumulator is used to accumulate the multiplication result a 2,e and the last accumulation result on the accumulator, and the accumulation result b 2,e is sent to a D flip-flop group. The operation period of the accumulator is configured as lat acc clock cycles, wherein the value of lat acc is determined according to the FPGA timing analysis result and needs to meet the established hold time requirement;

[0027] The D flip-flop group includes lat acc +1 D flip-flops connected in series, which is used to delay the accumulation result b 2,e for lat acc +1 clock cycles and then send the result to the tree adder as the output out 2,e of the second calculation unit CU2_e;

[0028] The third calculation unit CU3_f includes a variable-depth shift register, a first accumulator, a multiplier, a second accumulator and a D flip-flop, wherein:

[0029] The variable-depth shift register is used to delay the input data x(n) according to the time delay lat 3,f sent by the control module, and send the delayed input data x(n-lat 3,f ) to the first accumulator;

[0030] The first accumulator is used to accumulate the delayed input data x(n-lat 3,f ) and the last accumulation result on the first accumulator, and send the accumulation result a 3,f to the multiplier; the operation period of the first accumulator is configured as lat acc clock cycles;

[0031] The multiplier is used to multiply the accumulation result a 3,f and the coefficient coef 3,f , and send the multiplication result b 3,f to the second accumulator; the operation period of the multiplier is configured as lat mul clock cycles;

[0032] The second accumulator is used to accumulate the multiplication result b 3,f and the last accumulation result on the second accumulator, and send the accumulation result c 3,f to the D flip-flop. The operation period of the second accumulator is configured as lat accone clock cycle;

[0033] D flip-flop is used for accumulating result c 3,f After delaying 1 clock cycle, as the output out of the third calculation unit CU3_f 3,f Sent to the tree adder;

[0034] The tree adder is used to sum the received data out 2,e And out 3,f As the output out of the piecewise linear function calculation module PWL And sent to the fixed window length calculation module; The operation period of the two-input adder instantiated inside the tree adder is configured as lat add Clock cycles, wherein the value of lat add Is determined according to the FPGA timing analysis result, which needs to meet the hold time requirement.

[0035] The reconfigurable fractional order calculation system of the application can efficiently utilize FPGA resources. After the input data is normalized and converted into single-precision floating-point numbers by the data preprocessing module, the control module receives the binomial coefficient theoretical calculation parameters and the binomial coefficient piecewise linear fitting parameters set by the user, controls the binomial coefficient fitting module to calculate the binomial coefficient and perform piecewise linear fitting, configures the configuration parameters required by the fixed window length calculation module and the piecewise linear function calculation module according to the fitting result, and starts the fixed window length calculation module and the piecewise linear function calculation module to perform fractional order calculation after the configuration is completed, thereby obtaining the fractional order calculation result of the input data.

[0036] The application has the following beneficial effects:

[0037] 1) The fixed window length calculation module in the application adopts the fixed window (FWL) calculation method with error compensation, thereby improving the calculation accuracy;

[0038] 2) The binomial coefficient in the application adopts the piecewise linear fitting method, which can effectively reduce the logic quantity and improve the FPGA resource utilization efficiency;

[0039] 3) The fixed window length calculation module and the piecewise linear function calculation module in the application are optimally designed, thereby realizing the reconfiguration of the fractional order calculation system, improving the flexibility and application range of the system. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 is a relationship diagram of the binomial coefficient and the fractional order;

[0041] Figure 2 is a variation diagram of the fitting accuracy θ(j);

[0042] Figure 3 is the integral D of the digital signal x(n) -1 Time-domain waveform and absolute error diagram of x(n);

[0043] Figure 4 Fractional order waveform diagram of different window length;

[0044] Figure 5 Fractional order waveform diagram of different oversampling rate under steady state;

[0045] Figure 6 The calculation process diagram of fractional order by piecewise linear fitting in this embodiment;

[0046] Figure 7 The specific embodiment structure diagram of the reconfigurable fractional order calculation system with efficient FPGA resource utilization of the present application;

[0047] Figure 8 The structure diagram of the fixed window length calculation module in the present application;

[0048] Figure 9 The structure diagram of the first calculation unit in the present application;

[0049] Figure 10 The structure diagram of the piecewise linear function calculation module in the present application;

[0050] Figure 11 The structure diagram of the second calculation unit in the present application;

[0051] Figure 12 The structure diagram of the third calculation unit in the present application;

[0052] Figure 13 The absolute error comparison diagram of binomial coefficients of the present application and two comparative methods in this embodiment;

[0053] Figure 14 The time-domain waveform and absolute error comparison diagram of binomial coefficients obtained by the present application and K-PWL method in this embodiment;

[0054] Figure 15 The error comparison diagram of fractional order calculation results obtained by the present application and Matlab simulation and theoretical values in this embodiment;

[0055] Figure 16 The time-domain waveform and absolute error comparison diagram of the present application and FWL method, FWL&1PWL method, FWL&Quad. method and theoretical method under steady state in this embodiment. DETAILED DESCRIPTION

[0056] The specific embodiments of the present application are described below with reference to the accompanying drawings to better understand the present application by those skilled in the art. It should be particularly noted that in the following description, when detailed description of known functions and designs may obscure the main content of the present application, these descriptions will be omitted here.

[0057] In order to better illustrate the technical solutions of the present application, the principles of the present application are first briefly deduced and described.

[0058] According to the Grünwald-Letnikov definition, assuming x(t) is a continuous-time analog signal, t represents time, the fractional order calculation formula is as follows:

[0059]

[0060] wherein, represents a fractional order operator, α represents an order, α = 1 and α = -1 represent integer order differentiation and integration operation respectively, h represents an operation step, t0 and t represent start time and end time respectively. b(j) represents a binomial coefficient, and its calculation formula is as follows:

[0061]

[0062] Figure 1 is a binomial coefficient and fractional order relationship diagram. As Figure 1 shown, when 0 < α < 1, b(j) < 0 when j ≥ 1, and when -1 < α < 0, b(j) > 0. In particular, α = -1, b(0) = b(j) = 1; α = 1, b(0) = 1, b(j) = 0. As α decreases, the absolute value of b(j) decreases more slowly. In addition, as j increases, j and b(j) approximately satisfy a one-segment or multi-segment linear relationship, and b(j) > 0 for α < 0, b(j) < 0 for α > 0.

[0063] If x(t) is sampled at an interval of T s to a discrete digital signal x(n) by an ADC, assuming that the start collection time is t0 = 0, the discrete digital sequence of formula (2) can be expressed as follows:

[0064]

[0065] wherein, n represents a sampling point, D α x(n) represents a fractional order of the digital signal x(n).

[0066] From equation (3), it can be seen that b(j) and x(n) increase with n. When n is greater than the upper limit of the memory space of the processor, the subsequent operation will not be able to be performed. Therefore, according to the principle of limited memory, when the window length is fixed as WL, equation (3) can be written as follows:

[0067]

[0068] In fact, is the convolution sum of x(n-j) and b(j). According to Figure 1 the change rule of b(j) in equation (4), with the increase of j, the proportion of x(n-j) in D α x(n) is lower and lower, and b(j)≠0. In order to simplify the analysis, it is assumed that x(n-j)=1, and θ(j) is defined as the estimation function of the ideal window length WL idea =1000. The fitting accuracy θ(j) (1≤j<WL) is easily established:

[0069]

[0070] Figure 2 is a schematic diagram of the change of the fitting accuracy θ(j). As Figure 2 shown, with the decrease of α, the speed of θ(j) approaching 1 is slower. When θ(j)=0.95, the values of j corresponding to the fractional orders 1, 0.8, 0.6, 0.4, 0.2, -0.2, -0.4, -0.6, -0.8 and -1 are 946, 932, 911, 869, 754, 155, 44, 12, 5, 1 respectively. It can be seen that for the same fitting accuracy, with the decrease of α, the required window length WL is smaller; the window length WL of the differential operation is smaller than that of the integral operation. The larger the window length WL is, the higher θ(j) is.

[0071] The memory dependence of the fractional order system makes it difficult to be converted into hardware, because it needs to perform complex operations. For the fractional order operation of WL points, WL times of multiplication, WL-1 times of addition and storage space with a length of WL are required. Therefore, FPGA with IP core and parallel running characteristics can well realize complex fractional order calculation.

[0072] In practical applications, the digital signal x(n) is usually obtained by oversampling. The definition of the oversampling rate OSR is as follows:

[0073]

[0074] where f s and f inThese are the sampling rate of the ADC and the frequency of the input signal x(t), respectively. After quantization by the ADC, the bipolar periodic analog signal x(t) can be converted into a discrete digital signal x(n). According to the principle of digital sampling, every N... R A periodic sequence is formed by x(n) elements. The integral value of x(n) is x intg The formula for calculating (n) is as follows:

[0075]

[0076] Where n s =n%N R x intg x(n) is a number sequence with period OSR. That is, the integral of x(n) over consecutive integer periods is 0.

[0077] Since the internal logic resources (LUTS, RAM, DSP, FF) of an FPGA are limited, a trade-off must be made between an area-first or speed-first strategy. Figure 3 It is the integral D of the digital signal x(n). -1 A schematic diagram of the time-domain waveform and absolute error of x(n). Figure 3 The waveform shown corresponds to the sampling frequency f. s =100MHz, signal frequency f in =1MHz, amplitude A=1V. Figure 3 (a) shows the integral D under different window length methods. -1 The magnitude of x(n). It can be seen that when the fixed window length (FWL) is 150, the integral D... -1 The absolute error of x(n) is the largest. As the FML increases, the integral D... -1 The amplitude of x(n) first increases and then decreases, while the phase also increases. Figure 3 In (b), when FWL are respectively N R ,2N R and 3N R At this time, there is no error. As the fractional integral (FML) increases, the amplitude of the FML method also periodically increases and then decreases. In summary, when α = -1, to improve the accuracy of fractional integral operations, the choice of FWL should satisfy the constraint: WL = κN. R , where κ is a positive integer.

[0078] When α≠-1, the value of b(j) remains almost constant as j increases, so b(j) can be regarded as a constant b(j0). Compared with the fractional operation of α=-1, the fractional operation in (4) is simply multiplied by the constant b(j0). Figure 4 These are fractional-order waveforms with different window lengths. Figure 4 The N used in R= 100. In Figure 4 (a)-(b), because of the large weight of b(0)-b(99), the window length WL is increased, and the fractional order D -α x(n) is almost unchanged, and they are very close to the value of the infinite window length (UWL). The larger the α, the larger the D -α x(n). In Figure 4 (c)-(d), the larger the value of κ, the closer the D -α x(n) to the theoretical value. The smaller the α, the smaller the D -α x(n). When κ is not a positive integer, the fractional order D -α x(n) has an error, and the absolute error varies with the window length ML as shown in Figure 3 (b). In summary, when α≠-1, when α is fixed, the window length WL=κN R , the absolute error of the fractional order D -α x(n) decreases with the increase of κ. When α is fixed, WL≠κN R , the absolute error of the fractional order D -α x(n) periodically changes according to the law in Figure 3 (b). When the window length WL is a fixed value, the relative error of the fractional order calculation increases with the decrease of α.

[0079] Figure 5 are waveform diagrams of the fractional order in the stable state under different oversampling rates. From Figure 5 , it can be clearly found that the larger the oversampling rate N R , the smoother the waveform, and with the increase of the oversampling rate N R , the amplitude of the fractional order D α x(n) is almost unchanged. Therefore, in engineering applications, appropriate window length WL can be selected according to the resources of FPGA to improve the operation speed and save storage resources. In fractional order differentiation operation, the increase of the constant κ has no obvious effect on the amplitude change of the fractional order D α x(n). In fractional order integration operation, the larger the κ, the smaller the absolute error of the fractional order D α x(n) with the decrease of α. Therefore, appropriately reducing the oversampling rate N R and increasing the constant κ can improve the accuracy of the fractional order D α x(n). In addition, in Figure 5 , with the decrease of α, the phase of N R =20 gradually changes from the phase of N R =100 to the phase of N R =100 after. The amplitude of D α x(n) also decreases with the decrease of α.

[0080] In Figure 5 It can be seen clearly that the calculation accuracy of fractional order is almost the same when oversampling rate N R = 20 and N R = 100, while N R = 20 occupies less storage space and improves the calculation speed. Therefore, when N R > ML, the fractional order calculation can be realized by reducing N R first and then adjusting ML appropriately. The specific implementation steps are as follows:

[0081] 1) Determine the maximum window length ML max of fractional order calculation according to the logic resources of FPGA;

[0082] 2) Reduce the sampling rate of ADC by K d times, so that the oversampling rate N RD after reducing the sampling rate satisfies the following condition:

[0083]

[0084] Where P is the number of periods of input signal x(n) contained in the limited memory space in FPGA. N RD ≥ 20 is to maintain the accuracy of fractional order operation. Obviously, the above method is applicable to all fractional order calculations when α is different. Equation (8) gives the method for determining the oversampling rate and improving the calculation accuracy when implementing fractional order operation in FPGA for any α.

[0085] In order to solve the problem of limited logic resources of FPGA, the binomial coefficient can be calculated by function fitting to replace the theoretical value, thereby reducing the logic resources and improving the calculation accuracy. It has been proved by research that the binomial coefficient fitting method based on multi-segment linear function has higher accuracy. For binomial coefficient b(j), the expression of the segmented linear function of binomial coefficient b(j) is as follows:

[0086]

[0087] Let W(n) and S(n) represent nonlinear convolution and linear convolution respectively, and they are defined as follows:

[0088]

[0089]

[0090] Therefore, formula (9) can be simplified as follows:

[0091]

[0092] The linear convolution S(n) in equation (12) is composed of K piecewise linear functions. The calculation process of the piecewise linear function is as follows:

[0093] Suppose that K linear functions are used to fit L binomial coefficients from b(n k-1 ) to b(n k ). There are L k +1 binomial coefficients b(j) replaced by the kth (1≤k≤K) piecewise linear function y k (n), then:

[0094] y k (j) = β k j + μ k (13)

[0095] where n0 = WL-1, n k = n k-1 + L k , 1≤l k ≤L k . The improved total window length is WL s = WL+L. The slope β k and the intercept μ k can be obtained by the curve fitting function of Matlab. For example, when ML=4, K=2, L1=L2=4, and α=0.5, the coefficients of the two piecewise linear functions are fitted.

[0096] Table 1 is a list of the coefficients of the two piecewise linear functions in this embodiment.

[0097] k β k ]]> μ k ]]> n 1 0.00757 -0.075 [3:7] 2 0.00169 -0.028 [7:11]

[0098] Table 1

[0099] As shown in Table 1, suppose that y1(3) = 3β1+μ1 = b(3) = δ1, then b(3+l1) = β1(n0+l1)+μ1 = β1+l1λ1. Similarly, for multiple piecewise linear functions, we have:

[0100] b(n k-1 +l k ) = λ k ·l k + δ k (14)

[0101] where δ k = b(n k-1 ), δ K+1 = b(n K ). In equation (14), according to the definition of the fitting interval of the piecewise linear function, when l k = L kAt that time, we have b(n) k-1 +L k )=β k L k +δ k =δ k+1 For example, in Table 1, we have b(7) = β1 + 4λ1 = δ2 and b(11) = β2 + 4λ2 = δ3. According to... Figure 1 The variation law of b(j) in (13) is that when α>0 (or α<0), λ k <0, μ k >0 (or λ) k >0, μ k <0). Therefore, in order to ensure that b(j) > 0 (or b(j) < 0), the number of fitting coefficients b(j) of the k-th linear function has a maximum value. Otherwise, as j increases, the linear function fit b(j) will be incorrect. For example, in y2(n), when n > 568, y2(n) < 0, which conflicts with b(j) > 0.

[0102] Here, we take ML=4 and L1=L2=4 as examples to calculate the fractional order of piecewise linear fitting. Figure 6 This is a schematic diagram illustrating the calculation process of the piecewise linear fitting fractional order in this embodiment. For example... Figure 6 As shown, when 0 ≤ n ≤ 3, When 4≤n≤7 A fixed window (FWL), PWL1, and x(n) are used for convolution. When 8 ≤ n ≤ 11, Fixed window (FWL), PWL1, and PWL2 are convolved with x(n). b(j) in S1(n) and S2(n) can be obtained from equation (14). When n≥4, the convolution sum of the nth row in PWL1 and PWL2 is... k The convolution sum S from row (n) to row (n+1) k The increment ΔS of (n+1) k (n) in Figure 6 The text is marked, and there are examples such as... Figure 6 The recursive relationship is shown by the dashed single arrow. In PWL1,

[0103]

[0104] and This represents convolution. Based on the value of n, the complete recursive formula for S1(n) is as follows:

[0105] S1(n)=0,0≤n≤3 (16)

[0106]

[0107]

[0108] where b(7)=δ2, b(8)=b(7)+λ2. Similarly, in PWL2, b(11)=δ3. When n≥11, the complete recursive formula of S2(n) is as follows:

[0109] S2(n)=0, 0≤n≤7 (19)

[0110]

[0111]

[0112] When n≤7, the formula (19) and the formula (16)-(17) are combined and simplified as follows:

[0113]

[0114] When n≥8, the combined and simplified formula (18) and (21)-(22) are as follows:

[0115]

[0116] The formula (22)-(23) is extended to multiple piecewise linear functions, and is brought into the formula (12), and the general piecewise linear function fractional order calculation based on the GL definition can be written as follows.

[0117]

[0118] Wherein:

[0119] S(n)=0, n<WL

[0120]

[0121] Compared with the existing piecewise linear function fractional order calculation formula, the formula (24) provided by the present application is simpler, and considers the error compensation term -α s when more than the total window length WL z x(n-n L -1) and It avoids b(j)>0 for α>0 and b(j)<0 for α<0 as n increases, which can provide higher precision for long-time running of the formula (24).

[0122] According to the above derivation and analysis, the application provides a reconfigurable fractional order calculation system with efficient FPGA resource utilization, which realizes fast and reconfigurable fractional order calculation to adapt to FPGAs with different logic resources, so as to realize high-precision fractional order calculation in limited logic resources of the FPGA. Figure 7 is a specific embodiment structure diagram of the FPGA resource efficient reconfigurable fractional order calculation system of the application. As shown in Figure 7 , the FPGA resource efficient reconfigurable fractional order calculation system of the application includes a data preprocessing module 1, a control module 2, a binomial coefficient fitting module 3, a fixed window length calculation module 4, and a piecewise linear function calculation module 5, wherein the data preprocessing module 1, the fixed window length calculation module 4, and the piecewise linear function calculation module 5 are implemented in the FPGA. Next, each module is described in detail.

[0123] The data preprocessing module 1 is used to normalize the input data to the range [-1, 1] and convert it to a single-precision floating-point number, and then send the processed data x(n) to the fixed window length calculation module 4 and the piecewise linear function calculation module 5.

[0124] The control module 2 is used to receive the binomial coefficient theoretical calculation parameters set by the user, including the fractional order α and the total window length WL s , and the binomial coefficient piecewise linear fitting parameters, including the fixed window length WL, the number of fitting segments K, and the number of binomial coefficients per segment L k , k = 1, 2, …, K, wherein The binomial coefficient theoretical calculation parameters and the binomial coefficient piecewise linear fitting parameters are sent to the binomial coefficient fitting module 3. After the control module 2 receives the WL binomial coefficients b(0):b(WL-1) and the slope β k of each piecewise linear function fed back by the binomial coefficient fitting module 3, the configuration parameters required by the fixed window length calculation module 4 and the piecewise linear function calculation module 5 are calculated and configured, and after the configuration is completed, the fixed window length calculation module 4 and the piecewise linear function calculation module 5 are started for fractional order operation. The parameter calculation and configuration method is as follows:

[0125] For the fixed window length calculation module 4, first configure the number of first calculation units in it to be WL, and let the coefficient of the multiplier in the dth first calculation unit CU1_d be d = 1, 2, …, WL, and let the time delay lat1 of the variable depth shift register in the WL first calculation units CU1_d be 2 × lat acc + level × lat add , wherein lat acc is the operation period of the accumulator in the piecewise linear function calculation module 5, and latadd The operation period of each two-input adder in the tree adder in the piecewise linear function calculation module 5 is calculated, and level is the number of levels of the tree adder in the piecewise linear function calculation module 5.

[0126] For the piecewise linear function calculation module 5, first, the number of third calculation units therein is configured to be K+1, and then the number of levels level of the tree adder in the piecewise linear function calculation module is determined by using the following method:

[0127]

[0128] wherein, represents upward rounding.

[0129] Let the time delay lat 2,1 =0 in the second calculation unit CU2_1 in the piecewise linear function calculation module 5, and the coefficient Let the time delay lat 2,2 =L k -1 in the second calculation unit CU2_2, and the coefficient

[0130] Let the time delay lat in the third calculation unit CU3_f, and the coefficient wherein β0=β K+1 =0.

[0131] In the theoretical derivation part of Figure 5 , it can be clearly seen that the calculation accuracy of the fractional order is almost the same when N R =20 and N R =100, while N R =20 occupies less storage space and has higher calculation rate. Therefore, in actual application, the control module 2 can use the following method to optimize the setting of the total window length WL s : first, determine the maximum window length WL smax of the fractional order calculation according to the logic resources of the FPGA, obtain the oversampling multiple N R of the current input data x(n), when N R ≤WL smax , only the total window length WL s needs to be adjusted, that is, the window length WL s =κN R , wherein κ is a positive integer; when N R >WL smax , the input data x(n) is K d times down-sampled, so that the oversampling multiple N RD after the down-sampling rate satisfies the following condition:

[0132]

[0133] wherein P is the number of periods of the input signal x(n) contained in the finite memory space in the FPGA.

[0134] Then the window length WL is set as s = κN RD The preferred value of the constant κ is κ≤5.

[0135] After receiving the binomial coefficient theoretical calculation parameters and the binomial coefficient piecewise linear fitting parameters, the binomial coefficient fitting module 3 first calculates the binomial coefficient theoretical value b(j) according to the fractional order α and the total window length WL s using the theoretical calculation formula, j = 0, 1, …, WL s -1, and then performs piecewise linear fitting on the binomial coefficients according to the piecewise fitting parameters: set the piecewise linear function of each segment of the binomial coefficients as follows:

[0136] y k (j) = β k j + μ k (27)

[0137] wherein n k = n k-1 + L k , n0= WL-1, 1≤l k ≤L k , β k represents the slope, and μ k represents the intercept.

[0138] The binomial coefficient fitting module 3 performs linear function fitting on the theoretical value sequence b(j) in each segment to obtain the slope β k of each piecewise linear function of the binomial coefficients, and then feeds back the WL binomial coefficients b(0):b(WL-1) and the slope β k of each piecewise linear function to the control module 2.

[0139] The fixed window length calculation module (FWL) 4 is used to calculate the nonlinear convolution calculation part in the fractional order Figure 8 is the structure diagram of the fixed window length calculation module in the present application. As shown in Figure 7 and Figure 8 , the fixed window length calculation module 4 in the present application includes WL serially cascaded first calculation units CU1_d, d = 1, 2, …, WL. Figure 9 is the structure diagram of the first calculation unit in the present application. As shown in Figure 9 , the first calculation unit CU1_d in the present application includes a multiplier, a variable depth shift register, and an adder, wherein:

[0140] The multiplier is used to multiply the delayed input data x(n) with the coefficient coef 1,d , and send the multiplication result a 1,d to the variable depth shift register. The operation period of the multiplier is configured as lat mul clock cycles, where the value of lat mul is determined according to the result of the FPGA timing analysis, and needs to meet the requirement of establishing the holding time.

[0141] The variable depth shift register is used to delay the multiplication result a 1,d according to the time delay lat1 sent by the control module, and send the delayed result a to the adder.

[0142] The adder is used to add the delayed result a and the output out d+1 of the first calculation unit CU1 1,d+1 , where out 1,WL+1 = out PWL , and output the addition result as the output out 1,d of the first calculation unit CU1_d, where out 1,d′ is output to the first calculation unit CU1_d′-1, d′=2,3,…,WL, and out 1,1 is output as the fractional order calculation result D α x(n) of the input data x(n). The adder has an operation period of 1 clock cycle.

[0143] The piecewise linear function calculation module (PWL) 5 is used to calculate the linear convolution calculation part T s -α ·S(n) in the fractional order. Figure 10 is the structure diagram of the piecewise linear function calculation module in the present application. As shown in Figure 7 and Figure 10 , the piecewise linear function calculation module 5 in the present application includes 2 second calculation units CU2_e, K+1 third calculation units CU3_f and tree adders, e=1,2, f=1,2,…,K+1. Figure 11 is the structure diagram of the second calculation unit in the present application. As shown in Figure 11 , the second calculation unit in the present application includes a variable depth shift register, a multiplier, an accumulator and a D flip-flop group, where:

[0144] The variable depth shift register is used to delay the input data x(n) according to the time delay lat 2,e sent by the control module, and send the delayed input data x(n-lat 2,e ) to the multiplier.

[0145] The multiplier is used to convert the delayed input data x(n-lat) 2,e ) and coefficient coef 2,e Perform multiplication, and multiply the result a. 2,e Send to the accumulator. The multiplier's operation cycle is configured to lat. mul One clock cycle.

[0146] The accumulator is used to process the multiplication result a. 2,e Add the result b to the previous accumulation result of the accumulator. 2,e Send to the D flip-flop group. The accumulator's operation cycle is configured to 1t. acc 1 clock cycle, where lat acc The value is determined based on the FPGA timing analysis results and must meet the setup and hold time requirements.

[0147] The D flip-flop group includes lat acc +1 interconnected D flip-flops are used to process the accumulated result b. 2,e Delay lat acc +1 clock cycle later, the output of the second computing unit CU2_e will be used as out. 2,e Send to the tree adder.

[0148] According to the time delay lat 2,e and coefficient of coef 2,e From the settings of these two parameters, it can be seen that the second calculation unit CU2_1 calculates the formula (24) in the formula. The second computing unit CU2_1 calculates...

[0149] Figure 12 This is a structural diagram of the third computing unit in this invention. (See diagram below.) Figure 12 As shown, the third computing unit CU3_f in this invention includes a variable depth shift register, a first accumulator, a multiplier, a second accumulator, and a D flip-flop, wherein:

[0150] The variable depth shift register is used to adjust the latency according to the time delay sent by the control module. 3,f Delay the input data x(n), and then delay the input data x(n-lat). 3,f Send to the first accumulator.

[0151] The first accumulator is used to process the delayed input data x(n-lat). 3,f The result a is accumulated by adding the result of the previous accumulation of the first accumulator to the first accumulator. 3,f Send to the multiplier. The first accumulator's operation cycle is configured to lat. acc One clock cycle.

[0152] The multiplier is used to multiply the accumulated result a 3,f and the coefficient coef 3,f The multiplication result b 3,f is sent to the second accumulator. The operation period of the multiplier is configured as lat mul clock cycles.

[0153] The second accumulator is used to accumulate the multiplication result b 3,f and the last accumulated result of the second accumulator, and send the accumulated result c 3,f to the D flip-flop. The operation period of the second accumulator is configured as lat acc clock cycles.

[0154] The D flip-flop is used to delay the accumulated result c 3,f for 1 clock cycle (i.e. to beat once) and send the result as the output out 3,f of the third calculation unit CU3_f to the tree adder.

[0155] According to the setting of the time delay lat 3,f and the coefficient coef 3,f , it can be known that the K+1 third calculation units CU3_f calculate the

[0156] The tree adder is used to sum the received data out 2,e and out 3,f in a tree structure, and send the sum result as the output out PWL of the piecewise linear function calculation module to the fixed window length calculation module. Obviously, the output out PWL is the linear convolution calculation part in the fractional order calculation The operation period of the two-input adder instantiated inside the tree adder is configured as lat add clock cycles, wherein the value of lat add is determined according to the FPGA timing analysis result and needs to meet the setup time requirement.

[0157] In the embodiment, the multiplier, the adder and the accumulator in the reconfigurable fractional order calculation system with efficient FPGA resource utilization are implemented by using the Floating-point IP core inside the FPGA. Table 2 is the performance and resource utilization of the single-precision Floating-point IP core.

[0158]

[0159] Table 2

[0160] As shown in Table 2, when the data is in single-precision floating-point format, the fractional order operation based on the floating-point IP core can be configured in various ways between performance and resources, which is conducive to more rational use of FPGA resources to realize fractional order operation.

[0161] According to the above description, after the binomial coefficient fitting and parameter calculation and configuration of the reconfigurable fractional order calculation system with efficient FPGA resource utilization of the application are completed, the fixed window length calculation module and the segmented linear function calculation module perform two-link operations on the input data x(n) respectively. In the fixed window length calculation module FWL link, the input data x(n) enters WL first calculation units CU1 simultaneously in each effective clock cycle, and is multiplied by all the theoretical coefficients b T (j) = T s -α (j) to obtain all binomial product terms related to the input data x(n) of the current clock. However, only the current clock calculation result of the first calculation unit CU1_1 is needed to be output immediately, and the current clock calculation results of the remaining WL-1 first calculation units CU1_d' need to be added with the product terms of subsequent x(n) to be correct binomial summation output results. Therefore, after the cascade of the WL first calculation units CU1, the items that need to be waited for are finally output after each cascade transmission, and the binomial results are finally output after the missing item x(n)b T (0) is added, and the correct operation result is output. In the segmented linear function calculation module PWL link, the input data x(n) enters the second calculation module CU2 and the third calculation module CU3 after different delays, which is equivalent to the second calculation module CU2 and the third calculation module CU3 being started at different times, and the operation results are output simultaneously. After summation, the operation results are output to the start point of the cascade transmission of CU1_WL.

[0162] Next, the operation flow of the application is described by taking an example. In the example, the binomial coefficient segmented linear fitting parameters are WL=4, K=2, L1=L2=4. Table 3 is a working timing table of the fractional order calculation system in the embodiment.

[0163]

[0164] Table 3

[0165] As shown in Table 3, out 1,1 : out 1,4 is the output of the four first calculation units CU1, out PWL is the output of the segmented linear function calculation module PWL is the sum of two piecewise linear functions. From Table 3, it can be seen that FWL and PWL are working in pipeline mode simultaneously. When the module is in reset state (IDLE) and clk0, the output of all adders is 0. At the ith clock cycle clki, a 1,d (i) = x(i) · coef 1,d , (1≤d≤4), where out 1,d′ (i) = a 1,d′ (i) + out 1,d′+1 (i-1), 1≤d'≤3, out 1,4 (i) = a 1,4 (i) + out PWL (i). Figure 4 The adder (multiplier) in (a) realizes the functions of addition (multiplication) and delay simultaneously, which saves 2WL LUTs for data caching compared with the method in the document “E. M. Hamed, M. E. Fouda, and A. G. Radwan, “Multiple Pinch-Off Points in Memristive Equations: Analysis and Experiments,” IEEE Trans. Circuits Syst. I, vol. 66, no. 8, pp. 3052–3063, Aug. 2019, doi: 10.1109 / TCSI.2019.2912821.”

[0166] Since the FPGA resource efficient reconfigurable fractional order computing system of the application can configure the piecewise linear fitting parameters of binomial coefficients, and further configure the modules of the third computing unit in the fixed window length computing module and the piecewise linear function computing module, where the fixed window length WL determines the number of the first computing unit CU1 module, the fitting segment number K determines the number of the third computing unit CU3 and the number of the tree-shaped adder, therefore the architecture of the fractional order computing system can be changed by setting the parameters, and different fractional order computing methods can be realized. For example, when K = 0, then S(n) = 0, D α x(n) = W(n), then the fractional order computing system is a fixed window length based fractional order computing system (FWL). When WL = 0, then b T (0) = δ1, D α x(n) = S(n), then the fractional order computing system is a piecewise linear function based fractional order computing system (PWL). When K > 0 and WL > 0, b 2WL (n) = s(n), b TWL-1) = δ1, then the fractional order calculation system is a fractional order calculation system (FWL&PWL) combining fixed window length and piecewise linear function, and it can be seen that the hardware architecture proposed in the application is reconfigurable, so that the fractional order calculation is more flexible.

[0167] In order to better illustrate the technical effects of the application, experiments are carried out on the application by using specific examples.

[0168] First, the accuracy of binomial coefficient fitting in the application is experimented. In this experiment, the fitting coefficients y k (j) are calculated based on the summed square of residual (SSE) of each piecewise linear function, and the calculation formula of the residual square sum of the kth piecewise linear function is as follows:

[0169]

[0170] Wherein n>WL, y k (j) is the binomial coefficient fitted by the kth piecewise linear function, and b(j) is the theoretical value obtained by formula (2). MSE is used to determine the number L k of binomial coefficients b(j) fitted by each piecewise linear function PWL , θ PWL is the expected maximum fitting error SSE. Table 3 is the number table of piecewise linear function fitting b(j) when θ PWL =1e-5 and WL=32.

[0171] function α＝-0.8 α＝-0.2 α＝0.2 α＝0.8 PWL1 [20,30] [20,46] [20,77] [20,5000] PWL2 [30,45] [46,122] [77,981] NULL PWL3 [45,67] [122,379] NULL NULL PWL4 [67,99] [379,1434] NULL NULL PWL5 [99,145] NULL NULL NULL PWL6 [145,210] NULL NULL NULL PWL7 [210,300] NULL NULL NULL PWL8 [300,422] NULL NULL NULL PWL9 [422,587] NULL NULL NULL PWL10 [587,807] NULL NULL NULL

[0172] Table 3

[0173] As shown in Table 3, for the same SSE, the number of each piecewise linear function to replace the theoretical value decreases as α decreases. For the fixed WL s , in order to improve the fitting accuracy, the number of piecewise linear functions needs to be increased as α decreases. When the number of piecewise linear functions is fixed, WL s decreases as α decreases.

[0174] Next, the fitting accuracy of the binomial coefficients in the method in the literature “M. F. Tolba, L. A. Said, A. H. Madian, and A. G. Radwan, “FPGA implementation of fractional-order integrator and differentiator based on Grünwald Letnikov’s definition,” in 2017 29th International Conference on Microelectronics (ICM), Beirut, Lebanon, Dec. 2017, pp. 1-4. doi: 10.1109 / ICM.2017.8268872.” (denoted as FWL&1PWL, i.e., binomial coefficients linear fitting without segmentation) and the method in the literature “M. F. Tolba, L. A. Said, A. H. Madian, and A. G. Radwan, “FPGA Implementation of the Fractional Order Integrator / Differentiator: Two Approaches and Applications,” IEEE Trans. Circuits Syst. I, vol. 66, no. 4, pp. 1484-1495, Apr. 2019, doi: 10.1109 / TCSI.2018.2885013.” (denoted as FWL&Quad., i.e., binomial coefficients quadratic function fitting) and the method of the present application (denoted as FWL&K-PWL) are compared. Figure 13 is the absolute error comparison chart of the binomial coefficients of the present application and the two comparison methods in this embodiment. As shown in Figure 13 , with the increase of n, the absolute error decreases, and with the decrease of a, the absolute error increases.

[0175] Table 4 is a residual sum of squares comparison table of the binomial coefficients of the present application and the two comparison methods in this embodiment.

[0176] a FWL & 1PWL FWL & Quad. The present invention 0.8 1.40E-06 1.27E-06 2.47E-07 0.2 1.29E-04 1.05E-04 1.52E-05 -0.2 3.85E-03 2.47E-03 3.73E-05 -0.8 4.77E-01 1.41E-01 9.87E-05

[0177] Table 4

[0178] As shown in Table 4, the residual sum of squares SSE of the binomial coefficient segmented linear fitting method proposed by the present application is the smallest.

[0179] Figure 14 is the time domain waveform and absolute error comparison chart of the binomial coefficients obtained by the present application and the K-PWL method in this embodiment.Figure 14 K=4, sampling interval T s =1e-8, input data amplitude A=1V, input data frequency f in =1MHz, total window length WL s =500, the K-PWL method is denoted as 4PWL-Ref, and the method of the present application is denoted as 4PWL-this. As shown in Figure 14 (a), with the increase of the calculation time, the amplitude of the theoretical reference waveform gradually decreases, and the time-domain waveform of 4PWL-Ref moves downward, and the error of 4PWL-Ref is greater than that of 4PWL-New. As shown in Figure 14 (b), when n≤WL s , the absolute errors of the two methods are the same. When n>WL s , with the increase of the calculation time, the absolute error of 4PWL-Ref increases, and the absolute error of the method of the present application 4PWL-this decreases. This is because the waveform amplitude of the theoretical reference binomial coefficient gradually decreases, resulting in the change of the absolute error of the method of the present application 4PWL-this.

[0180] In terms of the fractional order calculation result, the calculation result of the present application is first compared with the result obtained by Matlab simulation in this embodiment. Figure 15 is the error comparison diagram of the fractional order calculation result obtained by the present application and Matlab simulation and the theoretical value in this embodiment. Figure 15 In (b), the fixed window length FWL=20, and the data sampling points are 1000 points. As shown in Figure 15 , consistent with the previous theoretical analysis, with the increase of the window length, the accuracy of the fractional order calculation is higher. With the decrease of α, the time for the fractional order calculation to enter the stable state is longer.

[0181] In order to illustrate the advantage of the present application in resource saving, the IP core number, time interval and reconstruction of the present application and four comparative methods are compared in this embodiment, and the four comparative methods are:

[0182] Comparative Method 1: Fixed window length based fractional order computation method disclosed in the literature “M. S. Monir, W. S. Sayed, A. H. Madian, A. G. Radwan, and L. A. Said, “A Unified FPGA Realization for Fractional-Order Integrator and Differentiator,” Electronics, vol. 11, no. 13, p. 2052, Jun. 2022, doi: 10.3390 / electronics11132052.” i.e. only FWL method is used.

[0183] Comparative Method 2: Piecewise linear function fitting based fractional order computation method disclosed in the literature “M. F. Tolba, L. A. Said, A. H. Madian, and A. G. Radwan, “FPGA Implementation of the Fractional Order Integrator / Differentiator: Two Approaches and Applications,” IEEE Trans. Circuits Syst. I, vol. 66, no. 4, pp. 1484–1495, Apr. 2019, doi: 10.1109 / TCSI.2018.2885013.” i.e. only PWL method is used.

[0184] Comparative Method 3: Fixed window length and piecewise linear function fitting based fractional order computation method disclosed in the literature “M. F. Tolba, B. M. Abo Al Naga, L. A. Said, A. H. Madian, and A. G. Radwan, “Fractional order integrator / differentiator: FPGA implementation and FOPID controller application,” AEU-International Journal of Electronics and Communications, vol. 98, pp. 220–229, Jan. 2019, doi: 10.1016 / j.aeue.2018.10.007.” i.e. FWL & 1PWL method.

[0185] Comparative Method 4: Fractional order calculation method based on fixed window length and binomial function fitting disclosed in the literature “M. F. Tolba, L. A. Said, A. H. Madian, and A. G. Radwan, “FPGA Implementation of the Fractional Order Integrator / Differentiator: Two Approaches and Applications,” IEEE Trans. Circuits Syst. I, vol. 66, no. 4, pp. 1484–1495, Apr. 2019, doi: 10.1109 / TCSI.2018.2885013.”, i.e. using the FWL&Quad. method, or fractional order calculation method based on multi-segment linear function fitting, i.e. using only the K-PWL method.

[0186] Table 5 is a comparison table of the number of IP cores, time interval and reconstruction of the present application and four comparative methods in this embodiment.

[0187]

[0188]

[0189] Table 5

[0190] As shown in Table 5, the number of DSP IP cores required by the fixed window length calculation module FWL in the fractional order calculation system of the present application is equal to that of the existing comparative methods, while the segmented linear function calculation module PWL can use fewer DSP IP cores. Compared with the existing methods, the Ts of the fractional order calculation system of the present application is smaller, and the calculation speed is improved by 1e6 times, and the real-time data bandwidth is as high as 3.2 Gbps.

[0191] Figure 16 is a comparison chart of time domain waveform and absolute error of the present application and FWL method, FWL&1PWL method, FWL&Quad. method and theoretical method in steady state in this embodiment. Figure 16 The sampling interval T used in s = 2e-8, input data amplitude A = 1V, input signal frequency f in = 1MHz, fractional order a = -0.2, L = 10 in the present application. From Figure 16 (a) Time domain waveform can clearly see that in steady state, the error of FWL&Quad. method is the largest compared with the theoretical value, while the error of the present application and the theoretical method is the smallest. From Figure 16It can be seen from the absolute error of (b) that the absolute error of the FWL&Quad. and FWL&lPWL methods increases with time at steady state, and the FWL&Quad. increases the fastest. These are because the FWL&Quad. and FWL&lPWL do not perform error compensation, >n>WL s While the absolute error of the FWL and the FWL&lO-PWL of the present application is almost fixed with the increase of time. In addition, as Figure 16 As shown in (b), the absolute error of the FWL&lO-PWL of the present application is the smallest and fixed.

[0192] Although the above describes the specific embodiments of the present application in order to facilitate the understanding of the present application for those skilled in the art, it should be clear that the present application is not limited to the scope of the specific embodiments, and all the applications using the concept of the present application are within the scope of protection as long as various changes are obvious to those skilled in the art within the spirit and scope of the present application defined and determined by the appended claims.

Claims

1. A reconfigurable fractional-order computing system with efficient utilization of FPGA resources, characterized in that... It includes a data preprocessing module, a control module, a binomial coefficient fitting module, a fixed window length calculation module, and a piecewise linear function calculation module. The data preprocessing module, fixed window length calculation module, and piecewise linear function calculation module are implemented in an FPGA. The data preprocessing module normalizes the input data to the range [-1, 1] and converts it to single-precision floating-point numbers, then processes the resulting data. Send to the fixed window length calculation module and the piecewise linear function calculation module; The control module is used to receive user-defined theoretical calculation parameters for binomial coefficients, including fractional order. Total window length And the piecewise linear fitting parameters of the binomial coefficients, including the fixed window length. Number of fitted segments and the number of binomial coefficients in each segment , ,in The theoretically calculated binomial coefficient parameters and the piecewise linear fitting parameters of the binomial coefficients are sent to the binomial coefficient fitting module; the control module receives the feedback from the binomial coefficient fitting module. binomial coefficients and the slope of each piecewise linear function Next, the required configuration parameters for the fixed window length calculation module and the piecewise linear function calculation module are calculated and configured. After configuration, the fixed window length calculation module and the piecewise linear function calculation module are started to perform fractional-order operations. The parameter calculation and configuration methods are as follows: For the fixed window length calculation module, first configure the number of the first calculation units as follows: , order the First computing unit The coefficients of the multiplier , Indicates the sampling interval. ,make First computing unit Delay of variable depth shift register ,in This refers to the operation cycle of the accumulator in the piecewise linear function calculation module. This represents the operation cycle of each two-input adder in the tree-structured adder within the piecewise linear function calculation module. The number of stages of the tree-like adder in the piecewise linear function calculation module; For the piecewise linear function calculation module, first configure the number of the third calculation units as follows: Then, the number of levels of the tree-like adders in the piecewise linear function calculation module is determined using the following method. : ， in, Indicates rounding up; Let the second calculation unit in the piecewise linear function calculation module Medium latency ,coefficient , , Second computing unit Medium latency ,coefficient , ; Let the third calculation unit Medium latency ,coefficient ,in ; The binomial coefficient fitting module, upon receiving the theoretical calculation parameters and the piecewise linear fitting parameters of the binomial coefficients, first uses the theoretical calculation formula based on the fractional order. Total window length The theoretical values ​​of the binomial coefficients were calculated. , Then, piecewise linear fitting is performed on the binomial coefficients based on the piecewise fitting parameters: [Setting parameters] arrive binomial coefficients The piecewise linear function is as follows: ， in , , , Indicates the slope. Indicates the intercept; The binomial coefficient fitting module performs a binomial coefficient fitting on each segment. A linear function fit is performed on the theoretical value sequence to obtain the slope of each piecewise linear function of the binomial coefficients. Then binomial coefficients and the slope of each piecewise linear function Feedback is sent to the control module; The fixed window length calculation module is used to calculate the nonlinear convolution part in fractional convolution. , Represents nonlinear convolution, including The first computing unit in a serial cascade , First computing unit It includes a multiplier, a variable-depth shift register, and an adder, wherein: The multiplier is used to delay the input data. With coefficient Multiply, and multiply the result Send to the variable depth shift register; the multiplier's operation cycle is configured as follows: One clock cycle, of which The value is determined based on the FPGA timing analysis results and must meet the setup and hold time requirements. The variable depth shift register is used to adjust the time delay sent by the control module. For the result of multiplication Delay the result Send to the adder; Adders are used to convert delayed results and the first computing unit Output Add them together, where , This represents the output of the piecewise linear function calculation module, with the summed result used as the first calculation unit. Output Output, where Output to the first computing unit , , As input data Fractional order calculation results Output is performed; the adder's operation cycle is configured to be 1 clock cycle; The piecewise linear function calculation module is used to calculate the fractional linear convolution part. , This represents a linear convolution, which includes two second computational units. , The third computing unit And tree-like adders, , ; The second computational unit includes a variable depth shift register, a multiplier, an accumulator, and a group of D flip-flops, wherein: The variable depth shift register is used to adjust the time delay sent by the control module. For input data Delay the input data. Send to the multiplier; The multiplier is used to delay the input data. Sum of coefficients Perform multiplication and multiply the results. Send to the accumulator; the multiplier's operation cycle is configured as follows: One clock cycle; An accumulator is used to process the multiplication result. The result is added to the previous accumulation result of the accumulator, and the accumulated result is... Send to the D flip-flop group; the accumulator's operation cycle is configured as follows: One clock cycle, of which The value is determined based on the FPGA timing analysis results and must meet the setup and hold time requirements. The D flip-flop group includes A series of interconnected D flip-flops are used to process the accumulated result. Delay After one clock cycle, it becomes the second computing unit. Output Send to the tree adder; Third Calculation Unit It includes a variable depth shift register, a first accumulator, a multiplier, a second accumulator, and a D flip-flop, wherein: The variable depth shift register is used to adjust the time delay sent by the control module. For input data Delay the input data. Send to the first accumulator; The first accumulator is used to process delayed input data. The result is added to the previous accumulation result of the first accumulator, and the accumulated result is... Send to the multiplier; the operation cycle of the first accumulator is configured as follows: One clock cycle; Multipliers are used to accumulate results Sum of coefficients Perform multiplication and multiply the results. Send to the second accumulator; the multiplier's operation cycle is configured as follows: One clock cycle; The second accumulator is used to process the multiplication result. The result is accumulated by adding the previous accumulation result of the second accumulator and then summing the results. Send to the D flip-flop; the second accumulator's operation cycle is configured as follows: One clock cycle; A D flip-flop is used to process the accumulated result. After a one-clock-cycle delay, it becomes the third computing unit. Output Send to the tree adder; Tree adders are used to process received data using a tree structure. and Perform summation and use the summation result as the output of the piecewise linear function calculation module. And send it to the fixed window length calculation module; the operation cycle of the two-input adder instantiated inside the tree adder is configured as follows: One clock cycle, of which The value is determined based on the FPGA timing analysis results and must meet the setup and hold time requirements.

2. The reconfigurable fractional-order computation system according to claim 1, characterized in that, The control module sets the total window length using the following method. : First, determine the maximum window length for fractional computation based on the FPGA's logic resources. Get the current input data oversampling factor ,when When, set the window length ,in is a positive integer; when At that time, for the input data conduct Doubling downsampling rate results in a higher oversampling factor after downsampling. The following conditions must be met: ， in, and These are the ADC sampling rate and the frequency of the input signal, respectively. It is the input signal contained in the limited memory space of the FPGA. The number of cycles; Then set the window length .

3. The reconfigurable fractional-order computation system according to claim 2, characterized in that, The positive integer The range of values ​​is .

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