Pixel Circuit, Driving Method Thereof, and Display Panel

Abstract

The present invention discloses a pixel circuit, a driving method thereof, and a display panel. The pixel circuit includes a driving module, a leakage current suppression module, an initialization module, a first compensation module, a first storage module, a second storage module, and a light-emitting module. A control end of the driving module is connected to the leakage current suppression module at a first node, the initialization module is connected to the leakage current suppression module at a second node, the first storage module is connected to the first node, the second storage module is connected to the second node, and the first compensation module is connected to the second node and is configured to perform voltage compensation on the second node in response to a voltage signal of the first node. The technical solution provided in this embodiment stabilizes the potential of the first node by setting the leakage current suppression module and the second storage module. In addition, by setting the first compensation module to perform self-compensation on the voltage of the second node, the voltage difference between the first node and the second node is reduced, further reducing the leakage current and improving the display effect.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, and a display panel. Background Art

[0002] With the development of display technologies, people's requirements for the display quality of images are also getting higher and higher.

[0003] A display panel usually includes a plurality of pixel circuits. The magnitude of the driving current flowing through a light-emitting module in a pixel circuit determines the light-emitting brightness of the display panel. Existing display panels have a problem of leakage current, which affects the display effect. Summary of the Invention

[0004] The present invention provides a pixel circuit, a driving method thereof, and a display panel to improve the display effect of a display panel applying the pixel circuit.

[0005] According to one aspect of the present invention, a pixel circuit is provided, including: a driving module, a leakage current suppression module, an initialization module, a first compensation module, a first storage module, a second storage module, and a light-emitting module;

[0006] A control terminal of the driving module is connected to the leakage current suppression module at a first node, and the initialization module is connected to the leakage current suppression module at a second node. The initialization module is configured to transmit an initialization voltage to the first node through the leakage current suppression module during an initialization stage to initialize a control terminal of the driving module; the driving module and the light-emitting module are connected between a first power supply line and a second power supply line, and the driving module is configured to drive the light-emitting module to emit light during a light-emitting stage;

[0007] The first storage module is connected to the first node and is configured to store a voltage of the first node; the second storage module is connected to the second node and is configured to store a voltage of the second node;

[0008] The first compensation module is connected to the second node and is configured to perform voltage compensation on the second node in response to a voltage signal of the first node.

[0009] Optionally, it further includes a second compensation module and a data writing module;

[0010] The data writing module is connected between a data line and a first end of the driving module, and the second compensation module is connected between a second end of the driving module and the second node;

[0011] The first end of the first storage module is connected to the first power supply line. The second end of the first storage module and the control end of the driving module are connected to the first node. The first end of the leakage suppression module is connected to the first node. The second end of the leakage suppression module and the second end of the initialization module are connected to the second node. The first end of the initialization module is connected to the initialization voltage. The first end of the second storage module is connected to the first power supply line. The second end of the second storage module is connected to the second node.

[0012] Optionally, the first compensation module includes a first compensation sub-unit and a second compensation sub-unit. The first end of the first compensation sub-unit is connected to the first power supply line. The second end of the first compensation sub-unit is connected to the second node. The control end of the first compensation sub-unit is connected to the first node.

[0013] The first end of the second compensation sub-unit is connected to the initialization voltage. The second end of the second compensation sub-unit is connected to the second node. The control end of the second compensation sub-unit is connected to the first node.

[0014] Wherein, the first compensation sub-unit and the second compensation sub-unit are not turned on simultaneously.

[0015] Optionally, the driving module includes a first transistor. The first compensation sub-unit includes a second transistor. The second compensation sub-unit includes a third transistor.

[0016] The gate of the second transistor and the gate of the first transistor are connected to the first node. The first pole of the second transistor is connected to the second node. The second pole of the second transistor is connected to the first power supply line. The gate of the third transistor is connected to the first node. The first pole of the third transistor is connected to the second node. The second pole of the third transistor is connected to the initialization voltage.

[0017] The channel types of the second transistor and the third transistor are different.

[0018] Optionally, the first storage module includes a first capacitor. The second storage module includes a second capacitor. The first end of the first capacitor is connected to the first power supply line. The second end of the first capacitor is connected to the first node. The first end of the second capacitor is connected to the first power supply line. The second end of the second capacitor is connected to the second node.

[0019] The capacitance value of the first capacitor is greater than the capacitance value of the second capacitor.

[0020] Optionally, the leakage current suppression module includes a fourth transistor, the initialization module includes a fifth transistor, the second compensation module includes a sixth transistor, and the data writing module includes a seventh transistor; the pixel circuit further includes a first light emission control module and a second light emission control module, the first light emission control module includes an eighth transistor, the second light emission control module includes a ninth transistor, and the light emission module includes a light emitting diode;

[0021] The gate of the fourth transistor is connected to the first scan signal, the first pole of the fourth transistor is connected to the first node, the second pole of the fourth transistor is connected to the second node, the gate of the fifth transistor is connected to the second scan signal, the first pole of the fifth transistor is connected to the initialization voltage, the second pole of the fifth transistor is connected to the second node, the gate of the sixth transistor is connected to the third scan signal, the first pole of the sixth transistor is connected to the second end of the driving module, the second pole of the sixth transistor is connected to the second node, the gate of the seventh transistor is connected to the third scan signal, the first pole of the seventh transistor is connected to the data line, and the second pole of the seventh transistor is connected to the first end of the driving module;

[0022] The gates of the eighth transistor and the ninth transistor are both connected to the light emission control signal, the first pole of the eighth transistor is connected to the first power supply line, the second pole of the eighth transistor is connected to the first end of the driving module, the first pole of the ninth transistor is connected to the second end of the driving module, the second pole of the ninth transistor is connected to the first pole of the light emitting diode, and the second pole of the light emitting diode is connected to the second power supply line;

[0023] Preferably, the fourth transistor, the fifth transistor, and the sixth transistor are double-gate transistors.

[0024] Optionally, the first compensation module includes a first compensation sub-unit and a second compensation sub-unit;

[0025] The first end of the first compensation sub-unit is connected to the second compensation module, the second end of the first compensation sub-unit is connected to the second node, and the control end of the first compensation sub-unit is connected to the first node;

[0026] The first end of the second compensation sub-unit is connected to the initialization module, the second end of the second compensation sub-unit is connected to the second node, and the control end of the second compensation sub-unit is connected to the first node;

[0027] Wherein, the first compensation sub-unit and the second compensation sub-unit are not simultaneously turned on.

[0028] According to another aspect of the present invention, there is provided a driving method for a pixel circuit, where the pixel circuit includes a driving module, a leakage current suppression module, an initialization module, a first compensation module, a first storage module, a second storage module, and a light-emitting module; a control end of the driving module is connected to the leakage current suppression module at a first node, the initialization module is connected to the leakage current suppression module at a second node, the driving module and the light-emitting module are connected between a first power supply line and a second power supply line, the first storage module is connected to the first node, the second storage module is connected to the second node, and the first compensation module is connected to the second node;

[0029] The driving method for the pixel circuit includes:

[0030] In an initialization stage, control the initialization module to transmit an initialization voltage to the first node through the leakage current suppression module to initialize the control end of the driving module;

[0031] In a light-emitting stage, control the driving module to drive the light-emitting module to emit light, and control the first compensation module to turn on in response to a voltage signal of the first node to perform voltage compensation on the second node.

[0032] Optionally, the pixel circuit further includes a second compensation module and a data writing module, the data writing module is connected between a data line and a first end of the driving module, and the second compensation module is connected between a second end of the driving module and the second node;

[0033] Before the light-emitting stage, the driving method for the pixel circuit further includes:

[0034] In a data writing stage, control the data writing module to transmit a data voltage on the data line to the control end of the driving module through the turned-on second compensation module;

[0035] The first compensation module includes a first compensation sub-unit and a second compensation sub-unit. A first end of the first compensation sub-unit is connected to the first power supply line, a second end of the first compensation sub-unit is connected to the second node, and a control end of the first compensation sub-unit is connected to the first node; a first end of the second compensation sub-unit accesses the initialization voltage, a second end of the second compensation sub-unit is connected to the second node, and a control end of the second compensation sub-unit is connected to the first node;

[0036] The step of controlling the first compensation module to turn on in response to a voltage signal of the first node to perform voltage compensation on the second node specifically includes:

[0037] When the voltage of the second node is negatively biased, control the first compensation subunit to turn on in response to the voltage signal of the first node, and perform positive compensation on the voltage of the second node;

[0038] When the voltage of the second node is positively biased, control the second compensation subunit to turn on in response to the voltage signal of the first node, and perform negative compensation on the voltage of the second node.

[0039] According to another aspect of the present invention, a display panel is provided, including the pixel circuit provided in any embodiment of the present invention.

[0040] The technical solution provided in this embodiment adopts a pixel circuit including a driving module, a leakage current suppression module, an initialization module, a first compensation module, a first storage module, a second storage module, and a light-emitting module; the control end of the driving module is connected to the leakage current suppression module at the first node, and the initialization module is connected to the leakage current suppression module at the second node. The initialization module is used to transmit the initialization voltage to the first node through the leakage current suppression module during the initialization stage to initialize the control end of the driving module; the driving module and the light-emitting module are connected between the first power supply line and the second power supply line, and the driving module is used to drive the light-emitting module to emit light during the light-emitting stage; the first storage module is connected to the first node and is used to store the voltage of the first node; the second storage module is connected to the second node and is used to store the voltage of the second node; the first compensation module is connected to the second node and is used to respond to the voltage signal of the first node to perform voltage compensation on the second node. During the light-emitting stage, on the one hand, the potential of the first node is stabilized by setting the leakage current suppression module and the second storage module; on the other hand, the voltage of the second node is self-compensated by setting the first compensation module to reduce the voltage difference between the first node and the second node, further reducing the leakage current, so as to improve the leakage phenomenon of the pixel circuit and improve the display effect.

[0041] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. Description of the Drawings

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0043] Figure 1 It is a schematic structural diagram of a pixel circuit provided in an embodiment of the present invention;

[0044] Figure 2 Another structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0045] Figure 3 Another structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0046] Figure 4 Another structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0047] Figure 5 Another structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0048] Figure 6 A driving timing waveform diagram of a pixel circuit provided by an embodiment of the present invention;

[0049] Figure 7 Another structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0050] Figure 8 A schematic diagram of a leakage current curve provided by an embodiment of the present invention;

[0051] Figure 9 Another structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0052] Figure 10 Another structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0053] Figure 11 Another structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0054] Figure 12 A flowchart of a driving method for a pixel circuit provided by an embodiment of the present invention;

[0055] Figure 13 A flowchart of another driving method for a pixel circuit provided by an embodiment of the present invention;

[0056] Figure 14 A structural schematic diagram of a display panel provided by an embodiment of the present invention. Detailed implementation manners

[0057] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0058] It should be noted that the terms "first", "second", etc. in the description, claims and above-mentioned drawings of the present invention are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0059] As described in the background art, there is a phenomenon of leakage current in existing display panels. After research by the inventor, it is found that the reason for the above problem is that the array substrate of the existing display panel structure is mostly an LTPS TFT substrate. The pixel circuit usually includes a driving transistor and an initialization transistor for resetting the gate potential of the driving transistor. Both the driving transistor and the initialization transistor are LTPS TFTs. Due to the large leakage current of LTPS TFTs, during the light-emitting stage, the gate potential of the driving transistor will be affected by the leakage current of the initialization transistor, resulting in unstable gate potential of the driving transistor, thus affecting the display effect. Existing solutions usually adopt the method of optimizing the voltage holding ability of the storage capacitor at the gate of the driving transistor, or use LGZO transistors with smaller leakage current (LTPO technology) to reduce leakage current, but the process is difficult and the cost is high, and the improvement effect on solving the leakage current problem is limited.

[0060] Based on the above problems, an embodiment of the present invention provides a pixel circuit. Figure 1 It is a schematic structural diagram of a pixel circuit provided by an embodiment of the present invention. Refer to Figure 1 , the pixel circuit includes a driving module 110, a leakage current suppression module 120, an initialization module 130, a first compensation module 140, a first storage module 150, a second storage module 160, and a light-emitting module 170.

[0061] The control end of the driving module 110 is connected to the leakage current suppression module 120 at a first node N1, and the initialization module 130 is connected to the leakage current suppression module 120 at a second node N2. The initialization module 130 is used to transmit the initialization voltage Vref to the first node N1 through the leakage current suppression module 120 during the initialization stage to initialize the control end of the driving module 110; the driving module 110 and the light-emitting module 170 are connected between a first power supply line L1 and a second power supply line L2, and the driving module 110 is used to drive the light-emitting module 170 to emit light during the light-emitting stage.

[0062] The first storage module 150 is connected to the first node N1 and is used to store the voltage of the first node N1; the second storage module 160 is connected to the second node N2 and is used to store the voltage of the second node N2; the first compensation module 140 is connected to the second node N2 and is used to respond to the voltage signal of the first node N1 and compensate the voltage of the second node N2.

[0063] Specifically, the first node N1 and the second node N2 are voltage nodes in the pixel circuit. Among them, the first node N1 is the connection node between the control end of the driving module 110 and the first end of the leakage suppression module 120, and the second node N2 is the connection node between the second end of the leakage suppression module 120 and the second end of the initialization module 130. The second end of the initialization module 130 is connected to the initialization voltage Vref, and this initialization voltage Vref can be provided by the initialization signal line.

[0064] In this embodiment, the first power supply line L1 is used to transmit the first power supply voltage VDD, and the second power supply line L2 is used to transmit the second power supply voltage VSS. When the discharge path between the first power supply line L1 and the second power supply line L2 is turned on, the driving module 110 drives the light-emitting module 170 to emit light according to the voltage of its control end. The first storage module 150 and the second storage module 160 are respectively used to store the voltages of the first node N1 and the second node N2, and maintain the voltage of these nodes during the light-emitting stage. For example, one end of the first storage module 150 and one end of the second storage module 160 are both connected to the first power supply voltage VDD, the other end of the first storage module 150 is connected to the first node N1, and the other end of the second storage module 160 is connected to the second node N2. When the initialization module 130 and the leakage suppression module 120 are both turned on, the initialization voltage Vref is written into the first node N1 to reset the potential of the control end of the driving module 110. Here, the initialization voltage Vref can be a negative voltage.

[0065] If the leakage suppression module 120 is not provided, during the light-emitting stage, the initialization module 130 is turned off, and the first storage module 150 maintains the voltage of the first node N1. However, due to the leakage current of the initialization module 130, the potential of the control end of the driving module 110 is unstable. Moreover, the lower the refresh rate, the longer the voltage holding time of the first storage module 150, the more serious the leakage current of the initialization module 130, and the greater the change degree of the display brightness within one display cycle, resulting in the display screen flickering.

[0066] In this embodiment, a leakage current suppression module 120 and a second storage module 160 are provided between the initialization module 130 and the first node N1 to reduce leakage current. After the initialization module 130 is turned off, the leakage current will flow to the second node N2, and the potential of the second node N2 will change. During the potential change process of the second node N2, the voltage difference between the first node N1 and the second node N2 gradually increases, further increasing the leakage current. Therefore, by providing the second storage module 160 to store and maintain the pressure of the potential of the second node N2, the voltage of the second node N2 is maintained at a relatively stable level, thereby stabilizing the voltage difference between the first node N1 and the second node N2, and further improving the leakage phenomenon of the first node N1.

[0067] On the other hand, the pixel circuit provided in this embodiment further includes a first compensation module 140. The first compensation module 140 can be turned on according to the voltage signal of the first node N1, and then compensate the voltage of the second node N2 to reduce the voltage difference between the first node N1 and the second node N2, ensuring that no leakage current flows through the leakage current suppression module 120, keeping the potential of the first node N1 constant, and thus improving the display effect of the display screen. Exemplarily, relative to the voltage of the first node N1, when the voltage of the second node N2 is positively biased, by controlling the first compensation module 140 to be turned on, a negative voltage is provided to the second node N2 for negative compensation of the second node N2, thereby reducing the voltage difference between the first node N1 and the second node N2. When the second node N2 is negatively biased, by controlling the first compensation module 140 to be turned on, a positive voltage is provided to the second node N2 for positive compensation of the second node N2, which can also reduce the voltage difference between the first node N1 and the second node N2.

[0068] The technical solution provided in this embodiment uses a pixel circuit including a driving module, a leakage suppression module, an initialization module, a first compensation module, a first storage module, a second storage module, and a light-emitting module; the control terminal of the driving module is connected to the leakage suppression module at a first node, the initialization module is connected to the leakage suppression module at a second node, and the initialization module is used to transmit an initialization voltage to the first node through the leakage suppression module during the initialization stage to initialize the control terminal of the driving module; the driving module and the light-emitting module are connected between a first power supply line and a second power supply line, and the driving module is used to drive the light-emitting module to emit light during the light-emitting stage; the first storage module is connected to the first node and is used to store the voltage of the first node; the second storage module is connected to the second node and is used to store the voltage of the second node; the first compensation module is connected to the second node and is used to respond to the voltage signal of the first node to perform voltage compensation on the second node. During the light-emitting stage, on the one hand, the potential of the first node is stabilized by setting the leakage suppression module and the second storage module; on the other hand, the voltage of the second node is self-compensated by setting the first compensation module to reduce the voltage difference between the first node and the second node, further reducing the leakage current, thereby being able to improve the leakage phenomenon of the pixel circuit and improve the display effect.

[0069] Figure 2 FIG. is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention. Refer to Figure 1 and Figure 2 , on the basis of the above technical solution, optionally, the pixel circuit further includes a second compensation module 180 and a data writing module 190. The data writing module 190 is connected between a data line Data and a first end of the driving module 110, and the second compensation module 180 is connected between a second end of the driving module 110 and the second node N2.

[0070] Among them, the pixel circuit can implement the threshold compensation function of the driving module 110. After the initialization stage ends, the driving module 110 is in a conducting state. After entering the data writing stage, the data voltage Vdata is written to the first node N1 through the data writing module 190, the driving module 110, the second compensation module 180, and the leakage suppression module 120. When the potential of the first node N1 turns off the driving module 110, the first storage module 150 stores the voltage of the first node N1, and this voltage includes the data voltage Vdata and the threshold information of the driving module 110, realizing the threshold compensation of the driving module 110.

[0071] During the light-emitting stage, the initialization module 130, the leakage suppression module 120, and the second compensation module 180 are all turned off, and the driving module 110 drives the light-emitting module 170 to emit light.

[0072] Figure 3 FIG. is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention. Refer toFigure 2 And Figure 3 Based on the above technical solution, the first compensation module 140 includes a first compensation subunit 141 and a second compensation subunit 142.

[0073] Specifically, the first end of the first compensation subunit 141 is connected to the first power supply line L1, the second end of the first compensation subunit 141 is connected to the second node N2, and the control end of the first compensation subunit 141 is connected to the first node N1; the first end of the second compensation subunit 142 accesses the initialization voltage Vref, the second end of the second compensation subunit 142 is connected to the second node N2, and the control end of the second compensation subunit 142 is connected to the first node N1. Among them, the first compensation subunit 141 and the second compensation subunit 142 are not turned on simultaneously.

[0074] At this time, there are two leakage paths for the voltage of the first node N1 (stored on the first storage module 150). One is through the second compensation module 180 for leakage, and the other is through the initialization module 130 for leakage. The leakage rate is positively correlated with the voltage difference across the corresponding module. After writing data, the voltages of the first node N1 and the second node N2 are equal, both being the difference between the data voltage Vdata and the threshold voltage of the driving module 110. During the leakage process, due to the different leakage rates of the two leakage paths, the potential change of the second node N2 is also different. As time goes by, when the potential of the second node N2 is positively biased, the second compensation subunit 142 is controlled to conduct, and the initialization voltage Vref charges negative charges into the second node N2 until the voltage difference between the second node N2 and the first node N1 satisfies the turn-off condition of the second compensation subunit 142, at which time the second compensation subunit 142 stops compensating the voltage of the second node N1. At this time, the voltage difference between the first node N1 and the second node N2 is small, so as to effectively suppress the leakage current from the second node N2 to the first node N1 through the leakage suppression module 130 and maintain the stability of the voltage of the first node N1.

[0075] Similarly, when the potential of the second node N2 is negatively biased, the first compensation subunit 141 is controlled to conduct, and the first power supply voltage VDD charges positive charges into the second node N2 until the voltage difference between the second node N2 and the first node N1 satisfies the turn-off condition of the first compensation subunit 141, at which time the first compensation subunit 141 stops compensating the voltage of the second node N1. At this time, the voltage difference between the first node N1 and the second node N2 is small, so as to effectively suppress the leakage current from the first node N1 to the second node N2 through the leakage suppression module 130 and maintain the stability of the voltage of the first node N1.

[0076] Exemplarily, Figure 4 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention, and showsFigure 3 A specific structure of the pixel circuit shown, refer to Figure 4 , based on the above technical solution, optionally, the first storage module 150 includes a first capacitor C1, the second storage module 160 includes a second capacitor C2, a first end of the first capacitor C1 is connected to the first power line L1, a second end of the first capacitor C1 is connected to the first node N1, a first end of the second capacitor C2 is connected to the first power line L1, and a second end of the second capacitor C2 is connected to the second node N2.

[0077] Among them, the capacitance value of the first capacitor C1 is greater than that of the second capacitor C2, that is, the voltage holding ability of the first capacitor C1 is greater than that of the second capacitor C2, which is convenient for adjusting the voltage of the second node N2.

[0078] The driving module 110 includes a first transistor T1, the first compensation sub-unit 141 includes a second transistor T2, and the second compensation sub-unit 142 includes a third transistor T3; a gate of the second transistor T2 and a gate of the first transistor T1 are connected to the first node N1, a first pole of the second transistor T2 is connected to the second node N2, a second pole of the second transistor T2 is connected to the first power line L1, a gate of the third transistor T3 is connected to the first node N1, a first pole of the third transistor T3 is connected to the second node N2, and a second pole of the third transistor T3 is connected to the initialization voltage Vref.

[0079] In this embodiment, the channel types of the second transistor T2 and the third transistor T3 are different. For example, the second transistor T2 is an N-type transistor and the third transistor T3 is a P-type transistor. After data writing is completed, the voltages of the first node N1 and the second node N2 are both Vdata - Vth1, where Vth1 is the threshold voltage of the first transistor T1. During the leakage process, as time goes by, the leakage currents of the two leakage paths make the potential of the second node N2 positively biased, and when the voltage of the second node N2 is greater than the difference between the voltage of the first node N1 and the threshold voltage Vth3 of the third transistor T3 (i.e., VN2 > VN1 + Vth3), the third transistor T3 is turned on and the second transistor T2 is turned off. Therefore, the initialization voltage Vref charges negative charges to the second node N2 through the third transistor T3 (that is, charges negative charges to the second capacitor C2), until VN2 = VN1 + Vth3, the third transistor T3 is turned off. At this time, it can be regarded that the voltage between the first node N1 and the second node N2 reaches a balance, and the voltage difference between the two is small, effectively suppressing the leakage current between the first node N1 and the second node N2.

[0080] If the leakage currents of two leakage paths negatively bias the potential of the second node N2, and the voltage of the second node N2 is less than the difference between the voltage of the first node N1 and the threshold voltage Vth2 of the second transistor T2 (i.e., VN2 < VN1 - Vth2), the second transistor T2 turns on and the third transistor T3 turns off. Therefore, the first power supply voltage VDD charges the second node N2 with positive charges through the second transistor T2 (i.e., charges the second capacitor C2 with positive charges) until VN2 = VN1 - Vth2, at which time the second transistor T2 turns off. At this time, it can be regarded that the voltage between the first node N1 and the second node N2 reaches a balance, and the voltage difference between them is small, effectively suppressing the leakage current between the first node N1 and the second node N2.

[0081] The technical solution provided in this embodiment controls the conduction of the second transistor T2 or the third transistor T3 according to the difference between the second node N2 and the first node N1 by setting the N-type second transistor T2 and the P-type third transistor T3, so as to perform self-compensation on the voltage of the second node N1, thereby reducing the cross-voltage between the first node N1 and the second node N2, and further reducing the leakage current between the first capacitor C1 and the second capacitor C2.

[0082] Figure 5 It is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention. On the basis of the above technical solutions, refer to Figure 5, the leakage current suppression module 120 includes a fourth transistor T4, the initialization module 130 includes a fifth transistor T5, the second compensation module 180 includes a sixth transistor T6, and the data writing module 190 includes a seventh transistor T7; the pixel circuit further includes a first light emission control module 111 and a second light emission control module 112, the first light emission control module 111 includes an eighth transistor T8, the second light emission control module 112 includes a ninth transistor T9, and the light emission module 170 includes a light emitting diode D1; the gate of the fourth transistor T4 is connected to the first scan signal S1, the first pole of the fourth transistor T4 is connected to the first node N1, the second pole of the fourth transistor T4 is connected to the second node N2, the gate of the fifth transistor T5 is connected to the second scan signal S2, the first pole of the fifth transistor T5 is connected to the initialization voltage Vref, the second pole of the fifth transistor T5 is connected to the second node N2, the gate of the sixth transistor T6 is connected to the third scan signal S3, the first pole of the sixth transistor T6 is connected to the second end of the driving module 110, the second pole of the sixth transistor T6 is connected to the second node N2, the gate of the seventh transistor T7 is connected to the third scan signal S3, the first pole of the seventh transistor T7 is connected to the data line Data, and the second pole of the seventh transistor T7 is connected to the first end of the driving module 110; the gates of the eighth transistor T8 and the ninth transistor T9 are both connected to the light emission control signal EM, the first pole of the eighth transistor T8 is connected to the first power line L1, the second pole of the eighth transistor T8 is connected to the first pole of the driving module 110, the first pole of the ninth transistor T9 is connected to the second pole of the driving module 110, the second pole of the ninth transistor T9 is connected to the first pole of the light emitting diode D1, and the second pole of the light emitting diode D1 is connected to the second power line L2.

[0083] Figure 6 A driving timing waveform diagram of a pixel circuit provided by an embodiment of the present invention can be used for Figure 5 the pixel circuit shown in Figure 5 and Figure 6 , taking the second transistor T2 as an N-type transistor and other transistors as P-type transistors as an example, the working process of the pixel circuit provided in this embodiment includes an initialization stage t1, a data writing stage t2, and a light emission stage t3.

[0084] In the initialization stage t1, the first scan signal S1 is at a low level, the second scan signal S2 is at a low level, the third scan signal S3 is at a high level, and the light emission control signal EM is at a high level. Therefore, the fourth transistor T4 and the fifth transistor T5 are turned on, and the initialization voltage Vref is written to the gate of the first transistor T1 through the fifth transistor T5 and the fourth transistor T4, resetting the gate voltage of the first transistor T1 to the initialization voltage Vref. At this time, the voltages of the first node N1 and the second node N2 are equal, both being the initialization voltage Vref. Therefore, the second transistor T2 and the third transistor T3 are in an off state.

[0085] In the data writing stage t2, the first scan signal S1 is at a low level, the second scan signal S2 is at a high level, the third scan signal S3 is at a low level, and the light emission control signal EM is at a high level. Therefore, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are turned on, and the fifth transistor T5 is turned off. The data voltage Vdata is written to the gate of the first transistor T1 through the seventh transistor T7, the first transistor T1, the sixth transistor T6, and the fourth transistor T4, realizing the data writing and compensation of the first transistor T1. At this time, the voltages of the first node N1 and the second node N2 are both Vdata + Vth1.

[0086] In the light emission stage t3, the first scan signal S1 is at a high level, the second scan signal S2 is at a high level, the third scan signal S3 is at a high level, and the light emission control signal EM is at a low level. Therefore, the eighth transistor T8 and the ninth transistor T9 are turned on, and the first transistor T1 generates a driving current according to its gate voltage to drive the light emitting diode D1 to emit light.

[0087] In the light emission stage t3, the specific working principle of reducing the leakage of the first node N1 is as follows:

[0088] Figure 7 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention, different from the Figure 5 shown pixel circuit in that Figure 7 the shown pixel circuit does not include a leakage suppression module 120, a first compensation sub-unit 141, and a second compensation sub-unit 142. In Figure 7After the gate of the first transistor T1 is written with the data voltage Vdata, it enters the light-emitting stage. Both the fifth transistor T5 and the sixth transistor T6 are in the off state. There are two leakage paths for the drain circuit of the first capacitor C1 (the first node N1). One is through the sixth transistor T6, and the other is through the fifth transistor T5. When |VDD - VN1| > |VN1 - Vref|, during the voltage holding process of the first capacitor C1, due to the leakage current, the first node N1 is charged with positive charges, and the voltage of the first node N1 is positively biased. After a period of time, it reaches the equilibrium state |VDD - VN1| = |VN1 - Vref|. At this time, the voltage of the first node N1 is the equilibrium voltage. Here, VDD - VN1 refers to the voltage difference across the sixth transistor T6 during the light-emitting stage, and VN1 - Vref refers to the voltage difference across the fifth transistor T5. Conversely, when |VDD - VN1| < |VN1 - Vref|, during the voltage holding process of the first capacitor C1, due to the leakage current, the first node N1 is charged with negative charges, and the voltage of the first node N1 is negatively biased. After a period of time, the first node N1 also reaches the equilibrium voltage. Therefore, Figure 7 The leakage current rate of the first node N1 of the pixel circuit shown gradually decreases, and has the maximum leakage current rate at the initial stage of the leakage current.

[0089] In Figure 5 At the initial moment of the leakage current, the voltage difference between the first node N1 and the second node N2 is zero. Therefore, the initial leakage current rate of the first node N1 is zero. As time goes by, the voltage of the second node N2 shifts due to the leakage current. However, due to the cut-off effect of the fourth transistor T4, the voltage difference between the first node N1 and the second node N2 gradually increases. The first node N1 starts to leak current and gradually increases. When the second node N2 reaches the equilibrium voltage, due to the leakage current of the fourth transistor T1, the first node N1 continues to leak current to the second node C2. As the voltage difference between the first node N1 and the second node N2 gradually decreases, the leakage current of the first node N1 also gradually decreases until the first node N1 and the second node N2 reach the equilibrium state.

[0090] Figure 8 It is a schematic diagram of a leakage current curve provided by an embodiment of the present invention. The solid line represents Figure 7 the leakage current of the first node N1 in the pixel circuit shown, the dotted line represents Figure 5 the leakage current of the first node N1 in the pixel circuit shown, the line AA' represents Figure 7 the time required for the first node N1 in the pixel circuit shown to reach the equilibrium voltage, and BB' represents Figure 5The time required for the first node N1 in the pixel circuit shown to reach the balance voltage. Compared with the pixel circuit without the leakage current suppression module 120, the technical solution provided in this embodiment makes the time for the first node N1 to reach the balance voltage longer, that is, the leakage current rate of the first node N1 is slower. Especially in the initial period of the leakage current, the leakage current of the first node N1 approaches zero.

[0091] Further, during the leakage current process, the second pole of the first transistor T1 is at a positive voltage, while the initialization voltage Vref is at a negative voltage, and the voltage difference across the sixth transistor T6 is inconsistent with the voltage difference across the fifth transistor T5. Therefore, the leakage current rates of the two leakage current paths are also different, which results in the voltage difference between the first node N1 and the second node N2 not being able to maintain at 0V, and there will still be leakage current generated.

[0092] In this embodiment, the voltage of the second node N2 is self-compensated by adding a second transistor T2 and a third transistor T3, thereby suppressing the leakage current between the first node N1 and the second node N2.

[0093] Specifically, according to the different leakage current rates of the two leakage current paths, when the leakage current makes the voltage of the second node N2 positively biased and VN2 > VN1 + Vth3, the third transistor T3 conducts and the second transistor T2 turns off. Therefore, the initialization voltage Vref charges negative charges into the second node N2 through the third transistor T3, that is, charges negative charges into the second capacitor C2. Until VN2 = VN1 + Vth3, the third transistor T3 turns off. At this time, it can be regarded that the voltage between the first node N1 and the second node N2 reaches a balance, and the voltage difference between them is small, effectively suppressing the leakage current between the first node N1 and the second node N2.

[0094] When the leakage current makes the voltage of the second node N2 negatively biased and VN2 < VN1 - Vth2, the second transistor T2 conducts and the third transistor T3 turns off. Therefore, the first power supply voltage VDD charges positive charges into the second node N2 through the second transistor T2 (that is, charges positive charges into the second capacitor C2). Until VN2 = VN1 - Vth2, the second transistor T2 turns off. At this time, it can be regarded that the voltage between the first node N1 and the second node N2 reaches a balance, and the voltage difference between them is small, effectively suppressing the leakage current between the first node N1 and the second node N2.

[0095] In this embodiment, through the self-compensation function of the second transistor T2 and the third transistor T3, the voltage difference between the first node N1 and the second node N2 is controlled within the range of (VN1 - |Vth2|) to (VN1 + |Vth3|), thereby effectively suppressing the leakage current from the first node N1 to the second node N2, ensuring the stability of the voltage of the first node N1, and further preventing the occurrence of flicker phenomena under low-frequency display.

[0096] Figure 9 This is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention. On the basis of the above technical solution, optionally, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are double-gate transistors. The double-gate transistor has a smaller leakage current than the single-gate transistor, and can further reduce the leakage of the first node N1.

[0097] Optionally, the first compensation module 140 may also have other connection manners. Figure 10 This is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention. Figure 11 This is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention, and shows Figure 10 the specific structure of the pixel circuit shown. Refer to Figure 2 and Figure 10 , on the basis of the above technical solutions, the first compensation module 140 includes a first compensation subunit 141 and a second compensation subunit 142; a first end of the first compensation subunit 141 is connected to the second compensation module 180, a second end of the first compensation subunit 141 is connected to the second node N2, and a control end of the first compensation subunit 141 is connected to the first node N1; a first end of the second compensation subunit 142 is connected to the initialization module 130, a second end of the second compensation subunit 142 is connected to the second node N2, and a control end of the second compensation subunit 142 is connected to the first node N1.

[0098] Specifically, refer to Figure 11 , the first compensation subunit 141 includes a second transistor T2, and the second compensation subunit 142 includes a third transistor T3. Among them, the second transistor T2 is connected between an intermediate node of the sixth transistor T6 and the second node N2, and the third transistor T3 is connected between an intermediate node of the fifth transistor T5 and the second node N2. Compared with Figure 5 the pixel circuit shown Figure 11In the pixel circuit shown, the voltage of the middle node of the sixth transistor T6 is closer to the first power supply voltage VDD than the voltage at point M1, and the positive charge leakage rate is greater; the voltage of the middle node of the fifth transistor T5 is closer to the initialization voltage Vref than the voltage at point M2, and the negative charge leakage rate is greater. When the leakage current at point M1 is greater than that at point M2, by turning on the third transistor T3, more negative charges can be provided to point M1 within the same time to balance the voltage of the second node N2. When the leakage current at point M1 is less than that at point M2, by turning on the second transistor T2, more positive charges can be provided to point M2 within the same time to balance the voltage of the second node N2. In addition, since the second transistor T2 and the third transistor T3 are not directly connected to the first power supply voltage VDD or the initialization voltage Vref, the increase in power consumption caused by the leakage current of the second transistor T2 and the third transistor T3 can be effectively avoided.

[0099] Optionally, an embodiment of the present invention further provides a driving method for a pixel circuit, which is used to drive the pixel circuit provided in any embodiment of the present invention. Figure 12 It is a flowchart of a driving method for a pixel circuit provided by an embodiment of the present invention, in combination with Figure 1 and Figure 12 , the driving method of the pixel circuit includes:

[0100] S110. In the initialization stage, control the initialization module to transmit the initialization voltage to the first node through the leakage current suppression module to initialize the control end of the driving module.

[0101] S120. In the light emitting stage, control the driving module to drive the light emitting module to emit light, and control the first compensation module to turn on in response to the voltage signal of the first node to compensate the voltage of the second node.

[0102] The technical solution provided in this embodiment adopts a pixel circuit including a driving module, a leakage suppression module, an initialization module, a first compensation module, a first storage module, a second storage module, and a light-emitting module. The control end of the driving module is connected to the leakage suppression module at a first node, and the initialization module is connected to the leakage suppression module at a second node. The initialization module is configured to transmit an initialization voltage to the first node through the leakage suppression module during the initialization phase to initialize the control end of the driving module. The driving module and the light-emitting module are connected between a first power supply line and a second power supply line. The driving module is configured to drive the light-emitting module to emit light during the light-emitting phase. The first storage module is connected to the first node and is configured to store the voltage of the first node. The second storage module is connected to the second node and is configured to store the voltage of the second node. The first compensation module is connected to the second node and is configured to perform voltage compensation on the second node in response to the voltage signal of the first node. During the light-emitting phase, on the one hand, the potential of the first node is stabilized by setting the leakage suppression module and the second storage module; on the other hand, the voltage of the second node is self-compensated by setting the first compensation module to reduce the voltage difference between the first node and the second node, further reducing the leakage current, thereby being able to improve the leakage phenomenon of the pixel circuit and enhance the display effect.

[0103] Optionally, Figure 13 is a flowchart of another driving method for the pixel circuit provided by an embodiment of the present invention. Combining Figure 3 and Figure 13 , the driving method includes:

[0104] S110. During the initialization phase, control the initialization module to transmit the initialization voltage to the first node through the leakage suppression module to initialize the control end of the driving module.

[0105] S210. During the data writing phase, control the data writing module to transmit the data voltage on the data line to the control end of the driving module through the conducting second compensation module.

[0106] S121. During the light-emitting phase, control the driving module to drive the light-emitting module to emit light. When the voltage of the second node is negatively biased, control the first compensation sub-unit to conduct in response to the voltage signal of the first node to perform positive compensation on the voltage of the second node; when the voltage of the second node is positively biased, control the second compensation sub-unit to conduct in response to the voltage signal of the first node to perform negative compensation on the voltage of the second node.

[0107] For the specific working principle of the driving method for the pixel circuit provided in this embodiment, reference can be made to the description of the pixel circuit in any of the above embodiments, and it has the same beneficial effects as those described in any of the above embodiments, which will not be elaborated here.

[0108] Optionally, an embodiment of the present invention further provides a display panel, including the pixel circuit provided in the above embodiment. Therefore, the display panel also has the beneficial effects described in any of the above embodiments. Figure 14 FIG. Figure 14 is a schematic structural diagram of a display panel provided in an embodiment of the present invention. In this embodiment, the display panel can be applied to a mobile phone or any electronic product with a display function, including but not limited to the following categories: television, notebook computer, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, in-vehicle display, medical device, industrial control device, touch interaction terminal, etc. The embodiments of the present invention do not make special limitations on this.

[0109] It should be understood that various forms of the processes shown above can be used, steps can be reordered, added or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. There is no limitation herein.

[0110] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A pixel circuit, characterized in that Comprising: a driving module, a leakage current suppression module, an initialization module, a first compensation module, a first storage module, a second storage module, and a light-emitting module; a control end of the driving module is connected to the leakage current suppression module at a first node, the initialization module is connected to the leakage current suppression module at a second node, and the initialization module is configured to transmit an initialization voltage to the first node via the leakage current suppression module during an initialization phase to initialize a control end of the driving module; the driving module and the light-emitting module are connected between a first power supply line and a second power supply line, and the driving module is configured to drive the light-emitting module to emit light during a light-emitting phase; the first storage module is connected to the first node and is configured to store a voltage of the first node; the second storage module is connected to the second node and is configured to store a voltage of the second node; the first compensation module is connected to the second node and is configured to perform voltage compensation on the second node in response to a voltage signal of the first node; further comprising a second compensation module, the second compensation module being connected between a second end of the driving module and the second node; the first compensation module includes a first compensation subunit and a second compensation subunit; a first end of the first compensation subunit is connected to the first power supply line, a second end of the first compensation subunit is connected to the second node, and a control end of the first compensation subunit is connected to the first node; a first end of the second compensation subunit accesses the initialization voltage, a second end of the second compensation subunit is connected to the second node, and a control end of the second compensation subunit is connected to the first node; alternatively, a first end of the first compensation subunit is connected to the second compensation module, a second end of the first compensation subunit is connected to the second node, and a control end of the first compensation subunit is connected to the first node; a first end of the second compensation subunit is connected to the initialization module, a second end of the second compensation subunit is connected to the second node, and a control end of the second compensation subunit is connected to the first node; wherein, the first compensation subunit and the second compensation subunit are not turned on simultaneously.

2. The pixel circuit according to claim 1, wherein further comprising a data writing module; the data writing module is connected between a data line and a first end of the driving module; a first end of the first storage module is connected to the first power supply line, a second end of the first storage module is connected to the control end of the driving module at the first node, a first end of the leakage current suppression module is connected to the first node, a second end of the leakage current suppression module is connected to a second end of the initialization module at the second node, a first end of the initialization module accesses the initialization voltage, a first end of the second storage module is connected to the first power supply line, and a second end of the second storage module is connected to the second node.

3. The pixel circuit according to claim 2, wherein the driving module includes a first transistor, the first compensation subunit includes a second transistor, and the second compensation subunit includes a third transistor; The gate of the second transistor is connected to the gate of the first transistor at the first node, the first pole of the second transistor is connected to the second node, the second pole of the second transistor is connected to the first power supply line, the gate of the third transistor is connected to the first node, the first pole of the third transistor is connected to the second node, and the second pole of the third transistor is connected to the initialization voltage; The channel types of the second transistor and the third transistor are different.

4. The pixel circuit according to claim 2, wherein The first storage module includes a first capacitor, and the second storage module includes a second capacitor; The first end of the first capacitor is connected to the first power supply line, the second end of the first capacitor is connected to the first node, the first end of the second capacitor is connected to the first power supply line, and the second end of the second capacitor is connected to the second node; The capacitance value of the first capacitor is greater than that of the second capacitor.

5. The pixel circuit according to claim 2, wherein The leakage suppression module includes a fourth transistor, the initialization module includes a fifth transistor, the second compensation module includes a sixth transistor, and the data writing module includes a seventh transistor; the pixel circuit further includes a first light emission control module and a second light emission control module, the first light emission control module includes an eighth transistor, the second light emission control module includes a ninth transistor, and the light emission module includes a light emitting diode; The gate of the fourth transistor is connected to a first scan signal, the first pole of the fourth transistor is connected to the first node, the second pole of the fourth transistor is connected to the second node, the gate of the fifth transistor is connected to a second scan signal, the first pole of the fifth transistor is connected to the initialization voltage, the second pole of the fifth transistor is connected to the second node, the gate of the sixth transistor is connected to a third scan signal, the first pole of the sixth transistor is connected to the second end of the driving module, the second pole of the sixth transistor is connected to the second node, the gate of the seventh transistor is connected to the third scan signal, the first pole of the seventh transistor is connected to the data line, and the second pole of the seventh transistor is connected to the first end of the driving module; The gates of the eighth transistor and the ninth transistor are both connected to a light emission control signal, the first pole of the eighth transistor is connected to the first power supply line, the second pole of the eighth transistor is connected to the first end of the driving module, the first pole of the ninth transistor is connected to the second end of the driving module, the second pole of the ninth transistor is connected to the first pole of the light emitting diode, and the second pole of the light emitting diode is connected to the second power supply line.

6. The pixel circuit according to claim 5, characterized in that, The fourth transistor, the fifth transistor, and the sixth transistor are double-gate transistors.

7. A driving method for a pixel circuit, characterized in that The pixel circuit includes a driving module, a leakage suppression module, an initialization module, a first compensation module, a first storage module, a second storage module, and a light-emitting module; a control terminal of the driving module is connected to the leakage suppression module at a first node, the initialization module is connected to the leakage suppression module at a second node, the driving module and the light-emitting module are connected between a first power supply line and a second power supply line, the first storage module is connected to the first node, the second storage module is connected to the second node, and the first compensation module is connected to the second node; The driving method of the pixel circuit includes: In the initialization stage, controlling the initialization module to transmit an initialization voltage to the first node through the leakage suppression module to initialize the control terminal of the driving module; In the light-emitting stage, controlling the driving module to drive the light-emitting module to emit light, and controlling the first compensation module to conduct in response to a voltage signal of the first node to perform voltage compensation on the second node; The first compensation module includes a first compensation sub-unit and a second compensation sub-unit. A first end of the first compensation sub-unit is connected to the first power supply line, a second end of the first compensation sub-unit is connected to the second node, and a control terminal of the first compensation sub-unit is connected to the first node; a first end of the second compensation sub-unit accesses the initialization voltage, a second end of the second compensation sub-unit is connected to the second node, and a control terminal of the second compensation sub-unit is connected to the first node; The step of controlling the first compensation module to conduct in response to a voltage signal of the first node to perform voltage compensation on the second node specifically includes: When the voltage of the second node is negatively biased, controlling the first compensation sub-unit to conduct in response to a voltage signal of the first node to perform positive compensation on the voltage of the second node; When the voltage of the second node is positively biased, controlling the second compensation sub-unit to conduct in response to a voltage signal of the first node to perform negative compensation on the voltage of the second node.

8. The driving method of the pixel circuit according to claim 7, characterized in that The pixel circuit further includes a second compensation module and a data writing module. The data writing module is connected between a data line and a first end of the driving module, and the second compensation module is connected between a second end of the driving module and the second node; Before the light-emitting stage, the driving method of the pixel circuit further includes: In the data writing stage, controlling the data writing module to transmit a data voltage on the data line to the control terminal of the driving module through the conducting second compensation module.

9. A display panel, characterized in that, Including the pixel circuit according to any one of claims 1-6.

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