Pixel circuit, driving method thereof, and display panel

Abstract

The present invention discloses a pixel circuit, a driving method thereof, and a display panel. The pixel circuit includes: a driving module, a data writing module, a first voltage regulating module, a second voltage regulating module, and a light-emitting module. In a writing frame, the second voltage regulating module is used to transmit an initialization voltage to the control terminal of the driving module via the first voltage regulating module during the initialization phase, and the data writing module is used to transmit a data voltage to the control terminal of the driving module during the data writing phase. In a holding frame, the first voltage regulating module is turned on and off at least once to adjust the voltage of the control terminal of the driving module. The technical solution provided by the embodiment of the present invention fine-tunes the potential of the control terminal of the driving module, thereby compensating for the effect of the potential reduction of the control terminal of the driving module due to leakage, facilitating the stabilization of the potential of the control terminal of the driving module and preventing the occurrence of bright spots, especially bright spots in low grayscale displays.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel circuit, a driving method thereof, and a display panel. Background Art

[0002] With the development of display technology, people have higher and higher requirements on the performance of display panels.

[0003] LTPO (Low Temperature Poly-Oxide) is a low-power OLED display technology that combines N-type IGZO transistors and P-type LTPS transistors. Existing technologies typically use LTPO display technology to reduce leakage current in pixel circuits, especially in medium- and large-sized or high-end small-sized display products. However, when LTPO pixel circuits operate at low refresh rates, they can exhibit low grayscale highlights, seriously affecting product yield. Summary of the Invention

[0004] The present invention provides a pixel circuit, a driving method thereof, and a display panel to solve the problem of low grayscale bright spots existing in the display panel during the display process.

[0005] According to one aspect of the present invention, a pixel circuit is provided, comprising: a driving module, a data writing module, a first voltage regulating module, a second voltage regulating module and a light emitting module;

[0006] The first voltage regulating module is connected between the control terminal of the driving module and the second voltage regulating module, the driving module and the light-emitting module are connected between a first power line and a second power line, and the driving module is used to drive the light-emitting module to emit light during a display cycle; wherein a display cycle includes a writing frame and a holding frame;

[0007] In the write frame, the second voltage regulating module is used to transmit the initialization voltage to the first voltage regulating module in the initialization phase, and then the first voltage regulating module transmits the initialization voltage to the control end of the driving module. The data writing module is used to transmit the data voltage to the control end of the driving module in the data writing phase.

[0008] In the holding frame, the first voltage regulating module is turned on and off at least once to regulate the voltage of the control terminal of the driving module.

[0009] Optionally, the second voltage regulation module includes a first initialization unit and a voltage regulation subunit, and the initialization voltage includes a first initialization voltage;

[0010] A first end of the data writing module is connected to the data voltage, a second end of the data writing module is connected to the first end of the driving module, a first end of the voltage regulating subunit is connected to the second end of the driving module, a second end of the voltage regulating subunit is connected to the first end of the first voltage regulating module, a second end of the first voltage regulating module is connected to the control end of the driving module, a first end of the first initialization unit is connected to the first initialization voltage, and a second end of the first initialization unit is connected to the first end of the first voltage regulating module;

[0011] In the write frame, the first initialization unit is used to transmit the first initialization voltage to the control end of the driving module through the first voltage regulation module that is turned on, and to the second end of the driving module through the voltage regulation subunit that is turned on; the data writing module is used to transmit the data voltage to the control end of the driving module through the voltage regulation subunit that is turned on and the first voltage regulation module during the data writing phase.

[0012] Optionally, a leakage suppression module is further included, which is connected between the first voltage regulation module and the first initialization unit and is used to cut off the leakage path of the second end of the driving module at least in the writing frame.

[0013] Optionally, the control end of the first voltage regulating module and the control end of the leakage suppression module are both connected to a first scanning signal, the control end of the first initialization unit is connected to a second scanning signal, and the control end of the voltage regulating subunit is connected to a third scanning signal; wherein the second scanning signal and the third scanning signal are double pulse signals;

[0014] In the write frame, the voltage regulating subunit is configured to transmit the data voltage to the control terminal of the driving module via the first voltage regulating module in response to the first pulse of the third scanning signal during the data write phase, and transmit the voltage of the second terminal of the driving module to the control terminal of the driving module via the first voltage regulating module in response to the second pulse of the third scanning signal during the subthreshold compensation phase;

[0015] When the first voltage regulating module and the leakage suppression module are turned on in response to the first scanning signal, the first initialization unit is turned off in response to the second scanning signal.

[0016] Optionally, the driving module includes a first transistor, the data writing module includes a second transistor, the first voltage regulating module includes a third transistor, the first initialization unit includes a fourth transistor, the voltage regulating subunit includes a fifth transistor, and the leakage suppression module includes a sixth transistor;

[0017] The gate of the second transistor is connected to the fourth scan signal, the first electrode of the second transistor is connected to the data voltage, the second electrode of the second transistor is connected to the first electrode of the first transistor, the first electrode of the fifth transistor is connected to the second electrode of the first transistor, the second electrode of the fifth transistor is connected to the first electrode of the third transistor, the second electrode of the third transistor is connected to the gate of the first transistor, the gate of the fifth transistor is connected to the third scan signal, and the gate of the third transistor is connected to the first scan signal; the first electrode of the fourth transistor is connected to the first initialization voltage, the second electrode of the fourth transistor is connected to the first electrode of the sixth transistor, the second electrode of the sixth transistor is connected to the first electrode of the third transistor, the gate of the fourth transistor is connected to the second scan signal, and the gate of the sixth transistor is connected to the first scan signal;

[0018] Preferably, a channel type of the third transistor is different from a channel type of the fifth transistor;

[0019] Preferably, the fifth transistor is a metal oxide transistor.

[0020] Optionally, the second voltage regulating module further includes a second initialization unit, the initialization voltage further includes a second initialization voltage, and the second initialization unit is connected to the first end of the light-emitting module, and is used to transmit the second initialization voltage to the first end of the light-emitting module;

[0021] Preferably, the pixel circuit further includes a storage module, a first light-emitting control module, and a second light-emitting control module, wherein a first end of the storage module is connected to the first power line, a second end of the storage module is connected to the control end of the driving module, a first end of the first light-emitting control module is connected to the first power line, a second end of the first light-emitting control module is connected to the first end of the driving module, a first end of the second light-emitting control module is connected to the second end of the driving module, a second end of the second light-emitting control module is connected to the first end of the light-emitting module, and a second end of the light-emitting module is connected to the second power line;

[0022] The second initialization unit includes a seventh transistor, the first light emitting control module includes an eighth transistor, the second light emitting control module includes a ninth transistor, the storage module includes a storage capacitor, and the light emitting module includes a light emitting diode;

[0023] a first electrode of the seventh transistor connected to the second initialization voltage, a second electrode of the seventh transistor connected to the first electrode of the light-emitting diode, a gate of the seventh transistor connected to the fifth scanning signal, a first electrode of the eighth transistor connected to the first power line, a second electrode of the eighth transistor connected to the first end of the driving module, a gate of the eighth transistor connected to the first light-emitting control signal, a gate of the ninth transistor connected to the second light-emitting control signal, a first electrode of the ninth transistor connected to the second end of the driving module, a second electrode of the ninth transistor connected to the first electrode of the light-emitting diode, and a second electrode of the light-emitting diode connected to the second power line;

[0024] Preferably, the first initialization voltage is multiplexed into the second initialization voltage, and the first light-emitting control signal is multiplexed into the second light-emitting control signal.

[0025] The second voltage regulation module includes a first initialization unit and a voltage regulation subunit;

[0026] The first end of the data writing module is connected to the data voltage, the second end of the data writing module is connected to the first end of the driving module, the first end of the voltage regulating subunit is connected to the second end of the driving module, the second end of the voltage regulating subunit is connected to the first end of the first voltage regulating module, the second end of the first voltage regulating module is connected to the control end of the driving module, the first end of the first initialization unit is connected to the initialization voltage, and the second end of the first initialization unit is connected to the first end of the light-emitting module;

[0027] In the write frame, the first initialization unit is used to transmit the initialization voltage to the control end of the driving module via the first voltage regulating module and the voltage regulating sub-unit that are turned on during the initialization phase; the data writing module is used to transmit the data voltage to the control end of the driving module via the voltage regulating sub-unit and the first voltage regulating module that are turned on during the data writing phase;

[0028] The pixel circuit also includes a first light-emitting control module, a second light-emitting control module and a storage module, wherein a first end of the storage module is connected to the first power line, a second end of the storage module is connected to the control end of the driving module, a first end of the first light-emitting control module is connected to the first power line, a second end of the first light-emitting control module is connected to the first end of the driving module, a first end of the second light-emitting control module is connected to the second end of the driving module, a second end of the second light-emitting control module is connected to the first end of the light-emitting module, and a second end of the light-emitting module is connected to the second power line.

[0029] According to another aspect of the present invention, a method for driving a pixel circuit is provided. The pixel circuit includes a driving module, a data writing module, a first voltage regulating module, a second voltage regulating module, and a light-emitting module. The first voltage regulating module is connected between a control terminal of the driving module and the second voltage regulating module. The driving module and the light-emitting module are connected between a first power line and a second power line. The driving module is configured to drive the light-emitting module to emit light within a display cycle. A display cycle includes a writing frame and a holding frame.

[0030] In the write frame:

[0031] In the initialization phase, controlling the second voltage regulating module to transmit the initialization voltage to the control terminal of the driving module via the turned-on first voltage regulating module;

[0032] In the data writing phase, controlling the data writing module to transmit the data voltage to the control terminal of the driving module;

[0033] In the light-emitting stage, controlling the driving module to drive the light-emitting module to emit light according to the data voltage;

[0034] In the hold frame:

[0035] The first voltage regulating module is controlled to be turned on and off at least once to regulate the voltage of the control terminal of the driving module.

[0036] Optionally, the pixel circuit further includes a leakage suppression module, and the second voltage regulation module includes a first initialization unit and a voltage regulation subunit; the leakage suppression module is connected between the first voltage regulation module and the first initialization unit, the first end of the data writing module is connected to the data voltage, the second end of the data writing module is connected to the first end of the driving module, the first end of the voltage regulation subunit is connected to the second end of the driving module, the second end of the voltage regulation subunit is connected to the first end of the first voltage regulation module, the second end of the first voltage regulation module is connected to the control end of the driving module, the first end of the first initialization unit is connected to the first initialization voltage, and the second end of the first initialization unit is connected to the first end of the first voltage regulation module; wherein, the control end of the first voltage regulation module and the control end of the leakage suppression module are both connected to the first scanning signal, the control end of the first initialization unit is connected to the second scanning signal, and the control end of the voltage regulation subunit is connected to the third scanning signal;

[0037] The driving method of the pixel circuit includes:

[0038] In the write frame:

[0039] In the initialization phase, the first initialization unit is controlled to be turned on in response to a first pulse of the second scanning signal, and the first initialization voltage is transmitted to the control terminal of the driving module via the turned-on first voltage regulating module; and the voltage regulating subunit is controlled to be turned on in response to a first pulse of the third scanning signal, and the first initialization voltage is transmitted to the second terminal of the driving module via the voltage regulating subunit.

[0040] In the data writing phase, controlling the data writing module to transmit the data voltage to the control end of the driving module via the voltage regulating subunit and the first voltage regulating module;

[0041] In the subthreshold compensation stage, the voltage regulating subunit is controlled to be turned on in response to the second pulse of the third scanning signal, and the voltage of the second end of the driving module is transmitted to the control end of the driving module via the first voltage regulating module.

[0042] According to another aspect of the present invention, a display panel is provided, comprising the pixel circuit provided by any embodiment of the present invention.

[0043] The technical solution provided by the embodiments of the present invention, by providing a first voltage regulating module and a second voltage regulating module, implements data writing and light emission in the pixel circuit during the write frame, and implements an intra-frame reset of the potential at the control terminal of the driver module during the hold frame. Specifically, after the write frame ends and the hold frame begins, the first voltage regulating module is turned on and then off, causing the potential at point N1 to increase due to the self-coupling effect of the first voltage regulating module, thereby fine-tuning the potential at the control terminal of the driver module (point G potential). This, in turn, compensates for the effect of leakage on the potential at the control terminal of the driver module, helps stabilize the potential at the control terminal of the driver module, and prevents the occurrence of bright spots, particularly those found in low grayscale displays.

[0044] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 Schematic diagram of the structure of a pixel circuit in the prior art;

[0047] Figure 2 A schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0048] Figure 3 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0049] Figure 4 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0050] Figure 5 A driving timing waveform diagram of a write frame corresponding to a pixel circuit provided by an embodiment of the present invention;

[0051] Figure 6 A driving timing waveform diagram of a holding frame corresponding to a pixel circuit provided by an embodiment of the present invention;

[0052] Figure 7 A driving timing waveform diagram of a writing frame corresponding to another pixel circuit provided by an embodiment of the present invention;

[0053] Figure 8 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0054] Figure 9 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0055] Figure 10 A driving timing waveform diagram of a writing frame corresponding to another pixel circuit provided by an embodiment of the present invention;

[0056] Figure 11 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0057] Figure 12 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0058] Figure 13 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0059] Figure 14 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0060] Figure 15 A driving timing waveform diagram of a writing frame corresponding to another pixel circuit provided by an embodiment of the present invention;

[0061] Figure 16 A flowchart of a method for driving a pixel circuit provided by an embodiment of the invention;

[0062] Figure 17A schematic structural diagram of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0063] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0064] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0065] As mentioned in the background technology, display panels in the prior art usually use LTPO display technology for display, which is prone to the problem of low grayscale bright spots, affecting the yield of the product. The inventors have found that the reason for the above problem is that there is leakage current in the gate of the driving transistor, which reduces its gate voltage, resulting in low grayscale bright spots. For example, Figure 1 This is a schematic diagram of a pixel circuit in the prior art. Figure 1The pixel circuit includes a driving transistor Q1, a first initialization transistor Q2, a second initialization transistor Q3, a data writing transistor Q4, a compensation transistor Q5, a first light-emission control transistor Q6, and a second light-emission control transistor Q7. During the initialization phase, a first initialization voltage Vref1 is written to the gate of the driving transistor Q1 via the first initialization transistor Q2 to initialize the gate potential of the driving transistor Q1, and a second initialization voltage Vref2 is written to the anode of the light-emitting diode D1 via the second initialization transistor Q3 to initialize the anode potential of the light-emitting diode D1. During the data writing phase, a data voltage is written to the gate of the driving transistor Q1 via the data writing transistor Q4 and the compensation transistor Q5. During the light-emission phase, the driving transistor Q1 controls the light-emitting diode D1 to emit light. In the prior art, to maintain the voltage at the gate of the driving transistor Q1, the first initialization transistor Q2 and the compensation transistor Q5 are typically configured as n-type IGZO transistors to reduce leakage at the gate of the driving transistor Q1. However, the gate control signal of the n-type IGZO transistor will jump downward after the compensation stage. Under the coupling of the parasitic capacitance of the n-type IGZO transistor, the gate voltage of the driving transistor Q1 is reduced, resulting in high display brightness. Bright spots are prone to appear under low-frequency driving, especially low grayscale bright spots, which seriously affect the display effect.

[0066] In view of the above problems, an embodiment of the present invention provides a pixel circuit to eliminate the problem of bright spots on display. Figure 2 A schematic structural diagram of a pixel circuit provided by an embodiment of the present invention, wherein: Figure 2 It is only a schematic diagram of a pixel circuit structure. Figure 2 The pixel circuit provided in this embodiment includes a driver module 110, a data writing module 120, a first voltage regulating module 130, a second voltage regulating module 140, and a light-emitting module 150. The first voltage regulating module 130 is connected between the control terminal of the driver module 110 and the second voltage regulating module 140. The driver module 110 and the light-emitting module 150 are connected between a first power line L1 and a second power line L2. The driver module 110 is used to drive the light-emitting module 150 to emit light during a display period. Here, the first power line L1 is used to provide a first power supply voltage VDD, and the second power line L2 is used to provide a second power supply voltage VSS.

[0067] Among them, a display cycle includes a write frame and a hold frame; in the write frame, the second voltage regulation module 140 is used to transmit the initialization voltage Vref to the first voltage regulation module 130 in the initialization stage, and then the first voltage regulation module 130 transmits it to the control end of the driving module 110, and the data writing module 120 is used to transmit the data voltage Vdata to the control end of the driving module 110 in the data writing stage.

[0068] In the holding frame, the first voltage regulating module 130 is turned on and off at least once to regulate the voltage of the control terminal of the driving module 110 .

[0069] Specifically, the operation process of the pixel circuit provided in this embodiment includes at least an initialization phase, a data writing phase, a voltage adjustment phase, and a light-emitting phase. A display cycle includes a write frame and a hold frame, for example, one write frame and at least one hold frame. The write frame is used for writing data and emitting light to the pixel circuit, and the hold frame is used for adjusting the voltage and emitting light to the pixel circuit.

[0070] In the write frame:

[0071] During the initialization stage, the first voltage regulation module 130 and the second voltage regulation module 140 are turned on in response to corresponding control signals (the control signals are not shown in the figure), and the second voltage regulation module 140 transmits the initialization voltage Vref to the control end of the driving module 110 through the first voltage regulation module 130, that is, the voltage at point G is the initialization voltage Vref, thereby resetting the voltage at the control end of the driving module 110 to prevent it from being affected by the residual charge of the previous frame.

[0072] In the data writing phase, the data writing module 120 is turned on in response to the corresponding control signal and transmits the data voltage Vdata to the control terminal of the driving module 110 , that is, the voltage at point G is the data voltage Vdata.

[0073] In the light-emitting stage, the driving module 110 generates a driving current according to the voltage between the control terminal and the first terminal thereof, and drives the light-emitting module 150 to emit light.

[0074] In the hold frame:

[0075] The first voltage regulating module 130 is turned on at least once in response to a control signal at its control terminal, and is then turned off once after being turned on. For example, the first voltage regulating module 130 is turned on in response to a low-level signal and turned off in response to a high-level signal. When the first voltage regulating module 130 changes from an on state to an off state, the control signal at its control terminal rises, and the parasitic capacitance couples the potential at point N1 to increase, causing the potential at point N1 to be higher than the potential at point G.

[0076] During the light-emission phase of the hold frame, driver module 110 generates a drive current based on the voltages at its control terminal and first terminal, driving light-emitting module 150 to emit light. During this process, because the potential at point N1 is higher than that at point G, the voltage at point N1 gradually charges toward point G due to leakage from the first voltage regulator module, causing the potential at point G to increase. This reduces the brightness of light-emitting module 150 and prevents the occurrence of low-grayscale bright spots.

[0077] In another alternative implementation of this embodiment, during the hold frame, the first voltage regulator module 130 is turned on at least once in response to a control signal from its control terminal, and is then turned off once after being turned on. For example, the first voltage regulator module 130 is turned on in response to a high-level signal and turned off in response to a low-level signal. When the first voltage regulator module 130 changes from the on state to the off state, the control signal from its control terminal drops, and the parasitic capacitance couples the potential of point N1 downward. Here, the potential of point N1 is still higher than the initialization voltage Vref. During the light-emitting phase of the hold frame, due to leakage from the first voltage regulator module 130, the voltage at point G gradually charges toward point N1, causing the potential at point G to decrease. Because the potential at point N1 is higher than the initialization voltage Vref, the leakage from point G to point N1 results in a smaller leakage current than if point G were to directly leak to the initialization voltage Vref. Therefore, the voltage fluctuation at point G is less severe, similarly alleviating the problem of bright dots in low grayscale.

[0078] In this embodiment, the first voltage regulating module 130 can be turned on and off multiple times within the holding frame to fine-tune the potential of the control terminal of the driving module 110 multiple times, which is beneficial to improving the resetting effect of the G point voltage.

[0079] The technical solution provided by the embodiments of the present invention, by providing a first voltage regulating module and a second voltage regulating module, implements data writing and light emission in the pixel circuit during the write frame, and implements an intra-frame reset of the potential at the control terminal of the driver module during the hold frame. Specifically, after the write frame ends and the hold frame begins, the first voltage regulating module is turned on and then off, causing the potential at point N1 to increase due to the self-coupling effect of the first voltage regulating module, thereby fine-tuning the potential at the control terminal of the driver module (point G potential). This, in turn, compensates for the effect of leakage on the potential at the control terminal of the driver module, helps stabilize the potential at the control terminal of the driver module, and prevents the occurrence of bright spots, particularly those found in low grayscale displays.

[0080] Optionally, the second voltage regulation module 140 may be used to implement an initialization function and a threshold compensation function. Figure 3 A schematic diagram of another pixel circuit according to an embodiment of the present invention is provided. Figure 3Based on the above technical solution, the second voltage regulation module 140 includes a first initialization unit 141 and a voltage regulation subunit 142, and the initialization voltage Vref includes a first initialization voltage Vref1; a first end of the data writing module 120 is connected to the data voltage Vdata, a second end of the data writing module 120 is connected to the first end of the driving module 110, a first end of the voltage regulation subunit 142 is connected to the second end of the driving module 110, a second end of the voltage regulation subunit 142 is connected to the first end of the first voltage regulation module 130, a second end of the first voltage regulation module 130 is connected to the control end of the driving module 110, a first end of the first initialization unit 141 is connected to the first initialization voltage Vref1, and a second end of the first initialization unit 141 is connected to the first end of the first voltage regulation module 130.

[0081] Specifically, the first initialization unit 141 and the voltage regulating subunit 142 are connected to point N1, the voltage regulating subunit 142 and the second end of the driving module 110 are connected to point D, and the data writing module 120 and the first end of the driving module 110 are connected to point S.

[0082] In the write frame:

[0083] During the initialization phase, the first voltage regulator module 130 turns on in response to the first scan signal S1, and the first initialization unit 141 turns on in response to the second scan signal S2. The first initialization unit 141 transmits the first initialization voltage Vref1 to the control terminal of the driver module 110 via the first voltage regulator module 130, resetting the potential of the control terminal of the driver module 110. Simultaneously, the voltage regulator subunit 142 turns on in response to the third scan signal S3, and the first initialization unit 141 transmits the first initialization voltage Vref1 to the second terminal and the first terminal of the driver module 110 via the voltage regulator subunit 142 (the driver module 110 is in the on state). This achieves initialization of the potentials of points G, S, and D.

[0084] During the data writing phase, the first voltage regulating module 130 is turned on in response to the first scanning signal S1, the voltage regulating subunit 142 is turned on in response to the third scanning signal S3, and the data writing module 120 is turned on in response to the fourth scanning signal S4. The data voltage Vdata is transmitted to the control terminal of the driving module 110 via the data writing module 120, the driving module 110, the voltage regulating subunit 142, and the first voltage regulating module 130. At this time, the voltage at point G is the voltage associated with the threshold information of the driving module 110. Here, the voltage regulating subunit 142 is multiplexed as a compensation module to implement the threshold compensation function of the driving module 110.

[0085] In the light emitting stage, the driving module 110 drives the light emitting module 150 to emit light according to the voltages at the control terminal and the first terminal.

[0086] In the holding frame, the light-emitting module 150 first stops emitting light (such as controlling the light-emitting module 150 to be extinguished through the first light-emitting control module 161 and the second light-emitting control module 162), the first initialization unit 141 and the voltage regulation subunit 142 remain turned off, and the first voltage regulation module 130 is turned on again and then turned off to couple the potential of point N1 to increase the potential of point N1, so that the potential of point N1 is higher than the potential of point G, thereby causing the voltage at point G to leak up, thereby achieving regulation of the voltage at point G.

[0087] For example, Figure 4 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention, Figure 5 A driving timing waveform diagram of a write frame corresponding to a pixel circuit provided by an embodiment of the present invention, Figure 6 A driving timing waveform diagram of a pixel circuit corresponding to a holding frame provided in an embodiment of the present invention, referring to Figure 4-Figure 6 The pixel circuit can be specifically composed of transistors. The driving module 110 includes a first transistor T1, the data writing module 120 includes a second transistor T2, the first voltage regulating module 130 includes a third transistor T3, the first initialization unit 141 includes a fourth transistor T4, and the voltage regulating subunit 142 includes a fifth transistor T5. The gate of the second transistor T2 is connected to the fourth scan signal S4, the first electrode of the second transistor T2 is connected to the data voltage Vdata, the second electrode of the second transistor T2 is connected to the first electrode of the first transistor T1, the first electrode of the fifth transistor T5 is connected to the second electrode of the first transistor T1, the second electrode of the fifth transistor T5 is connected to the first electrode of the third transistor T3, the second electrode of the third transistor T3 is connected to the gate of the first transistor T1, the gate of the fifth transistor T5 is connected to the third scan signal S3, and the gate of the third transistor T3 is connected to the first scan signal S1; the first electrode of the fourth transistor T4 is connected to the first initialization voltage Vref1, the second electrode of the fourth transistor T4 is connected to the first electrode of the third transistor T3, and the gate of the fourth transistor T4 is connected to the second scan signal S2.

[0088] The channel type of the third transistor T3 is different from the channel type of the fifth transistor T5. In this embodiment, the third transistor T3 is a P-type LTPS transistor, and the fifth transistor T5 and the fourth transistor T4 are both N-type IGZO transistors.

[0089] In the write frame:

[0090] In the pre-processing stage t1, the first scanning signal S1 is at a high level, the second scanning signal S2 jumps from a low level to a high level, the third scanning signal S3 is at a low level, the fourth scanning signal S4 is at a high level, and the first emission control signal EM1 and the second emission control signal EM2 are both at a high level. Therefore, the fourth transistor T4 switches from an off state to an on state.

[0091] During the initialization phase t2, the first scan signal S1 is at a low level, the second scan signal S2 is at a high level, the third scan signal S3 is at a high level, and the fourth scan signal S4 is at a high level. Both the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at a high level. Therefore, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned on. The fourth transistor T4 transmits the first initialization voltage Vref1 to the gate of the first transistor T1 through the third transistor T3 and to the second electrode of the first transistor T1 through the fifth transistor T5. At this point, the first transistor T1 is turned on by the gate voltage, and the voltage at the second electrode (point D) is transmitted to the first electrode (point S), thereby initializing the three electrodes of the first transistor T1.

[0092] During data writing phase t3, the first scan signal S1 is at a low level, the second scan signal S2 is at a low level, the third scan signal S3 is at a high level, and the fourth scan signal S4 is at a low level. The first and second light-emission control signals EM1 and EM2 are both at a high level. Therefore, the second transistor T2 and the fifth transistor T5 are turned on (here, the fifth transistor T5 is multiplexed as a compensation transistor), and the third transistor T3 is turned on again. The data voltage Vdata is written to the gate of the first transistor T1 via the second transistor T2, the first transistor T1, the fifth transistor T5, and the third transistor T3, achieving threshold compensation for the first transistor T1. At this point, the voltage at point G is Vdata + Vth1, where Vth1 is the threshold voltage of the first transistor T1.

[0093] In the first light-emitting sub-stage t4, the first scan signal S1 is at a high level, the second scan signal S2 is at a low level, the third scan signal S3 is at a low level, the fourth scan signal S4 is at a high level, and the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are both at a low level. Therefore, the first light-emitting control module 161 and the second light-emitting control module 162 are turned on, and the first transistor T1 drives the light-emitting diode D1 to emit light.

[0094] In the hold frame, the second scanning signal S2 and the third scanning signal S3 maintain a low level, and the fourth transistor T4 and the fifth transistor T5 are turned off:

[0095] In the light emitting reset phase t5 , the first light emitting control signal EM1 and the second light emitting control signal EM2 jump to a high level, the path of the driving current generated by the first transistor T1 is cut off, and the light emitting diode D1 stops emitting light.

[0096] During the reset phase t6 within the first frame, the first scan signal S1 transitions to a low level, turning on the third transistor T3 and then turning it off. Since the third transistor T3 is a P-type transistor, when it is turned off, the first scan signal S1 transitions to an upward level. Due to the coupling effect of the parasitic capacitance of the third transistor T3, the potential at point N1 is coupled up and is higher than the potential at point G (since point N1 is floating at this time, the potential at point N1 is significantly coupled), thereby compensating for the downward pull on the potential at point G caused by the fourth and fifth transistors T4 and T5 when they are turned off.

[0097] In the reset phase t7 within the second frame, the fourth scanning signal S4 switches levels, turning the second transistor T2 on and off, resetting the voltage at point S to the data voltage Vdata, and preventing the fine-tuning of the voltage at point G from affecting the switching characteristics of the first transistor T1.

[0098] In the second light-emitting sub-phase t8 , the first light-emitting control module 161 and the second light-emitting control module 162 are turned on again, and the light-emitting module 150 emits light.

[0099] It should be noted that the first light-emitting sub-stage t4 is a light-emitting stage within the writing frame, and the second light-emitting sub-stage t8 is a light-emitting stage within the maintaining frame, wherein there can be multiple second light-emitting sub-stages t8.

[0100] Optionally, the first voltage regulating module 130 is further configured to be turned on and off at least once after the data writing phase t3 of the writing frame to fine-tune the voltage of the control terminal of the driving module 110. For example, Figure 7 The drive timing waveform diagram of the writing frame corresponding to another pixel circuit provided in the embodiment of the present invention is also applicable to Figure 4 The pixel circuit shown. Figure 5 The difference between the drive timing shown is that Figure 7 The timing of the writing frame shown further includes a voltage adjustment phase t3 ′ during the data writing phase t3 .

[0101] During voltage regulation phase t3', the first and fourth scan signals S1 and S4 switch levels, causing the third transistor T3 to turn on and off at least once, and then turning the second transistor T2 on and off at least once. After data is written to the gate of the first transistor T1, the fifth and fourth transistors T5 and T4 remain off, leaving point N1 floating. The rising edge of the first scan signal S1 drives the potential at point N1 to rise above the potential at point G, causing current to leak from point N1 to point G. This fine-tunes the voltage at point G to compensate for the effect of the falling edge of the third scan signal S3 on the potential at point G.

[0102] The technical solution provided in this embodiment comprises a first voltage regulating module 130, wherein the first voltage regulating module 130 includes a P-type third transistor T3. By configuring a first scanning signal S1, the third transistor T3 is turned on and off at least once after the data of the write frame is written, thereby fine-tuning the voltage at the control terminal of the driver module 110. Furthermore, the third transistor T3 is turned on and off at least once before the light-emitting phase of the hold frame, thereby continuing to fine-tune the voltage at the control terminal of the driver module 110. Therefore, during this process, the potential at the control terminal of the driver module 110 gradually rises, and the driving current generated thereby gradually decreases, thereby reducing the brightness of the light-emitting module 150 and avoiding the problem of low-grayscale bright spots during the display process.

[0103] On the basis of the above technical solutions, since the third transistor T3 is a P-type LTPS transistor with a large leakage current, the first scanning signal S1 is set to a high-frequency signal so that the third transistor T3 can be turned on or off quickly, thereby making the fluctuation frequency of the G point voltage high frequency, thereby eliminating the low-frequency flicker phenomenon.

[0104] Optionally, the pixel circuit provided in this embodiment may further implement a subthreshold compensation function of the first transistor T1 . Figure 8 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention, Figure 9 A schematic diagram of another pixel circuit according to an embodiment of the present invention is provided. Figure 8 and Figure 9 In addition to the above technical solutions, the pixel circuit further includes a leakage suppression module 180, which is connected between the first voltage regulation module 130 and the first initialization unit 141 and is configured to cut off the leakage path at the second end of the driver module 110 at least during a write frame. The leakage suppression module 180 includes a sixth transistor T6.

[0105] Specifically, the voltage at the second electrode of the first transistor T1 (i.e., the voltage at point D) is positively correlated with the subthreshold swing (SS) of the first transistor T1. The larger the subthreshold swing of the first transistor T1, the brighter the display brightness at low grayscales, resulting in poor uniformity in low grayscale display. After data writing is completed, the voltage adjustment subunit 142 is turned on again, causing point D to charge toward point G, thereby fine-tuning the voltage at point G. The increase in the voltage at point G reduces the current generated by the first transistor T1, thereby reducing the subthreshold swing of the first transistor T1. This effectively compensates for the subthreshold swing of the first transistor T1, which helps reduce bright spots at low grayscales and improves display uniformity at low grayscales.

[0106] In this embodiment, by adding the sixth transistor T6, the voltage at point D will not leak through the first initialization unit 141 when the voltage regulating subunit 142 is turned on again after data writing is completed, that is, the leakage path from point D to the first initialization voltage Vref1 is cut off.

[0107] Specifically, Figure 10 Another driving timing waveform diagram of a pixel circuit corresponding to a writing frame provided in an embodiment of the present invention can be used to drive Figure 9 The pixel circuit shown. Figure 9 The working processes of the preprocessing stage t1, the initialization stage t2 and the data writing stage t3 are the same as those of the above technical solution and will not be repeated here.

[0108] In the subthreshold compensation stage t02, the first scan signal S1 is at a low level, the second scan signal S2 is at a low level, the third scan signal S3 is at a high level, the fourth scan signal S4 is at a high level, and the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are both at a high level. Therefore, the third transistor T3, the fifth transistor T5 and the sixth transistor T6 are turned on, and the voltage at point D is charged to point G through the fifth transistor T5 and the third transistor T3, thereby increasing the voltage at point G.

[0109] Phases t01 and t02 are both transition states. During phase t01, the second scan signal S2 is at a high level, turning on the fourth transistor T4. This causes point N1 to leak current to the first initialization voltage Vref1. In this embodiment, a sixth transistor T6 is added, which is turned off during the on-state period of the fourth transistor T4. This cuts off the leakage path at point N1, allowing point N1 to charge only point G, thus enabling the pixel circuit to operate normally.

[0110] The technical solution provided in this embodiment enables the second scan signal S2 and the third scan signal S3 to realize double pulses by adding the sixth transistor T6, so that the pixel circuit can compensate for the subthreshold swing of the first transistor T1 to improve the uniformity of low grayscale display.

[0111] Figure 11 A schematic diagram of another pixel circuit according to an embodiment of the present invention is provided. Figure 11 On the basis of the above technical solutions, optionally, the second voltage regulation module 140 further includes a second initialization unit 143, the initialization voltage Vref further includes a second initialization voltage Vref2, and the second initialization unit 143 is connected to the first end of the light-emitting module 150 for transmitting the second initialization voltage Vref2 to the first end of the light-emitting module 150.

[0112] The second initialization unit 143 can be turned on during the initialization phase in response to the fifth scan signal S5 to initialize the potential of the first terminal of the light-emitting module 150. In this embodiment, the fifth scan signal S5 can be the same as the first scan signal S1 or the second scan signal S2, as long as the second initialization unit 143 is turned on during the non-light-emitting phase.

[0113] Furthermore, the pixel circuit also includes a storage module 170, a first light-emitting control module 161 and a second light-emitting control module 162, the first end of the storage module 170 is connected to the first power line L1, the second end of the storage module 170 is connected to the control end of the driving module 110, the first end of the first light-emitting control module 161 is connected to the first power line L1, the second end of the first light-emitting control module 161 is connected to the first end of the driving module 110, the first end of the second light-emitting control module 162 is connected to the second end of the driving module 110, the second end of the second light-emitting control module 162 is connected to the first end of the light-emitting module 150, and the second end of the light-emitting module 150 is connected to the second power line L2.

[0114] Figure 12 A schematic diagram of another pixel circuit according to an embodiment of the present invention is provided. Figure 11 The specific structure of the pixel circuit shown is shown. The second initialization unit 143 includes a seventh transistor T7, the first light-emission control module 161 includes an eighth transistor T8, the second light-emission control module 162 includes a ninth transistor T9, the storage module 170 includes a storage capacitor Cst, and the light-emitting module 150 includes a light-emitting diode D1. A first electrode of the seventh transistor T7 is connected to the second initialization voltage Vref2, a second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting diode D1, and a gate of the seventh transistor T7 is connected to the fifth scan signal S5. A first electrode of the eighth transistor T8 is connected to the first power line L1, a second electrode of the eighth transistor T8 is connected to the first terminal of the driving module 110, a gate of the eighth transistor T8 is connected to the first light-emission control signal EM1, a gate of the ninth transistor T9 is connected to the second light-emission control signal EM2, a first electrode of the ninth transistor T9 is connected to the second terminal of the driving module 110, a second electrode of the ninth transistor T9 is connected to the first electrode of the light-emitting diode D1, and a second electrode of the light-emitting diode D1 is connected to the second power line L2. Here, the first light-emission control signal EM1 and the second light-emission control signal EM2 can be the same. The specific working process of the pixel circuit can refer to the relevant description in the above technical solution and will not be repeated here.

[0115] In this embodiment, the first scan signal S1, the third scan signal S3, and the fourth scan signal S4 can be high-frequency signals generated by the same scanning circuit group, the second scan signal S2 and the third scan signal S3 can be low-frequency signals generated by the same scanning circuit group, and the first light-emission control signal EM1 and the second light-emission control signal EM2 are high-frequency signals generated by the same scanning circuit group. For example, the frequencies of the first scan signal S1, the third scan signal S3, the fourth scan signal S4, the first light-emission control signal EM1, and the second light-emission control signal EM2 are all scan signals with a frequency higher than the frame rate, while the frequencies of the second scan signal S2 and the third scan signal S3 are scan signals synchronized with the frame rate. For example, when the frame rate is 1 Hz, the frequencies of the second scan signal S2 and the third scan signal S3 are also 1 Hz. Other high-frequency signals can be 120 Hz or 60 Hz, etc., which can cause transistors corresponding to the high-frequency signals to quickly turn on and off, thereby eliminating the flickering effect seen by the human eye when displaying images.

[0116] In this embodiment, the first initialization unit 141 and the second initialization unit 143 can be connected to the same initialization voltage (eg, both are connected to the first initialization voltage Vref1 ), which is beneficial to reducing the number of signal lines and improving PPI.

[0117] Figure 13 A schematic diagram of another pixel circuit according to an embodiment of the present invention is provided. Figure 13 As another optional implementation provided by the embodiment of the present invention, the second voltage regulating module 140 may only include a first initialization unit 141 and a voltage regulating subunit 142. Specifically, a first terminal of the data writing module 120 is connected to the data voltage Vdata, a second terminal of the data writing module 120 is connected to the first terminal of the driving module 110, a first terminal of the voltage regulating subunit 142 is connected to the second terminal of the driving module 110, a second terminal of the voltage regulating subunit 142 is connected to the first terminal of the first voltage regulating module 120, a second terminal of the first voltage regulating module 130 is connected to the control terminal of the driving module 110, a first terminal of the first initialization unit 141 is connected to the initialization voltage Vref, and a second terminal of the first initialization unit 141 is connected to the first terminal of the light-emitting module 150.

[0118] Figure 14 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention shows Figure 13 The specific structure of the pixel circuit shown in FIG. Figure 15 A driving timing waveform diagram of a write frame corresponding to another pixel circuit provided in an embodiment of the present invention is applicable to Figure 13 and Figure 14 The pixel circuit shown.

[0119] In the write frame:

[0120] During initialization phase t2, the first scan signal S1 and the second scan signal S2 switch from a high level to a low level, the fourth scan signal S4 is at a high level, the first emission control signal EM1 is at a high level, and the second emission control signal EM2 is at a low level. Consequently, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the ninth transistor T9 are turned on. The fourth transistor T4 transmits the initialization voltage Vref to the gate of the first transistor T1 via the ninth transistor T9 and the fifth transistor T5, thereby resetting the second electrode and the gate of the first transistor T1. During this process, the first transistor T1 is turned on, and the potential of the first electrode of the first transistor T1 is also reset.

[0121] During data writing phase t3, the first scan signal S1 is at a low level, the second scan signal S2 is at a low level, the fourth scan signal S4 is at a low level, and the first and second emission control signals EM1 and EM2 are both at a high level. Therefore, the second transistor T2 and the fifth transistor T5 are turned on, and the third transistor T3 is turned on again. The data voltage Vdata is written to the gate of the first transistor T1 via the second transistor T2, the first transistor T1, the fifth transistor T5, and the third transistor T3, achieving threshold compensation for the first transistor T1. The storage capacitor Cst stores the voltage at point G. This voltage at point G is Vdata + Vth1, where Vth1 is the threshold voltage of the first transistor T1.

[0122] During voltage regulation phase t3', the first, second, and fourth scan signals S1, S2, and S4 all switch to a high level. The first emission control signal EM1 remains high, and the fifth transistor T5 remains on. Therefore, point D slowly charges toward point N1. The greater the subthreshold swing of the first transistor T1, the higher the voltage at point D, and consequently, the higher the voltage at point N1.

[0123] During the subthreshold compensation phase t02, the fourth scan signal S4 remains low, and the second transistor T2 is turned off. The first light-emission control signal EM1 changes to a low level, and the fifth transistor T5 is turned off. When the low-level pulse of the first scan signal S1 arrives, the third transistor T3 turns on, connecting points N1 and G. The potential at point G is raised (the potential at point N1 is higher than the potential at point G). The higher the voltage at point N1, the greater the magnitude of the increase in the potential at point G. By raising the voltage at point G, the drive current of the first transistor T1 is reduced, thereby lowering the voltage at point D, compensating for the uneven grayscale display caused by the increased subthreshold swing of the first transistor T1.

[0124] Furthermore, since the third transistor T3 is a P-type LTPS transistor, the first scanning signal S1 jumps when it is turned off, so that the potential of point N1 is higher than the potential of point G. Point N1 charges point G through the third transistor T3, fine-tunes the voltage of point G, and increases the voltage of point G, compensating for the impact of the fifth transistor T5 being turned off on the voltage of point G, and preventing the occurrence of low grayscale bright spots.

[0125] In the first light-emitting sub-phase t4 , the second light-emitting control signal EM2 jumps to a low level, the discharge path of the driving current generated by the first driving transistor T1 is turned on, and the light-emitting diode D1 emits light.

[0126] In the holding frame, the working process of the pixel circuit is similar to the working process of the above technical solutions, and the third transistor T3 is turned on and off at least once again to fine-tune the voltage at point G.

[0127] Optionally, an embodiment of the present invention further provides a method for driving a pixel circuit, which can be used to drive the pixel circuit provided by any embodiment of the present invention. Figure 16 A flowchart of a driving method for a pixel circuit provided by an embodiment of the invention, combined with Figure 2 and Figure 16 , the driving method of the pixel circuit provided in this embodiment includes:

[0128] In the write frame:

[0129] S110 , in the initialization phase, controlling the second voltage regulating module to transmit the initialization voltage to the first voltage regulating module, and then transmitting the initialization voltage to the control end of the driving module by the first voltage regulating module.

[0130] S120 , in the data writing phase, controlling the data writing module to transmit the data voltage to the control terminal of the driving module.

[0131] S130 , in the light emitting stage, controlling the driving module to drive the light emitting module to emit light according to the data voltage.

[0132] In the hold frame:

[0133] S140 , controlling the first voltage regulating module to be turned on and off at least once to regulate the voltage of the control terminal of the driving module.

[0134] The technical solution provided by the embodiments of the present invention, by providing a first voltage regulating module and a second voltage regulating module, implements data writing and light emission in the pixel circuit during the write frame, and implements an intra-frame reset of the potential at the control terminal of the driver module during the hold frame. Specifically, after the write frame ends and the hold frame begins, the first voltage regulating module is turned on and then off, causing the potential at point N1 to increase due to the self-coupling effect of the first voltage regulating module, thereby fine-tuning the potential at the control terminal of the driver module (point G potential). This, in turn, compensates for the effect of leakage on the potential at the control terminal of the driver module, helps stabilize the potential at the control terminal of the driver module, and prevents the occurrence of bright spots, particularly those found in low grayscale displays.

[0135] Optionally, combined Figure 8 The pixel circuit further includes a leakage suppression module 180 , which is connected between the first voltage regulation module 130 and the first initialization unit 141 .

[0136] Step S110 specifically includes:

[0137] During the initialization stage, the first initialization unit is controlled to be turned on in response to the first pulse of the second scanning signal, and the first initialization voltage is transmitted to the first voltage regulation module, which is then transmitted to the control end of the driving module by the first voltage regulation module; and the voltage regulation subunit is controlled to be turned on in response to the first pulse of the third scanning signal, and the first initialization voltage is transmitted from the voltage regulation subunit to the second end of the driving module.

[0138] Step S120 specifically includes:

[0139] In the data writing phase, the data writing module is controlled to transmit the data voltage to the control end of the driving module via the voltage regulating subunit and the first voltage regulating module.

[0140] Before the light emitting stage and after the data writing stage, the driving method further includes:

[0141] In the subthreshold compensation stage, the control voltage regulating subunit is turned on in response to the second pulse of the third scanning signal, and transmits the voltage of the second end of the driving module to the control end of the driving module via the first voltage regulating module.

[0142] The specific working principle of the driving method of the pixel circuit provided in this embodiment can refer to the relevant description of the pixel circuit in any of the above embodiments. The driving method also has the beneficial effects described in any of the above embodiments.

[0143] Optionally, an embodiment of the present invention further provides a display panel, comprising the pixel circuit provided by the above embodiment, so the display panel also has the beneficial effects described in any of the above embodiments. Figure 17A structural schematic diagram of a display panel provided in an embodiment of the present invention. In this embodiment, the display panel can be applied to mobile phones, and can also be applied to any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc. The embodiment of the present invention does not specifically limit this.

[0144] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0145] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A pixel circuit, characterized in that: include: A driving module, a data writing module, a first voltage regulating module, a second voltage regulating module, a leakage suppression module and a light emitting module; The first voltage regulating module is connected between the control terminal of the driving module and the second voltage regulating module, the driving module and the light-emitting module are connected between a first power line and a second power line, and the driving module is used to drive the light-emitting module to emit light during a display cycle; wherein a display cycle includes a writing frame and a holding frame; In the write frame, the second voltage regulating module is used to transmit the initialization voltage to the first voltage regulating module in the initialization phase, and then the first voltage regulating module transmits the initialization voltage to the control end of the driving module. The data writing module is used to transmit the data voltage to the control end of the driving module in the data writing phase. In the holding frame, the first voltage regulating module is turned on and off at least once to regulate the voltage of the control terminal of the driving module; The leakage suppression module is connected between the first voltage regulating module and the second voltage regulating module, and is configured to cut off the leakage path of the second end of the driving module at least during the writing frame.

2. The pixel circuit according to claim 1, wherein: The second voltage regulating module includes a first initialization unit and a voltage regulating subunit, and the initialization voltage includes a first initialization voltage; A first end of the data writing module is connected to the data voltage, a second end of the data writing module is connected to the first end of the driving module, a first end of the voltage regulating subunit is connected to the second end of the driving module, a second end of the voltage regulating subunit is connected to the first end of the first voltage regulating module, a second end of the first voltage regulating module is connected to the control end of the driving module, a first end of the first initialization unit is connected to the first initialization voltage, and a second end of the first initialization unit is connected to the first end of the first voltage regulating module; In the write frame, the first initialization unit is used to transmit the first initialization voltage to the control end of the driving module through the first voltage regulation module that is turned on, and to the second end of the driving module through the voltage regulation subunit that is turned on; the data writing module is used to transmit the data voltage to the control end of the driving module through the voltage regulation subunit that is turned on and the first voltage regulation module during the data writing phase.

3. The pixel circuit according to claim 2, wherein: The leakage suppression module is connected between the first voltage regulation module and the first initialization unit.

4. The pixel circuit according to claim 3, wherein: The control end of the first voltage regulating module and the control end of the leakage suppression module are both connected to a first scanning signal, the control end of the first initialization unit is connected to a second scanning signal, and the control end of the voltage regulating subunit is connected to a third scanning signal; wherein the second scanning signal and the third scanning signal are double pulse signals; In the write frame, the voltage regulating subunit is configured to transmit the data voltage to the control terminal of the driving module via the first voltage regulating module in response to the first pulse of the third scanning signal during the data write phase, and transmit the voltage of the second terminal of the driving module to the control terminal of the driving module via the first voltage regulating module in response to the second pulse of the third scanning signal during the subthreshold compensation phase; When the first voltage regulating module and the leakage suppression module are turned on in response to the first scanning signal, the first initialization unit is turned off in response to the second scanning signal.

5. The pixel circuit according to claim 3, wherein: The driving module includes a first transistor, the data writing module includes a second transistor, the first voltage regulating module includes a third transistor, the first initialization unit includes a fourth transistor, the voltage regulating sub-unit includes a fifth transistor, and the leakage suppression module includes a sixth transistor; The gate of the second transistor is connected to the fourth scan signal, the first electrode of the second transistor is connected to the data voltage, the second electrode of the second transistor is connected to the first electrode of the first transistor, the first electrode of the fifth transistor is connected to the second electrode of the first transistor, the second electrode of the fifth transistor is connected to the first electrode of the third transistor, the second electrode of the third transistor is connected to the gate of the first transistor, the gate of the fifth transistor is connected to the third scan signal, and the gate of the third transistor is connected to the first scan signal; the first electrode of the fourth transistor is connected to the first initialization voltage, the second electrode of the fourth transistor is connected to the first electrode of the sixth transistor, the second electrode of the sixth transistor is connected to the first electrode of the third transistor, the gate of the fourth transistor is connected to the second scan signal, and the gate of the sixth transistor is connected to the first scan signal.

6. The pixel circuit according to claim 5, wherein: A channel type of the third transistor is different from a channel type of the fifth transistor.

7. The pixel circuit according to claim 6, wherein: The fifth transistor is a metal oxide transistor.

8. The pixel circuit according to claim 2, wherein: The second voltage regulating module further includes a second initialization unit, the initialization voltage further includes a second initialization voltage, and the second initialization unit is connected to the first end of the light emitting module for transmitting the second initialization voltage to the first end of the light emitting module.

9. The pixel circuit according to claim 8, wherein: The pixel circuit further includes a storage module, a first light control module, and a second light control module, wherein a first end of the storage module is connected to the first power line, a second end of the storage module is connected to the control end of the driving module, a first end of the first light control module is connected to the first power line, a second end of the first light control module is connected to the first end of the driving module, a first end of the second light control module is connected to the second end of the driving module, a second end of the second light control module is connected to the first end of the light-emitting module, and a second end of the light-emitting module is connected to the second power line; The second initialization unit includes a seventh transistor, the first light emitting control module includes an eighth transistor, the second light emitting control module includes a ninth transistor, the storage module includes a storage capacitor, and the light emitting module includes a light emitting diode; The first electrode of the seventh transistor is connected to the second initialization voltage, the second electrode of the seventh transistor is connected to the first electrode of the light-emitting diode, the gate of the seventh transistor is connected to the fifth scanning signal, the first electrode of the eighth transistor is connected to the first power line, the second electrode of the eighth transistor is connected to the first end of the driving module, the gate of the eighth transistor is connected to the first light-emitting control signal, the gate of the ninth transistor is connected to the second light-emitting control signal, the first electrode of the ninth transistor is connected to the second end of the driving module, the second electrode of the ninth transistor is connected to the first electrode of the light-emitting diode, and the second electrode of the light-emitting diode is connected to the second power line.

10. The pixel circuit according to claim 9, wherein: The first initialization voltage is multiplexed into the second initialization voltage, and the first light-emitting control signal is multiplexed into the second light-emitting control signal.

11. The pixel circuit according to claim 1, wherein: The second voltage regulation module includes a first initialization unit and a voltage regulation subunit; The first end of the data writing module is connected to the data voltage, the second end of the data writing module is connected to the first end of the driving module, the first end of the voltage regulating subunit is connected to the second end of the driving module, the second end of the voltage regulating subunit is connected to the first end of the first voltage regulating module, the second end of the first voltage regulating module is connected to the control end of the driving module, the first end of the first initialization unit is connected to the initialization voltage, and the second end of the first initialization unit is connected to the first end of the light-emitting module; In the write frame, the first initialization unit is used to transmit the initialization voltage to the control end of the driving module via the turned-on first voltage regulation module and the voltage regulation sub-unit in the initialization phase; The data writing module is used for transmitting the data voltage to the control end of the driving module via the turned-on voltage regulating subunit and the first voltage regulating module during the data writing phase; The pixel circuit also includes a first light-emitting control module, a second light-emitting control module and a storage module, wherein a first end of the storage module is connected to the first power line, a second end of the storage module is connected to the control end of the driving module, a first end of the first light-emitting control module is connected to the first power line, a second end of the first light-emitting control module is connected to the first end of the driving module, a first end of the second light-emitting control module is connected to the second end of the driving module, a second end of the second light-emitting control module is connected to the first end of the light-emitting module, and a second end of the light-emitting module is connected to the second power line.

12. A method for driving a pixel circuit, characterized in that: The pixel circuit includes a driving module, a data writing module, a first voltage regulating module, a second voltage regulating module, a leakage suppression module, and a light-emitting module, wherein the first voltage regulating module is connected between the control terminal of the driving module and the second voltage regulating module, the leakage suppression module is connected between the first voltage regulating module and the second voltage regulating module, the driving module and the light-emitting module are connected between a first power line and a second power line, and the driving module is used to drive the light-emitting module to emit light within a display cycle; wherein a display cycle includes a writing frame and a holding frame; In the write frame: In the initialization phase, the second voltage regulating module is controlled to transmit the initialization voltage to the first voltage regulating module, and then the first voltage regulating module transmits the initialization voltage to the control end of the driving module; In the data writing phase, controlling the data writing module to transmit the data voltage to the control terminal of the driving module; In the light-emitting stage, controlling the driving module to drive the light-emitting module to emit light according to the data voltage; In the hold frame: Controlling the first voltage regulating module to be turned on and off at least once to regulate the voltage of the control terminal of the driving module; The driving method of the pixel circuit further includes: The leakage suppression module is controlled to cut off the leakage path of the second end of the driving module at least in the writing frame.

13. The driving method of the pixel circuit according to claim 12, wherein: The second voltage regulation module includes a first initialization unit and a voltage regulation subunit; the leakage suppression module is connected between the first voltage regulation module and the first initialization unit, the first end of the data writing module is connected to the data voltage, the second end of the data writing module is connected to the first end of the driving module, the first end of the voltage regulation subunit is connected to the second end of the driving module, the second end of the voltage regulation subunit is connected to the first end of the first voltage regulation module, the second end of the first voltage regulation module is connected to the control end of the driving module, the first end of the first initialization unit is connected to the first initialization voltage, and the second end of the first initialization unit is connected to the first end of the first voltage regulation module; wherein, the control end of the first voltage regulation module and the control end of the leakage suppression module are both connected to the first scanning signal, the control end of the first initialization unit is connected to the second scanning signal, and the control end of the voltage regulation subunit is connected to the third scanning signal; The driving method of the pixel circuit includes: In the write frame: In the initialization phase, the first initialization unit is controlled to be turned on in response to a first pulse of the second scanning signal, and the first initialization voltage is transmitted to the control terminal of the driving module via the turned-on first voltage regulating module; and the voltage regulating subunit is controlled to be turned on in response to a first pulse of the third scanning signal, and the first initialization voltage is transmitted to the second terminal of the driving module via the voltage regulating subunit. In the data writing phase, controlling the data writing module to transmit the data voltage to the control end of the driving module via the voltage regulating subunit and the first voltage regulating module; In the subthreshold compensation stage, the voltage regulating subunit is controlled to be turned on in response to the second pulse of the third scanning signal, and the voltage of the second end of the driving module is transmitted to the control end of the driving module via the first voltage regulating module.

14. A display panel, characterized in that: The method comprises the pixel circuit according to any one of claims 1 to 11.

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