A memory operation method, a memory and a storage system

Abstract

Embodiments of the present application provide a memory operation method, a memory and a storage system. The operation method comprises: obtaining at least one set of read voltages; each set of read voltages comprises an initial voltage value and an offset voltage value with a certain offset amount relative to the initial voltage value; the initial voltage value in each set of read voltages is a preset read voltage for distinguishing two adjacent storage states of a memory cell of the memory; performing a read operation based on the initial voltage value and the offset voltage value in each set of read voltages respectively, obtaining the number of memory cells whose read results corresponding to each voltage value satisfy a set condition; determining the difference between the two numbers corresponding to each two adjacent voltage values belonging to the same set of read voltages; and determining the optimal read voltage for distinguishing the two adjacent storage states based on the difference.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory, and in particular to a memory operation method, a memory and a storage system. BACKGROUND

[0002] Recently, with the development of memory, the memory can be volatile or non-volatile. The non-volatile memory can keep data even in the case of no power supply, and has been widely used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices, especially 3D NAND flash applications. The 3D NAND flash realizes the function of data storage by capturing and storing electric charges in the gate dielectric layer of the storage unit contained therein. However, with the increase of storage time, the electric charges of the gate dielectric layer of the storage unit will slowly leak; and when repeatedly reading the storage unit, the electric charges of the gate dielectric layer of the storage unit will be captured, similar to programming. In any case, the change of the electric charges of the gate dielectric layer of the storage unit will cause the change of the threshold voltage of the storage unit, thereby affecting the correctness of reading the data stored in the storage unit. SUMMARY

[0003] Therefore, the present application provides a memory operation method, a memory and a storage system to solve the above technical problems.

[0004] To achieve the above object, the technical scheme of the present application is as follows:

[0005] In a first aspect, the present application provides a memory operation method, comprising:

[0006] obtaining at least one group of read voltages; each group of read voltages in the at least one group of read voltages comprises an initial voltage value and an offset voltage value having a certain offset amount relative to the initial voltage value; the initial voltage value in each group of read voltages is a preset read voltage used to distinguish two adjacent storage states of the storage unit of the memory;

[0007] performing a read operation based on the initial voltage value and the offset voltage value in each group of read voltages respectively, to obtain the number of storage units whose read results corresponding to each voltage value satisfy a set condition;

[0008] determining the difference between the two numbers corresponding to each two adjacent voltage values belonging to the same group of read voltages;

[0009] determining the optimal read voltage used to distinguish the two adjacent storage states based on the difference.

[0010] In a second aspect, the present application also provides a memory, comprising: a storage array, the storage array comprising a storage unit;

[0011] and a peripheral circuit coupled with the memory array and configured to control the memory array;

[0012] The peripheral circuit is configured to perform the operation method.

[0013] In a third aspect, the embodiments of the present application further provide a storage system, comprising: one or more memories as described above; and a memory controller coupled with the memories; the memory controller is configured to send a first command to the memories; the memories are configured to perform the operation method in response to the first command.

[0014] In a fourth aspect, the embodiments of the present application further provide a storage system, comprising: one or more memories; and a memory controller coupled with the memories; wherein,

[0015] The memory controller is configured to obtain at least one set of read voltages; each set of read voltages in the at least one set of read voltages comprises an initial voltage value and an offset voltage value having a certain offset amount relative to the initial voltage value; the initial voltage value in each set of read voltages is a preset read voltage used to distinguish two adjacent storage states of a storage cell of the memories; and the memory controller is configured to send a corresponding read command to a storage surface contained in the memories based on the initial voltage value and the offset voltage value in the at least one set of read voltages respectively.

[0016] The memories are configured to read the corresponding storage surface in response to the corresponding read command, and send a read result of each storage cell in the storage surface to the memory controller.

[0017] The memory controller is further configured to receive the read result, count a number of storage cells whose read result meets a set condition corresponding to each voltage value, determine a difference between two numbers corresponding to two adjacent voltage values belonging to the same set of read voltages, and determine an optimal read voltage used to distinguish the two adjacent storage states based on the difference.

[0018] In a fifth aspect, the embodiments of the present application further provide a storage system, comprising: one or more memories; and a memory controller coupled with the memories; wherein,

[0019] The memory controller is configured to: obtain at least one set of read voltages; each set of read voltages in the at least one set of read voltages comprises an initial voltage value and an offset voltage value having a certain offset amount relative to the initial voltage value; the initial voltage value in each set of read voltages is a preset read voltage for distinguishing two adjacent storage states of a storage cell of the memory; and based on the initial voltage value and the offset voltage value in the at least one set of read voltages, a corresponding read command is sent to a storage surface contained in the memory.

[0020] The memory is configured to: in response to the corresponding read command, read the corresponding storage surface; count the number of storage cells whose read results corresponding to each voltage value meet a set condition; and send the number to the memory controller.

[0021] The memory controller is further configured to: receive the number; determine the difference between two numbers corresponding to each two adjacent voltage values belonging to the same set of read voltages; and based on the difference, determine an optimal read voltage for distinguishing the storage cells of the two adjacent storage states.

[0022] Embodiments of the present application provide a memory operation method, a memory and a storage system. The memory operation method comprises: obtaining at least one set of read voltages; each set of read voltages in the at least one set of read voltages comprises an initial voltage value and an offset voltage value having a certain offset amount relative to the initial voltage value; the initial voltage value in each set of read voltages is a preset read voltage for distinguishing two adjacent storage states of a storage cell of the memory; and based on the initial voltage value and the offset voltage value in the at least one set of read voltages, a read operation is performed to obtain the number of storage cells whose read results corresponding to each voltage value meet a set condition; the difference between two numbers corresponding to each two adjacent voltage values belonging to the same set of read voltages is determined; and based on the difference, an optimal read voltage for distinguishing the two adjacent storage states is determined. The memory operation method provided by embodiments of the present application sets at least one set of read voltages containing multiple voltage values, performs a read operation on the storage cell of the memory using each voltage value to obtain the number of read results meeting a set condition; then, according to the difference between the numbers corresponding to each two adjacent voltage values belonging to the same set of read voltages, the optimal read voltage for distinguishing the two adjacent storage states of the storage cell of the memory corresponding to the set of read voltages is determined based on the difference. The corresponding storage cell of the memory is read using the obtained optimal read voltage, which greatly increases the probability of correctly reading the data stored in the storage cell. BRIEF DESCRIPTION OF DRAWINGS

[0023] The aspects of the application can best be understood from the following detailed description when read with the accompanying drawings. It is emphasized that, according to the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion.

[0024] Figure 1 A block diagram illustrating an example system with memory in the related art;

[0025] Figure 2 A schematic diagram illustrating an example memory card with memory;

[0026] Figure 3 A schematic diagram illustrating an example solid state drive (SSD) with memory;

[0027] Figure 4 A schematic diagram illustrating an example memory including peripheral circuitry;

[0028] Figure 5 A side view illustrating a cross-section of an example memory array including NAND memory strings;

[0029] Figure 6 A block diagram illustrating an example memory including a memory array and peripheral circuitry;

[0030] Figure 7 A flowchart illustrating a method of operating a memory according to embodiments of the application;

[0031] Figure 8 A diagram illustrating a distribution of threshold voltages of any two adjacent memory states of a memory cell according to embodiments of the application;

[0032] Figure 9 A diagram illustrating a relationship of a first set of read voltages according to embodiments of the application;

[0033] Figure 10 A diagram illustrating a number of memory cells of each memory plane satisfying a set condition according to embodiments of the application; Figure 9

[0034] A diagram illustrating a number of memory cells of each memory plane satisfying a set condition according to embodiments of the application; Figure 11 Figure 10 A diagram illustrating a number of memory cells of each memory plane satisfying a set condition according to embodiments of the application;

[0035] Figure 12 A diagram illustrating a number of memory cells of each memory plane satisfying a set condition according to embodiments of the application;

[0036] Figure 13 ​When the at least one group of read voltages provided by the embodiment of the present application is shown to include the first group of read voltages and the second group of read voltages, a kind of relationship schematic diagram that initial voltage value Vrdn1 contained in the first group of read voltages is greater than initial voltage value Vrdn2 contained in the second group of read voltages is shown.

[0037] Figure 14 A flowchart diagram of one kind of operation method provided by the embodiment of the present application is shown.

[0038] Figure 15 A flowchart diagram of another kind of operation method provided by the embodiment of the present application is shown. DETAILED DESCRIPTION

[0039] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present application. These are, of course, merely examples and are not intended to be limiting. For example, the making of first and second features on or adjacent each other described below can include embodiments where the first and second features are formed directly contacting each other, and can also include embodiments where additional features can be formed between the first and second features such that the first and second features can not directly contact each other. Additionally, the present application can repeat references to data and / or alphabets in various examples. Such repetition is for the purpose of simplicity and clarity and does not itself indicate relationships between various embodiments and / or configurations discussed.

[0040] In addition, spatially relative terms such as "beneath", "below", "lower", "above", "upper" and the like can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0041] The technical solutions of the present application are described in detail below with reference to the accompanying drawings.

[0042] Figure 1 A block diagram of an exemplary system having a memory in the related art is shown. In Figure 1In this context, system 100 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. For example... Figure 1 As shown, system 100 may include a host 108 and a storage system 102, wherein the storage system 102 has one or more memories 104 and a memory controller 106; the host 108 may be a processor of an electronic device, such as a central processing unit (CPU) or a system-on-a-chip (SoC), wherein the SoC may be, for example, an application processor (AP). The host 108 may be configured to send data to or receive data from the memory 104. Specifically, the memory 104 may be any memory disclosed in this application, such as phase-change random access memory (PCRAM), three-dimensional NAND flash memory, etc.

[0043] According to some embodiments, a memory controller 106 is coupled to the memory 104 and the host 108. And is configured to control the memory 104. The memory controller 106 can manage data stored in the memory 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed for operation in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices in low duty cycle environments such as personal computers, digital cameras, mobile telephones, etc. In some embodiments, the memory controller 106 is designed for operation in a high duty cycle environment, such as a Solid State Drive (SSD) or an embedded Multi Media Card (eMMC), where the SSD or eMMC is used as a data storage for mobile devices in high duty cycle environments such as smartphones, tablet computers, laptop computers, etc. as well as enterprise storage arrays. The memory controller 106 can be configured to control operations of the memory 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions with respect to data stored in or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to handle Error Correction Codes (ECC) with respect to data read from or written to the memory 104. The memory controller 106 can also perform any other suitable functions, for example, formatting the memory 104. The memory controller 106 can communicate with external devices (e.g., the host 108) according to a particular communication protocol.For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnection (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachmnet (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, etc.

[0044] The memory controller 106 and the one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the storage system 102 can be implemented and packaged into different types of end electronic products. In the case of a memory card 202 as shown in FIG. 2A, the memory controller 106 and the single memory 104 can be integrated into the memory card 202. The memory card can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card can also include a memory card connector 204 that couples the memory card with a host (e.g., the host 108 in FIG. 1). In the case of a solid state drive (SSD) 302 as shown in FIG. 2B, the memory controller 106 and the multiple memories 104 can be integrated into the SSD 302. The SSD can also include an SSD connector 304 that couples the SSD with a host (e.g., the host 108 in FIG. 1). In some embodiments, the storage capacity and / or operating speed of the SSD is greater than that of the memory card. In addition, the memory controller 106 can also be configured to control the erase, read, write operations of the memories 104. Figure 2 Figure 1 Figure 3 Figure 1

[0045] Figure 4 A schematic diagram showing an exemplary memory including a peripheral circuit. In Figure 4 ​​​​As shown, the memory 104 can include a storage array 401 and a peripheral circuit 402 coupled at a periphery of the storage array 401, where the storage array 401 can be a NAND flash storage array in which storage cells 406 are provided in an array of NAND memory strings 408, each NAND memory string 408 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 408 includes a plurality of storage cells 406 coupled in series and stacked vertically. Each storage cell 406 can hold a continuous analog value, e.g., a voltage or charge, that depends on the number of electrons trapped within a storage region of the storage cell 406. Each storage cell 406 can be a floating gate type of storage cell that includes a floating gate transistor, or a charge trap type of storage cell that includes a charge trap transistor.

[0046] In some embodiments, each storage cell 406 is a single level cell (SLC) that has two possible memory states and thus can store one bit of data, e.g., a first memory state "0" can correspond to a first voltage range and a second memory state "1" can correspond to a second voltage range. In some embodiments, each storage cell 406 is a multi level cell (MLC) that has four or more memory states, e.g., an MLC can store two bits per cell, three bits per cell (also referred to as a trinary level cell (TLC)), or four bits per cell (also referred to as a quadruple level cell (QLC)). Note that the memory states referred to herein are also referred to as storage states of the storage cells. Different types of storage cells have different numbers of storage states, e.g., an SLC type of storage cell has two storage states (i.e., two memory states), where the two storage states include one program state and one erase state. As another example, an MLC type of storage cell has four storage states, where the four storage states include one erase state and three program states. As another example, a TLC type of storage cell has eight storage states, where the eight storage states include one erase state and seven program states. In some embodiments, a QLC type of storage cell has sixteen storage states, where the sixteen storage states include one erase state and fifteen program states.

[0047] As Figure 4As shown, each NAND memory string 408 can include a source select gate (SSG) 410 at its source end and a drain select gate (DSG) 412 at its drain end. The SSG 410 and the DSG 412 can be configured to activate a selected NAND memory string 408 (column of the array) during read and program (or write) operations. In some embodiments, the sources of the NAND memory strings 408 in the same block 404 are coupled through the same source line (SL) 414 (e.g., a common SL). In other words, according to some implementations, all NAND memory strings 408 in the same block 404 have an array common source (ACS). According to some implementations, the DSG 412 of each NAND memory string 408 is coupled to a respective bit line 416 from which data can be read and written via an output bus (not shown). In some embodiments, each NAND memory string 408 is configured to be selected or deselected by applying a select voltage (e.g., higher than a threshold voltage of a transistor having the DSG 412) or a deselect voltage (e.g., 0 volts (V)) to the respective DSG 412 via one or more DSG lines 413 and / or a select voltage (e.g., higher than a threshold voltage of a transistor having the SSG 410) or a deselect voltage (e.g., 0 V) to the respective SSG 410 via one or more SSG lines 415.

[0048] As Figure 4As shown, NAND memory strings 408 can be organized into multiple blocks 404, each of which can have a common source line 414 (e.g., coupled to ground). In some embodiments, each block 404 is a basic data unit with an erase operation, i.e., all memory cells 406 on the same block 404 are erased simultaneously. To erase memory cells 406 in a selected block 404, a source line 414 biased to the selected block 404 and unselected blocks 404 on the same plane as the selected block 404 can be used. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of blocks. Memory cells 406 of adjacent NAND memory strings 408 can be coupled via word lines 418, which select which row of memory cells 406 receives read and program operations. In some embodiments, memory cells 406 coupled to the same word line 418 are referred to as (physical) pages 420. A page 420 is a basic unit of data used for programming or reading operations, and the size of a page 420, measured in bits, can be related to the number of NAND memory strings 408 coupled by word lines 418 in a block 404. Each word line 418 may include multiple control gates (gate electrodes) at each memory cell 406 within the corresponding page 420, as well as gate lines coupling the control gates.

[0049] Figure 5 A side view of a cross-section of an exemplary memory array 401 including NAND memory cell strings 408 according to some aspects of this application is shown. Figure 5 As shown, the NAND memory cell string 408 can extend vertically through the memory stack layer 502 above the substrate 501. The substrate 501 can include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0050] The memory stack 502 can include alternating gate conductive layers 503 and gate-to-gate dielectric layers 504. The number of pairs of gate conductive layers 503 and gate-to-gate dielectric layers 504 in the memory stack 502 can determine the number of memory cells 406 in the memory array 401. The gate conductive layers 503 can include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate conductive layer 503 includes a metal layer, e.g., a tungsten layer. In some embodiments, each gate conductive layer 503 includes a doped polysilicon layer. Each gate conductive layer 503 can include a control gate that surrounds a memory cell 406 and can extend laterally at a top of the memory stack 502 as a DSG line 413, at a bottom of the memory stack 502 as a SSG line 415, or between the DSG line 413 and the SSG line 415 as a word line 418.

[0051] As shown in Figure 5 The NAND cell string 408 includes a channel structure 505 that extends vertically through the memory stack 502. In some embodiments, the channel structure 505 includes a channel hole filled with semiconductor material(s) and dielectric material(s). In some embodiments, the semiconductor channel includes silicon, e.g., polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a “charge-trapping / storage layer”), and a blocking layer. The channel structure 505 can have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the blocking layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film can include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0052] Referring back to Figure 4The peripheral circuitry 402 can be coupled to the memory array 401 through the bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413. The peripheral circuitry 402 can include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of the memory array 401 by applying voltage signals and / or current signals to and sensing voltage signals and / or current signals from each target memory cell 406 via the bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413. The peripheral circuitry 402 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 Some example peripheral circuitry is shown, the peripheral circuitry 402 includes a page buffer / sense amplifier 604, a column decoder / bit line driver 606, a row decoder / word line driver 608, a voltage generator 610, control logic 612, registers 614, an interface 616, and a data bus 618. It will be appreciated that additional peripheral circuitry not shown in FIG. 6 can also be included in some examples. Figure 7

[0053] The page buffer / sense amplifier 604 can be configured to read data from and program (write) data to the memory array 401 according to control signals from the control logic 612. In one example, the page buffer / sense amplifier 604 can store a page of program data (write data) to be programmed into one page 420 of the memory array 401. In another example, the page buffer / sense amplifier 604 can perform a program verify operation to ensure that data has been correctly programmed into the memory cells 406 coupled to a selected word line 418. In yet another example, the page buffer / sense amplifier 604 can also sense low-power signals from the bit lines 416 representing data bits stored in the memory cells 406 and amplify small voltage swings to identifiable logic levels in read operations. The column decoder / bit line driver 606 can be configured to be controlled by the control logic 612 and select one or more NAND memory strings 408 by applying bit line voltages generated from the voltage generator 610.

[0054] ​Row decoders / word line drivers 608 can be configured to be controlled by control logic 612 and to select / deselect blocks 404 of memory array 401 and to select / deselect word lines 418 of blocks 404. Row decoders / word line drivers 608 can also be configured to drive word lines 418 using word line voltages generated from voltage generator 610. In some embodiments, row decoders / word line drivers 608 can also select / deselect and drive SSG lines 415 and DSG lines 413. As described in detail below, row decoders / word line drivers 608 are configured to perform erase operations on memory cells 406 coupled to selected word line(s) 418. Voltage generator 610 can be configured to be controlled by control logic 612 and to generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to memory array 401.

[0055] Control logic 612 can be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. Registers 614 can be coupled to control logic 612 and include status registers, command registers, and address registers to store status information, command operation codes (OP codes), and command addresses for controlling the operation of each of the peripheral circuits. Interface 616 can be coupled to control logic 612 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to control logic 612, and to buffer status information received from control logic 612 and relay them to the host. Interface 616 can also be coupled to column decoders / bit line drivers 606 via data bus 618 and act as a data I / O interface and data buffer to buffer data and relay them to or from memory array 401.

[0056] Based on the above-described storage system and memory, the charge stored in the memory cells changes over time, repeated read operations, etc., and thus affects the correctness of data reading. A set of offset voltages that can correctly read data can be found by repeatedly trying to add offset voltages from a preset read voltage offset table to an initial voltage value. After a long time of storage, the data in the memory block of the memory has different threshold voltage offsets in the memory cells in each memory page. Then, a large amount of data needs to be read repeatedly by polling the preset read voltage offset table, and the operations of hardware decoding and software decoding are superimposed, which consumes a long time. Such a reading process obviously affects the performance of the memory, especially for enterprise-level applications, which can cause the quality of service (QoS) to be unable to meet the standard.

[0057] To address the aforementioned technical problems, embodiments of this application provide a method for operating a memory, as detailed below. Figure 7 As shown, the operation method may include:

[0058] S701: Obtain at least one set of read voltages; each set of read voltages includes an initial voltage value and an offset voltage value with a certain offset relative to the initial voltage value; the initial voltage value in each set of read voltages is a preset read voltage used to distinguish two adjacent storage states of the memory cell.

[0059] It should be noted that the memory operation method provided in this application is a method for determining the optimal read voltage. Here, the memory cell can be of type SLC, MLC, TLC, QLC, etc. The two adjacent memory states can refer to any two adjacent memory states of any type of memory cell. That is to say, the operation method provided in this application is applicable to determining the optimal read voltage for any two adjacent memory states.

[0060] For how to distinguish between two adjacent storage states of a storage unit, see [example]. Figure 8 As shown, it illustrates the threshold voltage distribution corresponding to any two adjacent storage states of a memory cell. Figure 8 In the diagram, the regions f1 and f2 enclosed by dashed lines represent the threshold voltage distributions of memory cells in storage states P1 and P2 before the charge count changes. At this point, when reading data from the memory, the initial voltage value V is used. 初 It is applied to the memory cell. It is quite clear that the initial voltage value V... 初 The voltage value is greater than the threshold voltage of the memory cell corresponding to f1, and less than the threshold voltage of the memory cell corresponding to f2. Therefore, before the charge count of the memory cell changes, the initial voltage value V is used. 初 When reading a memory cell in storage state P1 or storage state P2, it is easy to distinguish whether the memory cell is in storage state P1 or storage state P2 in order to obtain the data stored in the memory cell. However, during the use of the memory, as the usage time increases, the read interference, the number of program erase cycles, the data retention capability, and the cross temperature of the memory will all change, and the threshold voltage of each memory cell will also change accordingly. Figure 8 Regions f3 and f4 in the diagram represent the threshold voltage distribution after the charge count of memory cells with storage states P1 and P2 changes, respectively. Figure 8 In the middle, f3 and f4 show shifts and broadening in shape relative to f1 and f2, respectively. At the initial voltage value V... 初 An overlap region between two storage states has appeared nearby. At this point, the initial voltage value V is used again. 初When reading data from each storage unit, it is possible to misclassify storage state P2 in region 2 as storage state P1, and storage state P1 in region 1 as storage state P2, and the threshold voltage is equal to the initial voltage value V. 初 Similarly, it is impossible to correctly determine whether the storage unit is in storage state P1 or storage state P2, which increases the probability of read errors.

[0061] As storage time and the number of reads increase, the threshold voltage deviation of the aforementioned storage cells is unavoidable. To obtain correct data reads, the memory incorporates an error correction code (ECC) function. It should be understood that the fewer the number of bits counted as errors, the fewer bits require ECC correction, thus increasing the probability of correct reads and reducing the required read time. Therefore, the corresponding read voltage is optimal. Figure 8 Regarding the threshold voltage distribution of the two adjacent storage states shown, the read voltage V 交 At the intersection point M of the two memory states corresponding to f3 and f4, the number of bits with statistical errors is minimized, and the read voltage V is at this point. 交 This refers to the optimal read voltage. This intersection point M can also be called the valley where the threshold voltage ranges corresponding to two adjacent memory states overlap. In other words, the operation method provided in this application embodiment determines this valley position or the direction of this valley position to determine the optimal read voltage.

[0062] Here, the initial voltage value included in each set of read voltages can refer to a preset read voltage used to distinguish two adjacent memory states of the memory cell. This preset read voltage can be an empirical value or a default value configured at the time of manufacture, which is obtained through extensive simulation experiments before the memory leaves the factory. Each initial voltage value can distinguish two adjacent memory states during previous read operations.

[0063] In some embodiments, obtaining at least one set of read voltages may include:

[0064] Determine at least one of the initial voltage values;

[0065] Based on the first initial voltage value among the at least one initial voltage value, a first offset voltage value with a certain offset relative to the first initial voltage value is obtained by sequentially increasing or decreasing by equal offsets.

[0066] A set of read voltages is obtained based on the first initial voltage value and the first offset voltage value;

[0067] The at least one set of reading voltages is obtained based on the corresponding set of reading voltages for each group.

[0068] It should be noted that two adjacent memory states may have multiple initial voltage values ​​with a certain voltage difference during actual use. Based on the foregoing description, the initial voltage value may be an empirical value or a factory default value. Therefore, determining at least one initial voltage value here means obtaining multiple empirical values ​​or multiple default values ​​from factory testing.

[0069] After obtaining at least one initial voltage value, each of the at least one initial voltage value is offset to obtain an offset voltage value with a certain offset relative to each initial voltage value. In this way, each initial voltage value and its corresponding offset voltage value are combined to form a set of read voltages, ultimately obtaining at least one set of read voltages. Since the acquisition method for each set of read voltages is similar, only the first initial voltage value is used as an example for explanation. The first initial voltage value is any one of the at least one initial voltage values.

[0070] Specifically, based on the first initial voltage value, a first offset voltage value with a certain offset relative to the first initial voltage value is obtained by sequentially increasing or decreasing the offset by equal amounts; then, the first initial voltage value and the first offset voltage value are combined to form a set of reading voltages relative to the first initial voltage value.

[0071] For example, such as Figure 9 As shown. In Figure 9 In this example, assuming the initial voltage value is Vrdn, the offset voltage values ​​relative to the initial voltage value are, in order: Vrdn_1, Vrdn_2, Vrdn_3, and Vrdn_4. These offset voltage values ​​are located to the left of the initial voltage value Vrdn and decrease sequentially with equal offsets. It should be noted that this is only one example; the offset voltage values ​​can also increase sequentially with equal offsets to the right of the initial voltage value.

[0072] It should also be noted that for different initial voltage values ​​among the at least one initial voltage value, the offsets that yield the corresponding offset voltage values ​​can be equal or unequal.

[0073] For example, suppose the at least one initial voltage value includes a first initial voltage value and a second initial voltage value, wherein the first initial voltage value obtains an equal offset of U millivolts (mV) to the offset voltage value, and the second initial voltage value obtains an equal offset of U mV to the offset voltage value, or any possible value other than U mV.

[0074] S702: performing a read operation based on an initial voltage value and an offset voltage value in the at least one set of read voltages respectively, to obtain a number of memory cells whose read results satisfy a set condition corresponding to each voltage value.

[0075] In some embodiments, the performing a read operation based on an initial voltage value and an offset voltage value in the at least one set of read voltages respectively, to obtain a number of memory cells whose read results satisfy a set condition corresponding to each voltage value can include:

[0076] reading one memory plane in the memory using the initial voltage value and the offset voltage value in each of the at least one set of read voltages respectively;

[0077] counting a number of memory cells whose read results satisfy a set condition in the memory plane read using each voltage value.

[0078] It should be noted that the memory can include a plurality of memory planes. In actual application, before programming each memory cell in the memory to store data, the data to be stored is subjected to scrambling processing, so as to reduce the occurrence of continuous digital 0 or continuous digital 1, and thus ensure that the probability of occurrence of digital 0 or digital 1 is close to 50%. This results in that for the same storage state, the number of memory cells in each memory plane of the memory in the storage state is substantially equal. Therefore, the voltage values in one set of read voltages can be used to read one memory plane of the memory, so as to count the number of memory cells in each memory plane in the storage state.

[0079] Here, the read result satisfying the set condition can mean that the read result is a set number, which can be 1 or 0. In an optional implementation, the read result of the memory cell with a threshold voltage less than the read voltage is the set number (the set number is 1), and the read result of the memory cell with a threshold voltage greater than the read voltage is 0. In another optional implementation, the read result of the memory cell with a threshold voltage greater than the read voltage is the set number (the set number is 0), and the read result of the memory cell with a threshold voltage less than the read voltage is 1.

[0080] The reading process described here is as follows: Each set of at least one set of reading voltages contains an initial voltage value and an offset voltage value, which are used to read a memory surface. Then, the number of memory cells in each memory surface whose read results satisfy a set condition is counted. In other words, each voltage value from each set of at least one set of reading voltages is applied to a memory surface to perform a read operation, and then the number of memory cells in each memory surface whose read result is a set number is counted.

[0081] For example, such as Figure 10 As shown, when the at least one set of read voltages includes a set of read voltages, if the set of read voltages includes: Vrdn, Vrdn_1, Vrdn_2, Vrdn_3, Vrdn_4, and the set number is 1, the above-mentioned reading process is to use Vrdn, Vrdn_1, Vrdn_2, Vrdn_3, Vrdn_4 to read a storage surface in the memory respectively, such as reading the storage surfaces Plane0, Plane1, Plane2, Plane3, and Plane4 of the memory respectively. Then, count the number of memory cells with a read result of 1 in each memory plane. For example, Plane0 contains the following number of memory cells with a read result of 1: C1_Vrdn; Plane1 contains the following number of memory cells with a read result of 1: C2_Vrdn; Plane2 contains the following number of memory cells with a read result of 1: C3_Vrdn; Plane3 contains the following number of memory cells with a read result of 1: C4_Vrdn; and Plane4 contains the following number of memory cells with a read result of 1: C5_Vrdn.

[0082] S703: Determine the difference between the two quantities corresponding to every two adjacent voltage values ​​belonging to the same group of read voltages.

[0083] Here, each pair of adjacent voltage values ​​belonging to the same group of read voltages can refer to: a certain initial voltage value and each pair of adjacent voltage values ​​in its corresponding offset voltage. For example, each pair of adjacent voltage values ​​in the initial voltage value Vrdn and its corresponding offset voltage values ​​Vrdn_1, Vrdn_2, Vrdn_3, and Vrdn_4 are respectively: (Vrdn, Vrdn_1); (Vrdn_1, Vrdn_2); (Vrdn_2, Vrdn_3); (Vrdn_3, Vrdn_4). Based on the above statistics of the number of storage units in the storage surface corresponding to each voltage value in this group of read voltages containing the read result of the set number, the difference between the quantities corresponding to each pair of adjacent voltage values ​​can be obtained as follows:

[0084] e1_Vrdn = C1_Vrdn - C2_Vrdn;

[0085] e2_Vrdn = C2_Vrdn - C3_Vrdn;

[0086] e3_Vrdn = C3_Vrdn - C4_Vrdn;

[0087] e4_Vrdn = C4_Vrdn - C5_Vrdn.

[0088] Wherein, the difference between the two quantities corresponding to each two adjacent voltage values belonging to the same group of read voltage can be intuitively seen from the schematic diagram of each difference value. Figure 11

[0089] S704: determining the optimal read voltage for distinguishing the two adjacent storage states based on the difference value.

[0090] In some embodiments, the at least one group of read voltages includes a first group of read voltages, and the determining the optimal read voltage for distinguishing the two adjacent storage states based on the difference value can include:

[0091] When the change trend of the difference value is consistent with the change trend of the voltage values in the first group of read voltages, determining the offset direction of the optimal read voltage relative to the initial voltage value in the first group of read voltages;

[0092] Determining the optimal read voltage based on the offset direction and a preset read voltage offset table.

[0093] It should be noted that what is described here is that the at least one group of read voltages only includes the first group of read voltages, that is, only includes an initial voltage value and an offset voltage value relative to the initial voltage value. In this case, the determination of the optimal read voltage based on the difference value can be divided into two cases: one is how to determine the optimal read voltage when the change trend of the difference value is consistent with the change trend of the voltage values in the first group of read voltages; the other is how to determine the optimal read voltage when the change trend of the difference value is inconsistent with the change trend of the voltage values in the first group of read voltages.

[0094] ​For the former case, when the trend of the difference is consistent with the trend of the voltage values in the first set of read voltages, the direction of the shift of the optimal read voltage relative to the initial voltage value in the first set of read voltages is determined first; then, the optimal read voltage is determined according to the shift direction and a preset read voltage shift table. The preset read voltage shift table can include a plurality of sets of preset voltage shift values obtained through a large amount of experience or experiments. In use, each preset voltage shift value in the preset read voltage shift table is loaded on a default initial read voltage (such as V 初 or Vrdn, which can also be the value thereof) to obtain a read voltage each time, and a set of preset shift voltage values that can correctly read data is found through repeated attempts to obtain an optimal set of read voltages, thereby increasing the probability of correctly reading data. The specific preset read voltage shift table is shown in Table 1.

[0095] It should be noted that Rd1 to Rd7 in Table 1 represent different initial read voltages. Since different types of storage units include different numbers of storage states, the default initial read voltage for each two adjacent storage states is different, that is, the preset read voltage shift table includes a set of preset shift voltage values corresponding to the default initial read voltage of each two adjacent storage states. Each set of preset shift voltage values includes a positive shift value that increases in the direction of being greater than the default initial read voltage and a negative shift value that decreases in the direction of being less than the default initial read voltage. For example, for the default initial read voltage Rd7, +V1, +V2, +V3, and +V4 are positive shift values, and V1, V2, V3, and V4 increase in value in turn; -V5 to -V11 are negative shift values, and V5 to V11 decrease in value in turn.

[0096] Table 1: Preset read voltage shift table 1

[0097]

[0098] In some embodiments, the determination of the shift direction of the optimal read voltage relative to the initial voltage value in the first set of read voltages can include:

[0099] When the trend of the voltage values in the first set of read voltages decreases in turn relative to the initial voltage value in the first set of read voltages, the shift direction of the optimal read voltage relative to the initial voltage value in the first set of read voltages is determined to be leftward shift;

[0100] When the trend of the voltage values in the first set of read voltages increases in turn relative to the initial voltage value in the first set of read voltages, the shift direction of the optimal read voltage relative to the initial voltage value in the first set of read voltages is determined to be rightward shift.

[0101] Specifically, when the bias voltage values of the first set of read voltages are on the left side of the initial voltage value of the first set of read voltages, and the variation trend is sequentially decreasing with respect to the initial voltage value of the first set of read voltages, it is determined that the offset direction of the optimal read voltage with respect to the initial voltage value of the first set of read voltages is leftward, that is, the optimal read voltage is on the left side of the first initial voltage value; when the bias voltage values of the first set of read voltages are on the right side of the initial voltage value of the first set of read voltages, and the variation trend is sequentially increasing with respect to the initial voltage value of the first set of read voltages, it is determined that the offset direction of the optimal read voltage with respect to the initial voltage value of the first set of read voltages is rightward, that is, the optimal read voltage is on the right side of the initial voltage value of the first set of read voltages.

[0102] After obtaining the offset direction of the optimal read voltage, in some embodiments, the determining the optimal read voltage based on the offset direction and a preset read voltage offset table can include:

[0103] selecting a first optimal offset from the preset read voltage offset table based on the offset direction;

[0104] determining the optimal read voltage based on the first optimal offset and the initial voltage value in the first set of read voltages.

[0105] It should be noted that after determining the offset direction of the optimal read voltage, a first optimal offset can be selected from the preset read voltage offset table; and then the optimal read voltage is determined based on the first optimal offset and the initial voltage value in the first set of read voltages. Here, the first optimal offset can include at least one preset offset voltage. When the first optimal offset includes a plurality of preset offset voltages, the determining the optimal read voltage based on the first optimal offset and the initial voltage value in the first set of read voltages can mean that each preset offset voltage included in the first optimal offset is loaded to the corresponding default initial read voltage, and a plurality of experiments are performed to find a preset offset voltage that can correctly read the stored data of the storage unit, and the optimal read voltage is obtained. In this way, after determining the offset direction of the optimal read voltage, a group of first optimal offsets that approach the optimal read voltage can be found in the preset read voltage offset table, and one or more preset offset voltages in these first optimal offsets are loaded to the corresponding default initial read voltage to obtain a plurality of read voltages, which narrows the range of preset offset voltages required for repeated attempts to correctly read data and reduces the read rate.

[0106] For example, refer to Table 2. If the initial voltage value Vrdn1 included in the first group of read voltages is -V5, and the optimal read voltage is shifted to the left relative to the initial voltage value -V5, that is, shifted to a direction smaller than the initial voltage value. Based on this, in combination with the preset read voltage shift table shown in Table 1, the first optimal shift amount includes preset shift voltage amounts -V5 to -V11, and then these preset shift voltage amounts are loaded on the default initial read voltage Rd7 to attempt to obtain the optimal read voltage, so that it is not necessary to attempt +V1 to +V4 in the positive direction, which narrows the range of preset shift voltage amounts required to repeatedly attempt to obtain the data that can be correctly read, and reduces the re-reading rate.

[0107] Table 2: Preset read voltage shift table 2

[0108]

[0109] For the latter case, in some embodiments, the method can further include:

[0110] determining a minimum difference value in the difference values when the trend of the difference values is inconsistent with the trend of the voltage values in the first group of read voltages;

[0111] determining the optimal read voltage based on the minimum difference value.

[0112] It should be noted that, according to the characteristics of the threshold voltage distribution of the storage unit of the memory, when the trend of the difference values is inconsistent with the trend of the voltage values in the first group of read voltages, that is, the trend of the difference values is not monotonous, but contains an inflection point (minimum difference value) in the middle, which means that when the storage unit in one of the two adjacent storage states is read with the voltage values in the first group of read voltages, the number of storage units whose read results satisfy the set condition corresponding to each voltage value is not monotonous, which means that there is an intersection point between the two adjacent storage states. According to the foregoing Figure 9 , when the intersection point M exists between the threshold voltage distributions corresponding to the two adjacent storage states, the read voltage V 交 is the optimal read voltage. Therefore, when the range between the two adjacent voltage values in the first group of read voltages corresponding to the inflection point of the difference value contains the read voltage V 交 , that is, the optimal read voltage.

[0113] For example, as previously Figure 11 indicated, the schematic diagram of each difference value is shown. e2_Vrdn<e3_Vrdn<e1_Vrdn / e4_Vrdn (as Figure 12When the minimum difference value is obtained (as shown in FIG. 2), the e2_Vrdn can be determined as the minimum difference value, and the optimal read voltage is the average voltage value of the two adjacent voltage values corresponding to the minimum difference value.

[0114] In some embodiments, the determining the optimal read voltage based on the minimum difference value can include:

[0115] determining two adjacent voltage values corresponding to the minimum difference value from the offset voltage values in the first set of read voltages;

[0116] determining the average voltage value of the two adjacent voltage values as the optimal read voltage.

[0117] It should be noted that the optimal read voltage here is the average voltage value of the two adjacent voltage values corresponding to the minimum difference value.

[0118] In actual application, after the two adjacent voltage values corresponding to the minimum difference value are obtained, one or more preset offset voltage values between the two adjacent voltage values are determined from a preset read voltage offset table; then, the optimal read voltage is obtained from the one or more preset offset voltage values between the two adjacent voltage values in the manner of obtaining the optimal read voltage from the preset offset voltage values contained in the first optimal offset value.

[0119] The above-described scheme is a determination manner of the optimal read voltage when the at least one set of read voltages only includes the first set of read voltages. In some embodiments, the at least one set of read voltages further includes a second set of read voltages, wherein the initial voltage value in the second set of read voltages has a certain voltage difference with the initial voltage value in the first set of read voltages; the offset voltage value in the second set of read voltages is located between the initial voltage value in the second set of read voltages and the initial voltage value in the first set of read voltages; the difference value includes a first sub-difference value corresponding to the first set of read voltages and a second sub-difference value corresponding to the second set of read voltages.

[0120] The determining the optimal read voltage for distinguishing the two adjacent storage states based on the difference value includes:

[0121] determining the optimal read voltage based on a first change trend of the first sub-difference value and / or a second change trend of the second sub-difference value.

[0122] The initial voltage value in the second set of read voltages is greater than or less than the initial voltage value in the first set of read voltages.

[0123] It should be noted that the scheme described herein is that at least one set of read voltages includes a first set of read voltages and a second set of read voltages, wherein the first set of read voltages includes an initial voltage value and the second set of read voltages includes an initial voltage value, and there is a certain voltage difference between the initial voltage value included in the first set of read voltages and the initial voltage value included in the second set of read voltages; the initial voltage value included in the first set of read voltages is greater than or less than the initial voltage value included in the second set of read voltages; the offset voltage value included in the first set of read voltages and the offset voltage value included in the second set of read voltages are between the initial voltage value of the first set of read voltages and the initial voltage value of the second set of read voltages. It should be noted that only when the offset voltage value is between the two initial voltage values, the optimal read voltage can be determined by using the two sets of read voltages described above. For details, please refer to Figure 13 It is shown that the difference includes a first sub-difference corresponding to the first set of read voltages and a second sub-difference corresponding to the second set of read voltages. In this case, the determination of the optimal read voltage can include: determining based on a first change trend of the first sub-difference and / or a second change trend of the second sub-difference. It should be noted that,

[0124] Because no matter whether the initial voltage value included in the first set of read voltages is greater than or less than the initial voltage value included in the second set of read voltages, the way of determining the optimal read voltage is the same.

[0125] Therefore, in some embodiments, when the initial voltage value in the first set of read voltages is greater than the initial voltage value in the second set of read voltages, the determination of the optimal read voltage based on the first change trend of the first sub-difference and / or the second change trend of the second sub-difference includes:

[0126] When the first change trend is inconsistent with the change trend of the voltage value in the first set of read voltages and the second change trend is consistent with the change trend of the voltage value in the second set of read voltages, the optimal read voltage is determined based on the minimum value of the first sub-difference.

[0127] It should be noted that in this case, there is an inflection point between the first sub-differences, and the optimal read voltage is between the voltage values in the first set of read voltages corresponding to the inflection point. How to obtain the foregoing has been described in detail, and will not be repeated here.

[0128] In other embodiments, the operation method further includes:

[0129] When the first change trend is inconsistent with the change trend of the voltage value in the first set of read voltages and the second change trend is inconsistent with the change trend of the voltage value in the second set of read voltages, the optimal read voltage is determined based on the minimum value of the first sub-difference and / or the minimum value of the second sub-difference.

[0130] It should be noted that in this case, if the inflection point corresponding to the first sub-difference value and the second sub-difference value is one, the optimal read voltage is determined based on two adjacent voltage values in the first group of read voltages corresponding to the minimum value in the first sub-difference value, or the optimal read voltage is determined based on two adjacent voltage values in the second group of read voltages corresponding to the minimum value in the second sub-difference value. How to determine the foregoing in only the first group of read voltages has been described in detail, and will not be repeated here. If the inflection points corresponding to the first sub-difference value and the second sub-difference value are different, the optimal read voltage is determined based on two adjacent voltage values in the first group of read voltages corresponding to the minimum value in the first sub-difference value and based on two adjacent voltage values in the second group of read voltages corresponding to the minimum value in the second sub-difference value.

[0131] Specifically, assuming that the two adjacent voltage values in the first group of read voltages corresponding to the minimum value in the first sub-difference value are a first voltage value and a second voltage value, respectively, and the two adjacent voltage values in the second group of read voltages corresponding to the minimum value in the second sub-difference value are a third voltage value and a fourth voltage value, respectively, based on this, the way to determine the optimal read voltage based on the first voltage value, the second voltage value, the third voltage value and the fourth voltage value can adopt the following several ways:

[0132] The first, the average voltage value of the first voltage value, the second voltage value, the third voltage value and the fourth voltage value is the optimal read voltage.

[0133] The second, one or more preset offset voltages included in the voltage value range composed of the first voltage value, the second voltage value, the third voltage value and the fourth voltage value are obtained based on a preset read voltage offset table, and then the optimal read voltage is obtained according to the foregoing attempt method.

[0134] The third, a first average voltage value between the first voltage value and the second voltage value is obtained, and a second average voltage value between the third voltage value and the fourth voltage value is obtained, and then one or more preset offset voltages included in the voltage value range composed of the first average voltage value and the second average voltage value are obtained based on a preset read voltage offset table, and then the optimal read voltage is obtained according to the foregoing attempt method.

[0135] It should be noted that the foregoing three ways to determine the optimal read voltage based on the first voltage value, the second voltage value, the third voltage value and the fourth voltage value are only three examples, and other possible implementation ways are also included in actual application process, and the specific implementation process does not deviate from the technical solutions described in the present application, and will not be repeated here.

[0136] In some embodiments, the operation method further comprises:

[0137] when the first change trend is consistent with the change trend of the voltage values in the first set of read voltages and the second change trend is inconsistent with the change trend of the voltage values in the second set of read voltages, determining the optimal read voltage based on the minimum value of the second sub-difference values.

[0138] It should be noted that in this case, the second sub-difference values contain an inflection point, and the voltage values in the second set of read voltages corresponding to the inflection point contain the optimal read voltage. The specific way of obtaining the foregoing has been described above, and will not be repeated here.

[0139] In yet some embodiments, the operation method further comprises:

[0140] when the first change trend is consistent with the change trend of the voltage values in the first set of read voltages and the second change trend is consistent with the change trend of the voltage values in the second set of read voltages, determining a first offset direction of the optimal read voltage relative to the initial voltage value in the first set of read voltages, and determining a second offset direction of the optimal read voltage relative to the initial voltage value in the second set of read voltages;

[0141] determining a second optimal offset amount from the preset read voltage offset table based on the first offset direction and the second offset direction;

[0142] determining the optimal read voltage based on the initial voltage value in the first set of read voltages, the initial voltage value in the second set of read voltages, and the second optimal offset amount.

[0143] It should be noted that the foregoing has been defined that the initial voltage value in the first set of read voltages is greater than the initial voltage value in the second set of read voltages, therefore, the offset direction of the optimal read voltage relative to the initial voltage value in the first set of read voltages is left offset, that is, the first offset direction is the offset direction of the optimal read voltage relative to the initial voltage value in the first set of read voltages is left offset; the offset direction of the optimal read voltage relative to the initial voltage value in the second set of read voltages is right offset, that is, the second offset direction is the offset direction of the optimal read voltage relative to the initial voltage value in the second set of read voltages is right offset. Based on this, based on the first offset direction and the second offset direction, one or more preset offset voltage amounts contained in the second optimal offset amount are obtained from the preset read voltage offset table, and the optimal read voltage is obtained based on these preset offset voltage amounts in the manner described above. The specific manner will not be repeated here.

[0144] For example, refer to Table 3. If the initial voltage value Vrdn1 of the first group of read voltages is -V8, and the initial voltage value Vrdn2 of the second group of read voltages is -V6, since the values of V5 to V11 decrease in turn, the smaller the offset of -V5 to -V11 in the negative direction, and thus Vrdn1 is greater than Vrdn2. At this time, the one or more preset offset voltage amounts included in the second optimal offset amount include -V6 to -V8, and then the optimal read voltage is obtained based on these preset offset voltage amounts. The foregoing has described how to determine the optimal read voltage based on the preset offset voltage amount, and thus will not be described here again.

[0145] Table 3: Preset read voltage offset table

[0146]

[0147] In some embodiments, the operation method can be used when the memory is idle or during user operation.

[0148] It should be noted that the operation method provided by the embodiments of the present application can be used when the memory is idle or during user operation, wherein the idle can mean that the memory is not read or programmed and various operations, and during this period, all steps of the operation method provided by the embodiments of the present application can be run once to obtain the optimal read voltage group. The user operation period can mean that the user reads or writes to the memory and other operations, and during this period, all steps of the operation method provided by the embodiments of the present application can be executed step by step during the user operation period to ultimately obtain the optimal read voltage group.

[0149] In some embodiments, the memory includes a register for storing the optimal read voltage.

[0150] For the operation method provided by the embodiments of the present application described above, there are two ways in the actual implementation process,

[0151] An alternative embodiment, for example, Figure 14As shown, the number of different storage planes in one DIE is usually even. For two adjacent storage states, a plurality of offset voltage values are set based on the initial voltage value Vrdn, which are Vrdn_1, Vrdn_2, Vrdn_3, Vrdn_4, to form a set of read voltages. Each voltage value in the set of read voltages is used to simultaneously perform read operations on the five planes in one DIE, that is, the memory controller causes the control logic unit included in the memory to simultaneously send read commands containing different read voltages to the five planes (for example, Plane0, Plane1, Plane2, Plane3, and Plane4), so that Plane0 uses Vrdn for reading, Plane1 uses Vrdn_1 for reading, Plane2 uses Vrdn_2 for reading, Plane3 uses Vrdn_3 for reading, and Plane4 uses Vrdn_4 for reading. Then, the master digital signal processing (DSP) included in the memory controller receives the read results of each storage unit in each plane and counts the number of storage units in each plane that meet the set condition. Then, the DSP determines the optimal read voltage based on the number to guide the next read operation.

[0152] Another optional embodiment is as shown in Figure 15 When the storage array of the memory is a NAND flash memory, if the NAND flash memory has a statistical function, Figure 15 and Figure 14 The only difference is that the step of counting the number of storage units with the set value is counted by the control logic unit in the peripheral circuit carried by the NAND, and the number of storage units in each plane that meet the set condition is sent to the DSP included in the memory controller. The remaining steps are the same as those shown in Figure 14 and have been described in detail above, and will not be repeated here.

[0153] The operation method of the memory provided in the embodiments of the present application comprises the following steps: at least one set of read voltages comprising a plurality of voltage values is set, read operation is performed on the memory cells of the memory by using each voltage value respectively, and the number of read results satisfying a set condition is obtained; then, the difference between the numbers corresponding to each two adjacent voltage values in the same set of read voltages is determined, and the optimal read voltage for distinguishing the two adjacent storage states of the memory cells corresponding to the set of read voltages is determined based on the difference. The corresponding memory cells of the memory are read by using the obtained optimal read voltage, which greatly increases the probability of correctly reading the data stored in the memory cells. The operation method provided in the embodiments of the present application is a method for obtaining the optimal read voltage of the memory online. In other words, the operation method is a method for determining the optimal read voltage by using real data generated during the actual operation of the memory, instead of a method for determining the optimal read voltage by using simulation data in the production process of the memory. The operation method can obtain the optimal read voltage set online, improve the decoding success rate, or obtain the threshold offset method of the optimal read voltage online, more selectively select the read voltage, and reduce the read times, so as to save time.

[0154] Based on the same inventive concept, the embodiments of the present application also provide a memory, a memory array, and a peripheral circuit.

[0155] The memory array comprises memory cells.

[0156] The peripheral circuit is coupled to the memory array and is configured to control the memory array.

[0157] In some embodiments, the peripheral circuit comprises a register for storing the optimal read voltage.

[0158] It should be noted that the technical solutions described in the memory and the technical solutions of the operation method described above belong to the same inventive concept, and have the same technical features. The terms appearing in the technical solutions of the operation method provided in the embodiments of the present application have been described in detail above, and the meanings of the terms appearing in the present description can be understood according to the above description, which will not be described here.

[0159] The embodiments of the present application also provide a memory system, comprising: one or more memories described above;

[0160] and a memory controller coupled to the memory; the memory controller is configured to: send a first command to the memory.

[0161] The memory is configured to: in response to the first command, perform the operation method described above.

[0162] The first command is used to start the execution of the operation method, and the first command includes a command indicating that the memory obtains at least one set of read voltages, and a command using voltage values in the at least one set of read voltages to read one memory surface respectively, and various commands for implementing the operation method.

[0163] In some embodiments, the present application also provides a storage system, comprising: one or more memories; and a memory controller coupled to the memories; wherein,

[0164] The memory controller is configured to: obtain at least one set of read voltages; each set of read voltages includes an initial voltage value and an offset voltage value having a certain offset amount relative to the initial voltage value; the initial voltage value in each set of read voltages is a preset read voltage used to distinguish two adjacent storage states of a storage unit of the memory; and send corresponding read commands to a memory surface included in the memory based on the initial voltage value and the offset voltage value in the at least one set of read voltages respectively.

[0165] The memory is configured to: read the corresponding memory surface in response to the corresponding read command; and send the read results of each storage unit in the memory surface to the memory controller.

[0166] The memory controller is further configured to: receive the read results; count the number of storage units whose read results meet a set condition corresponding to each voltage value; determine the difference between two numbers corresponding to two adjacent voltage values belonging to the same set of read voltages; and determine the optimal read voltage used to distinguish the two adjacent storage states based on the difference.

[0167] It should be noted that the storage system can implement the above-mentioned Figure 14 implementation.

[0168] In some embodiments, the present application also provides another storage system, comprising: one or more memories; and a memory controller coupled to the memories; wherein,

[0169] The memory controller is configured to: obtain at least one set of read voltages; each set of read voltages includes an initial voltage value and an offset voltage value having a certain offset amount relative to the initial voltage value; the initial voltage value in each set of read voltages is a preset read voltage used to distinguish two adjacent storage states of a storage unit of the memory; and send corresponding read commands to a memory surface included in the memory based on the initial voltage value and the offset voltage value in the at least one set of read voltages respectively.

[0170] The memory is configured to read a corresponding memory surface in response to the corresponding read command, count a number of memory cells whose read results corresponding to each voltage value meet a set condition, and send the number to the memory controller.

[0171] The memory controller is further configured to receive the number, determine a difference between two numbers corresponding to two adjacent voltage values belonging to the same group of read voltages, and determine an optimal read voltage for distinguishing memory cells in the two adjacent storage states based on the difference.

[0172] It should be noted that the storage system herein can implement the foregoing Figure 15 The implementation manner shown.

[0173] In some embodiments, any of the foregoing storage systems is a solid state drive (SSD) or a memory card.

[0174] It should be noted that the storage system herein includes the foregoing memory, both of which have the same technical features. The foregoing has described the structure of the memory and the terms appearing in the technical solutions of the present application in detail. Therefore, the terms appearing herein can be understood according to the meanings described above, and will not be described again.

[0175] The above merely describes preferred embodiments of the present application and is not intended to limit the protection scope of the present application.

Claims

1. A method of operating a memory, the method comprising: The method comprises the following steps: obtaining at least one set of read voltages; each set of read voltages comprises an initial voltage value and an offset voltage value having a certain offset amount relative to the initial voltage value; the initial voltage value in each set of read voltages is a preset read voltage used to distinguish two adjacent storage states of a storage cell of the memory; based on the initial voltage value and the offset voltage value in each set of read voltages, a read operation is performed respectively to obtain the number of storage cells whose read results corresponding to each voltage value meet a set condition; determining the difference between the two numbers corresponding to each two adjacent voltage values belonging to the same set of read voltages; based on the difference, determining the optimal read voltage used to distinguish the two adjacent storage states.

2. The method of claim 1, wherein, The method comprises the following steps: determining at least one initial voltage value; based on a first initial voltage value in the at least one initial voltage value, a first offset voltage value having a certain offset amount relative to the first initial voltage value is obtained by sequentially increasing or decreasing in equal offset amounts; based on the first initial voltage value and the first offset voltage value, a corresponding set of read voltages is obtained; based on each corresponding set of read voltages, the at least one set of read voltages is obtained.

3. The method of claim 1, wherein, The method comprises the following steps: using the initial voltage value and the offset voltage value contained in each set of read voltages in the at least one set of read voltages to read a storage surface in the memory respectively; counting the number of storage cells in the storage surface read by each voltage value and whose read results meet a set condition.

4. The operating method according to claim 1, characterized in that, The at least one set of read voltages comprises a first set of read voltages, and the method comprises the following steps: when the change trend of the difference is consistent with the change trend of the voltage values in the first set of read voltages, determining the offset direction of the optimal read voltage relative to the initial voltage value in the first set of read voltages; based on the offset direction and a preset read voltage offset table, determining the optimal read voltage.

5. The method of claim 4, wherein, The method comprises the following steps: when the change trend of the voltage values in the first set of read voltages is sequentially decreased relative to the initial voltage value in the first set of read voltages, determining that the offset direction of the optimal read voltage relative to the initial voltage value in the first set of read voltages is left offset; when the change trend of the voltage values in the first set of read voltages is sequentially increased relative to the initial voltage value in the first set of read voltages, determining that the offset direction of the optimal read voltage relative to the initial voltage value in the first set of read voltages is right offset.

6. The method of claim 4, wherein, The method comprises the following steps: based on the offset direction, selecting a first optimal offset amount from the preset read voltage offset table; determining the optimal read voltage based on the first optimal offset and an initial voltage value in the first set of read voltages.

7. The method of claim 4, wherein, The method further comprises: determining a minimum difference value in the difference values when the trend of the difference values is inconsistent with the trend of the voltage values in the first set of read voltages; determining the optimal read voltage based on the minimum difference value.

8. The method of claim 7, wherein, The determining the optimal read voltage based on the minimum difference value comprises: determining two adjacent voltage values corresponding to the minimum difference value from the offset voltage values in the first set of read voltages; determining an average voltage value of the two adjacent voltage values as the optimal read voltage.

9. The method of claim 4, wherein, The at least one set of read voltages further comprises a second set of read voltages, wherein an initial voltage value in the second set of read voltages has a certain voltage difference with the initial voltage value in the first set of read voltages; an offset voltage value in the second set of read voltages is located between the initial voltage value in the second set of read voltages and the initial voltage value in the first set of read voltages; the difference values comprise a first sub-difference value corresponding to the first set of read voltages and a second sub-difference value corresponding to the second set of read voltages; The determining the optimal read voltage based on the difference values for distinguishing the two adjacent storage states comprises: determining the optimal read voltage based on a first trend of the first sub-difference value and / or a second trend of the second sub-difference value; wherein the initial voltage value in the second set of read voltages is greater than or less than the initial voltage value in the first set of read voltages.

10. The method of claim 9, wherein, When the initial voltage value in the first set of read voltages is greater than the initial voltage value in the second set of read voltages, the determining the optimal read voltage based on the first trend of the first sub-difference value and / or the second trend of the second sub-difference value comprises: determining the optimal read voltage based on a minimum value of the first sub-difference value when the first trend is inconsistent with the trend of the voltage values in the first set of read voltages and the second trend is consistent with the trend of the voltage values in the second set of read voltages.

11. The method of claim 10, wherein, The operation method further comprises: determining the optimal read voltage based on a minimum value of the first sub-difference value and / or a minimum value of the second sub-difference value when the first trend is inconsistent with the trend of the voltage values in the first set of read voltages and the second trend is inconsistent with the trend of the voltage values in the second set of read voltages.

12. The method of claim 10, wherein, The operation method further comprises: determining the optimal read voltage based on a minimum value of the second sub-difference value when the first trend is consistent with the trend of the voltage values in the first set of read voltages and the second trend is inconsistent with the trend of the voltage values in the second set of read voltages.

13. The method of claim 10, wherein, The operation method further comprises: determining a first offset direction of the optimal read voltage relative to an initial voltage value in the first set of read voltages when the first change trend is consistent with the change trend of the voltage values in the first set of read voltages and the second change trend is consistent with the change trend of the voltage values in the second set of read voltages; and determining a second offset direction of the optimal read voltage relative to an initial voltage value in the second set of read voltages; determining a second optimal offset amount from the preset read voltage offset table based on the first offset direction and the second offset direction; determining the optimal read voltage based on the initial voltage value in the first set of read voltages, the initial voltage value in the second set of read voltages, and the second optimal offset amount.

14. The operating method according to claim 1, characterized in that, The operation method is executed when the memory is idle or during user operation.

15. A memory, comprising: Comprising: a memory array comprising memory cells; and a peripheral circuit coupled with the memory array and configured to control the memory array; the peripheral circuit is configured to implement the operation method of any one of claims 1 to 14.

16. The memory of claim 15, wherein, The peripheral circuit comprises a register for storing the optimal read voltage.

17. A storage system, comprising: Comprising: one or more memories of claim 15 or 16; and a memory controller coupled with the memories; wherein; the memory controller is configured to send a first command to the memories; the memories are configured to execute the operation method of claims 1 to 14 in response to the first command.

18. A storage system, comprising: Comprising: one or more memories; and a memory controller coupled with the memories; wherein, the memory controller is configured to obtain at least one set of read voltages; each set of read voltages in the at least one set of read voltages comprises an initial voltage value and an offset voltage value having an offset amount relative to the initial voltage value; the initial voltage value in each set of read voltages is a preset read voltage for distinguishing two adjacent storage states of memory cells of the memories; and send corresponding read commands to a corresponding memory surface included in the memories based on the initial voltage value and the offset voltage value in each set of read voltages; the memories are configured to read the corresponding memory surface in response to the corresponding read commands; and send read results of each memory cell in the memory surface to the memory controller; the memory controller is further configured to receive the read results; count the number of memory cells whose read results satisfy a set condition corresponding to each voltage value; determine the difference between two numbers corresponding to two adjacent voltage values belonging to the same set of read voltages; and determine the optimal read voltage for distinguishing the two adjacent storage states based on the difference.

19. A storage system, comprising: Comprising: one or more memories; and a memory controller coupled with the memories; wherein, The memory controller is configured to obtain at least one set of read voltages, each set of read voltages in the at least one set of read voltages comprising an initial voltage value and an offset voltage value having a certain offset amount relative to the initial voltage value, the initial voltage value in each set of read voltages being a preset read voltage for distinguishing two adjacent storage states of a storage cell of the memory, and sending a corresponding read command to a storage surface contained in the memory based on the initial voltage value and the offset voltage value in the at least one set of read voltages respectively. The memory is configured to read a corresponding storage surface in response to the corresponding read command, count a number of storage cells whose read results corresponding to each voltage value satisfy a set condition, and send the number to the memory controller. The memory controller is further configured to receive the number, determine a difference between two numbers corresponding to two adjacent voltage values belonging to a same set of read voltages, and determine an optimal read voltage for distinguishing storage cells of the two adjacent storage states based on the difference.

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