A packaging substrate with microfluidic channel and preparation method thereof

Abstract

The present invention provides a microfluidic packaging substrate and a preparation method thereof, wherein the microfluidic packaging substrate comprises a silicon substrate and a wiring layer located on the upper surface of the silicon substrate; the silicon substrate comprises an upper silicon wafer, an intermediate glass wafer and a lower silicon wafer that are bonded and connected; the upper silicon wafer, the lower silicon wafer and the intermediate glass wafer have interconnected areas to form a sealed flow channel structure, and an inlet and an outlet connected to the sealed flow channel structure are processed below the lower silicon wafer; the TSV structures of the upper silicon wafer and the lower silicon wafer are opposite, and a longitudinal through-hole structure is processed on the intermediate glass wafer to form a contact window corresponding to the TSV structure, and a patterned electrode interconnection line is prepared on the inner surface of the contact window; the TSV structure and the interconnected electrode structure realize the vertical interconnection of electrical signals, and the wiring layer realizes the planar interconnection of electrical signals in the X and Y directions. The silicon-based packaging substrate prepared by the present invention can be wired on the upper and lower surfaces, and at the same time meet the three-dimensional electrical interconnection and chip heat dissipation requirements of the integrated microsystem.

Description

Technical Field

[0001] The present invention relates to the field of packaging technology, and in particular to a packaging substrate with a microfluidic channel and a preparation method thereof, which are used for three-dimensional integration of radio frequency microsystems, navigation microsystems, etc. Background Art

[0002] With the rapid development of integrated circuits, three-dimensional (3D) packaging and micro-integration of integrated circuit systems, radio frequency systems, and navigation systems have brought new opportunities. However, the high assembly density, high integration, and operating frequency continue to increase, while the system size continues to shrink, resulting in an increase in heat per unit area and unit volume. The chips located at the periphery of the system can achieve heat transfer through heat diffusers and heat sinks to achieve the purpose of heat dissipation, but the heat dissipation problem of the middle layer chips of the integrated microsystem requires special methods. The temperature accumulation of the middle layer chips of the integrated microsystem seriously affects the long-term reliability of the system, and the heat dissipation problem of the three-dimensional integrated microsystem needs to be solved urgently.

[0003] Microchannel is a good heat dissipation technology. Microchannel can be closely attached to the surface of the chip, and the accumulated heat inside can be conducted away through the circulation of liquid inside the channel. However, the preparation of heat dissipation microchannel for integrated microsystems currently usually adopts silicon-silicon direct bonding technology, low-temperature thermosetting materials or thermoplastic materials to bond the upper and lower channels to form a sealed microchannel. Due to many reasons such as process temperature and equipment limitations, it is difficult to make the microchannel together with the TSV (Through Silicon Vias) structure and wiring layer, and the heat dissipation microchannel needs to be welded on the packaging substrate. Summary of the invention

[0004] In order to overcome the deficiencies in the prior art, the inventors have conducted intensive research and provided a microfluidic packaging substrate and a preparation method thereof. By utilizing the compatibility of the silicon-glass anodic bonding process and adopting the silicon-glass-silicon three-layer anodic bonding technology, the TSV structure, microfluidic channels, and wiring layers are integrated into a silicon-based substrate, which can realize three-dimensional interconnection of electrical signals of a three-dimensional integrated microsystem and solve the chip heat dissipation problem through microfluidics.

[0005] The technical solution provided by the present invention is as follows:

[0006] In a first aspect, a microfluidic channel packaging substrate comprises a silicon substrate and a wiring layer; the silicon substrate comprises an upper silicon wafer, an intermediate glass wafer and a lower silicon wafer which are bonded to each other, and the two silicon wafers have corresponding TSV structures; the upper silicon wafer, the lower silicon wafer and the intermediate glass wafer have interconnected areas to form a sealed channel structure, and an inlet and an outlet connected to the sealed channel structure are processed below the lower silicon wafer; the TSV structures of the upper silicon wafer and the lower silicon wafer are opposite, a longitudinal through-hole structure is processed on the intermediate glass wafer to form a contact window corresponding to the TSV structure, and a patterned electrode interconnection line is prepared on the inner surface of the contact window, and the TSV structures of the upper silicon wafer and the lower silicon wafer and the electrode interconnection line realize vertical interconnection of electrical signals;

[0007] The wiring layer is located on the upper surface of the silicon substrate, and includes an inner insulating layer structure and an outer electrical interconnection line structure. The wiring layer is used to realize planar interconnection of electrical signals in the X and Y directions.

[0008] In a second aspect, a method for preparing a microfluidic package substrate comprises the following steps:

[0009] Step (i), preparing a first silicon wafer and a second silicon wafer, the silicon wafers already containing the desired TSV structure; depositing a mask layer on the surface of the first silicon wafer and the second silicon wafer, and patterning the mask layer by photolithography, wet etching process or dry etching process to obtain a first etching mask structure;

[0010] Step (ii), on the surfaces of the two silicon wafers, a silicon wet etching process or a silicon dry etching process is used to prepare the flow channel structure of the first silicon wafer and the second silicon wafer;

[0011] Step (iii), using a wet etching process to remove the first etching mask structure on the surface of the first silicon wafer and the surface of the second silicon wafer, to obtain a third silicon wafer and a fourth silicon wafer with a flow channel structure;

[0012] Step (iv), using a silicon-glass anodic bonding process to bond the third silicon wafer to the first glass wafer to obtain a composite substrate;

[0013] Step (V), using wet etching and chemical mechanical polishing processes to thin and polish the first glass sheet to obtain a second glass sheet;

[0014] Step (six), on the surface of the second glass sheet, a composite metal layer mask Cr / Au is prepared by a magnetron sputtering process or an electron beam evaporation process, and the composite metal layer Cr / Au is patterned by a photolithography and etching process to obtain a second etching mask structure;

[0015] Step (VII), patterning the second glass sheet by wet etching to form a contact window, the contact window being located above the TSV structure, removing the second etching mask structure, so that the contact window exposes the conductor or semiconductor in the middle of the TSV structure;

[0016] Step (eight), on the patterned second glass sheet, a composite metal layer is prepared by electron beam evaporation, and the composite metal layer is patterned and etched by a lift-off process to form a patterned electrode interconnection line on the inner surface of the contact window;

[0017] Step (IX), using an anodic bonding process to bond the upper surface of the fourth silicon wafer and the second glass wafer of the composite substrate together, with the fourth silicon wafer serving as a lower silicon wafer, the second glass wafer serving as an intermediate glass wafer, and the third silicon wafer serving as an upper silicon wafer, to obtain a silicon substrate and a sealed flow channel structure in the silicon substrate;

[0018] Step (10), repeating the process of step (1) to prepare an insulating layer structure on the upper surface of the silicon substrate, wherein the insulating layer structure covers the insulating dielectric layer of the TSV structure but does not cover the area above the conductor or semiconductor in the middle of the TSV structure;

[0019] Step (XI): on the upper surface of the silicon substrate, a patterned electrical interconnection structure is prepared by a lift-off process, wherein the insulating layer structure and the electrical interconnection structure together constitute a wiring layer;

[0020] Step (twelve), repeat the process of steps (a) and (b) to prepare the inlet and outlet of the microchannel on the lower surface of the silicon substrate.

[0021] A microfluidic package substrate and a preparation method thereof provided by the present invention have the following beneficial effects:

[0022] (1) The present invention provides a microfluidic packaging substrate and a preparation method thereof, which uses a silicon-glass-silicon three-layer anodic bonding technology to integrate a TSV structure, a microfluidic channel, and a wiring layer onto a silicon-based substrate, and the TSV structure and the interconnection electrode structure realize vertical interconnection of electrical signals, and the wiring layer realizes planar interconnection of electrical signals in the X and Y directions, which can simultaneously meet the three-dimensional electrical interconnection of the integrated microsystem and the heat dissipation requirements of the chip through the microfluidic channel;

[0023] (2) The present invention provides a microfluidic packaging substrate and a preparation method thereof, which is a silicon-glass-silicon three-layer composite structure and adopts a two-time anodic bonding process to realize the preparation of sealed microfluidic channels. The anodic bonding process has good compatibility and can realize the preparation of various silicon-based microfluidic channels;

[0024] (3) The present invention provides a packaging substrate with microfluidic channels and a preparation method thereof, which can realize multi-layer packaging substrate stacking and is suitable for heat dissipation of multi-layer stacking and multi-chip integrated structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of the silicon wafer structure selected for the present invention;

[0026] Figure 2 to Figure 5This is a schematic diagram of the preparation process of the single-sided silicon flow channel structure of the present invention;

[0027] Figure 6 to Figure 10 This is a schematic diagram of the process for preparing the silicon-glass composite substrate of the present invention;

[0028] Fig.11 This is a schematic diagram of the sealed microchannel structure of the present invention;

[0029] Figure 12-13 A schematic diagram of the single-layer wiring preparation process of the present invention;

[0030] Fig.14 It is a schematic diagram of the outlet and inlet structure of the microchannel of the present invention. DETAILED DESCRIPTION

[0031] The following detailed description of the present invention will make the features and advantages of the present invention more clear and explicit.

[0032] The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise noted.

[0033] According to a first aspect of the present invention, a method for preparing a microfluidic package substrate is provided, which uses fluid heat dissipation to solve the problem of heat accumulation between layers of a three-dimensional integrated microsystem. The preparation method comprises the following steps:

[0034] Step (i), prepare a first silicon wafer 1 and a second silicon wafer 2, the silicon wafers contain the required TSV structure 3, and the TSV structures of the two silicon wafers correspond to each other, which can be a low-resistance silicon vertical interconnection structure (Si-TSV structure) or a metal vertical interconnection structure (Met-TSV structure), see Figure 1 .

[0035] The thickness of the first and second silicon wafers is 200 μm-300 μm, and the resistivity is ≤0.1 Ω·cm.

[0036] The resistivity of the Si-TSV structure is 0.001 to 0.01 Ω·cm, and the insulating dielectric layer material is silicon oxide or silicon oxide-undoped polysilicon composite film structure. The commonly used Met-TSV structure is the Cu-TSV structure.

[0037] Step (ii): depositing a mask layer 4 on the surface of the first silicon wafer 1 and the surface of the second silicon wafer 2 by using a physical vapor deposition (PECVD) or chemical vapor deposition (LPCVD) process. Figure 2 .

[0038] The mask layer 4 may be silicon oxide, silicon nitride, or a composite mask layer of silicon oxide and silicon nitride.

[0039] Step (iii): on the surface of the mask layer 4, the mask layer 4 is patterned by photolithography, wet etching or dry etching process to prepare a first etching mask structure 5, the first etching mask structure 5 covers the TSV structure 3, and the non-covered part corresponds to the flow channel structure, see Figure 3 .

[0040] Step (iv), using a silicon wet etching process or a silicon dry etching process, prepare the flow channel structure 6 of the first silicon wafer 1 and the second silicon wafer 2, Figure 4 .

[0041] The depth h of the flow channel structure 6 is 50 μm-100 μm.

[0042] Step (V) using a wet etching process to remove the first etching mask structure 5 on the surface of the first silicon wafer 1 and the surface of the second silicon wafer 2, to obtain a third silicon wafer 7 and a fourth silicon wafer 8 with a flow channel structure 6. Figure 5 .

[0043] Step (six), using silicon-glass anodic bonding process, the third silicon wafer 7 and the first glass wafer 9 are bonded together to obtain a composite substrate. Figure 6 .

[0044] The first glass sheet 9 is borosilicate glass or photolithographic glass with a thickness of ≤100 μm. The anodic bonding process parameters are bonding voltage 300V-500V, bonding pressure 300N-500N, bonding temperature 800°C, and bonding vacuum degree is normal pressure.

[0045] Step (VII): Wet etching is used to thin the first glass sheet 9, and then the first glass sheet 9 is polished by chemical mechanical polishing. At this time, the composite substrate comprises the thinned first glass sheet 9 (defined as the second glass sheet 10) and the third silicon sheet 7. Figure 7 .

[0046] The thickness of the second glass sheet 10 is ≤30 μm, preferably 10-30 μm, and the surface roughness after polishing is ≤5 nm.

[0047] Step (eight), on the surface of the second glass sheet 10, a composite metal layer mask Cr / Au is prepared by a magnetron sputtering process or an electron beam evaporation process, and the composite metal layer Cr / Au is patterned by photolithography and etching processes to obtain a second etching mask structure 11. The second etching mask structure 11 does not cover the flow channel structure 6 and the area above the conductor or semiconductor in the middle of the TSV structure 3, but covers the insulating dielectric layer of the TSV structure 3. Figure 8 .

[0048] The composite metal layer mask Cr / Au includes a Cr metal layer and an Au metal layer; the Au metal layer is attached to the outer side of the Cr metal layer; the thickness of the Cr metal layer is 20nm-50nm; the thickness of the Au metal layer is 500nm-1000nm; the thickness of the Au metal layer is determined according to the thickness of the second glass sheet 10, 10μm thick glass corrosion requires an Au metal layer thickness of 500nm, 30μm thick glass corrosion requires an Au metal layer thickness of 1000nm; the composite metal layer mask Cr / Au requires nitridation treatment during the preparation process.

[0049] Step (IX): patterning the second glass sheet 10 by wet etching to form a contact window 12, the contact window 12 being located above the TSV structure 3, and removing the second etching mask structure 11 by wet etching to expose the conductor or semiconductor in the middle of the TSV structure 3 by the contact window 12. Fig. 9 .

[0050] Step (10): On the patterned second glass sheet 10, a composite metal layer is prepared by electron beam evaporation, and the composite metal layer is patterned and etched by a lift-off process to form a patterned electrode interconnection line 13 on the inner surface of the contact window 12. Fig.10 .

[0051] The electrode interconnection line 13 is a composite metal layer, including a Cr metal layer and an Au metal layer; the Au metal layer is attached to the outer side of the Cr metal layer; the thickness of the Cr metal layer is 20nm-50nm; the thickness of the Au metal layer is 200nm-300nm.

[0052] Step (eleven), using an anodic bonding process, the upper surface of the fourth silicon wafer 8 and the second glass wafer 10 of the composite substrate are bonded together, the fourth silicon wafer 8 is used as the lower silicon wafer, the second glass wafer 10 is used as the middle glass wafer, and the third silicon wafer 7 is used as the upper silicon wafer. The TSV structure 3 of the third silicon wafer 7 and the fourth silicon wafer 8 and the interconnection electrode structure 13 realize vertical interconnection of electrical signals, and a silicon substrate 15 and a sealed flow channel structure 14 in the silicon substrate are obtained. Fig.11 .

[0053] When the thickness of the second glass sheet 10 is 20 μm-30 μm, the anodic bonding process parameters are bonding voltage 100 V-150 V, bonding pressure 300 N-500 N, and bonding temperature 800-850° C.

[0054] Step (twelve), repeating the process of step (two) and step (three), preparing an insulating layer structure 16 on the upper surface of the silicon substrate 15, the insulating layer structure 16 covers the insulating dielectric layer of the TSV structure 3, but does not cover the area above the conductor or semiconductor in the middle of the TSV structure 3, see Fig.12 .

[0055] The insulating layer structure 16 may be silicon dioxide or a patternable polymer.

[0056] Step (thirteen), on the upper surface of the silicon substrate 15, a patterned electrical interconnection structure 17 is prepared by a stripping process, the insulating layer structure 16 and the electrical interconnection structure 17 together form a wiring layer 18, and the wiring layer 18 realizes the planar interconnection of the electrical signal in the X and Y directions, see Fig.13 .

[0057] The electrical interconnection structure 17 is a composite metal layer, including a Cr metal layer and an Au metal layer; the Au metal layer is attached to the outer side of the Cr metal layer; the thickness of the Cr metal layer is 20nm-50nm; the thickness of the Au metal layer is 200nm-300nm.

[0058] Step (fourteen), repeat the process of step (two), step (three) and step (four), prepare the inlet 19 and outlet 20 of the microchannel on the lower surface of the silicon substrate 15, see Fig.14 .

[0059] According to a second aspect of the present invention, there is provided a microfluidic packaging substrate, comprising a silicon substrate 15 and a wiring layer 18; the silicon substrate 15 comprises an upper silicon wafer 7 (i.e., a third silicon wafer 7), an intermediate glass wafer (i.e., a second glass wafer 10) and a lower silicon wafer 8 (i.e., a fourth silicon wafer 8) which are bonded to each other, and the two silicon wafers have corresponding TSV structures 3; the upper silicon wafer 7, the lower silicon wafer 8 and the intermediate glass wafer 10 have interconnected regions to form a sealed flow channel structure 14, and an inlet 19 and an outlet 20 connected to the sealed flow channel structure 14 are processed below the lower silicon wafer 8; the TSV structures of the upper silicon wafer 7 and the lower silicon wafer 8 are opposite, and a longitudinal through-hole structure is processed on the intermediate glass wafer 10 to form a contact window 12 corresponding to the TSV structure, and a patterned electrode interconnection line 13 is prepared on the inner surface of the contact window 12, and the TSV structures of the upper silicon wafer 7 and the lower silicon wafer 8 and the electrode interconnection line 13 realize vertical interconnection of electrical signals;

[0060] The wiring layer 18 is located on the upper surface of the silicon substrate 15, and includes an inner insulating layer structure 16 and an outer electrical interconnection line structure 17. The wiring layer 18 is used to realize planar interconnection of electrical signals in the X and Y directions.

[0061] The thickness of the upper silicon wafer and the lower silicon wafer is 200 μm-300 μm, and the resistivity is ≤0.1 Ω·cm.

[0062] The TSV structure can be a low-resistance silicon vertical interconnect structure (Si-TSV structure) or a metal vertical interconnect structure (Met-TSV structure). The resistivity of the Si-TSV structure is 0.001 to 0.01Ω·cm, and the insulating dielectric layer material is silicon oxide or silicon oxide-undoped polysilicon composite film structure. The commonly used Met-TSV structure is the Cu-TSV structure.

[0063] The intermediate glass sheet 10 is borosilicate glass or photolithographic glass, with a thickness of ≤30 μm, preferably 10-30 μm, and a surface roughness of ≤5 nm.

[0064] The electrode interconnection line 13 is a composite metal layer, including a Cr metal layer and an Au metal layer; the Au metal layer is attached to the outer side of the Cr metal layer; the thickness of the Cr metal layer is 20nm-50nm; the thickness of the Au metal layer is 200nm-300nm.

[0065] The insulating layer structure 16 may be silicon dioxide or a patternable polymer such as photoresist.

[0066] The electrical interconnection structure 17 is a composite metal layer, including a Cr metal layer and an Au metal layer; the Au metal layer is attached to the outer side of the Cr metal layer; the thickness of the Cr metal layer is 20nm-50nm; the thickness of the Au metal layer is 200nm-300nm.

[0067] The present invention has been described in detail above in conjunction with specific implementations and exemplary examples, but these descriptions cannot be understood as limiting the present invention. Those skilled in the art understand that, without departing from the spirit and scope of the present invention, a variety of equivalent substitutions, modifications or improvements may be made to the technical solution of the present invention and its implementation methods, all of which fall within the scope of the present invention. The scope of protection of the present invention shall be subject to the attached claims.

[0068] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

Claims

1. A microfluidic package substrate, characterized in that: The invention comprises a silicon substrate (15) and a wiring layer (18); the silicon substrate (15) comprises an upper silicon wafer (7), an intermediate glass wafer (10) and a lower silicon wafer (8) which are bonded to each other, and the two silicon wafers are provided with corresponding TSV structures (3); the upper silicon wafer (7), the lower silicon wafer (8) and the intermediate glass wafer (10) have mutually connected areas to form a sealed flow channel structure (14), and a flow channel inlet (19) and a flow channel outlet (20) are processed below the lower silicon wafer (8) to be connected to the sealed flow channel structure (14); the TSV structures of the upper silicon wafer (7) and the lower silicon wafer (8) are opposite to each other, and a longitudinal through-hole structure is processed on the intermediate glass wafer (10) to form a contact window (12) corresponding to the TSV structure, and a patterned electrode interconnection line (13) is prepared on the inner surface of the contact window (12), and the TSV structures of the upper silicon wafer (7) and the lower silicon wafer (8) and the electrode interconnection line (13) realize vertical interconnection of electrical signals; The wiring layer (18) is located on the upper surface of the silicon substrate (15), and comprises an inner insulating layer structure (16) and an outer electrical interconnection line structure (17). The wiring layer (18) is used to realize planar interconnection of electrical signals.

2. The microfluidic package substrate according to claim 1, characterized in that: The thickness of the upper silicon wafer and the lower silicon wafer is 200 μm-300 μm, and the resistivity is ≤0.1 Ω·cm; and / or The intermediate layer glass sheet is borosilicate glass or photolithographic glass, with a thickness of ≤30 μm and a surface roughness of ≤5 nm.

3. The microchannel package substrate according to claim 1, characterized in that: The electrode interconnection line (13) is a composite metal layer, including a Cr metal layer and an Au metal layer; the Au metal layer is attached to the outer side of the Cr metal layer; the Cr metal layer has a thickness of 20nm-50nm; the Au metal layer has a thickness of 200nm-300nm; and / or The electrical interconnection structure (17) is a composite metal layer, comprising a Cr metal layer and an Au metal layer; the Au metal layer is attached to the outer side of the Cr metal layer; the thickness of the Cr metal layer is 20nm-50nm; the thickness of the Au metal layer is 200nm-300nm.

4. A method for preparing a microfluidic package substrate, characterized in that: The steps include: Step (1), preparing a first silicon wafer (1) and a second silicon wafer (2), wherein the silicon wafers already contain a desired TSV structure (3); depositing a mask layer (4) on the surface of the first silicon wafer (1) and the second silicon wafer (2), and patterning the mask layer (4) by photolithography, a wet etching process or a dry etching process to obtain a first etching mask structure (5); Step (ii), on the surfaces of the two silicon wafers, a silicon wet etching process or a silicon dry etching process is used to prepare the flow channel structure (6) of the first silicon wafer (1) and the second silicon wafer (2); Step (iii), using a wet etching process to remove the first etching mask structure (5) on the surface of the first silicon wafer (1) and the surface of the second silicon wafer (2), to obtain a third silicon wafer (7) and a fourth silicon wafer (8) with a flow channel structure (6); Step (iv), using a silicon-glass anodic bonding process to bond the third silicon wafer (7) and the first glass wafer (9) together to obtain a composite substrate; the anodic bonding process parameters are a bonding voltage of 300V-500V and a bonding pressure of 300N-500N; Step (V), using wet etching and chemical mechanical polishing processes to thin and polish the first glass sheet (9) to obtain a second glass sheet (10); Step (six), on the surface of the second glass sheet (10), a composite metal layer mask Cr / Au is prepared by a magnetron sputtering process or an electron beam evaporation process, and the composite metal layer Cr / Au is patterned by photolithography and etching processes to obtain a second etching mask structure (11); Step (seven), patterning the second glass sheet (10) by wet etching to form a contact window (12), wherein the contact window (12) is located above the TSV structure (3), and removing the second etching mask structure (11) so that the contact window (12) exposes the conductor or semiconductor in the middle of the TSV structure (3); Step (eight), preparing a composite metal layer on the patterned second glass sheet (10) by electron beam evaporation, patterning and etching the composite metal layer by a lift-off process, and forming a patterned electrode interconnection line (13) on the inner surface of the contact window (12); Step (nine), using an anodic bonding process to bond the upper surface of the fourth silicon wafer (8) and the second glass wafer (10) of the composite substrate together, with the fourth silicon wafer (8) serving as a lower silicon wafer, the second glass wafer (10) serving as an intermediate glass wafer, and the third silicon wafer (7) serving as an upper silicon wafer, to obtain a silicon substrate (15) and a sealed flow channel structure (14) in the silicon substrate; the anodic bonding process parameters are a bonding voltage of 100V-150V and a bonding pressure of 300N-500N; Step (10), repeating the process of step (1) to prepare an insulating layer structure (16) on the upper surface of the silicon substrate (15), wherein the insulating layer structure (16) covers the insulating dielectric layer of the TSV structure (3) but does not cover the area above the conductor or semiconductor in the middle of the TSV structure (3); Step (eleven), preparing a patterned electrical interconnection structure (17) on the upper surface of the silicon substrate (15) by a lift-off process, wherein the insulating layer structure (16) and the electrical interconnection structure (17) together form a wiring layer (18); Step (twelve), repeat the process of steps (a) and (b) to prepare the inlet (19) and outlet (20) of the microchannel on the lower surface of the silicon substrate (15).

5. The method for preparing a microfluidic package substrate according to claim 4, characterized in that: In step (1), the TSV structure (3) is a low-resistance silicon vertical interconnect structure or a metal vertical interconnect structure; The mask layer (4) is silicon oxide, silicon nitride, or a composite mask layer of silicon oxide and silicon nitride.

6. The method for preparing a microfluidic package substrate according to claim 4, characterized in that: In step (ii), the depth of the flow channel structure (6) is 50 μm-100 μm.

7. The method for preparing a microfluidic package substrate according to claim 4, characterized in that: In step (iv), the first glass sheet (9) is borosilicate glass or photolithographic glass, with a thickness of ≤100 μm; The bonding temperature of the anodic bonding process parameters is 800° C. and the bonding vacuum degree is normal pressure.

8. The method for preparing a microfluidic package substrate according to claim 4, characterized in that: In step (six), the composite metal layer mask Cr / Au includes a Cr metal layer and an Au metal layer; the Au metal layer is attached to the outer side of the Cr metal layer; the thickness of the Cr metal layer is 20nm-50nm; the thickness of the Au metal layer is 500nm-1000nm.

9. The method for preparing a microfluidic package substrate according to claim 4, characterized in that: In step (nine), the thickness of the second glass sheet (10) is 20 μm-30 μm, and the bonding temperature of the anodic bonding process parameters is 800° C.

10. The method for preparing a microfluidic package substrate according to claim 4, characterized in that: In step (eight), the electrode interconnection line (13) is a composite metal layer, including a Cr metal layer and an Au metal layer; the Au metal layer is attached to the outer side of the Cr metal layer; the thickness of the Cr metal layer is 20nm-50nm; the thickness of the Au metal layer is 200nm-300nm; In step (eleven), the electrical interconnect structure (17) is a composite metal layer, including a Cr metal layer and an Au metal layer; the Au metal layer is attached to the outer side of the Cr metal layer; the thickness of the Cr metal layer is 20nm-50nm; the thickness of the Au metal layer is 200nm-300nm.

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