Integrated assembly and method of forming an integrated assembly

Abstract

Embodiments of the present disclosure relate to integrated assemblies and methods of forming integrated assemblies. Some embodiments include an integrated assembly including a first structure including one or more transition metals and including a second structure over the first structure. The second structure has a first region directly against the first structure and has a second region spaced apart from the first structure by a gap region. The second structure includes a semiconductor material having at least one element selected from Group 13 of the periodic table and at least one element selected from Group 15 and Group 16 of the periodic table. An ionic compound is within the gap region. Some embodiments include a method of forming an integrated assembly.

Description

Technical Field

[0001] Integrated assemblies (e.g., integrated memory). Methods for forming integrated assemblies. Background Technology

[0002] The memory may use memory cells, which individually include access means (e.g., access transistors) combined with storage elements (e.g., capacitors, resistive memory devices, phase-change memory devices, etc.).

[0003] The goal is to develop improved transistors and improved memory architectures. Summary of the Invention

[0004] According to one embodiment of this disclosure, an integrated assembly is provided. The integrated assembly includes: a first structure comprising one or more transition metals; a second structure above the first structure and having a first region directly abutting the first structure and a second region spaced apart from the first structure by a gap region; and an ionic compound within the gap region. The second structure includes a semiconductor material comprising at least one element selected from Group 13 of the periodic table and at least one element selected from Groups 15 and 16 of the periodic table.

[0005] According to another embodiment of this disclosure, a memory configuration is provided. The memory configuration includes: a digital line comprising one or more transition metals; a transistor above the digital line and having an active region comprising a semiconductor material containing at least one element selected from Group 13 of the periodic table and at least one element selected from Groups 15 and 16 of the periodic table; an ionic compound within the gap region; and a memory element above and coupled to the active region. The active region is coupled to the digital line and has a lower surface having a first portion directly abutting the digital line and a second portion spaced apart from the digital line by the gap region. The transistor includes a gating structure operatively adjacent to the active region, wherein the gating structure is coupled to the word line. The ionic compound comprises at least one of the one or more transition metals from the digital line.

[0006] According to another embodiment of this disclosure, a method for forming an integrated assembly is provided. The method for forming the integrated assembly includes: forming a first structure comprising one or more transition metals; forming a second structure above the first structure and having a first region directly abutting the first structure and a second region spaced apart from the first structure by a gap region; and forming an ionic compound within the gap region. The second structure comprises a semiconductor material containing at least one element selected from Group 13 of the periodic table and at least one element selected from Groups 15 and 16 of the periodic table. Attached Figure Description

[0007] Figure 1 This is a schematic cross-sectional side view of an example assembly.

[0008] Figure 2A A schematic cross-sectional side view of an example assembly to illustrate an example problem.

[0009] Figure 2A-1 In order to be in Figure 2A The instance process phase following the process phase Figure 2A A schematic cross-sectional side view of an instance assembly, showing the assembly processed by an instance method for curing or at least alleviating an instance problem.

[0010] Figure 2B In order to be in Figure 2A After the process phase (and in) Figure 2A-1 (After the process phase) Instance process phase Figure 2A A schematic cross-sectional side view of an example assembly.

[0011] Figure 2B-1 To showcase Figure 2B A schematic cross-sectional side view of an enlarged area of ​​an example assembly.

[0012] Figure 3 This is a schematic cross-sectional side view of another example assembly.

[0013] Figure 4A and 4B To demonstrate the integration into the instance memory structure Figure 2B A schematic cross-sectional side view of an example assembly. Figure 4A view along Figure 4B The line AA, and Figure 4B view along Figure 4A BB line.

[0014] Figure 5 This is a schematic diagram of the instance region of an instance memory array. Detailed Implementation

[0015] Some embodiments include integrated assemblies having an ionic compound along the interface between the transistor active region and the underlying conductive structure. Some embodiments include memory cells and memory arrays. Some embodiments include methods of forming integrated assemblies, such as those comprising memory cells and memory arrays. Reference Figures 1 to 5 Describe an example implementation.

[0016] refer to Figure 1 The integrated assembly 10 includes a conductive first structure 12 extending within an insulating material 14.

[0017] The first structure 12 includes a conductive material 16. The conductive material 16 may include any suitable conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, molybdenum, tantalum, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, the conductive material 16 is a metal-containing material comprising one or more transition metals (wherein transition metals are to be understood as elements selected from Groups 3 to 12 of the periodic table, and including elements of the lanthanides and actinides). In some embodiments, the conductive material 16 is a metal-containing material comprising one or more of cobalt (Co), copper (Cu), iridium (Ir), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), titanium (Ti), and tungsten (W). The conductive material 16 may be homogeneous (as shown), or may be a layer of two or more different compositions, etc. In some embodiments, the conductive material 16 may include one or more metals, wherein at least one of such metals is in the form of a metal oxide, a metal silicide, a metal carbide, a metal nitride, and / or a metal boride.

[0018] The insulating material 14 may include any suitable composition, and in some embodiments may include one or both of silicon dioxide and silicon nitride, be mainly composed of one or both of them, or be composed of one or both of them. The insulating material 14 may be homogeneous (as shown) and may include a laminate of two or more different compositions, etc.

[0019] The conductive structure 12 and the insulating material 14 may be supported by a semiconductor substrate (not shown). The substrate may include semiconductor materials and may include, for example, monocrystalline silicon, be primarily composed of monocrystalline silicon, or be composed of monocrystalline silicon. The substrate may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction that includes semiconductor materials, including but not limited to bulk semiconductor materials, such as semiconductor wafers (alone or in combinations of other materials), and semiconductor material layers (alone or in combinations of other materials). The term "substrate" means any support structure, including but not limited to the semiconductor substrates described above.

[0020] The second structure 18 is located above the first structure 12 and has a lower surface 19 directly abutting the first structure. The second structure 18 includes a semiconductor material 20. The semiconductor material 20 may include any suitable composition, and in some embodiments may include at least one metal (e.g., one or more of aluminum, gallium, indium, thallium, tin, cadmium, zinc, etc.) combined with one or more of oxygen, nitrogen, sulfur, selenium, and tellurium, or be composed primarily of, or be composed of, such metals. In some embodiments, the semiconductor material 20 may include at least one element from Group 13 of the periodic table (e.g., gallium), and at least one element from Groups 15 and 16 of the periodic table (e.g., nitrogen, oxygen, etc.). For example, the semiconductor material 20 may include at least one element selected from the group consisting of gallium, indium, and mixtures thereof, and at least one element selected from the group consisting of oxygen, nitrogen, sulfur, selenium, tellurium, and mixtures thereof. In some embodiments, the semiconductor material 20 may include a semiconductor oxide (i.e., a semiconductor material including oxygen), be composed primarily of, or be composed of, semiconductor oxides. For example, in some embodiments, the semiconductor material 20 may include InGaZnO, be primarily composed of InGaZnO, or be composed of InGaZnO (wherein the chemical formula indicates the major component rather than a specific stoichiometry). The material 20 may be homogeneous and may include a layer of two or more different compositions, etc.

[0021] exist Figure 1 In the illustrated embodiment, structure 18 is configured as a vertically extending column. In other embodiments, structure 18 may have different configurations.

[0022] Structure 18 can be considered to include a central region (central portion) 22 and outer regions (outer portions) 24 and 26 on opposite sides of the central region. Outer regions 24 and 26 may include the same composition 20 as the central region 22, or may include a different composition relative to the central region 22. If outer regions 24 and 26 include a composition different from the central region 22, then outer regions 24 and 26 may include the same composition as each other or may include a different composition relative to each other.

[0023] In some embodiments, outer regions 24 and 26 may be configured as conductive regions. In such embodiments, outer regions 24 and 26 may include a conductive oxide material (e.g., a conductive metal oxide) 28. The conductive oxide material may include any suitable composition and in some embodiments may include one or more of oxygen-bonded indium, zinc, and tin, or be primarily composed of or composed of them. In some embodiments, the conductive oxide material 28 may include oxygen-bonded zinc (e.g., may include zinc oxide), and may further include one or both of aluminum and gallium. Aluminum and gallium may be present as dopants within the zinc oxide. In some embodiments, the conductive oxide material 28 may include oxygen-bonded indium (e.g., may include indium oxide), be primarily composed of, or be composed of them. Dopants may or may not be present within the indium oxide.

[0024] The dashed line 27 is provided to illustrate, in a schematic manner, the boundary in an embodiment in which the outer regions 24 and 26 may include a composition different from that of the central region 22.

[0025] In some embodiments, Figure 1 The assembly 10 can be formed by initially forming a first structure 12 to extend within an opening provided through the insulating material 14. Subsequently, material of a second structure is formed over the first structure 12 and patterned into the second structure 18.

[0026] Figure 1 The integrated assembly 10 has an idealized interface between the second structure 18 and the first structure 12. In practice, it can be etched into one or both of structures 12 and 18 during the patterning of the second structure 18 and / or during other process steps, which can produce… Figure 2A The gap region 30 is of the type shown. The gap region 30 undercuts a portion of the second structure 18, and allows for a more theoretically usable electrical connection between the second structure 18 and the first structure 12. Figure 1 The idealized configuration results in a worse electrical connection. Some embodiments involve providing a conductive material within the gap region 30 to improve the electrical connection between the first structure 12 and the second structure 18.

[0027] In some embodiments, Figure 2A The second structure 18 can be considered to have a configuration in which the first region 32 directly abuts the upper surface of the conductive first structure 12 and the second region 34 is spaced apart from the first structure 12 by a gap region 30. In the illustrated embodiment, the second region 34 is vertically offset from the upper surface of the conductive first structure 12.

[0028] The gap region 30 is shown to extend into the material of the second structure 18, but not into the material of the first structure 12. In other embodiments, in addition to extending into the material of the second structure 18, or alternatively into the material of the second structure, the gap region 30 may also extend into the material of the first structure 12.

[0029] In the illustrated embodiment, the gap region extends into the outer portion 24 of structure 18. Therefore, in some embodiments, the gap region 30 may extend into the conductive oxide material 28 of the outer region 24.

[0030] Electrodeless plating (and / or other suitable treatments) can be used to form ionic compounds 36 (e.g.) within the interstitial region 30. Figure 2A-1 (As shown in 2B and 2B-1). Ionic compound 36 may comprise one or more transition metals from the first material 16, one or more elements from the semiconductor material 20, one or more elements from the conductive oxide material 28 (in embodiments where material 28 is present), and / or may comprise one or more elements other than those present in materials 16, 20, and 28. Although material 36 is referred to as an "ionic compound," it should be understood that in some embodiments, the material may comprise a mixture of multiple ionic compounds. Such mixtures may or may not be homogeneous. The formation of ionic compound 36 within interstitial region 30 may be described as a "self-healing" process that cures the defects imparted by interstitial region 30.

[0031] Figure 2A-1 Assembly 10 is shown during an example electrodeless plating process at an example stage. Assembly 10 is provided within solution 38, and subsequently, an ionic compound 36 is generated. The ionic compound is shown as selectively plating material within the gap region 30. The ionic compound 36 may be plating along the surface of conductive material 16 and / or along the surface of metal oxide material 28 (when such material is present) and / or along the surface of semiconductor material 20 (specifically, if such surfaces are exposed along the gap region 30). In some embodiments, material 36 (ionic compound material) is selectively plating only within the gap region 30. In other embodiments, material 36 may extend beyond the gap region 30. If excess material 36 is problematic, such material can be removed using one or more suitable etching processes.

[0032] The ionic compound 36 may include one or more transition metals from the first structure 16. Alternatively, the ionic compound 36 may include one or more elements from the semiconductor material 20 and / or from the metal oxide material 28 (when present). Alternatively, the ionic compound 36 may include one or more elements from additives (e.g., ionic salts) provided within the solution 38. In some embodiments, the conductive material 16 of the first structure 12 includes tungsten, the second material 20 of the second structure 18 includes Ga, In, and Zn, and the ionic compound 36 includes or is primarily composed of one or more of gallium tungstate (Ga2[WO4]3), indium tungstate (In2[WO4]3), and zinc tungstate (Zn[WO4]); wherein tungsten is provided from the first structure 12, and gallium, indium, and / or zinc are provided from the second structure 18. In some embodiments, the conductive metal oxide 28 is present within the outer region 24 and includes one or both of indium oxide and zinc oxide, the first structure 12 includes tungsten, and the ionic compound 36 includes one or both of In2[WO4]3 and Zn[WO4] or is mainly composed of them; wherein tungsten is provided from the first structure 12, and indium and / or zinc are provided from the material 28 of the second structure 18.

[0033] Possible reactions that can be utilized during electrodeless plating in this example are:

[0034] (I)In→In 3+ +3e-

[0035] (II)Ga→Ga 3+ +3e-

[0036] (III) Zn→Zn 2+ +2e-

[0037] (IV)W + 4H₂O + 2e⁻ → WO₄ 2- +4H2

[0038] (V)In + (3 / 2)W + 6H2O → In 3+ +(3 / 2)WO4 2- +6H2 (E°=1.949)

[0039] (VI)Ga + (3 / 2)W + 6H₂O → Ga 3+ +(3 / 2)WO4 2- +6H2 (E°=2.14)

[0040] (VII) Zn + W + 4H₂O → Zn 2+ +WO4 2- +4H2 (E°=1.837)

[0041] (VIII)2In 3+ +3WO42- →2In2[WO4]3

[0042] (IX)2Ga 3+ +3WO4 2- →2Ga2[WO4]3

[0043] (X)Zn 2+ +WO4 2- →Zn[WO4]

[0044] The symbol E° represents the standard electrode potential. Reactions V, VI, and VII can occur spontaneously to form ionic compound 36. Such spontaneous reactions can occur at any suitable temperature and pressure, including, for example, room temperature (about 20°C) and atmospheric pressure (about 760 mm Hg).

[0045] Solution 38 may be alkaline, neutral, or acidic. In some embodiments, solution 38 may include water (e.g., deionized water). Besides water, solution 38 may or may not include additional additives. In some embodiments, solution 38 may include citric acid to make the solution acidic, or may include ammonium hydroxide to make the solution alkaline, etc. In some embodiments, solution 38 may include an additive known in the industry as SC1 (Standard Clean 1), which may contain ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2).

[0046] Solution 38 may contain one or more ionic salts having a cationic component incorporated into ionic compound 36. Example ionic salts may contain Ga... 3+ Sulfates, phosphates, citrates, etc., and Ga 3+ Gallium tungstate can be incorporated into ionic compound 36. Similarly, example ionic salts may contain Zn. 2+ In 3+ The cationic component within the ionic salt may or may not be the same as the element within the semiconductor material 20 and / or the conductive metal oxide 28 (when such conductive metal oxide is present).

[0047] This document describes example mechanisms for forming material 36 to help the reader understand some possible aspects of the invention, but does not limit the invention unless such mechanisms are expressly described in the appended claims (if any).

[0048] Figure 2B The assembly 10 is shown after the ionic compound 36 has been formed within the interstitial region 30. In the illustrated embodiment, the ionic compound 36 substantially completely fills the interstitial region 30. Generally, the material 36 may be formed to fill at least a majority of the interstitial region 30, and in some embodiments, it may be formed to fill the entire interstitial region.

[0049] Figure 2B-1exhibit Figure 2B An enlarged view of a portion of the assembly 10, showing that the ionic compound 36 substantially completely fills the gap region 30 to form a conductive interconnect 40 extending across the gap region 30 to improve the electrical connection between the first structure 12 and the second structure 18.

[0050] Figure 2B The embodiment illustrates a conductive interconnect 40 primarily along the upper surface of the conductive structure 12. In other embodiments, the conductive interconnect 40 of the ionic compound 36 may extend along one side of the first structure 12 and along the upper surface of the first structure 12, such as... Figure 3 As shown in the image.

[0051] In some embodiments, structures 12 and 18 may be incorporated into a memory configuration. Figure 4A and 4B The illustration shows a memory configuration 42 including structures 12 and 18 of assembly 10. The figures show cross-sectional views of the same configuration, in which... Figure 4A view along Figure 4B The line AA, and Figure 4B view along Figure 4A BB line.

[0052] The first conductive structure 12 corresponds to the digital line 44, and the second structure 18 corresponds to the active region 50 of the access transistor 46. The active region contains semiconductor material 20 within the central region 22 of structure 18, and conductive oxide material 28 within the outer regions 24 and 26 of structure 18. The boundary 27 is shown as a solid line to indicate... Figure 4A and 4B Such boundaries exist in the illustrated embodiments (but are not optional). In other embodiments, the metal oxide material 28 may be optional in the active region of the access transistor.

[0053] The outer regions 24 and 26 are the lower and upper conductive regions of the active region 50, respectively, and the central region 22 is the channel region of the active region 50. In some embodiments, regions 24 and 26 may be referred to as source / drain regions.

[0054] The lower conductive region 24 is electrically coupled to the digital line 44. The digital line 44 is a straight-line extending structure, which is relative to... Figure 4A The cross-sectional view extends into and out of the page, and its relative to... Figure 4B The cross-sectional view extends along the page.

[0055] The upper conductive region 26 is electrically coupled to the storage element 48. The storage element 48 can be any suitable device having at least two detectable states. In some embodiments, the storage element 48 can be, for example, a capacitor, a resistive memory device, a conductive bridging device, a phase-change memory (PCM) device, a programmable metallization cell (PMC), etc. If the storage element 48 is a capacitor, it can be a ferroelectric capacitor (i.e., it may include a ferroelectric insulating material between a pair of capacitor electrodes) or a non-ferroelectric capacitor (i.e., it may only include a non-ferroelectric insulating material between a pair of capacitor electrodes). Examples of ferroelectric insulating materials may include one or more of transition metal oxides, zirconium, zirconium oxide, niobium, niobium oxide, hafnium, hafnium dioxide, lead zirconium titanate, and barium strontium titanate. Examples of non-ferroelectric insulating materials may include silicon dioxide, be primarily composed of silicon dioxide, or be composed of silicon dioxide.

[0056] The access transistor 46 includes an insulating material 52 along the sidewalls of the active region 50. In the illustrated embodiment, the insulating material 52 extends to the upper surface of the upper conductive region 26. In other embodiments, the insulating material 52 may extend along the active region 50 to different heights.

[0057] The insulating material 52 may be referred to as the gate dielectric material. The insulating material 52 may include any suitable composition, and in some embodiments may include silicon dioxide and / or one or more high-k compositions (wherein the term "high-k" means a dielectric constant greater than that of silicon dioxide). Examples of high-k compositions (materials) include alumina, zirconium oxide, hafnium dioxide, etc.

[0058] A gate structure (conductive gate) 54 is adjacent to the active region 50. The gate structure 54 includes a conductive gate material 56. The conductive gate material may include any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, molybdenum, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.) and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.).

[0059] Conductive material 56 may be coupled to word line 58 (and in some embodiments may be a portion of the word line), the word line being relative to... Figure 4B The cross-sectional view extends into and out of the page.

[0060] The operation of transistor 46 involves gate-coupled conductive regions 24 and 26 to each other through central region 22 (region 22 may be referred to as the gated channel region, or simply the channel region). When used herein, the term "gate-coupled" refers to the controlled coupling / decoupling of regions 24 and 26 that can be triggered by the electrical activation / deactivation of word line 58. In some operating modes of transistor 46, the current through channel region 22 is induced by the electric field provided by gate structure 54 (word line 58), and thus digital line 44 is electrically coupled to memory element 48 through active region 50. In other operating modes, no suitable electric field is provided to channel region 22, and thus digital line 44 is decoupled from memory element 48.

[0061] Memory cell 60 can be considered to include access transistor 46 and memory element 48. A memory cell can refer to a number of substantially identical memory cells in a memory array (memory configuration 42), where the term "substantially identical" means identical within reasonable manufacturing and measurement tolerances. Similarly, word line 58 can refer to a number of substantially identical word lines, and digital line 44 can refer to a number of substantially identical digital lines. Figure 5 An example area of ​​the example memory array 70 is illustrated schematically. The memory array includes a plurality of memory cells 60, a plurality of digital lines 44 (labeled DL1 to DL3), and a plurality of word lines 58 (labeled WL1 to WL3). Each of the memory cells 60 is uniquely addressed by a combination of one of the word lines and one of the digital lines. The memory array may include any suitable number of memory cells, word lines, and digital lines; and in some embodiments may include thousands, hundreds of thousands, hundreds of millions, etc., of memory cells, and a suitable number of word lines and digital lines.

[0062] The assemblies and structures discussed above can be utilized within integrated circuits (where the term "integrated circuit" refers to electronic circuits supported by a semiconductor substrate); and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and special-purpose modules, and can comprise multi-layered, multi-chip modules. Electronic systems can be any of the following wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0063] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed by any suitable method now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0064] The terms “dielectric” and “insulating” are used to describe materials having insulating electrical properties. These terms are considered synonymous in this disclosure. The use of the term “dielectric” in some cases and the term “insulating” (or “electrically insulating”) in others may be for the purpose of providing linguistic variation within this disclosure to simplify the premises of the following claims, and not to indicate any significant chemical or electrical differences.

[0065] The terms "electrical connection" and "electrical coupling" are both used in this disclosure. The terms are considered synonymous. The use of one term in some cases and another in others may be to provide linguistic variation within this disclosure to simplify the premises of the following claims.

[0066] The specific orientations of the various embodiments in the drawings are for illustrative purposes only, and in some applications, embodiments may be rotated relative to the shown orientation. The description provided herein and the appended claims relate to any structure having the described relationships between various features, regardless of whether the structure is in or rotated relative to the specific orientation of the drawings.

[0067] Unless otherwise specified, the cross-sectional views accompanying the drawings show only the features within the plane of the cross-section and not the material behind the plane of the cross-section, in order to simplify the drawings.

[0068] When a structure is referred to above as being “on,” “adjacent to,” or “against” another structure, the structure may be directly on the other structure or there may be intervening structures. In contrast, when a structure is referred to as being “directly on,” “directly adjacent to,” or “directly against” another structure, there are no intervening structures. The terms “directly below,” “directly above,” etc., do not indicate direct physical contact (unless otherwise explicitly stated), but instead indicate upright alignment.

[0069] A structure (e.g., a layer, material, etc.) may be described as “vertically extending” to indicate that the structure typically extends upward from the underlying substrate (e.g., a base plate). A vertically extending structure may extend substantially orthogonally relative to or not relative to the upper surface of the substrate.

[0070] Some embodiments include an integrated assembly comprising a first structure containing one or more transition metals and a second structure above the first structure. The second structure has a first region directly abutting the first structure and a second region spaced apart from the first structure by a gap region. The second structure comprises a semiconductor material having at least one element selected from Group 13 of the periodic table and at least one element selected from Groups 15 and 16 of the periodic table. An ionic compound is present in the gap region.

[0071] Some embodiments include a memory configuration comprising a digital line containing one or more transition metals and a transistor above the digital line. The transistor has an active region comprising a semiconductor material containing at least one element selected from Group 13 of the periodic table and at least one element selected from Groups 15 and 16 of the periodic table. The active region is coupled to the digital line and has a lower surface having a first portion directly abutting the digital line and a second portion spaced apart from the digital line by a gap region. The transistor includes a gating structure operatively adjacent to the active region. The gating structure is coupled to the word line. An ionic compound is located within the gap region. The ionic compound comprises at least one of the one or more transition metals from the digital line. A memory element is located above and coupled to the active region.

[0072] Some embodiments include a method of forming an integrated assembly. A first structure is formed to include one or more transition metals. A second structure is formed over the first structure. The second structure has a first region directly abutting the first structure and a second region spaced apart from the first structure by a gap region. The second structure includes a semiconductor material comprising at least one element selected from Group 13 of the periodic table and at least one element selected from Groups 15 and 16 of the periodic table. An ionic compound is formed in the gap region.

[0073] As specified herein, the subject matter disclosed herein has been described in nearly concrete language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include exemplary embodiments. Therefore, the claims have the full scope as stated in the writings and should be properly interpreted in accordance with the principle of equivalence.

Claims

1. An integrated assembly comprising: The first structure contains one or more transition metals; The second structure is above the first structure and completely spans the first and second structures to establish an interface. The second structure has a first region that directly abuts against the first structure at the interface and a second region that is spaced apart from the first structure; The gap region is located at the interface; the second structure includes a semiconductor material comprising at least one element selected from Group 13 of the periodic table and at least one element selected from Groups 15 and 16 of the periodic table. as well as Ionic compounds, which are located in the interstitial region.

2. The integrated assembly of claim 1, wherein the ionic compound comprises at least one of the one or more transition metals from the first structure.

3. The integrated assembly according to claim 2, wherein the at least one of the one or more transition metals comprises one or more of cobalt, copper, iridium, molybdenum, ruthenium, tantalum, titanium, and tungsten.

4. The integrated assembly of claim 2, wherein the first structure comprises at least one of the one or more transition metals in the form of one or more of metal oxides, metal silicides, metal carbides, metal nitrides and metal borides.

5. The integrated assembly of claim 2, wherein the ionic compound further comprises one or more of the elements of the semiconductor material of the second structure.

6. The integrated assembly of claim 2, wherein the ionic compound further comprises one or more elements not present in the first structure or the second structure.

7. The integrated assembly of claim 2, wherein the first structure comprises tungsten, the second structure comprises gallium, and the ionic compound comprises gallium tungstate.

8. The integrated assembly of claim 2, wherein the first structure comprises tungsten, the second structure comprises indium, and the ionic compound comprises indium tungstate.

9. The integrated assembly of claim 2, wherein the one or more transition metals of the first structure are first transition metals, wherein the second structure includes one or more second transition metals, and wherein the ionic compound includes at least one of the second transition metals.

10. The integrated assembly of claim 9, wherein the one or more second transition metals comprise zinc, wherein the one or more first transition metals comprise tungsten, and wherein the ionic compound comprises zinc tungstate.

11. The integrated assembly of claim 1, wherein the second structure is included in a central portion between a pair of outer portions; wherein the central portion comprises the semiconductor material; wherein the outer portions comprise one or more conductive oxide materials; and wherein the first region and the second region are along the outer surface of one of the outer portions.

12. The integrated assembly of claim 11, wherein the external portions comprise the same conductive oxide material as each other.

13. The integrated assembly of claim 11, wherein the external portions comprise conductive oxide materials that are different from each other.

14. The integrated assembly of claim 11, wherein one of the external portions comprises indium oxide, wherein the first structure comprises tungsten, and wherein the ionic compound comprises indium tungstate.

15. The integrated assembly of claim 1, wherein the ionic compound fills at least a majority of the gap region.

16. The integrated assembly of claim 1, wherein the ionic compound fills the entire gap region.

17. A memory configuration comprising: Digital lines, which contain one or more transition metals; A transistor is provided above a digital line and has an active region comprising a semiconductor material containing at least one element selected from Group 13 of the periodic table and at least one element selected from Groups 15 and 16 of the periodic table; the active region is coupled to the digital line and has a lower surface having a first portion directly abutting the digital line and a second portion spaced apart from the digital line by a gap region; the transistor includes a gated structure operatively adjacent to the active region, wherein the gated structure is coupled to a word line. An ionic compound, wherein the ionic compound comprises at least one of the one or more transition metals from the digital line, within the gap region; as well as A storage element that is above and coupled to the active region.

18. The memory configuration of claim 17, wherein the memory element is a capacitor.

19. The memory configuration according to claim 17, wherein: The character line is one of many largely identical character lines; The digital line is one of many substantially the same digital lines; The memory cell includes the storage element and the transistor; and The memory cell is one of many substantially identical memory cells in a memory array, wherein each of the memory cells is uniquely addressed by one of the word lines in combination with one of the digital lines.

20. The memory configuration of claim 17, wherein the at least one of the one or more transition metals comprises one or more of cobalt, copper, iridium, molybdenum, ruthenium, tantalum, titanium, and tungsten.

21. The memory configuration of claim 17, wherein the ionic compound further comprises one or more of the elements of the active region.

22. The memory configuration of claim 17, wherein the ionic compound further comprises one or more elements not present in the active region or the digital line.

23. The memory configuration of claim 17, wherein the digital line comprises tungsten, the semiconductor material comprises one or both of indium and gallium, and the ionic compound comprises one or both of indium tungstate and gallium tungstate.

24. The memory configuration according to claim 17, wherein: The digital line comprises tungsten; The semiconductor material includes one or more of indium, gallium, and zinc; and The ionic compound includes one or more of indium tungstate, gallium tungstate, and zinc tungstate.

25. The memory configuration of claim 17, wherein the active region is contained in a central portion between a pair of outer portions; wherein the central portion comprises the semiconductor material; wherein the outer portions comprise one or more conductive oxide materials; and wherein the first portion and the second portion are along the outer surface of one of the outer portions.

26. The memory configuration of claim 25, wherein one of the external portions comprises indium oxide, wherein the digital line comprises tungsten, and wherein the ionic compound comprises indium tungstate.

27. A method of forming an integrated assembly, comprising: Forming a first structure comprising one or more transition metals; A second structure is formed, which is above the first structure and completely spans the first and second structures to establish an interface. The second structure has a first region directly abutting the first structure at the interface and a second region spaced apart from the first structure; a gap region is formed at the interface; the second structure includes a semiconductor material, the semiconductor material comprising at least one element selected from Group 13 of the periodic table and at least one element selected from Groups 15 and 16 of the periodic table; as well as Ionic compounds are formed in the interstitial region.

28. The method of claim 27, wherein the ionic compound comprises at least one of the one or more transition metals from the first structure.

29. The method of claim 27, wherein the ionic compound comprises at least one of the elements from the semiconductor material of the second structure.

30. The method of claim 27, wherein the ionic compound comprises: At least one of the one or more transition metals from the first structure; as well as At least one of the elements derived from the semiconductor material of the second structure.

31. The method of claim 27, wherein the formation of the ionic compound comprises exposing the interstitial region to water and one or more ionic salts dissolved in the water.

32. The method of claim 31, wherein the ionic compound comprises a cationic component derived from one or more ionic salts dissolved in the water.

33. The method of claim 32, wherein the cationic component comprises one of the elements of the semiconductor component.

34. The method of claim 32, wherein the cationic component is different from all the elements of the semiconductor component.

35. The method of claim 27, wherein the formation of the ionic compound comprises exposing the interstitial region to water.

36. The method of claim 27, wherein the formation of the ionic compound comprises exposing the interstitial region to acidic or alkaline conditions.

37. The method of claim 27, wherein the formation of the ionic compound comprises exposing the interstitial region to ammonium hydroxide or citric acid.

38. The method of claim 27, wherein the first structure is a digit line.

39. The method of claim 38, wherein the second structure is an active region of a transistor.

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