Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a semiconductor substrate, including a resistive region, on which a resistive structure material layer is formed; forming one or more parallel trenches in the resistive structure material layer within the resistive region, the trenches penetrating a portion of the resistive structure material layer's thickness; after forming the trenches, patterning the resistive structure material layer, removing a portion of the resistive structure material layer outside the trenches, and retaining the portion of the resistive structure material layer containing the trenches as the resistive structure; forming a dielectric layer on the semiconductor substrate at the side of the resistive structure, the dielectric layer also filling the trenches, and the dielectric layer exposing the top of the resistive structure; removing a portion of the resistive structure at the interface between the resistive structure and the dielectric layer along the extension direction of the resistive structure, forming an opening surrounded by the dielectric layer and the remaining resistive structure; and forming an electrode in the opening. The trenches formed at the top of the resistive structure reduce the probability of depression defects appearing on the top surface of the resistive structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] Integrated circuits typically include active and passive components. Active components include MOS transistors, while passive components include resistors. Resistors are indispensable components in integrated circuit design, and in integrated circuit design, the resistors can be polysilicon resistors or metal resistors.

[0003] In devices with metal gate structures, polysilicon resistor structures are typically used. Furthermore, the dimensions of currently described polysilicon resistor structures are generally large. Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a semiconductor substrate including a resistive region; a resistive structure located on the semiconductor substrate of the resistive region, wherein one or more parallel trenches are formed on the top of the resistive structure, the trenches penetrating a portion of the thickness of the resistive structure; electrodes located in the resistive region along the extending direction of the resistive structure, the electrodes being located on both sides of the resistive structure and connected to the sidewalls of the resistive structure; and a dielectric layer located on the semiconductor substrate on the sides of the resistive structure and electrodes, the dielectric layer further filling the trenches, the dielectric layer exposing the top of the resistive structure and electrodes.

[0006] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a semiconductor substrate including a resistive region, wherein a resistive structure material layer is formed on the semiconductor substrate of the resistive region; forming one or more parallel trenches in the resistive structure material layer in the resistive region, the trenches penetrating a portion of the thickness of the resistive structure material layer; after forming the trenches, patterning the resistive structure material layer, removing a portion of the resistive structure material layer outside the trenches, and retaining the portion of the resistive structure material layer containing the trenches as a resistive structure; forming a dielectric layer on the semiconductor substrate on the side of the resistive structure, the dielectric layer further filling the trenches, and the dielectric layer exposing the top of the resistive structure; removing a portion of the resistive structure at the junction of the resistive structure and the dielectric layer along the extension direction of the resistive structure, forming an opening surrounded by the dielectric layer and the remaining resistive structure; and forming an electrode in the opening.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] In the semiconductor structure provided by this invention, one or more parallel trenches are formed on the top of the resistor structure. During the formation of the resistor structure and dielectric layer, a planarization process is typically included. During planarization, if the resistor structure is large, severe dishing defects are likely to appear on its top surface. Furthermore, in this embodiment, the electrodes are located on both sides of the resistor structure along its extension direction, and the electrodes are only used to electrically connect the resistor structure. Therefore, the electrodes are relatively small, resulting in a larger remaining resistor structure size, making dishing defects more likely. Thus, by forming trenches on the top of the resistor structure, the contact area between the polishing pad and the top surface of the resistor structure during planarization is reduced, thereby reducing the probability of dishing defects on the top surface of the resistor structure, improving the flatness of the top surface, ensuring the integrity of the resistor structure, reducing the probability of resistance value shift, and ultimately improving the performance of the semiconductor structure.

[0009] In the semiconductor structure formation method provided by this invention, one or more parallel trenches are formed in the resistive structure material layer. During the formation of the resistive structure and dielectric layer, a planarization process is typically included. During planarization, if the resistive structure is large, severe dishing defects are likely to appear on its top surface. Furthermore, in this embodiment, the electrodes are formed on both sides of the resistive structure along its extension direction, and the electrodes are only used to electrically connect the resistive structure. Therefore, the electrodes are relatively small, resulting in a larger remaining resistive structure size, making dishing defects more likely. Thus, by forming trenches on the top of the resistive structure, the contact area between the polishing pad and the top surface of the resistive structure during planarization is reduced, thereby reducing the probability of dishing defects on the top surface of the resistive structure, improving the flatness of the top surface, ensuring the integrity of the resistive structure, reducing the probability of resistance value shift, and ultimately improving the performance of the semiconductor structure. Attached Figure Description

[0010] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0011] Figures 5 to 7 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0012] Figures 8 to 20This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0013] The performance of semiconductor structures still needs improvement. This paper analyzes the reasons why the performance of semiconductor structures still needs improvement, using one semiconductor structure formation method as an example.

[0014] refer to Figures 1 to 4 The diagram shows a schematic representation of each step in a method for forming a semiconductor structure.

[0015] refer to Figure 1 A semiconductor substrate 10 is provided, the semiconductor substrate 10 including a resistive region 10R and a device region 10H, a resistive structure material layer 20 is formed on the semiconductor substrate 10, the resistive structure material layer 20 including a metal barrier layer 22 and a top resistive layer 23 located on the metal barrier layer 22.

[0016] refer to Figure 2 The resistive structure material layer 20 is graphically represented, and the remaining resistive structure material layer 20 on the semiconductor substrate 10 in the resistive region 10R is retained as the resistive structure 30. In the device region 10H, the top resistive layer 23 on the remaining metal barrier layer 22 is retained as the pseudo gate layer 31.

[0017] After the resistive structure material layer 20 is patterned, the remaining metal barrier layer 22 in the resistive region 10R is used as the bottom resistive layer in the resistive structure 30.

[0018] Wherein, the extension direction of the resistor structure 30 is the first direction (not indicated), and the arrangement direction of the resistor structure 30 and the dummy gate layer 31 is the second direction (e.g., ...). Figure 2 (As shown in the X direction). The first direction is perpendicular to the second direction, and both the first and second directions are parallel to the surface of the semiconductor substrate 10.

[0019] refer to Figure 3 , Figure 3 It is a cross-sectional view along the second direction, showing that a dielectric layer 40 is formed on the semiconductor substrate 10 on the side of the resistor structure 30.

[0020] The process of forming the dielectric layer 40 usually includes a planarization process. However, since the linewidth of the resistor structure 30 is relatively large, a severe dent defect is likely to appear on the top of the resistor structure 30 after the planarization process.

[0021] refer to Figure 4 , Figure 4It is a cross-sectional view along the first direction. Along the first direction, a portion of the resistor structure 30 at the junction of the resistor structure 30 and the dielectric layer 40 is removed to form an opening surrounded by the dielectric layer 40 and the remaining resistor structure 30; an electrode 35 is formed in the opening.

[0022] During the formation of the electrode 35, a planarization process is usually included. This planarization process can easily cause the top surface of the resistor structure 30 to be further recessed, or even cause the top resistor layer 23 in the resistor structure 30 to be excessively recessed, thereby exposing the metal barrier layer 22 at its bottom. Since the metal barrier layer 22 has a significant impact on the resistance value of the resistor structure 30, it can easily cause the resistance value of the resistor structure 30 to shift.

[0023] Moreover, since the electrodes 35 are formed on both sides of the resistor structure 30 along the first direction (i.e., the extension direction of the resistor structure 30), the remaining resistor structure 30 is larger in size and more prone to dent defects.

[0024] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a semiconductor substrate including a resistive region, wherein a resistive structure material layer is formed on the semiconductor substrate of the resistive region; forming one or more parallel trenches in the resistive structure material layer in the resistive region, the trenches penetrating a portion of the resistive structure material layer; after forming the trenches, patterning the resistive structure material layer, removing a portion of the resistive structure material layer outside the trenches, retaining the portion of the resistive structure material layer containing the trenches as a resistive structure; forming a dielectric layer on the semiconductor substrate on the side of the resistive structure, the dielectric layer further filling the trenches, and the dielectric layer exposing the top of the resistive structure; removing a portion of the resistive structure at the interface between the resistive structure and the dielectric layer along the extension direction of the resistive structure, forming an opening surrounded by the dielectric layer and the remaining resistive structure; and forming an electrode in the opening.

[0025] In the semiconductor structure formation method provided by this invention, one or more parallel trenches are formed in the resistive structure material layer. During the formation of the resistive structure and dielectric layer, a planarization process is typically included. During planarization, if the resistive structure is large, severe dishing defects are likely to appear on its top surface. Furthermore, in this embodiment, the electrodes are formed on both sides of the resistive structure along its extension direction, and the electrodes are only used to electrically connect the resistive structure. Therefore, the electrodes are relatively small, resulting in a larger remaining resistive structure size, making dishing defects more likely. Thus, by forming trenches on the top of the resistive structure, the contact area between the polishing pad and the top surface of the resistive structure during planarization is reduced, thereby reducing the probability of dishing defects on the top surface of the resistive structure, improving the flatness of the top surface, ensuring the integrity of the resistive structure, reducing the probability of resistance value shift, and ultimately improving the performance of the semiconductor structure.

[0026] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] Reference Figures 5 to 7 A schematic diagram of an embodiment of the semiconductor structure of the present invention is shown, wherein, Figure 5 This is a top view of the resistor structure. Figure 6 yes Figure 5 Cross-sectional view based on the AA direction, Figure 7 yes Figure 5 Sectional view based on the BB direction.

[0028] For ease of illustration, Figure 7 The device area is not shown in the diagram, and Figure 7 Only the resistance region is shown.

[0029] The semiconductor structure includes: a semiconductor substrate 101 including a resistive region 101R; a resistive structure 301 located on the semiconductor substrate 101 of the resistive region 101R, wherein one or more parallel trenches (not shown) are formed at the top of the resistive structure 301, the trenches penetrating a portion of the thickness of the resistive structure 301; and an electrode 351 located in the resistive region 101R, along the extending direction of the resistive structure 301 (e.g., ...). Figure 7 and Figure 9In the X direction), the electrode 351 is located on both sides of the resistor structure 301 and is connected to the sidewall of the resistor structure 301; the dielectric layer 401 is located on the semiconductor substrate 101 on the side of the resistor structure 301 and the electrode 351, the dielectric layer 401 is also filled in the trench, and the dielectric layer 401 is exposed on the top of the resistor structure 301 and the electrode 351.

[0030] In the semiconductor structure provided by this embodiment of the invention, one or more parallel trenches are formed on the top of the resistor structure 301. During the formation of the resistor structure 301 and the dielectric layer 401, a planarization process is typically included. However, during planarization, if the size of the resistor structure 301 is large, severe dishing defects are likely to appear on the top surface of the resistor structure 301. Furthermore, in this embodiment, the electrodes 351 are located on both sides of the resistor structure 301 along the extension direction of the resistor structure 301, and the electrodes 351 are only used to electrically connect the resistor structure 301. Therefore, the size of the electrodes 351 is small, and the remaining resistor structure 301 is larger, making it more prone to dent defects. Therefore, by forming a groove on the top of the resistor structure 301, the contact area between the polishing pad and the top surface of the resistor structure 301 during the planarization process is reduced, thereby reducing the probability of dent defects appearing on the top surface of the resistor structure 301, improving the flatness of the top surface of the resistor structure 301, which helps to ensure the integrity of the resistor structure, thereby reducing the probability of resistance value shift of the resistor structure, and thus improving the performance of the semiconductor structure.

[0031] The semiconductor substrate 101 provides the basis for the process operation of forming the semiconductor structure.

[0032] In this embodiment, the semiconductor substrate 101 is made of silicon. In other embodiments, the semiconductor substrate may also be made of one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium phosphate. The semiconductor substrate may also be a silicon-on-insulator (SiI) semiconductor substrate or a germanium-on-insulator (CHI) semiconductor substrate, or other types of semiconductor substrates. The material of the semiconductor substrate 101 may be suitable for process requirements or easy to integrate.

[0033] In this embodiment, the semiconductor substrate 101 includes a resistive region 101R and a device region 101H. The resistive region 101R is used to form a resistive structure, and the device region 101H is used to form a MOS transistor.

[0034] In this embodiment, the device region 101H is a low-voltage (LV) device region used to form low-voltage devices. As an example, the operating voltage of the low-voltage device is less than 2V.

[0035] It should be noted that the semiconductor substrate 101 may further include a high-voltage device region (not shown) for forming a high-voltage device. The operating voltage of the high-voltage device is greater than that of the low-voltage device. As an example, the operating voltage of the high-voltage device is greater than 10V.

[0036] In this embodiment, the semiconductor structure further includes an isolation structure 111 located in the semiconductor substrate 101 of the resistive region 101R.

[0037] The isolation structure 111 is used to isolate the resistive structure 301 on the isolation structure 111 from the semiconductor substrate 101 to prevent short circuits between the resistive structure 301 and the well region in the semiconductor substrate 101. The isolation structure 111 is also used to achieve insulation between different devices. For example, in CMOS manufacturing processes, an isolation structure is typically formed between NMOS transistors and PMOS transistors. Specifically, the isolation structure 111 is a shallow trench isolation (STI) structure.

[0038] The material of the isolation structure 111 is an insulating material. In this embodiment, the material of the isolation structure 111 includes silicon oxide or silicon oxynitride.

[0039] It should be noted that in this embodiment, the metal gate structure of the second device region 101H is formed using a high-k first metal gate last process, and the resistor structure 301 and the dummy gate layer of the second device region 101H are formed together. The dummy gate layer is used to occupy space for the gate electrode layer of the second device region 101H.

[0040] Therefore, in this embodiment, the semiconductor structure further includes: a gate dielectric layer 211 located on the semiconductor substrate 101 of the device region 101H and the resistor region 101R; a metal barrier layer 221 located on the gate dielectric layer 211; and a gate electrode layer 361 located on the metal barrier layer 221 of the device region 101H.

[0041] In this embodiment, in the device region 101H, the gate dielectric layer 211, the metal barrier layer 221, and the gate electrode layer 361 constitute a metal gate structure.

[0042] The gate dielectric layer 211 is used to isolate the electrode 351 from the semiconductor substrate 101, and the gate electrode layer 361 from the semiconductor substrate 101.

[0043] The gate dielectric layer 211 is made of one or more of the following materials: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer 211 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. A high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. Specifically, the high-k dielectric material includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0044] It should be noted that the gate dielectric layer 211 may further include a gate oxide layer located between the high-k gate dielectric layer and the semiconductor substrate 101. As an example, the material of the gate oxide layer is silicon oxide.

[0045] The metal barrier layer 221 is used to isolate the gate dielectric layer 211 and the electrode 351, as well as the gate dielectric layer 211 and the gate electrode layer 361, to protect the gate dielectric layer 211. In addition, the metal barrier layer 221 is also used to prevent easily diffusible ions (e.g., Al ions) in the electrode 351 and the gate electrode layer 361 from diffusing into the gate dielectric layer 211.

[0046] Specifically, the material of the metal barrier layer 221 includes one or both of titanium nitride (TiN) and silicon-doped titanium nitride (TiSiN). In this embodiment, the material of the metal barrier layer 221 is titanium nitride.

[0047] The gate electrode layer 361 includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the formed transistor, and the electrode layer is used to bring out the electrical properties of the gate electrode layer 361.

[0048] The resistor structure 301 serves as a passive device in the integrated circuit.

[0049] In this embodiment, the resistor structure 301 includes a metal barrier layer 221 located in the resistor region 101R, and a top resistor layer 231 located on the metal barrier layer 221. The metal barrier layer 221 is used as the bottom resistor layer in the resistor structure.

[0050] In this embodiment, the resistor structure 301 is located on the isolation structure 111 of the resistor 101R region, so that the resistor structure 301 is insulated from the semiconductor substrate 101.

[0051] In this embodiment, the material of the top resistive layer 231 includes polycrystalline silicon.

[0052] It should be noted that since the resistance of the top resistive layer 231 is much greater than that of the metal barrier layer 221, the current of the resistor structure 301 mainly flows through the metal barrier layer 221 when it is working. Accordingly, compared with the top resistive layer 231, the metal barrier layer 221 has a greater influence on the resistance of the resistor structure 301.

[0053] In this embodiment, the trench penetrates a portion of the thickness of the resistor structure 301 while retaining a portion of the thickness of the resistor structure 301, thereby ensuring that the resistance of the resistor structure 301 meets performance requirements and protecting other film layers located under the resistor structure 301.

[0054] Specifically, the trench penetrates a portion of the thickness of the top resistive layer 231.

[0055] In this embodiment, the extension direction of the plurality of parallel grooves is the same as the extension direction of the resistor structure 301. This reduces the contact area between the grinding pad and the top surface of the resistor structure 301 during the planarization process by forming a smaller number of grooves, thereby saving process costs, reducing process complexity, and improving process efficiency.

[0056] In this embodiment, the arrangement direction of the plurality of parallel grooves is perpendicular to the extension direction of the resistor structure 301. Therefore, in the direction perpendicular to the extension direction of the resistor structure 301, a sufficient number of grooves are arranged according to the width of the resistor structure 301 to greatly reduce the contact area with the top surface of the resistor structure 301 during the planarization process, thereby reducing the probability of the top surface of the resistor structure 301 having a depression defect.

[0057] It should be noted that the depth h of the trench cannot be too large or too small. If the trench depth h is too large, too much of the resistor structure 301 will be removed, which may affect the resistance of the resistor structure 301. Moreover, if the trench depth h is too large, it may cause damage to other film layers below the trench during the formation of the trench. If the trench depth h is too small, the height of the resistor structure 301 protruding around the trench will be too small. During the planarization process of the dielectric layer 401, it is easy to remove the resistor structure 301 protruding around the trench. As a result, during the planarization process, it is easy to come into contact with the resistor structure 301 at the bottom of the trench, making it difficult to reduce the contact area with the top surface of the resistor structure 301 during the planarization process, and thus making it difficult to reduce the probability of the top surface of the resistor structure 301 having a depression defect. Therefore, in this embodiment, the trench depth h is 1 / 4 to 1 / 3 of the thickness of the resistor structure 301.

[0058] It should be noted that the width w1 of the trench cannot be too large or too small. If the trench width w1 is too large, too much of the resistor structure 301 will be removed, which may affect the resistance of the resistor structure 301. Moreover, during the planarization process, the dielectric layer 401 located in the trench is prone to severe top surface depression. If the trench width w1 is too small, the linewidth of the protruding resistor structure 301 around the trench will still be large, making it difficult to reduce the contact area with the top surface of the resistor structure 301 during the planarization process. This makes it difficult to reduce the probability of top surface depression defects of the resistor structure 301, and also increases the difficulty of the photolithography process used to form the trench. Therefore, in this embodiment, the trench width w1 is 0.15μm to 2μm.

[0059] It should also be noted that the distance w2 between adjacent trenches cannot be too large or too small. If the distance w2 between adjacent trenches is too large, that is, the linewidth of the protruding resistor structure 301 around the trench is still large, it will be difficult to reduce the contact area with the top surface of the resistor structure 301 during the planarization process, thus making it difficult to reduce the probability of the top surface of the resistor structure 301 having a depression defect. Moreover, the width w1 of the trench will be too small. If the distance w2 between adjacent trenches is too small, the width w1 of the formed trench will easily be too large, resulting in too much resistor structure 301 being removed, which can easily affect the resistance of the resistor structure 301. Furthermore, during the planarization process, the dielectric layer 401 located in the trench is prone to severe top surface depression. Therefore, in this embodiment, the distance w2 between adjacent trenches is 0.15μm to 2μm.

[0060] In this embodiment, the semiconductor structure further includes a protective layer 341 located on the sidewall of the trench.

[0061] During the planarization process of the resistor structure 301 and the dielectric layer 401, the protective layer 341 protects the resistor structure 301 on the trench sidewall, reduces the probability of over-grinding the resistor structure 301, further effectively reduces the probability of pitting defects on the top surface of the resistor structure 301, improves the flatness of the top surface of the resistor structure 301, and thus improves the performance of the semiconductor structure.

[0062] In this embodiment, the protective layer 341 conformally covers the sidewalls and bottom of the trench. Thus, the protective layer 341 not only protects the resistor structure 301 on the sidewalls of the trench, but also protects the resistor structure 301 at the bottom of the protective layer 341.

[0063] In this embodiment, the material of the protective layer 341 includes silicon nitride or silicon oxynitride.

[0064] The silicon nitride has high hardness, and during the planarization process, it can provide good protection for the resistive structure 301 on the sidewalls and bottom of the trench.

[0065] Along the extending direction of the resistor structure 301, the electrode 351 is located on both sides of the resistor structure 301 and is connected to the sidewall of the resistor structure 301, that is, the electrode 351 is connected to the end of the resistor structure 301.

[0066] Specifically, the electrode 351 is located on the metal barrier layer 221 on both sides of the top resistive layer 231.

[0067] The electrode 351 is used to make an electrical connection with the conductive plug, thereby realizing the electrical connection of the resistor structure 301 with other circuits.

[0068] The electrode 351 is located at the end of the resistor structure 301. Since the longer the resistor structure 301 is, the greater its resistance, by placing the electrode 351 at the end of the resistor structure 301, the length of the resistor structure 301 can be maximized, thereby enabling the resistor structure 301 to obtain a larger resistance.

[0069] In this embodiment, the electrode 351 is made of a metallic material. The metallic material has good conductivity, which is beneficial for improving the electrical connection performance between the resistor structure 301 and the external interconnect structure, thereby improving the electrical performance of the semiconductor structure.

[0070] In this embodiment, the electrode 351 and the gate electrode layer 361 in the MOS transistor have the same material and stacked structure, thereby enabling the electrode 351 and the gate electrode layer 361 in the MOS transistor to be formed in the same process. For example, the device gate structure used in the low-voltage device region is a metal gate structure. Using a metal gate structure is beneficial to improving the electrical performance of the MOS transistor and reducing leakage current.

[0071] Accordingly, during the formation of the semiconductor structure, the electrode 351 is formed simultaneously in the step of forming the gate electrode layer 361.

[0072] In this embodiment, the material of the electrode 351 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0073] In this embodiment, the electrode 351 and the gate electrode layer 361 are made of the same material, so the electrode 351 and the gate electrode layer 361 can be formed in the same step, which improves process efficiency and saves process costs.

[0074] The electrode 351 includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer, the electrode layer being used to draw out the electrical properties of the electrode 351.

[0075] The dielectric layer 401 serves as an isolation layer between adjacent devices.

[0076] In this embodiment, the dielectric layer 401 fills the trench and covers the sidewall of the protective layer 341, thereby improving the flatness of the top of the resistor structure 301 and providing a better process platform for subsequent manufacturing processes.

[0077] In this embodiment, the material of the dielectric layer 401 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0078] It should be noted that the process of forming the dielectric layer 401 usually includes a planarization process of the resistor structure 301 and the dielectric layer 401. In this embodiment, a groove is formed on the top of the resistor structure 301, which reduces the contact area between the polishing pad and the top surface of the resistor structure 301 during the planarization process, thereby reducing the probability of a depression defect appearing on the top surface of the resistor structure 301.

[0079] In this embodiment, the semiconductor structure further includes a capping layer 501 covering the dielectric layer 401, the resistive structure 301, and the electrode 351.

[0080] In this embodiment, the cover layer 401 also covers the gate electrode layer 361.

[0081] The cover layer 501 is used to provide a process platform for forming conductive plugs.

[0082] The material of the cover layer 501 is an insulating material. In this embodiment, the material of the cover layer 501 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0083] In this embodiment, the semiconductor structure further includes a conductive plug 511 that penetrates the top of the electrode 351 through the cover layer 501 and is electrically connected to the electrode 351.

[0084] The conductive plug 511 is used to achieve electrical connection of the electrode 351.

[0085] In this embodiment, the material of the conductive plug 511 includes tungsten, ruthenium, or cobalt.

[0086] It should be noted that the process of forming the electrode 351 usually includes a planarization process of the resistor structure 301 and the electrode 351. In this embodiment, a groove is formed on the top of the resistor structure 301, which reduces the contact area between the grinding pad and the top surface of the resistor structure 301 during the planarization process, thereby reducing the probability of a depression defect appearing on the top surface of the resistor structure 301.

[0087] It should also be noted that this embodiment improves the flatness of the top surface of the resistor structure 301, thereby improving the formation quality of the electrode 351, which in turn improves the electrical connection reliability between the conductive plug 511 and the electrode 351, and further improves the performance of the semiconductor structure.

[0088] Figures 8 to 20 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0089] refer to Figure 8 A semiconductor substrate 100 is provided, including a resistive region 100R, on which a resistive structure material layer 200 is formed.

[0090] The semiconductor substrate 100 provides the basis for subsequent process operations.

[0091] In this embodiment, the semiconductor substrate 100 is made of silicon. In other embodiments, the semiconductor substrate may also be made of one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium phosphate. The semiconductor substrate may also be a silicon-on-insulator (SiI) semiconductor substrate or a germanium-on-insulator (CHI) semiconductor substrate, or other types of semiconductor substrates. The material of the semiconductor substrate 100 may be suitable for process requirements or easy to integrate.

[0092] In this embodiment, the semiconductor substrate 100 includes a resistive region 100R, which is used to form a resistive structure.

[0093] In this embodiment, the semiconductor substrate 100 further includes a device region 100H, which is used to form a MOS transistor. The MOS transistor serves as an active device in an integrated circuit.

[0094] In this embodiment, the device region 100H is a low-voltage device region used to form low-voltage devices. As an example, the operating voltage of the low-voltage device is less than 2V.

[0095] It should be noted that the semiconductor substrate 100 may further include a high-voltage device region (not shown) for forming a high-voltage device. The operating voltage of the high-voltage device is greater than that of the low-voltage device. As an example, the operating voltage of the high-voltage device is greater than 10V.

[0096] It should also be noted that in this embodiment, the metal gate structure of the second device region 100H is formed by first forming a high k gate dielectric layer and then forming a metal gate (high kfirst metal gate last) process, and the resistor structure formed in the resistor region 100R and the dummy gate layer formed in the second device region 100H are formed together.

[0097] Therefore, in this embodiment, a gate dielectric layer 210 is also formed between the resistive structure material layer 200 and the semiconductor substrate 100, and the resistive structure material layer 200 includes a metal barrier layer 220 and a top resistive layer 250 located on the metal barrier layer 220.

[0098] The gate dielectric layer 210 is used to isolate the subsequently formed electrodes from the semiconductor substrate 100, and the subsequently formed gate electrode layer from the semiconductor substrate 100.

[0099] The gate dielectric layer 210 is made of one or more of the following materials: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer 210 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. A high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. Specifically, the high-k dielectric material includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0100] It should be noted that the gate dielectric layer 210 may further include a gate oxide layer located between the high-k gate dielectric layer and the semiconductor substrate 101. As an example, the material of the gate oxide layer is silicon oxide.

[0101] The metal barrier layer 220 is used to isolate the gate dielectric layer 210 from the subsequently formed electrodes, as well as the gate dielectric layer 210 from the subsequently formed gate electrode layer, to protect the gate dielectric layer 210. In addition, the metal barrier layer 220 is also used to prevent easily diffusible ions (e.g., Al ions) in the electrodes and gate electrode layers from diffusing into the gate dielectric layer 210.

[0102] Specifically, the material of the metal barrier layer 220 includes one or both of titanium nitride (TiN) and silicon-doped titanium nitride (TiSiN). In this embodiment, the material of the metal barrier layer 220 is titanium nitride.

[0103] The resistive structure material layer 200 is used to form a resistive structure in the future, and the metal barrier layer 220 of the resistive region 100R is used as a bottom resistive layer in the future.

[0104] In this embodiment, the material of the top resistive layer 250 includes polycrystalline silicon.

[0105] In this embodiment, the resistive structure material layer 200 is also formed on the semiconductor substrate 100 of the device region 100H, for use in preparation for the subsequent formation of a dummy gate layer in the device region 100H. The dummy gate layer occupies space for the formation of the metal gate structure.

[0106] In this embodiment, an isolation structure 110 is also formed in the semiconductor substrate 100 of the resistor region 101R.

[0107] A resistive structure is subsequently formed on the isolation structure 110. The isolation structure 110 is used to isolate the resistive structure from the semiconductor substrate 100 to prevent short circuits between the resistive structure and the well region in the semiconductor substrate 100. The isolation structure 110 is also used to achieve insulation between different devices. For example, in CMOS manufacturing processes, an isolation structure is typically formed between NMOS transistors and PMOS transistors. Specifically, the isolation structure 110 is a shallow trench isolation (STI) structure.

[0108] The isolation structure 110 is made of an insulating material. In this embodiment, the material of the isolation structure 110 includes silicon oxide or silicon oxynitride.

[0109] Reference Figure 9 and Figure 10 , Figure 10 This is a top view of the resistive structure material layer 200 of the resistive region 100R. Figure 9 yes Figure 10 Based on the cross-sectional view along the AA direction, one or more parallel trenches 230 are formed in the resistive structural material layer 200 in the resistive region 100R, the trenches 230 penetrating a portion of the thickness of the resistive structural material layer 200.

[0110] After the subsequent patterned resistive structure material layer 200 is formed to create a resistive structure located in the resistive region 100R, the trench 230 is located in the resistive structure.

[0111] The formation of the resistor structure and dielectric layer typically includes a planarization process. During planarization, if the resistor structure is large, severe dishing defects are likely to appear on its top surface. In this embodiment, the electrodes are formed on both sides of the resistor structure along its extension direction, and these electrodes are only used to electrically connect the resistor structure. Therefore, the electrodes are small, resulting in a larger remaining resistor structure size, which is more prone to dishing defects. By forming a trench 230 on the top of the resistor structure, the contact area between the polishing pad and the top surface of the resistor structure during planarization is reduced, thereby reducing the probability of dishing defects on the top surface of the resistor structure, improving the flatness of the top surface, ensuring the integrity of the resistor structure, reducing the probability of resistance value shift, and ultimately improving the performance of the semiconductor structure.

[0112] In this embodiment, the trench 230 penetrates a portion of the thickness of the resistive structure material layer 200, while retaining a portion of the thickness of the resistive structure material layer 200, thereby maintaining the normal performance and resistance of the subsequent resistive structure and protecting the metal barrier layer 220 located under the resistive structure material layer 200 to reduce or avoid the influence on the resistance value of the resistive structure.

[0113] Specifically, the trench 230 penetrates a portion of the thickness of the top resistive layer 250.

[0114] In this embodiment, a dry etching process is used to form one or more parallel trenches 230.

[0115] The dry etching process has the characteristics of anisotropic etching. Therefore, by selecting the dry etching process, it is beneficial to reduce the damage to the remaining resistive structure material layer 200 on the side of the trench 230. At the same time, the dry etching is more directional, which is beneficial to improve the sidewall morphology quality and dimensional accuracy of the trench 230.

[0116] In this embodiment, the extension direction of the plurality of parallel grooves 230 is the same as the extension direction of the resistor structure material layer 200. This can reduce the contact area with the top surface of the resistor structure 301 during the planarization process by forming a smaller number of grooves, thereby saving process costs, reducing process complexity, and improving process efficiency.

[0117] In this embodiment, the arrangement direction of the plurality of parallel grooves 230 is perpendicular to the extension direction of the resistive structure material layer 200. In the direction perpendicular to the extension direction of the resistive structure material layer 200, a sufficient number of grooves 230 are arranged according to the width of the resistive structure 300, which greatly reduces the contact area with the top surface of the resistive structure during the planarization process, thereby reducing the probability of dent defects appearing on the top surface of the resistive structure.

[0118] It should be noted that the depth h of the trench 230 cannot be too large or too small. If the depth h of the trench 230 is too large, too much of the resistive structure material layer 200 will be removed, which may damage the metal barrier layer 220 below the trench 230, thereby affecting the resistance value of the resistive structure 300. If the depth h of the trench 230 is too small, the height of the resistive structure protruding around the trench 230 will be too small. During the planarization process of the dielectric layer 401, the resistive structure protruding around the trench 230 may be easily removed. This may lead to contact with the resistive structure at the bottom of the trench 230 during the planarization process, making it difficult to reduce the contact area with the top surface of the resistive structure during the planarization process, and thus making it difficult to reduce the probability of a depression defect appearing on the top surface of the resistive structure. Therefore, in this embodiment, the depth h of the trench 230 is 1 / 4 to 1 / 3 of the thickness of the resistive structure material layer 200.

[0119] It should be noted that the width w1 of the trench 230 cannot be too large or too small. If the width w1 of the trench 230 is too large, a dielectric layer will be formed in the trench 230 later. During the planarization process, the dielectric layer in the trench is prone to severe top surface depression. If the width w1 of the trench 230 is too small, the linewidth of the protruding resistor structure around the trench 230 will still be large. Therefore, during the planarization process, it will be difficult to reduce the contact area with the top surface of the resistor structure, thus making it difficult to reduce the probability of depression defects on the top surface of the resistor structure. Moreover, it will also increase the process difficulty of the photolithography and dry etching processes used to form the trench 230. Therefore, in this embodiment, the width w1 of the trench 230 is 0.15μm to 2μm.

[0120] It should also be noted that the distance w2 between adjacent trenches 230 cannot be too large or too small. If the distance w2 between adjacent trenches 230 is too large, that is, the linewidth of the protruding resistor structure around the trench 230 is still large, it will be difficult to reduce the contact area with the top surface of the resistor structure during the planarization process, thus making it difficult to reduce the probability of depression defects on the top surface of the resistor structure. Moreover, this will result in the width w1 of the trench 230 being too small. If the distance w2 between adjacent trenches 230 is too small, it will easily lead to the width w1 of the formed trench 230 being too large. Subsequently, a dielectric layer will be formed in the trench 230. During the planarization process, the dielectric layer in the trench 230 is prone to severe top surface depression problems. Furthermore, it will easily increase the process difficulty of the photolithography and dry etching processes for forming the trench 230. Therefore, in this embodiment, the distance w2 between adjacent trenches 230 is 0.15μm to 2μm.

[0121] Reference Figure 11 and Figure 12 , Figure 11 and Figure 12 Based on Figure 9 The cross-sectional view shows that after the trench 230 is formed, the resistive structure material layer 200 is graphically represented. A portion of the resistive structure material layer 200 outside the trench 230 is removed, and the portion of the resistive structure material layer 200 containing the trench 230 is retained as the resistive structure 300.

[0122] Retaining a portion of the resistive structure material layer 200 containing the trench 230 as the resistive structure 300 reduces the contact area between the polishing pad and the top surface of the resistive structure 300 during subsequent planarization. This reduces the probability of depressions on the top surface of the resistive structure 300, improves the flatness of the top surface, helps ensure the integrity of the resistive structure 300, and protects the integrity of the metal barrier layer 220. This reduces the probability of resistance shift in the resistive structure 300, thereby improving the performance of the semiconductor structure.

[0123] The resistor structure 300 serves as a passive device in an integrated circuit.

[0124] In this embodiment, the remaining metal barrier layer 220 and top resistive layer 250 in the resistive region 100R serve as the resistive structure 300, and the metal barrier layer 220 serves as the bottom resistive layer in the resistive structure 300.

[0125] In this embodiment, the resistor structure 300 is located on the isolation structure 110 of the resistor 100R region, so that the resistor structure 300 is insulated from the semiconductor substrate 100.

[0126] In this embodiment, the resistive structure material layer 200 directly forms the resistive structure 300; therefore, the material of the top resistive layer 250 includes polycrystalline silicon.

[0127] It should be noted that since the resistance of the top resistive layer 250 is much greater than that of the metal barrier layer 220, the current of the resistor structure 300 during operation mainly flows through the metal barrier layer 220. Accordingly, compared with the top resistive layer 250, the metal barrier layer 220 has a greater impact on the resistance of the resistor structure 300.

[0128] In this embodiment, after the trench 230 is formed and before a dielectric layer is subsequently formed on the semiconductor substrate 100 on the side of the resistor structure 300, a protective layer 340 is formed on the sidewall of the trench 230.

[0129] During the planarization process of the resistor structure 300 and the dielectric layer 400, the protective layer 340 protects the resistor structure 300 on the trench sidewall, reduces the probability of over-grinding the resistor structure 300, further effectively reduces the probability of pitting defects on the top surface of the resistor structure 300, improves the flatness of the top surface of the resistor structure 300, and thus improves the performance of the semiconductor structure.

[0130] In this embodiment, the protective layer 340 is formed before the dielectric layer is formed on the semiconductor substrate 100 on the side of the resistor structure 300. The protective layer 340 conformally covers the sidewalls and bottom of the trench 230, so that the protective layer 340 protects the resistor structure 300 on the sidewalls of the trench 230 and also protects the resistor structure 300 at the bottom of the protective layer 340.

[0131] In this embodiment, the material of the protective layer 340 includes silicon nitride or silicon oxynitride.

[0132] The silicon nitride has high hardness, and during the planarization process, it can provide good protection for the resistive structure 300 on the sidewalls and bottom of the trench.

[0133] Specifically, in this embodiment, the protective layer 340 is formed before patterning the resistive structure material layer 200, so that the protective layer 340 is also used as an etching mask for patterning the resistive structure material layer 200, which simplifies the process steps.

[0134] refer to Figure 11 The step of forming the protective layer 340 includes: forming a protective material layer 240 on the resistive structural material layer 200, wherein the protective material layer 240 conformally covers the bottom and sidewalls of the trench 230 and the top of the resistive structural material layer 200.

[0135] The protective material layer 240 is used to form the protective layer 340.

[0136] In this embodiment, the protective material layer 240 is formed using atomic layer deposition (ALD).

[0137] The protective material layer 240 formed by atomic layer deposition has good thickness uniformity and good step coverage, which allows the protective material layer 240 to cover the bottom and sidewalls of the trench 230 and the top of the resistive structure material layer 200 in good conformal manner.

[0138] refer to Figure 12 The protective material layer 240 outside the trench 230 is removed to form a protective layer 340 that conformally covers the bottom and sidewalls of the trench 230 and extends to cover part of the top of the resistive material layer 200.

[0139] The protective layer 340 is also used as an etching mask for patterning the resistive structure material layer 200.

[0140] In this embodiment, a dry etching process is used to remove part of the protective material layer 240 outside the trench 230.

[0141] The dry etching process has the characteristics of anisotropic etching. Therefore, by selecting the dry etching process, it is beneficial to reduce the damage to the resistive structure material layer 200. At the same time, the dry etching is more directional, which is beneficial to improve the sidewall morphology quality and dimensional accuracy of the protective layer 340 and the resistive structure 300.

[0142] Continue to refer to Figure 12 The step of graphically representing the resistive structure material layer 200 includes: using the protective layer 340 as a mask, removing the resistive structure material layer 200 exposed by the protective layer 340.

[0143] Using the protective layer 340 as a mask to form a resistor structure 300 is beneficial for forming a resistor structure 300 with high dimensional accuracy.

[0144] In this embodiment, during the step of patterning the resistive structure material layer 200, a portion of the top resistive layer 250 located on the semiconductor substrate 100 of the device region 100H is retained as a dummy gate layer 310.

[0145] The pseudo-gate layer 310 occupies space for the gate electrode layer to be formed in subsequent processes.

[0146] In this embodiment, the dummy gate layer 310 and the resistor structure 300 are formed in the same step, thereby simplifying the process steps for forming the semiconductor structure. Therefore, the dummy gate layer 310 is made of the same material as the top resistor layer 250.

[0147] In this embodiment, after the resistive structure material layer 200 is patterned, before the dielectric layer is subsequently formed, the method further includes: removing the gate dielectric layer 210 exposed by the resistive structure 300 and the pseudo gate layer 310.

[0148] refer to Figure 13 A dielectric layer 400 is formed on the semiconductor substrate 100 on the side of the resistor structure 300. The dielectric layer 400 also fills the trench 230 and exposes the top of the resistor structure 300.

[0149] The dielectric layer 400 serves as an isolation layer between adjacent devices.

[0150] In this embodiment, the dielectric layer 400 is formed using a chemical vapor deposition process.

[0151] In this embodiment, the dielectric layer 400 fills the trench 230 and covers the sidewall of the protective layer 340, thereby improving the flatness of the top of the resistor structure 300 and providing a better process platform for subsequent manufacturing processes.

[0152] In this embodiment, the dielectric layer 400 exposes the top of the resistor structure 300, in preparation for the subsequent removal of a portion of the resistor structure 300 to form an electrode.

[0153] In this embodiment, the dielectric layer 400 also exposes the top of the dummy gate layer 310, in preparation for the subsequent removal of the dummy gate layer 310.

[0154] In this embodiment, the material of the interlayer dielectric layer 400 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0155] In this embodiment, the step of forming the dielectric 400 layer includes: forming a dielectric material layer (not shown) covering the resistive structure 300 on the semiconductor substrate 100.

[0156] The dielectric material layer is used to form the dielectric layer 400.

[0157] In this embodiment, the material of the interlayer dielectric material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0158] In this embodiment, the step of forming the dielectric layer 400 further includes: planarizing the protective layer 340 on top of the resistor structure 300 and the dielectric material layer, and removing the protective layer 340 and the dielectric material layer that are higher than the top of the resistor structure 300.

[0159] By planarizing the protective layer 340 and the dielectric material layer on the top of the resistor structure 300, the top of the resistor structure 300 is exposed, which facilitates the subsequent formation of electrodes in the resistor structure 300. At the same time, a resistor structure 300 with a high top surface flatness is formed, providing a better process platform for subsequent fabrication.

[0160] It should be noted that during the planarization process of the top of the dielectric material layer, if the depth of the formed trench 230 is small or the dielectric material layer is excessively ground, the dielectric layer 400 in the trench 230 may be removed, thereby retaining the protective layer 340 in the trench 230. In this embodiment, the case in which the dielectric layer 400 is retained in the trench 230 is described.

[0161] Reference Figures 14 to 16 , Figure 14 This is a top view of resistor structure 300. Figure 15 yes Figure 14 Cross-sectional view based on the AA direction, Figure 16 Figure 14 Based on the cross-sectional view along the BB direction, a portion of the resistor structure 300 at the junction of the resistor structure 300 and the dielectric layer 400 is removed along the extension direction of the resistor structure 300, forming an opening 330 surrounded by the dielectric layer 400 and the remaining resistor structure 300.

[0162] The opening 330 is used to provide space for the subsequent formation of electrodes.

[0163] In this embodiment, the opening 330 is formed using a dry etching process.

[0164] In this embodiment, in the step of removing part of the resistor structure 300 at the junction of the resistor structure 300 and the dielectric layer 400, part of the top resistor layer 250 at the junction of the resistor structure 300 and the dielectric layer 400 is removed to form an opening 330 surrounded by the dielectric layer 400, the metal barrier layer 220 and the remaining top resistor layer 250, and the dummy gate layer 310 is also removed to form a gate opening 320.

[0165] The gate opening 320 is used to provide space for the subsequent formation of the gate electrode layer.

[0166] In this embodiment, the gate opening 320 is formed using a dry etching process.

[0167] Reference Figures 17 to 19 , Figure 17 This is a top view of resistor structure 300. Figure 16 yes Figure 17 Cross-sectional view based on the AA direction, Figure 19 Figure 17 Based on the cross-sectional view along the BB direction, an electrode 350 is formed in the opening 330.

[0168] In this embodiment, along the extending direction of the resistor structure 300, the electrode 350 is located between the resistor structure 300 and the dielectric layer 400. That is, the electrode 350 is connected to the end of the resistor structure 300. Specifically, the electrode 350 is located on the metal barrier layer 220 on both sides of the top resistor layer 250.

[0169] The electrode 350 is located at the end of the resistor structure 300. Since the longer the resistor structure 300 is, the greater its resistance, placing the electrode 350 at the end of the resistor structure 300 maximizes its length, thus enabling the resistor structure 300 to achieve a larger resistance.

[0170] The electrode 350 is used to make an electrical connection with the conductive plug, thereby enabling the electrical connection of the resistor structure 300 with other circuits.

[0171] In this embodiment, the electrode 350 is made of a metallic material. The metallic material has good conductivity, which is beneficial for improving the electrical connection performance between the resistive structure 300 and the external interconnect structure, thereby improving the electrical performance of the semiconductor structure.

[0172] In this embodiment, the electrode 350 and the gate electrode layer in the MOS transistor have the same material and stacked structure, thereby enabling the electrode 350 and the gate electrode layer in the MOS transistor to be formed in the same process. For example, the device gate structure used in the low-voltage device region is a metal gate structure. Using a metal gate structure is beneficial to improving the electrical performance of the MOS transistor and reducing leakage current.

[0173] Accordingly, in this embodiment, the electrode 350 is formed simultaneously during the step of forming the gate electrode layer of the MOS transistor, thereby simplifying the process steps for forming the semiconductor structure.

[0174] Continue to refer to Figure 18 The step of forming an electrode 350 in the opening 330 further includes forming a gate electrode layer 360 in the gate opening 320.

[0175] The gate electrode layer 360 is used to control the opening or closing of the transistor channel.

[0176] In this embodiment, the gate electrode layer 360 and the resistor structure 300 are formed in the same step, thereby simplifying the process steps for forming the semiconductor structure. Therefore, the gate electrode layer 360 and the electrode 350 are made of the same material.

[0177] In this embodiment, the metal gate structure is formed using a high-k first metalgate last process. Therefore, the metal gate layer 360 includes a work function layer (not shown) on the high-k gate dielectric layer and an electrode layer (not shown) on the work function layer. The work function layer is used to adjust the threshold voltage of the MOS transistor, and the electrode layer is used to bring out the electrical properties of the gate electrode layer 361.

[0178] In this embodiment, in the device region 100H, the gate dielectric layer 210, the metal barrier layer 220, and the gate electrode layer 360 constitute a metal gate structure.

[0179] It should be noted that the process of forming the electrode 350 and the gate electrode layer 360 usually includes a planarization process of the resistor structure 300, the electrode 350 and the gate electrode layer 360. In this embodiment, a groove is formed on the top of the resistor structure 300, which reduces the contact area between the polishing pad and the top surface of the resistor structure 300 during the planarization process, thereby reducing the probability of a depression defect appearing on the top surface of the resistor structure 300.

[0180] refer to Figure 20 , Figure 20 Based on Figure 19 A cross-sectional view shows a conductive plug 510 electrically connected to the electrode 350 formed on top of the electrode 350.

[0181] The conductive plug 510 is used to achieve electrical connection of the electrode 350.

[0182] In this embodiment, the material of the conductive plug 510 includes tungsten, ruthenium, or cobalt.

[0183] In this embodiment, before forming the conductive plug 510, the method further includes forming a cover layer 500 covering the dielectric layer 340, the resistive structure 300, and the electrode 350.

[0184] The cover layer 500 is used to provide a process platform for forming the conductive plug 510.

[0185] The material of the cover layer 500 is an insulating material. In this embodiment, the material of the cover layer 500 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.

[0186] In this embodiment, the cover layer 500 also covers the gate electrode layer 360.

[0187] In this embodiment, the step of forming a conductive plug 510 electrically connected to the electrode 350 on the top of the electrode 350 includes: forming a cover layer 500 that penetrates the top of the electrode 350 and exposes a conductive hole (not shown) of the electrode 350; and forming the conductive plug 510 in the conductive hole.

[0188] The conductive plug 510 penetrates the cover layer 500 at the top of the electrode 350, thereby achieving an electrical connection with the electrode 350.

[0189] It should also be noted that this embodiment improves the flatness of the top surface of the resistor structure 300, thereby improving the formation quality of the electrode 350, which in turn improves the electrical connection reliability between the conductive plug 510 and the electrode 350, and further improves the performance of the semiconductor structure.

[0190] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Semiconductor substrate, including resistive regions; A resistive structure is located on a semiconductor substrate in the resistive region, wherein one or more parallel trenches are formed on the top of the resistive structure, and the trenches are located in the resistive structure, the trenches penetrating a portion of the thickness of the resistive structure; Electrodes are located in the resistive region, along the extending direction of the resistive structure, on both sides of the resistive structure, and connected to the sidewalls of the resistive structure; A dielectric layer is located on a semiconductor substrate on the side of the resistor structure and electrodes, the dielectric layer also fills the trench, and the dielectric layer is exposed on top of the resistor structure and electrodes.

2. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes a protective layer located on the sidewall of the trench; The medium layer fills the trench and covers the sidewalls of the protective layer.

3. The semiconductor structure as described in claim 2, characterized in that, The protective layer conformally covers the sidewalls and bottom of the trench.

4. The semiconductor structure as described in claim 1, characterized in that, The extension direction of the plurality of parallel grooves is the same as the extension direction of the resistor structure. The arrangement direction of the plurality of parallel grooves is perpendicular to the extension direction of the resistor structure.

5. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes an isolation structure located in the semiconductor substrate of the resistive region; The resistor structure is located on the isolation structure of the resistor region.

6. The semiconductor structure as described in claim 1, characterized in that, The semiconductor substrate further includes a device region; The semiconductor structure further includes: a gate dielectric layer located on the semiconductor substrate of the device region and the resistor region; a metal barrier layer located on the gate dielectric layer; and a gate electrode layer located on the metal barrier layer of the device region. The resistive structure includes a metal barrier layer located in the resistive region, and a top resistive layer located on the metal barrier layer, wherein the metal barrier layer serves as the bottom resistive layer in the resistive structure. The electrodes are located on the metal barrier layers on both sides of the top resistive layer, and the electrodes and the gate electrode layer are made of the same material.

7. The semiconductor structure as described in claim 1, characterized in that, The depth of the trench is 1 / 4 to 1 / 3 of the thickness of the resistor structure.

8. The semiconductor structure as described in claim 1, characterized in that, The width of the groove is 0.15 μm to 2 μm, and the distance between adjacent grooves is 0.15 μm to 2 μm.

9. The semiconductor structure as described in claim 2, characterized in that, The material of the protective layer includes silicon nitride or silicon oxynitride.

10. The semiconductor structure as described in claim 6, characterized in that, The material of the metal barrier layer includes one or both of titanium nitride and silicon-doped titanium nitride; the material of the top resistive layer includes polycrystalline silicon.

11. The semiconductor structure as claimed in claim 1, characterized in that, The electrode material includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

12. The semiconductor structure as described in claim 5, characterized in that, The material of the isolation structure includes silicon oxide or silicon oxynitride.

13. The semiconductor structure as claimed in claim 6, characterized in that, The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

14. A method for forming a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, including a resistive region, wherein a resistive structure material layer is formed on the semiconductor substrate of the resistive region; In the resistive region, one or more parallel trenches are formed in the resistive structural material layer, the trenches penetrating a portion of the thickness of the resistive structural material layer; After the trench is formed, the resistive structure material layer is patterned, and a portion of the resistive structure material layer outside the trench is removed, leaving the portion of the resistive structure material layer containing the trench as the resistive structure. A dielectric layer is formed on a semiconductor substrate on the side of the resistor structure, the dielectric layer also fills the trench, and the dielectric layer is exposed on the top of the resistor structure; Along the extending direction of the resistive structure, a portion of the resistive structure at the interface between the resistive structure and the dielectric layer is removed to form an opening surrounded by the dielectric layer and the remaining resistive structure; An electrode is formed in the opening.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, After the trench is formed, and before a dielectric layer is formed on the semiconductor substrate on the side of the resistor structure, a protective layer is formed on the sidewall of the trench.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The protective layer is formed before the resistive structure material layer is patterned; The step of forming the protective layer includes: forming a protective material layer on the resistive structural material layer, the protective material layer conformally covering the bottom and sidewalls of the trench, and the top of the resistive structural material layer; Remove a portion of the protective material layer outside the trench to form a protective layer that conformally covers the bottom and sidewalls of the trench and extends to cover a portion of the top of the resistive material layer; The step of graphically representing the resistive structure material layer includes: using the protective layer as a mask, removing the resistive structure material layer exposed by the protective layer.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The step of forming the dielectric layer includes: forming a dielectric material layer covering the resistive structure on the semiconductor substrate; The protective layer and the dielectric material layer on top of the resistor structure are planarized, and the protective layer and the dielectric material layer that are higher than the top of the resistor structure are removed.

18. The method for forming a semiconductor structure as described in claim 14, characterized in that, In the step of providing a semiconductor substrate, the semiconductor substrate further includes a device region, and the resistive structure material layer is further formed on the semiconductor substrate of the device region. The resistive structure material layer includes a metal barrier layer and a top resistive layer located on the metal barrier layer, and a gate dielectric layer is further formed between the resistive structure material layer and the semiconductor substrate. In the step of patterning the resistive structure material layer, the remaining metal barrier layer and top resistive layer in the resistive region serve as the resistive structure. The metal barrier layer is used as the bottom resistive layer in the resistive structure, and a portion of the top resistive layer located on the semiconductor substrate of the device region is also retained as a dummy gate layer. After the resistive structure material layer is patterned and before the dielectric layer is formed, the method further includes: removing the gate dielectric layer exposed by the resistive structure and the dummy gate layer; In the step of forming the dielectric layer, the dielectric layer also exposes the top of the dummy gate layer; In the step of removing part of the resistive structure at the junction of the resistive structure and the dielectric layer, part of the top resistive layer at the junction of the resistive structure and the dielectric layer is removed to form an opening surrounded by the dielectric layer, the metal barrier layer and the remaining top resistive layer, and the dummy gate layer is also removed to form a gate opening in the device region; The step of forming an electrode in the opening further includes forming a gate electrode layer in the gate opening.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, The material of the metal barrier layer includes one or both of titanium nitride and silicon-doped titanium nitride, and the material of the top resistive layer includes polycrystalline silicon.

20. The method for forming a semiconductor structure as described in claim 16, characterized in that, The protective material layer is formed using atomic layer deposition (ALD).

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