A testability circuit for integrated circuit chips

Abstract

The present invention discloses a testability circuit for an integrated circuit chip, belonging to the field of integrated circuits. The circuit includes a counter and setter, a signal multiplexer, a signal latch, and an output multiplexer. The testability circuit for a hybrid digital-analog chip can conveniently and quickly observe the hybrid digital-analog interface signals within the chip and provide real-time monitoring of the chip's internal signals under normal operating mode. By utilizing a time-division multiplexing method, the circuit enables observation of important analog-digital interface signals and digital signals within the hybrid digital-analog chip. This circuit plays a crucial role in chip application development, particularly in the design and debugging of application software by application engineers developing MCU-type chips.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, in particular to a testability circuit of an integrated circuit chip. Background Art

[0002] With the advancement of integrated circuit technology, the number of functions and components in integrated circuits has rapidly expanded, and circuit structures have become increasingly complex, making chip testing and debugging increasingly difficult. This increased functionality has led to testing costs becoming an increasingly significant component of product costs. Testing time also directly impacts time to market, and thus economic benefits. Currently, one of the most effective methods for controlling testing costs is to employ design for testability (DFT) techniques during chip design. Circuit designers must consider test requirements when designing systems and circuits. The criteria for evaluating a circuit include not only performance and the number of components, but also testability, including ease of testing and test code generation. This is the essence of design for testability in integrated circuits.

[0003] Design for test (DFT) is widely used in digital circuits, and EDA tools, such as Synopsys' DFT compiler, facilitate DFT implementation. However, for mixed-signal interface signals, or for debugging and observing internal signals during normal operation, existing EDA tools lack a standard DFT methodology.

[0004] In addition, the testability design implemented by EDA tools is mainly used to test chip products during the production test process. However, there is currently no good solution to the need to observe internal key signals during the application development process of chips, especially MCU chips, and during the process of application engineers developing application software design and debugging. Summary of the Invention

[0005] The object of the present invention is to provide a testability circuit for an integrated circuit chip to solve the problems raised in the above background technology.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] A testability circuit for an integrated circuit chip includes a counter and setter, a signal multiplexer, a signal latch, and an output multiplexer.

[0008] The counter and setter is connected to the signal multiplexer and is used to select a designated input signal of the signal multiplexer;

[0009] The signal multiplexer is used to select the signal to be observed according to the selection signal output by the counter and setter, and send the signal to the signal latch and the output multiplexer;

[0010] The signal latch is used to latch the observation signal selected by the signal multiplexer and send it to the output multiplexer;

[0011] The output multiplexer is connected to the two selection signals SEL0 and SEL1, and selects the signal output by the signal multiplexer to be directly output or output after being latched, or selects the output signal in the normal mode;

[0012] As a further technical solution of the present invention: the counter and setter latches a designated selection signal or counts from 0 to a maximum count value to obtain a selection signal according to a count enable signal and a set enable signal.

[0013] As a further technical solution of the present invention: the output end of the output multiplexer is also connected to a digital output module.

[0014] As a further technical solution of the present invention: the digital output module processes the signal selected by the output multiplexer and outputs it to the PAD port.

[0015] As a further technical solution of the present invention: the counter and setter is connected to the signal set_en and the signal cnt_en. When the signal set_en is 1, it is a set function. At this time, no matter what the value of the signal cnt_en is, it sets the input 7-bit signal A[6:0] to the counter, so that the output S[6:0] = A[6:0].

[0016] As a further technical solution of the present invention: when the signal cnt_en is 1, the counter and setter performs a continuous counting function between 0 and the maximum count value, and performs a wrap-around operation after counting to the maximum value, that is, continuously performs the counting function from 0 to the maximum count value.

[0017] As a further technical solution of the present invention: the digital output module is an output IO module.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] The testability circuit for hybrid digital-analog chips of the present invention enables convenient and rapid observation of the chip's analog-digital interface signals and provides real-time monitoring of the chip's internal signals during normal operation. By utilizing time-division multiplexing, it enables observation of important analog-digital interface signals and digital signals within the hybrid digital-analog chip. This plays a crucial role in chip application development, particularly during the design and debugging of application software by application engineers developing MCU-type chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a circuit structure block diagram of the present invention.

[0021] Figure 2 This is a waveform diagram of a different configuration of the present invention.

[0022] Figure 3 yes Figure 2 Zoomed in view of the first portion of the waveform. DETAILED DESCRIPTION

[0023] The following is a clear and complete description of the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0024] Example 1, as Figure 1-3 As shown, a testability circuit of an integrated circuit chip includes: a counter and setter, a signal multiplexer, a signal latch ( Figure 1 REG) and output multiplexer;

[0025] The counter and setter latches the specified selection signal or counts from 0 to the maximum count value to obtain the selection signal according to the count enable signal and the set enable signal, and is used to select the specified input signal of the signal multiplexer.

[0026] The signal multiplexer is used to select a signal to be observed according to a selection signal output by the counter and setter, and send the signal to the signal latch and the output multiplexer.

[0027] The signal latch is used to latch the observation signal selected by the signal multiplexer and send it to the output multiplexer.

[0028] The output multiplexer can select the signal output by the signal multiplexer to be output directly or output after being latched through the two selection signals SEL0 and SEL1, and can also select the output signal in normal mode.

[0029] The digital output module processes the signal selected by the output multiplexer and outputs it to the PAD port.

[0030] In Example 2, based on Example 1, the digital output module may be a standard output IO module.

[0031] Here's how it works:

[0032] The counter and setter in the present invention can realize the setting and counting functions. Figure 1 When set_en is 1, it is a set function. At this time, regardless of the value of cnt_en, it sets the input 7-bit signal A[6:0] to the counter, making the output S[6:0] = A[6:0]. This function is used to directly select a signal for output observation.

[0033] Figure 1 When cnt_en is 1, the counter and setter perform continuous counting between 0 and the maximum count value. After counting to the maximum value, the counter and setter wrap around, that is, the counter continues to count from 0 to the maximum count value. This function is used to output all signals in sequence.

[0034] When both set_en and cnt_en are 0, the counter and setter maintain the previous bit value or count value and remain unchanged.

[0035] The signal multiplexer in the present invention is a module implemented using digital standard cells, whose output signal is the selected observation signal D_sel. A specific signal multiplexer may include seven selection signals S0-S6 and 128 internal signals; the seven selection signals S0-S6 are derived from the output of a counter and setter. The 128 internal signals are allocated as follows: the first eight signals, D0-D7, are fixed to 10101010 (AA), serving as the start code; the last eight signals, D120-D127, are fixed to 11110000 (F0), serving as the end code; and the 112 signals in the middle are key signals for the internal circuits, such as analog and digital module interface signals, external input PAD signals, and key internal digital signals that require testing and observation. This configuration aims to ensure that when cnt_en is 1, all internal signals to be observed are output sequentially, with the header code (AA) and tail code (F0) of the continuously output signals, facilitating the timing location of key signals.

[0036] The signal latch input is the observation signal D_sel selected by the signal multiplexer. This module can be implemented using a register, and its latched output is sent to the output multiplexer. The signal latch performs a signal sampling correction on the observation signal selected by the signal multiplexer, generating the latched signal D_sel_reg. This ensures that the pulse width of the signal observed by the PAD port remains consistent, preventing glitches from being sent to the PAD port when the multiplexer signal switches.

[0037] The output multiplexer can select the signal output by the signal multiplexer to be directly output as D_sel or to be output as D_sel_reg after being latched, through the two selection signals SEL0 and SEL1, or to select the output signal Out_signal in normal mode.

[0038] Combining the control signals from the counter and setter, the final output of the output multiplexer is shown in the following table. In the table, x indicates that both 0 and 1 are acceptable, i.e., don't care.

[0039] Table 1: Final output signal table of the output multiplexer;

[0040]

[0041]

[0042] Among them, when set_en and cnt_en are both 0, the output of the counter and setter remains unchanged and is determined by the previous state value.

[0043] Through the output multiplexer, the signal to be tested or observed can be output through the idle PAD pins under normal function, minimizing the PAD resources increased due to testability requirements.

[0044] The digital output module processes the signal selected by the output multiplexer and outputs it to the PAD port. This module can be a standard output IO module.

[0045] Figure 2 and Figure 3 There are two working waveforms. Figure 2 In the example, the first part is configured as 0110, which means all internal signals to be observed are latched and output in sequence, D_sel_reg; the second part is configured as 1010, which specifies the latch output of the selection signal, D_sel_reg; the third part is configured as 1000, which is the output signal configuration in normal mode, output Out_signal.

[0046] Figure 3 It is aimed at Figure 2 In the enlarged waveform of the first part, it can be seen that the PAD waveform follows the internal signal to be observed and continuously latches the output D_sel_reg in sequence; the start code AA and the end code F0, as well as the intermediate signal output, can be seen.

[0047] The testability circuit for hybrid digital-analog chips of the present invention enables convenient and rapid observation of the chip's analog-digital interface signals and provides real-time monitoring of the chip's internal signals during normal operation. By utilizing time-division multiplexing, it enables observation of important analog-digital interface signals and digital signals within the hybrid digital-analog chip. This plays a crucial role in chip application development, particularly during the design and debugging of application software by application engineers developing MCU-type chips.

[0048] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations that come within the meaning and range of equivalents of the claims be embraced therein.

[0049] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A testability circuit for an integrated circuit chip, comprising a counter and setter, a signal multiplexer, a signal latch, and an output multiplexer, characterized in that: The counter and setter is connected to the signal multiplexer and is used to select a designated input signal of the signal multiplexer; The signal multiplexer is used to select the signal to be observed according to the selection signal output by the counter and setter, and send the observed signal to the signal latch and the output multiplexer; The signal latch is used to latch the observation signal selected by the signal multiplexer and send it to the output multiplexer; The output multiplexer is connected to the two selection signals SEL0 and SEL1, and selects the signal output by the signal multiplexer to be directly output or output after being latched, or selects the output signal in the normal mode; The counter and setter latches a designated selection signal or obtains a selection signal by counting from 0 to a maximum count value according to a count enable signal and a set enable signal; The output end of the output multiplexer is also connected to the digital output module; The digital output module processes the signal selected by the output multiplexer and outputs it to the PAD port; The counter and setter is connected to the signal set_en and the signal cnt_en. When the signal set_en is 1, it is a set function. At this time, no matter what the value of the signal cnt_en is, it sets the input 7-bit signal A[6:0] to the counter, so that the output S[6:0]=A[6:0]; When the signal cnt_en is 1, the counter and setter perform a continuous counting function between 0 and the maximum count value, and perform a wrap-around operation after counting to the maximum value, that is, the counting function between 0 and the maximum count value is continuously performed.

2. The testability circuit of an integrated circuit chip according to claim 1, characterized in that: The digital output module is an output IO module.

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