Active stylus receiving circuit and touch panel system using active stylus

Abstract

A stylus receiving circuit receives a vector data signal emitted by a stylus, the vector data signal carrying vector data, the vector data including in-phase data and quadrature data, the stylus receiving circuit comprising: an integrating delta-sigma analog-to-digital converter converting the vector data signal into a one-bit bit stream using integrating delta-sigma operation; and a first logic gate circuit and a second logic gate circuit, the first logic gate circuit performing logical and quadrature operation on the one-bit bit stream and an in-phase modulated carrier signal to generate demodulated in-phase data, the second logic gate circuit performing logical and quadrature operation on the one-bit bit stream and a quadrature modulated carrier signal to generate demodulated quadrature data, whereby demodulated vector data is obtained.

Description

Technical Field

[0001] This invention relates to the technical field of active pens, and more particularly to an active pen receiving circuit and a touch panel system using an active pen. Background Technology

[0002] Active styluses are widely used in electronic devices with touch panels to provide input. An active stylus contains a transmitting circuit that emits modulated vector data signals, which are received by the touch panel to detect the stylus's coordinates. To correctly receive and demodulate the vector data signals emitted by the stylus, the touch panel is equipped with multiple sensors to detect these signals, and corresponding receiving circuits receive and demodulate these signals to obtain vector data.

[0003] In the aforementioned process of modulation, transmission, reception, and demodulation of vector data, the active pen modulates the vector data, for example, with a carrier wave. The vector data includes in-phase data and quadrature data. The modulated vector data signal is emitted by the active pen and received by the corresponding receiving circuit. The receiving circuit uses a successive-approximation register analog-to-digital converter (SAR ADC) to convert the received vector data signal into an N-bit digital signal (N is, for example, 10). Then, two multipliers demodulate this N-bit digital signal with in-phase carrier and quadrature carrier respectively to demodulate the in-phase data and quadrature data, so as to obtain the original vector data.

[0004] However, in the aforementioned architecture of a touch panel using an active pen, the touch panel needs a large number of sensors to correctly sense the vector data signals emitted by the active pen. Therefore, the number of corresponding receiving circuits is also extremely large. Each receiving circuit requires an analog-to-digital converter and two multipliers, resulting in the need for a large number of analog-to-digital converters and multipliers. This not only makes the hardware cost too high but also occupies too much circuit area, making it difficult to implement. In addition, since the data rate of the analog-to-digital converter determines the sampling rate of the signal emitted by the active pen, considering circuit area and power consumption, the data rate of a cyclic asymptotic analog-to-digital converter is generally 1.6MHz. Therefore, it is not easy to increase the sampling rate of the signal, which affects the quality of signal reception.

[0005] Therefore, the design of the existing active pen receiver circuit still has many shortcomings and needs to be improved. Summary of the Invention

[0006] The main purpose of this invention is to provide an active pen receiving circuit and a touch panel system using an active pen. By using an integral triangular analog-to-digital converter and logic AND gates to demodulate vector data, the quality of signal reception can be effectively improved. Furthermore, since no hardware multiplier is required, hardware costs can be significantly reduced and circuit area can be saved, thereby effectively reducing power consumption.

[0007] According to a feature of the present invention, an active pen receiving circuit is proposed. The active pen receiving circuit receives a vector data signal emitted by an active pen. The vector data signal carries vector data, which includes in-phase data and quadrature data. The active pen receiving circuit includes: an integral-delta analog-to-digital converter that converts the vector data signal into a 1-bit bit stream using integral-delta operations; and a first logic gate circuit and a second logic gate circuit. The first logic gate circuit performs a logical AND-quadrature operation on the 1-bit bit stream and the in-phase modulated carrier signal to generate demodulated in-phase data. The second logic gate circuit performs a logical AND-quadrature operation on the 1-bit bit stream and the quadrature modulated carrier signal to generate demodulated quadrature data, thereby obtaining the demodulated vector data.

[0008] According to another feature of the present invention, a touch panel system is proposed, comprising: an active pen that emits a vector data signal carrying vector data, wherein the vector data includes in-phase data and quadrature data; a touch panel having a plurality of sensors for sensing the vector data signal emitted by the active pen; and a receiving device having a plurality of active pen receiving circuits, each active pen receiving circuit being connected to at least one sensor, and comprising: an integral-delta analog-to-digital converter that converts the vector data signal into a 1-bit bit stream using integral-delta operations; and a first logic gate circuit and a second logic gate circuit, wherein the first logic gate circuit performs a logical AND-orthogonal operation on the 1-bit bit stream and the in-phase modulated carrier signal to generate demodulated in-phase data, and the second logic gate circuit performs a logical AND-orthogonal operation on the 1-bit bit stream and the quadrature modulated carrier signal to generate demodulated quadrature data, thereby obtaining the demodulated vector data. Attached Figure Description

[0009] Figure 1 This invention demonstrates a touch panel system using an active pen according to the present invention.

[0010] Figure 2 This diagram shows the vector data signal emitted by the active pen.

[0011] Figure 3 This is a schematic diagram of the active pen receiving circuit.

[0012] Figure 4 This is a circuit diagram of one embodiment of an active pen receiving circuit.

[0013] Figure 5 This is a circuit diagram of another embodiment of the active pen receiving circuit.

[0014] Figure 6 This is a circuit diagram of another embodiment of the active pen receiving circuit.

[0015] Active pen 10

[0016] Pen nib 11, Pen ring 13

[0017] Touch panel 20

[0018] Receiver 30 Active pen receiver circuit 31

[0019] Sensor Sx Multiplexer 40

[0020] Microcontroller 50 Integrated Circuit 60

[0021] Integral-trigonometric analog-to-digital converter 311

[0022] Logic gates 312 and 313

[0023] Equivalent logic AND units 321, 322

[0024] Input terminals a, b; Output terminal c Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of implementation methods and are not intended to limit the scope of the invention.

[0026] Figure 1 The diagram shows a touch panel system using an active pen according to the present invention, comprising an active pen 10, a touch panel 20, and a receiving device 30. The receiving device 30 is disposed in an integrated circuit (IC) 60, which further includes a plurality of multiplexers 40 and a microcontroller (MCU) 50. The active pen 10 has a tip 11 and a ring 13, capable of emitting vector data signals. The touch panel 20 has a plurality of sensors Sx arranged in a matrix, capable of sensing the vector data signals emitted by the tip 11 or ring 13 of the active pen 10. The receiving device 30 has a plurality of active pen receiving circuits 31 to receive and process the vector data signals to obtain vector data X(t).

[0027] Figure 2The diagram shows the aforementioned active pen 10 transmitting vector data signals. As shown in the figure, the aforementioned active pen 10 modulates the vector data X(t) with a carrier signal cos(2πωt)+sin(2πωt) so that the vector data signal carries the vector data X(t), wherein the vector data X(t) includes in-phase data Xi(t) and quadrature data Xq(t). The modulated vector data signal Xi(t)cos(2πωt)+Xq(t)sin(2πωt) is emitted by the pen tip 11 or pen ring 13 of the active pen 10.

[0028] Please refer to the above as well. Figure 1 and Figure 2 The aforementioned touch panel 20's sensor Sx can sense the vector data signal Xi(t)cos(2πωt)+Xq(t)sin(2πωt) emitted by the pen tip 11 or pen ring 13 of the active pen 10, and this signal is received by the corresponding active pen receiving circuit 31 of the receiving device 30. Each sensor Sx can correspond to one active pen receiving circuit 31. However, in practice, to reduce the number of active pen receiving circuits 31 required, each active pen receiving circuit 31 is connected to at least one sensor Sx. For example, N sensors Sx can be connected to one active pen receiving circuit 31 through an N-to-1 multiplexer 40, where N is an integer greater than 1. This allows one active pen receiving circuit 31 to receive the vector data signal Xi(t)cos(2πωt)+Xq(t)sin(2πωt) sensed by N sensors Sx in a multiplexed manner. That is, through the setting of the multiplexer 40, N sensors Sx correspond to one active pen receiving circuit 31. Figure 1 The figure shows N=4, but this is only an example and is not intended to limit the invention.

[0029] Figure 3The diagram above illustrates the aforementioned active pen receiving circuit 31. As shown, each active pen receiving circuit 31 includes an integrating delta-Sigma ADC 311, a first logic gate circuit 312, and a second logic gate circuit 313. The integrating delta-Sigma ADC 311 converts the received vector data signal Xi(t)cos(2πωt) + Xq(t)sin(2πωt) into a 1-bit digital signal using integrating delta operations. This 1-bit digital signal is then demodulated by the first logic gate circuit 312 and subjected to logical AND-orthogonal operations with the in-phase modulation carrier signal cos(2πωt), generating the demodulated in-phase data Xi(t). Similarly, the 1-bit digital signal is demodulated by the second logic gate circuit 313 and subjected to logical AND-orthogonal operations with the quadrature modulation carrier signal sin(2πωt), generating the demodulated quadrature data Xq(t). The demodulated vector data X(t) is then obtained and transmitted to the appropriate circuit. Figure 1 The microcontroller 50 shown is used for touch input, and the touch coordinates are obtained after calculation. Figure 3 The diagram shows that the first logic gate circuit 312 has a plurality of first equivalent logic AND units 321. Each first equivalent logic AND unit 321 has a first input terminal a connected to a 1-bit bit stream, a second input terminal b connected to a corresponding bit in the in-phase modulated carrier signal cos(2πωt), and an output terminal c for outputting in-phase data Xi(t). The second logic gate circuit 313 has a plurality of second equivalent logic AND units 322. Each second equivalent logic AND unit 322 has a first input terminal a connected to the 1-bit bit stream, a second input terminal b connected to a corresponding bit in the quadrature modulated carrier signal sin(2πωt), and an output terminal c for outputting quadrature data Xq(t). The number of equivalent logic AND units 321, 322 in each logic gate circuit 312, 313 is determined by the number of in-phase modulated carrier signals cos(2πωt) and... The accuracy of the quadrature modulation carrier signal sin(2πωt) is determined by the precision of the in-phase modulation carrier signal cos(2πωt). That is, when the in-phase modulation carrier signal cos(2πωt) or the quadrature modulation carrier signal sin(2πωt) has an accuracy of M bits, each logic gate circuit 312, 313 has M equivalent logic AND units 321, 322. Accordingly, one input terminal a of each of the M equivalent logic AND units 321, 322 is connected to the 1-bit bit stream output by the integrating delta analog-to-digital converter 311, and the other input terminal b is connected to 1 bit of the M bits of the in-phase modulation carrier signal cos(2πωt) or the quadrature modulation carrier signal sin(2πωt), so that the output terminal c of the M equivalent logic AND units 321, 322 of a logic gate circuit 312, 313 can output in-phase data Xi(t) or quadrature data Xq(t).

[0030] Figure 4 This is a circuit diagram of one embodiment of the active pen receiving circuit. In this embodiment, the aforementioned equivalent logic AND units 321 and 322 are implemented by AND gates. As shown in the figure, the first equivalent logic AND unit 321 or the second equivalent logic AND unit 321 is an AND gate, wherein the AND gate has two input terminals, which are respectively used as the first input terminal a and the second input terminal b of the first equivalent logic AND unit 321 or the second equivalent logic AND unit 322, and an output terminal, which is used as the output terminal c of the first equivalent logic AND unit 321 or the second equivalent logic AND unit 322.

[0031] Figure 5 This is a circuit diagram of another embodiment of the active pen receiving circuit. In this embodiment, the aforementioned equivalent logic AND units 321 and 322 are implemented by a 2-to-1 multiplexer. As shown in the figure, the first equivalent logic AND unit 321 or the second equivalent logic AND unit 322 is a 2-to-1 multiplexer, wherein the 2-to-1 multiplexer has a selection terminal as the first input terminal a of the first equivalent logic AND unit 321 or the second equivalent logic AND unit 322, two input terminals as the second input terminal b and input logic 0 of the first equivalent logic AND unit 321 or the second equivalent logic AND unit 322, respectively, and an output terminal as the output terminal c of the first equivalent logic AND unit 321 or the second equivalent logic AND unit 322.

[0032] Figure 6 This is a circuit diagram of another embodiment of the active pen receiving circuit. In this embodiment, the aforementioned equivalent logic AND units 321 and 322 are implemented by an OR gate and a NOT gate. As shown in the figure, the first equivalent logic AND unit 321 or the second equivalent logic AND unit 322 is composed of an OR gate and three NOT gates. The OR gate has two input terminals connected to a NOT gate to serve as the first input terminal a and the second input terminal b of the first equivalent logic AND unit 321 or the second equivalent logic AND unit 322, and an output terminal connected to a NOT gate to serve as the output terminal c of the first equivalent logic AND unit 321 or the second equivalent logic AND unit 322.

[0033] Accordingly, the present invention can implement logic gate circuits 312 and 313 with simple combinational logic elements, achieving the effect of signal demodulation without the need for complex multiplier circuits. In addition, besides using the aforementioned AND gate, 2-to-1 multiplexer, OR gate, and NOT gate, the aforementioned equivalent AND units 321 and 322 can also be implemented with other combinational logic elements, such as using a NAND gate with an output terminal connected to a NOT gate, or using a NOR gate with two input terminals respectively connected to two NOT gates.

[0034] The aforementioned integral-triangular analog-to-digital converter 311 is an oversampling rate analog-to-digital converter that utilizes noise shaving and oversampling techniques to achieve a sufficient signal-to-noise ratio (SNR). Its second-order input (In) / output (out) relationship can be expressed as:

[0035] out(z) = In(z) + Q(z) × (1-Z) -1 ) 2 ,

[0036] out(z)=In(z)*SFT+Q(z)*NFT,

[0037] Where z / Z represents z-domain transform, STF represents signal transfer function, Q(z) represents z-domain quantization noise, and NTF represents noise transfer function. When the input signal enters integral triangular modulation and undergoes oversampling and noise frequency shifting, it no longer undergoes digital filtering down-conversion. Instead, it directly obtains in-phase data (Xi_rx) and quadrature data (Xq_rx) through quadrature modulation. The noise, after frequency shifting, is filtered out by quadrature modulation, thus achieving the function of an analog-to-digital converter. Therefore, the signal processing performed by the aforementioned active pen receiving circuit 31 can be expressed as:

[0038] ADC IN =Xi×cos(2πωt)+Xq×sin(2πωt),

[0039] ADC OUT =ADC IN *SFT+Qn*NFT,

[0040] Xi_rx=Xi+Qn×NFT×cos(2πωt),

[0041] Xq_rx=Xq+Qn×NFT×sin(2πωt),

[0042] Among them, ADC IN Represents the input of the integrating delta analog-to-digital converter 311, ADC OUTXi represents the output of the in-phase analog-to-digital converter 311, Xq represents the quadrature data transmitted by the active pen 10, cos(2πωt) represents the in-phase modulated carrier signal, sin(2πωt) represents the quadrature modulated carrier signal, Xi_rx represents the output data of the active pen receiving circuit 31 (demodulated in-phase data), Xq_rx represents the output data of the active pen receiving circuit 31 (demodulated quadrature data), STF represents the signal transformation function, Qn represents the time domain quantization noise, and NTF represents the noise transformation function.

[0043] In the aforementioned active pen receiving circuit 31, the data rate of the integrating delta analog-to-digital converter 311 can reach 10MHz or higher, thus having an extremely high signal sampling rate, which can effectively improve the quality of signal reception. Furthermore, since the digital signal output by the integrating delta analog-to-digital converter 311 is a 1-bit bit stream, the 1-bit bit stream can be demodulated by performing logical and quadrature operations on the in-phase modulation carrier signal cos(2πωt) or the quadrature modulation carrier signal sin(2πωt) using logic gates 312 and 313. This not only simplifies the operation but also eliminates the need for hardware multipliers, thereby significantly reducing hardware costs and saving circuit area, and effectively reducing power consumption.

[0044] The above embodiments are merely illustrative examples for ease of explanation. The scope of the claims made in this invention should be determined by the claims themselves, and not limited to the above embodiments.

Claims

1. An active pen receiving circuit receiving a vector data signal emitted by an active pen, the vector data signal carrying vector data, the vector data comprising in-phase data and quadrature data, characterized in that, The active pen receiving circuit includes: an integrating delta sigma analog-to-digital converter for converting the vector data signal into a 1-bit bitstream through integrating delta sigma operation; and a first logic gate circuit and a second logic gate circuit, the first logic gate circuit performing logical and quadrature operation on the 1-bit bitstream and an in-phase modulated carrier signal to generate demodulated in-phase data, and the second logic gate circuit performing logical and quadrature operation on the 1-bit bitstream and a quadrature modulated carrier signal to generate demodulated quadrature data, so as to obtain the demodulated vector data, wherein the first logic gate circuit has a plurality of first equivalent logical and units, each first equivalent logical and unit having a first input end connected to the 1-bit bitstream, a second input end connected to a corresponding bit of the in-phase modulated carrier signal, and an output end for outputting the in-phase data; and the second logic gate circuit has a plurality of second equivalent logical and units, each second equivalent logical and unit having a first input end connected to the 1-bit bitstream, a second input end connected to a corresponding bit of the quadrature modulated carrier signal, and an output end for outputting the quadrature data.

2. Active pen receiving circuit according to claim 1, characterized in that, The vector data signal is Xi(t)cos(2πωt)+Xq(t)sin(2πωt), wherein Xi(t) represents in-phase data, Xq(t) represents quadrature data, cos(2πωt) represents an in-phase modulated carrier signal, and sin(2πωt) represents a quadrature modulated carrier signal.

3. Active pen receiving circuit according to claim 1, characterized in that, The data rate of the integrating delta sigma analog-to-digital converter is greater than or equal to 10 MHz.

4. The active pen receiving circuit of claim 1, wherein, The integrating delta sigma analog-to-digital converter has a second-order input / output relationship as follows: out(z) = In(z) + Q(z) x (1 - Z -1 )²; and out(z)=In(z)*STF+Q(z)*NTF, wherein z / Z represents z-domain conversion, STF represents a signal transfer function, Q(z) represents z-domain quantization noise, and NTF represents a noise transfer function.

5. The active pen receiving circuit of claim 1, wherein, The first equivalent logical and unit or the second equivalent logical and unit is a logical and gate having two input ends as the first input end and the second input end of the first equivalent logical and unit or the second equivalent logical and unit, and an output end as the output end of the first equivalent logical and unit or the second equivalent logical and unit.

6. The active pen receiving circuit of claim 1, wherein, The first equivalent logical and unit or the second equivalent logical and unit is a 2-to-1 multiplexer having a selection end as the first input end of the first equivalent logical and unit or the second equivalent logical and unit, two input ends as the second input end and the input logical 0 of the first equivalent logical and unit or the second equivalent logical and unit, and an output end as the output end of the first equivalent logical and unit or the second equivalent logical and unit.

7. The active pen receiving circuit of claim 1, wherein, The first equivalent logical and unit or the second equivalent logical and unit includes a logical or gate having two input ends connected to logical NOT gates as the first input end and the second input end of the first equivalent logical and unit or the second equivalent logical and unit, and an output end connected to a logical NOT gate as the output end of the first equivalent logical and unit or the second equivalent logical and unit.

8. A touch panel system, characterized by comprising: The active pen receiving circuit includes: A stylus, emitting a vector data signal carrying vector data, wherein the vector data comprises in-phase data and quadrature data; A touch panel, having a plurality of sensors to sense the vector data signal emitted by the stylus; and A receiving device, having a plurality of stylus receiving circuits, each stylus receiving circuit connected to at least one sensor, and comprising: An integrating delta-sigma analog-to-digital converter, converting the vector data signal into a 1-bit bitstream by integrating delta-sigma operation; and A first logic gate circuit and a second logic gate circuit, the first logic gate circuit performing logical and quadrature operation on the 1-bit bitstream and in-phase modulated carrier signal to generate demodulated in-phase data, and the second logic gate circuit performing logical and quadrature operation on the 1-bit bitstream and quadrature modulated carrier signal to generate demodulated quadrature data, thereby obtaining demodulated vector data, wherein the first logic gate circuit has a plurality of first equivalent logic and units, each first equivalent logic and unit having a first input connected to the 1-bit bitstream, a second input connected to a corresponding bit of the in-phase modulated carrier signal, and an output to output the in-phase data; and the second logic gate circuit has a plurality of second equivalent logic and units, each second equivalent logic and unit having a first input connected to the 1-bit bitstream, a second input connected to a corresponding bit of the quadrature modulated carrier signal, and an output to output the quadrature data.

9. The touch panel system of claim 8, wherein, The stylus modulates vector data with carrier signal to generate the vector data signal as: Xi(t)cos(2πωt)+Xq(t)sin(2πωt), wherein Xi(t) represents in-phase data, Xq(t) represents quadrature data, cos(2πωt) represents in-phase modulated carrier signal, and sin(2πωt) represents quadrature modulated carrier signal.

10. The touch panel system of claim 8, wherein, N sensors of the plurality of sensors in the touch panel are connected to a stylus receiving circuit through an N-to-1 multiplexer, wherein N is an integer greater than 1.

11. The touch panel system of claim 8, wherein, The data rate of the integrating delta-sigma analog-to-digital converter is greater than or equal to 10 MHz.

12. The touch panel system of claim 8, wherein, The integrating delta-sigma analog-to-digital converter has a second-order input / output relationship as: out(z) = In(z) + Q(z) x (1 - Z -1 )², out(z)=In(z)*STF+Q(z)*NTF, wherein z / Z represents z-domain conversion, STF represents signal transfer function, Q(z) represents z-domain quantization noise, and NTF represents noise transfer function.

13. The touch panel system of claim 8, wherein, The first equivalent logic and unit or the second equivalent logic and unit is a logic and gate having two inputs as the first input and the second input of the first equivalent logic and unit or the second equivalent logic and unit, and an output as the output of the first equivalent logic and unit or the second equivalent logic and unit.

14. The touch panel system of claim 8, wherein, The first equivalent logic AND unit or the second equivalent logic AND unit is a 2-to-1 multiplexer, which has a selection end as a first input end of the first equivalent logic AND unit or the second equivalent logic AND unit, two input ends as a second input end and an input logic 0 of the first equivalent logic AND unit or the second equivalent logic AND unit respectively, and an output end as an output end of the first equivalent logic AND unit or the second equivalent logic AND unit.

15. The touch panel system of claim 8, wherein, The first equivalent logic AND unit or the second equivalent logic AND unit comprises a logic OR gate, which has two input ends connected with a logic NOT gate as a first input end and a second input end of the first equivalent logic AND unit or the second equivalent logic AND unit respectively, and an output end connected with a logic NOT gate as an output end of the first equivalent logic AND unit or the second equivalent logic AND unit.

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