High energy efficiency orthogonal demodulation method and device based on envelope signal

Abstract

This invention discloses a high-efficiency orthogonal demodulation method and apparatus based on envelope signals. The method, applied at a receiving end, includes: recovering the amplitude and phase based on the envelope information of the orthogonal modulation signal; subtracting the recovered phase from the phase of the low-frequency local oscillator signal used for digital down-conversion to obtain the phase of the baseband signal, thereby achieving equivalent digital down-conversion; and reconstructing the I and Q components of the baseband signal based on the recovered amplitude and the baseband signal phase. This invention significantly simplifies the calculation process and improves processing speed and efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, and in particular to a high-energy-efficiency orthogonal demodulation method and device based on envelope signals. BACKGROUND

[0002] With the expansion of 5G / 6G wireless communication to millimeter wave (mmWave) and sub-terahertz (sub-THz) frequency bands, the local oscillator (LO) frequency synthesis, distribution, and phase-locked loop (PLL) circuit of traditional coherent receivers face problems such as high power consumption, large chip area, and complex implementation, which have become the main bottleneck for the improvement of system energy efficiency and integration.

[0003] As a new type of architecture without a local oscillator at the receiving end, the Kramers-Kronig (KK) receiver obtains the input signal amplitude by envelope detection, and reconstructs the phase using Hilbert transform, achieving equivalent signal demodulation to coherent receivers. The core signal relationship can be expressed as:

[0004]

[0005]

[0006] wherein, is a complex baseband signal, is the angular frequency of a low-frequency carrier introduced by the transmitting end to meet the minimum phase signal condition, is a minimum phase signal constructed from the complex baseband signal, is a phase signal reconstructed from the amplitude, is the received envelope amplitude signal, denotes the Hilbert transform.

[0007] The transmitter first processes the original complex baseband QAM signal to generate a minimum-phase signal, which is then modulated onto the transmission carrier. The receiver uses envelope detection and the Kramers-Kronig algorithm to recover the amplitude and phase of the minimum-phase complex baseband signal, and then reconstructs the I and Q components of the original complex baseband signal from it, thereby achieving high-order QAM demodulation while maintaining low system complexity and wideband spectral advantages. There are two main ways to implement KK receivers. The first is to use a standalone commercial DSP to implement the KK digital signal processing algorithm. This approach has the following problems: (i) The processing power of commercial DSP platforms is limited. Under high sampling rates and high-order modulation, algorithms such as Hilbert transform, digital downconversion, and coordinate transformation are prone to becoming throughput bottlenecks. (ii) The digital signal processing algorithms are highly complex. For example, operations such as square root, natural logarithm mapping, Hilbert-FIR filtering, and interpolation downsampling require multiple levels of loops and pipelined operations on the DSP, resulting in large processing delays. (iii) High power consumption. In high-speed processing mode, the dynamic power consumption of the DSP increases significantly, making it difficult to meet the requirements of low power consumption and high speed. (iv) Large interface and data transfer overhead. A high-speed interface is required between the ADC and the DSP, increasing design complexity. (v) Increased system cost and area. Due to the need for additional DSPs, interfaces, and peripherals, the overall receiver area is large, making it difficult to apply to millimeter-wave phased array systems. The second implementation method is to use a fully analog circuit, but it also has the following problems: (i) The bandwidth of the analog Hilbert transform filter is limited, making it difficult to support high communication rates and limiting the application of KK receivers in millimeter waves and higher frequency bands; (ii) The recovered amplitude and phase signals are intermediate frequency signals, which are difficult to combine directly in the analog domain and still require digital processing to complete amplitude / phase combining and downconversion; (iii) Amplitude and phase need to be sampled by independent ADCs, which increases hardware complexity and weakens the low power consumption advantage. Summary of the Invention

[0008] To address any of the problems in the prior art, the present invention provides a high-efficiency quadrature demodulation method and apparatus based on envelope signals.

[0009] The first objective of this invention is to provide a high-efficiency quadrature demodulation method based on envelope signals.

[0010] The second objective of this invention is to provide a high-efficiency quadrature demodulation device based on envelope signals.

[0011] The first objective of this invention can be achieved by adopting the following technical solution:

[0012] A high-efficiency orthogonal demodulation method based on envelope signals, applied at the receiver, the method comprising:

[0013] Amplitude and phase are recovered based on the envelope information of quadrature modulated signals;

[0014] The phase of the baseband signal is obtained by subtracting the phase of the low-frequency local oscillator signal used for digital down-conversion from the recovered phase, thus achieving equivalent digital down-conversion.

[0015] Based on the recovered amplitude and baseband signal phase, the I and Q components of the baseband signal are reconstructed.

[0016] Preferably, the reconstructing of the I and Q components of the baseband signal based on the recovered amplitude and the phase of the baseband signal includes:

[0017] The phase of the baseband signal is mapped by cosine and sine respectively to obtain the non-amplitude parts of the I and Q components of the baseband signal;

[0018] The non-amplitude components of the baseband signal I and Q are multiplied by the recovered amplitude to obtain the I and Q components of the baseband signal.

[0019] Preferably, the I and Q components of the baseband signal obtained after multiplication are filtered to remove single-tone interference; the frequency of the single-tone interference is the frequency of the low-frequency local oscillator signal used for digital down-conversion.

[0020] Preferably, the filtering is implemented using a root-raised cosine FIR filter, which achieves single-tone interference suppression by setting a zero at the frequency of the low-frequency local oscillator signal used for digital down-conversion.

[0021] Preferably, the filtering includes sequentially passing the input sequence through zero interpolation, filtering, and downsampling to achieve the conversion from the input oversampling rate to the target oversampling rate, while simultaneously outputting the I and Q components of the baseband signal with multiple sampling points per symbol.

[0022] Preferably, the recovery of amplitude and phase information from the envelope information of the quadrature modulation signal includes:

[0023] The square root operation is performed on the square sequence of envelope amplitudes to generate the amplitude of the minimum phase signal, thereby achieving amplitude recovery;

[0024] The amplitude of the minimum-phase signal is mapped using the natural logarithm to generate the real part of the analytic signal;

[0025] The phase recovery is achieved by extracting the imaginary part of the analytic signal from its real part using the Hilbert transform to obtain the phase of the minimum-phase signal.

[0026] Preferably, the Hilbert transform is implemented using a windowed Type-III FIR Hilbert filter to reduce in-band jitter and improve phase recovery accuracy; the even-order tap coefficients of the Type-III FIR Hilbert filter are zero to reduce computational complexity.

[0027] Preferably, the constant multiplier of the windowed Type-III FIR Hilbert filter is implemented through a lookup table, which can simultaneously perform square root, natural logarithm mapping and FIR constant multiplication operations to reduce logic delay and computational complexity.

[0028] Preferably, when processing a parallel input sequence of length N, the method applies one or more single-cycle delays to the parallel input sequence to form multiple sequences with different time alignments, and concatenates the multiple sequences with different time alignments into a continuous sequence with a length greater than N, so as to meet the convolution processing requirements when the number of taps of the Type-III FIR Hilbert filter is greater than N; where N is a positive integer greater than 1.

[0029] The second objective of this invention can be achieved by adopting the following technical solution:

[0030] A high-efficiency quadrature demodulation device based on envelope signals, applied at a receiving end, the device comprising:

[0031] The recovery module is used to recover the amplitude and phase based on the envelope information of the quadrature modulated signal;

[0032] The frequency conversion module is used to subtract the phase of the low-frequency local oscillator signal used for digital down-conversion from the recovered phase to obtain the phase of the baseband signal, so as to achieve equivalent digital down-conversion.

[0033] The reconstruction module is used to reconstruct the I and Q components of the baseband signal based on the recovered amplitude and phase of the baseband signal.

[0034] The present invention has the following advantages over the prior art:

[0035] (1) Simplified digital downconversion implementation: This invention abandons the traditional downconversion structure that relies on complex multiplication and addition operations. It achieves equivalent digital downconversion simply by subtracting the phase of the low-frequency local oscillator signal used for digital downconversion from the phase of the recovered minimum phase signal. This design significantly simplifies the calculation process, greatly reduces hardware complexity, and improves processing speed and efficiency.

[0036] (2) Highly efficient interference suppression and matched filtering: This invention employs a root-raised cosine FIR filter, which not only completes the matched filtering of the receiver baseband, but also precisely aligns the zero point of the frequency response with the frequency component of the low-frequency local oscillator signal used for digital down-conversion through a special design. This design enables the system to effectively eliminate high-amplitude single-tone interference introduced by the digital signal processing mechanism of the Kramers-Kronig receiver, even when using a lower filter order, thereby strongly guaranteeing the quality of the baseband signal.

[0037] (3) Excellent phase recovery accuracy: In response to the Gibbs effect introduced by the Hilbert transform, the present invention adopts a windowed Hilbert filter. By windowing the impulse response, the ringing effect is mainly limited to the out-of-band frequency band, thereby achieving high-precision phase recovery under low-order filter conditions and significantly improving the error vector amplitude (EVM) performance of the system.

[0038] (4) Extreme logic optimization and low latency: This invention employs a deep logic optimization strategy, utilizing lookup table (LUT) technology to combine square root, natural logarithm mapping, and FIR constant multiplication operations together, and combining this with a fully parallel pipeline structure to successfully reduce the logic latency of the critical path to the level of a single adder. This optimization significantly reduces area footprint and dynamic power consumption, enabling this invention to achieve high-throughput and efficient deployment on ASIC, FPGA, or DSP platforms. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0040] Figure 1 This is a flowchart of a high-efficiency orthogonal demodulation method based on envelope signals according to an embodiment of the present invention;

[0041] Figure 2 This is a flowchart of the digital signal processing of the Kramers-Kronig receiver according to an embodiment of the present invention;

[0042] Figure 3 This is a flowchart of the digital signal processing of a conventional Kramers-Kronig receiver according to an embodiment of the present invention;

[0043] Figure 4 This is a schematic diagram of the fully parallel architecture for implementing a high-efficiency orthogonal demodulation method based on envelope signals according to an embodiment of the present invention;

[0044] Figure 5 This is a schematic diagram of the structure of the IQ processing unit according to an embodiment of the present invention;

[0045] Figure 6 This is a schematic diagram of the frequency response of a band-limited Hilbert filter according to an embodiment of the present invention;

[0046] Figure 7 This is a schematic diagram of the impulse response of a windowed Type-III FIR Hilbert filter according to an embodiment of the present invention;

[0047] Figure 8 This is a schematic diagram of the frequency response of a windowed Type-III FIR Hilbert filter according to an embodiment of the present invention;

[0048] Figure 9 This is a schematic diagram of the frequency response amplitude error of a windowed Type-III FIR Hilbert filter according to an embodiment of the present invention;

[0049] Figure 10 This is a schematic diagram of the equivalent matched filter impulse response according to an embodiment of the present invention;

[0050] Figure 11 This is a schematic diagram of the impulse response of a multi-matched filter according to an embodiment of the present invention;

[0051] Figure 12 This is a schematic diagram of the frequency response of the equivalent matched filter according to an embodiment of the present invention;

[0052] Figure 13 This is an EVM effect diagram of digital signal processing according to an embodiment of the present invention;

[0053] Figure 14 This is a structural block diagram of a high-efficiency quadrature demodulation device based on envelope signals according to an embodiment of the present invention. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. It should be understood that the specific embodiments described are merely used to explain this application and are not intended to limit this application.

[0055] like Figure 1 , 2 As shown, this embodiment provides a high-efficiency orthogonal demodulation method based on envelope signals, applied at the receiving end, including the following steps:

[0056] (1) Recover amplitude and phase based on envelope signal.

[0057] First, the square of the envelope amplitude of the radio frequency signal is sampled by an analog-to-digital converter (ADC) to obtain its digital form.

[0058] In one embodiment, the digital form is obtained by sampling at a 5x oversampling rate, with each QAM symbol containing 5 sampling points.

[0059] Then, the square root operation and natural logarithm mapping are performed sequentially on the squared signal of the digital envelope amplitude to obtain an intermediate signal that can be used for phase recovery of the minimum phase signal.

[0060] Subsequently, the intermediate signal passes through an FIR Hilbert filter to recover the phase portion of the minimum phase signal; while the signal after square root processing can be directly used as the amplitude portion of the minimum phase signal.

[0061] (2) Based on the recovered phase, the phase of the baseband signal is obtained, and the equivalent digital downconversion is completed.

[0062] After reconstructing the amplitude and phase of the minimum phase signal, the phase of the minimum phase signal is subtracted from the phase of the low-frequency local oscillator signal used for digital downconversion to obtain the phase of the baseband signal, thus completing the equivalent digital downconversion.

[0063] (3) Based on the phase of the baseband signal and the recovered amplitude, reconstruct the I and Q components of the baseband signal.

[0064] By performing cosine and sine mapping on the phase of the baseband signal, the non-amplitude parts of the I and Q components of the baseband signal can be obtained. Then, by multiplying them by the amplitude of the minimum phase signal, the coordinate transformation from amplitude to phase to real to imaginary (IQ) can be completed, thus obtaining the I and Q components of the baseband signal containing single-tone interference.

[0065] (4) Perform matched filtering on the I and Q components of the baseband signal.

[0066] A strong DC component exists in the minimum phase signal. During digital down-conversion, this DC component is shifted to the low-frequency local oscillator signal, forming single-tone interference (STO). This interference is located outside the effective baseband frequency range. To suppress this interference and achieve matched filtering at the receiver, a low-pass matched filter (root-raised cosine filter) with a polyphase structure is used to process the I and Q components, and downsampling is performed during the filtering process. This processing not only effectively removes STO interference but also optimizes signal recovery performance. A flowchart of the digital signal processing of a traditional Kramers-Kronig receiver can be found here. Figure 3 .

[0067] In one embodiment, downsampling from 5x oversampling rate to 2x oversampling rate is performed during the filtering process.

[0068] refer to Figure 4The high-efficiency orthogonal demodulation method based on envelope signals is implemented using a fully parallel architecture, which includes multiple IQ processing units and multiple matched filter units. Multiple IQ processing units (IQUs) are used to implement steps (1) to (3) of the above method, and multiple matched filter units (MFUs) are used to implement step (4) of the method described in this example; each unit works in parallel to achieve high-efficiency demodulation, which is applicable to ASIC, FPGA and DSP platforms.

[0069] Specifically, the input signal is a time series that has undergone a 10x serial-to-parallel conversion, meaning each input consists of 10 consecutive sampling points. This serial-to-parallel conversion can be automatically performed by a time-interleaved ADC without additional hardware. The output of the time-interleaved ADC is the parallel signal. Since the FIR Hilbert filter implemented in the IQU has 11 taps, which is greater than the length of a single input sequence of 10, each input sequence of length 10 needs to be delayed by one cycle before being concatenated with a new input sequence of length 10 to form a continuous sequence of length 20. This continuous sequence is distributed among 10 fully parallelized IQ processing units (IQUs), each of which can process one sampling point in one cycle. Thus, 10 IQU units can achieve a throughput of 10 sampling points in one cycle, enabling real-time processing of the input sequence while significantly reducing the logic delay requirement of a single IQU unit. The signals output by these IQU units are baseband I and Q components with single-tone interference, which serve as the input to the matched filter. The matched filter employs a root-raised cosine filter, simultaneously performing single-tone interference filtering, downsampling, and matched filtering. The input is an IQU output signal with 5 samples per symbol (5 SPS). After matched filtering and downsampling to 2 samples per symbol (2 SPS), the parallel computation requirements of the filter are significantly reduced. The original sequence inputs 10 samples per cycle, containing 2 symbols; the output after matched filtering still contains 2 symbols, but each symbol is converted into 2 samples, each containing both I and Q components. Therefore, a total of 4 matched filter units (MFUs) are used to implement matched filtering of the I and Q components of the baseband signal. The input to the matched filter is a 10-length sequence from the IQU output, which, after one-cycle delay and two-cycle delay, forms a continuous sequence of length 30, which is then distributed across the 4 matched filter units. Each filter unit corresponds to two samples per symbol; therefore, the matched filter contains two phases: two units for the first phase and two units for the second phase. Each matched filter set contains two identical filter cores (MFUs) that process the interpolation of the I and Q components, respectively.

[0070] Specifically, such as Figure 5As shown, the IQ processing unit (IQU) adopts a fully parallel architecture. An input sequence of length 11 is input to the IQU each cycle, and a processing result containing I and Q components is output each cycle. The Hilbert filter uses a windowed Type-III FIR structure, with even-numbered taps being zero; therefore, only 6 of the 11 taps are non-zero. Before being input to the Hilbert filter, the squared envelope amplitude signal needs to be mapped using the square root and natural logarithm. This mapping is typically implemented using a lookup table (LUT). The FIR filter can be implemented using multiplication-accumulation logic. A non-zero tap filter of length N is commonly implemented using N constant multipliers and N–1 adders. In traditional implementations, constant multipliers are usually implemented using shifting and addition. Their logic delay depends on the number of adders and the bit width, and the number of adders is usually greater than 1. Therefore, constant multipliers often become the logic delay bottleneck of the FIR filter and introduce significant area and power consumption. This design employs a lookup table to implement a constant multiplier, which can simultaneously perform square root and natural logarithm mapping operations. Since the square root and natural logarithm mapping lookup tables are necessary in the implementation, the lookup table approach does not incur additional resource overhead and directly eliminates the need for a constant multiplier implemented using shift-addition. Furthermore, the data processing can be pipelined, reducing the maximum logic delay per clock cycle of the processing unit to the logic delay of a single adder, thereby significantly improving the upper limit of processing speed. In terms of functional implementation, the IQ processing unit not only performs phase recovery of the minimum-phase signal through square root, natural logarithm mapping, and Hilbert filtering, but also implements equivalent digital downconversion and coordinate transformation based on phase subtraction. The equivalent digital downconversion converts the phase of the minimum-phase signal into the phase of a baseband signal with single-tone interference; the coordinate transformation converts the amplitude and phase into complex I and Q components, implemented through sine and cosine lookup tables and multiplication. Multiplication can also be pipelined, reducing the maximum logic delay per clock cycle to the adder delay. Throughout the entire IQU unit, the maximum logic latency is optimized to be only the logic latency of an adder, thereby significantly increasing the upper limit of processing speed.

[0071] Specifically, the impulse response of the FIR Hilbert filter is generated by low-pass filtering, sampling, and windowing of the impulse response of the ideal Hilbert filter. Specifically, the ideal Hilbert impulse response is first low-pass filtered to the cutoff sampling frequency to avoid singularities; the filtered response exhibits band-pass-like characteristics, with its amplitude being zero at zero and high frequencies, such as... Figure 6 As shown in the figure. Subsequently, the continuous-time impulse response is sampled to obtain the discrete-time impulse response. To improve the amplitude characteristics, a Hamming window is applied to the filter. The impulse response and frequency response with rectangular window and Hamming window are shown in the figures respectively. Figure 7 , Figure 8As shown. Compared to the ideal frequency response, the windowed FIR Hilbert filter's main errors are concentrated in the transition band, while the amplitude is flat in the passband, without the in-band ringing (Gibbs effect) caused by the rectangular window. Figure 9 As shown, since the input signal of the filter is a natural logarithmic mapping of the amplitude of the minimum-phase signal, its spectrum is mainly concentrated in the intermediate frequency region. Therefore, the frequency response error introduced by windowing has a relatively small impact on the effective bandwidth of the signal. This significantly reduces the phase recovery error of the minimum-phase signal, thereby effectively improving the receiver's error vector amplitude (EVM) performance.

[0072] Specifically, the matched filter unit (MFU) adopts a design approach similar to the IQU, and its maximum logic delay is also optimized to the logic delay of a single adder. The filtering process simultaneously performs the conversion from 5x oversampling rate to 2x oversampling rate, which can be equivalent to first performing zero interpolation to 10x oversampling rate, then filtering, and finally downsampling to 2x oversampling rate. The odd or even taps of the two matched filters are both zero, with the odd taps of the first phase being zero and the even taps of the second phase being zero. Figure 10 As shown, the non-zero taps of the two matched filters are collectively equivalent to the impulse response of a single root-raised cosine filter; in other words, the non-zero taps of the two matched filters can be considered as samples obtained from the impulse response of a single root-raised cosine filter. The phase relationship between the impulse responses of the two matched filters is as follows: Figure 11 As shown. Because the amplitude of the DC component in the analyzed signal is much higher than that of the effective signal, a high-amplitude single-tone interference will be generated during the down-conversion process. For example... Figure 12 As shown, the frequency of this single-tone interference is the frequency of the low-frequency local oscillator signal used for digital down-conversion, which is outside the effective baseband frequency range. Therefore, by properly designing a matched filter, a zero can be set at this frequency. Even if the interference is extremely strong relative to the effective signal, this method can achieve significant suppression at a lower order without increasing the number of filter taps.

[0073] In one alternative embodiment, a high-efficiency quadrature demodulation method based on envelope signals is implemented on a 65-nm CMOS process to achieve a complete ASIC circuit design, including front-end synthesis, placement and routing, and back-end verification. Each module is designed according to the aforementioned fully parallel architecture and single adder critical path principle to obtain high throughput and low power consumption characteristics.

[0074] In this embodiment, both the IQ processing unit (IQU) and the matched filter unit (MFU) adopt a multi-stage pipeline structure, dividing the critical data path to the combinational logic depth containing only a single adder or lookup table access operation. The constant multiplier is implemented through a lookup table and merged with the square root and natural logarithm mapping tables, thereby avoiding a large-scale shift adder tree structure and significantly shortening the combinational path length. After placement and routing, results obtained through static timing analysis tools show that the architecture of this invention can stably achieve operating frequencies above 500MHz in a 65nm process. This improvement in timing performance mainly comes from:

[0075] (1) The critical path is shortened to the level of a single adder, which significantly reduces combinational logic latency;

[0076] (2) The high parallelization of IQU and MFU significantly reduces the computational load on a single path;

[0077] (3) The lookup table replaces the multiplier structure, reducing the adder depth and wiring burden in traditional FIR filters.

[0078] Regarding power consumption, results obtained from backend power analysis tools show that the total power consumption of the complete digital processing chain in this embodiment is as low as 25mW under nominal operating conditions. This power consumption level is significantly lower than that of traditional multiplier-type FIR filter structures, mainly due to the following reasons:

[0079] (1) The lookup table implementation reduces the flipping activity of large-bit-width adders;

[0080] (2) After the pipeline is split, the flip load of registers at each stage is more even, which helps to reduce dynamic power consumption;

[0081] (3) Parallel structure improves throughput, enabling the overall clock frequency to maintain high performance at lower voltages.

[0082] In terms of area, the post-layout and routing statistics of this embodiment show that the standard cell area of ​​the complete design is approximately 360μm × 390μm. By reducing the number of FIR non-zero taps, using lookup tables instead of multipliers, and increasing parallelism to reduce single-path load, the overall logic area is significantly reduced compared to the traditional FIR + digital downconverter structure. In addition, the modular parallel architecture significantly reduces wiring congestion, further reducing the area footprint.

[0083] like Figure 13 As shown, the EVM introduced in this embodiment for the Kramers-Kronig receiver is as low as -23.8dB under 16QAM modulation, which fully meets the requirements of high-order modulation.

[0084] In summary, the actual ASIC implementation results on the 65nm CMOS process in this embodiment verify that the architecture has significant advantages in four aspects: high processing accuracy, high clock frequency, low power consumption, and small area, making it suitable for widespread application in high-speed Kramers-Kronig receiver digital signal processing chips.

[0085] This embodiment relies on a fully parallel architecture and a unique sequence splicing mechanism to seamlessly connect with the high-speed parallel output of a time-interleaved ADC, effectively solving the edge effect problem of the filter when processing block data. This architecture supports parallel processing of multiple sampling points within a single clock cycle, breaking through the rate bottleneck of traditional serial processing, thereby realizing real-time and continuous processing of ultra-high-speed signals and meeting the stringent high-throughput requirements of modern communication systems.

[0086] It should be noted that although the method operations of the above embodiments are described in a specific order, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. On the contrary, the described steps may be performed in a different order. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0087] This embodiment also provides a high-efficiency quadrature demodulation device based on envelope signals, such as... Figure 14 As shown, the device includes a recovery module 1401, a frequency converter module 1402, and a reconstruction module 1403, wherein:

[0088] Recovery module 1401 is used to recover the amplitude and phase based on the envelope information of the quadrature modulation signal;

[0089] The frequency conversion module 1402 is used to subtract the phase of the recovered phase from the phase of the low-frequency local oscillator signal used for digital down-conversion to obtain the phase of the baseband signal, so as to achieve equivalent digital down-conversion.

[0090] The reconstruction module 1403 is used to reconstruct the I and Q components of the baseband signal based on the recovered amplitude and the phase of the baseband signal.

[0091] The specific implementation of each module in this embodiment can be found in the above-described high-efficiency quadrature demodulation method based on envelope signals, and will not be repeated here. It should be noted that the device provided in this embodiment is only illustrated by the division of the above-described functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure can be divided into different functional modules to complete all or part of the functions described above.

[0092] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope disclosed in the present invention, based on the technical solution and inventive concept of the present invention, shall fall within the scope of protection of the present invention.

Claims

1. A high-efficiency orthogonal demodulation method based on envelope signals, applied at the receiving end, characterized in that, The method includes: Amplitude and phase are recovered based on the envelope information of quadrature modulated signals; The phase of the baseband signal is obtained by subtracting the phase of the low-frequency local oscillator signal used for digital down-conversion from the recovered phase, thus achieving equivalent digital down-conversion. Based on the recovered amplitude and baseband signal phase, the I and Q components of the baseband signal are reconstructed.

2. The high-efficiency orthogonal demodulation method according to claim 1, characterized in that, The reconstruction of the I and Q components of the baseband signal based on the recovered amplitude and phase of the baseband signal includes: The phase of the baseband signal is mapped by cosine and sine respectively to obtain the non-amplitude parts of the I and Q components of the baseband signal; The non-amplitude components of the baseband signal I and Q are multiplied by the recovered amplitude to obtain the I and Q components of the baseband signal.

3. The high-efficiency orthogonal demodulation method according to claim 2, characterized in that, The I and Q components of the baseband signal obtained after multiplication are filtered to remove single-tone interference; the frequency of the single-tone interference is the frequency of the low-frequency local oscillator signal used for digital down-conversion.

4. The high-efficiency orthogonal demodulation method according to claim 3, characterized in that, The filtering is implemented using a root-raised cosine FIR filter, which achieves single-tone interference suppression by setting a zero at the frequency of the low-frequency local oscillator signal used for digital down-conversion.

5. The high-efficiency orthogonal demodulation method according to claim 3, characterized in that, The filtering process involves sequentially passing the input sequence through zero interpolation, filtering, and downsampling to achieve the conversion from the input oversampling rate to the target oversampling rate, while simultaneously outputting the I and Q components of the baseband signal with multiple sampling points for each symbol.

6. The high-efficiency orthogonal demodulation method according to any one of claims 1 to 5, characterized in that, The recovery of amplitude and phase information from the envelope information of the quadrature modulated signal includes: The square root operation is performed on the square sequence of envelope amplitudes to generate the amplitude of the minimum phase signal, thereby achieving amplitude recovery; The amplitude of the minimum-phase signal is mapped using the natural logarithm to generate the real part of the analytic signal; The phase recovery is achieved by extracting the imaginary part of the analytic signal from its real part using the Hilbert transform to obtain the phase of the minimum-phase signal.

7. The high-efficiency orthogonal demodulation method according to claim 6, characterized in that, The Hilbert transform is implemented using a windowed Type-III FIR Hilbert filter to reduce in-band jitter and improve phase recovery accuracy; the even-order tap coefficients of the Type-III FIR Hilbert filter are zero to reduce computational complexity.

8. The high-efficiency orthogonal demodulation method according to claim 7, characterized in that, The constant multiplier of the windowed Type-III FIRHilbert filter is implemented through a lookup table, which can simultaneously perform square root, natural logarithm mapping and FIR constant multiplication operations to reduce logic delay and computational complexity.

9. The high-efficiency orthogonal demodulation method according to any one of claims 7 to 8, characterized in that, When processing a parallel input sequence of length N, the method applies one or more single-cycle delays to the parallel input sequence to form multiple sequences with different time alignments, and then concatenates the multiple sequences with different time alignments into a continuous sequence with a length greater than N, so as to meet the convolution processing requirements when the number of taps of the Type-III FIR Hilbert filter is greater than N; where N is a positive integer greater than 1.

10. A high-efficiency quadrature demodulation device based on envelope signals, applied at a receiving end, characterized in that, The device includes: The recovery module is used to recover the amplitude and phase based on the envelope information of the quadrature modulated signal; The frequency conversion module is used to subtract the phase of the low-frequency local oscillator signal used for digital down-conversion from the recovered phase to obtain the phase of the baseband signal, so as to achieve equivalent digital down-conversion. The reconstruction module is used to reconstruct the I and Q components of the baseband signal based on the recovered amplitude and phase of the baseband signal.

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