Processing system, control method, chip and computer readable storage medium

Abstract

Provided are a processing system, a control method, a chip and a computer readable storage medium. The processing system comprises: a memory management unit configured to manage a memory; and a processor on which an operating system is run, the processor being configured to: generate first mapping data, the first mapping data being used to indicate a mapping relationship between a first virtual address of the operating system and a first physical address of the memory; store the first mapping data in a cache; and if the memory management unit does not take the first mapping data from the cache, control the cache such that the first mapping data is not replaced into the memory. Embodiments of the application can avoid the first mapping data being replaced from the cache to the memory, thereby avoiding repeated access between the memory management unit and the memory, helping to reduce power consumption and improve system performance.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of data storage, and more particularly, to a processing system, a control method, a chip and a computer readable storage medium. BACKGROUND

[0002] In current large-scale system-on-chip, the operating system generally needs to manage the storage space based on virtual addresses, and the mapping relationship from the virtual address to the physical address is usually stored in the memory in the form of a page table. The operating system uses a memory management unit to be responsible for the conversion of the virtual address to the physical address of the page table.

[0003] The newly created page table is usually present in the cache of the central processing unit, and if the memory management unit does not have time to take the page table in the cache, the page table can be replaced to the memory by hardware. The memory management unit needs to take the page table from the memory, thereby causing increased power consumption and performance loss. SUMMARY

[0004] Embodiments of the present application provide a processing system, a control method, a chip and a computer readable storage medium, and the following introduces each aspect of the embodiments of the present application.

[0005] In a first aspect, a processing system is provided, comprising: a memory management unit configured to manage a memory; and a processor having an operating system running thereon, the processor being configured to: generate first mapping data, the first mapping data being configured to indicate a mapping relationship between a first virtual address of the operating system and a first physical address of the memory; store the first mapping data in a cache; and if the memory management unit does not take the first mapping data from the cache, control the cache such that the first mapping data is not replaced to the memory.

[0006] In a second aspect, a control method is provided, comprising: generating first mapping data, the first mapping data being configured to indicate a mapping relationship between a first virtual address of an operating system and a first physical address of a memory; storing the first mapping data in a cache; and if a memory management unit does not take the first mapping data from the cache, controlling the cache such that the first mapping data is not replaced to the memory.

[0007] In a third aspect, a chip is provided, comprising the processing system of the first aspect.

[0008] In a fourth aspect, a computer readable storage medium is provided, having a computer program stored thereon, the computer program being configured to execute the control method of the second aspect.

[0009] The embodiment of the present application creates first mapping data in the cache, and the first mapping data cannot be replaced from the cache to the memory before the memory management unit takes away the first mapping data. The embodiment of the present application can avoid the first mapping data from being replaced from the cache to the memory, thereby avoiding repeatedly accessing between the memory management unit and the memory, helping to reduce the memory power consumption and improve the system performance. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a flowchart of a process in which the memory management unit acquires the page table in the cache.

[0011] Figure 2 is a flowchart of a process in which the memory management unit acquires the page table in the memory.

[0012] Figure 3 is a structural diagram of a processing system provided by the embodiment of the present application.

[0013] Figure 4 is a structural diagram of a processing system provided by the embodiment of the present application. Figure 3 is a structural diagram of a processing system provided by the embodiment of the present application.

[0014] Figure 5 is a flowchart of a control method provided by the embodiment of the present application.

[0015] Figure 6 is a flowchart of a control method provided by the embodiment of the present application. Figure 5 is a flowchart of a control method provided by the embodiment of the present application.

[0016] Figure 7 is a structural diagram of a chip provided by the embodiment of the present application. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application.

[0018] Currently, in a system on chip (SOC) chip, if a relatively complex operating system such as an Android, Linux or the like operating system is involved, the operating system generally needs to manage the storage space based on a virtual address. The SOC is also called a system-level chip, which integrates a complete system on a single chip. The so-called complete system generally includes a central processing unit (CPU), a memory, and a peripheral circuit, etc. The CPU is also called a central processing unit or a microprocessor. The virtual address is an address used by an accesser (for example, a central processing unit) that needs to access the chip storage space, and the physical address is the real address of the chip storage space. The mapping relationship from the virtual address to the physical address is usually stored in the memory in the form of a page table.

[0019] Memory management unit (MMU) is used to be responsible for the conversion between virtual address and physical address of page table. MMU is a chip internal module, and its basic function is address mapping, through which a virtual address can access a specified physical address.

[0020] When the application software newly creates a page table, the new page table usually exists in the cache of the CPU or the memory, at this time the memory management unit needs to take the page table from the cache or the memory.

[0021] The storage device is a device for storing information, which is located on-chip or off-chip of the processor and is configured to retrieve and store data associated with a physical memory address. According to different uses, it can be generally divided into memory and external storage (auxiliary memory), and the memory is also called internal memory, main memory or main storage. The memory can be divided into random access memory (RAM) and read only memory (ROM) according to working principle, and RAM is an important memory. The storage device can also include cache, which includes one or more levels of cache memory.

[0022] Cache refers to a memory that can exchange data at high speed. Cache usually has a small capacity, and stores data that is accessed more frequently by the CPU, but has a much higher speed than the memory, and exchanges data with the CPU before the memory, which can significantly improve the processing speed of the computer system. The working principle of cache is that when the CPU wants to read a data, it first searches in the CPU cache, and if found, it is immediately read and sent to the CPU for processing. If not found, it is read from the memory with a relatively slow speed and sent to the CPU for processing, and at the same time the data block where the data is located is called into the cache, so that the subsequent reading of the whole block of data is carried out from the cache, without having to call the memory again.

[0023] Figure 1 is a flowchart of the process in which the memory management unit obtains the page table in the cache. For ease of introduction, a shared cache in a multi-core processor system is taken as an example for illustration. As shown in Figure 1 , the processor system includes CPU 110, memory management unit 130 and memory 140. Among them, the cache 120 is located in the CPU 110, and the cache 120 is a three-level cache, which is also a shared cache of the multi-core processor. The memory management unit 130 completes the virtual-real address conversion of the page table, and to complete a memory access instruction of the page table, the following steps need to be experienced under normal circumstances:

[0024] In step one, in response to the application software's instruction to create a new page table, a new page table is created in cache 120. When the software creates a new page table, the new page table will most likely exist in cache 120 of CPU 110. Typically, the page table in the cache is a fast table, while the page table in memory is a slow table.

[0025] In step two, the memory management unit 130 promptly retrieves the new page table from the cache 120.

[0026] In step three, if the process needs to read or write to memory 140, and if the process involves data in the new page table, the access and transfer are handled by memory management unit 130, which completes the translation of the virtual address to the physical address of the new page table.

[0027] In step four, the memory management unit 130 transmits the access instruction to the memory 140 and performs a memory access operation on the memory 140 according to the physical address. At this point, the entire instruction transmission is complete.

[0028] When application software creates a new page table in the CPU's cache, if the memory management unit (MMU) cannot retrieve the page table from the cache in time, the page table may be swapped into memory by hardware. In this case, the MMU must retrieve the page table from memory, but memory access speed is several times slower than cache access speed, resulting in increased power consumption and performance loss.

[0029] Figure 2 This is a flowchart illustrating the process by which the memory management unit retrieves page tables from memory. For example... Figure 2 As shown, the processor system includes a CPU 110, a memory management unit 130, and memory 140, wherein cache 120 is located in the CPU 110. The memory management unit 130 performs the virtual-to-physical address translation of the page tables in memory 140. To complete a memory access instruction of the page table, the following steps are required:

[0030] In step one, in response to the application software's instruction to create a new page table, a new page table is created in cache 120.

[0031] In step two, the memory management unit 130 fails to retrieve the new page table from the cache 120 in a timely manner. Typically, the cache space is small, and if the page table is not retrieved from the cache 120 in time, it will be replaced in memory 140.

[0032] In step three, the CPU 110 accesses and transfers data via the memory management unit 130 because the process needs to read or write memory 140, for example, the process involves data in a new page table.

[0033] In step four, if the memory management unit 130 does not contain the required page table, it will initiate an access to the memory 140.

[0034] In step five, the memory management unit 130 retrieves the page table from memory 140.

[0035] In step six, the memory management unit 130 completes the translation from the virtual address to the physical address of the new page table. The memory management unit 130 then transmits the access instruction to the memory 140, performing read and write operations on the memory 140 according to the physical address. At this point, the entire instruction transmission is complete.

[0036] It is evident that when the page table has been replaced by memory, the number of steps required for a single read / write operation by the CPU or other peripherals exceeds the time required for the page table to be retrieved by the MMU. This results in repeated memory accesses between the MMU and memory, leading to increased memory power consumption, significant latency, and performance loss.

[0037] It should be noted that the scenario mentioned above, in which page tables are replaced in memory and cause performance loss, is only an example. This application embodiment can be applied to any type of scenario where the mapping relationship between virtual and physical addresses in the cache is replaced before being taken away by the MMU, resulting in increased power consumption.

[0038] Therefore, developing a memory management solution that reduces power consumption waste is a problem that needs to be solved.

[0039] Based on this, the present application proposes a processing system, and the embodiments of the present application are described in detail below.

[0040] Figure 3 This is a schematic diagram of the structure of a processing system provided in an embodiment of this application. Figure 3 As shown, the processing system includes a memory management unit 310, memory 320, a processor 330, and a cache 340.

[0041] The memory management unit 310 is connected to the memory 320 and is used to manage the memory 320. The basic function of the memory management unit 310 is address mapping, which allows a virtual address to access a specified physical address. For example, it translates a virtual address in the page table into a physical address.

[0042] The memory management unit 310 can be the memory management unit corresponding to the processor 330, or it can be the memory management unit corresponding to the first external device. An external device, also called a peripheral device, is typically an input or output device; therefore, the memory management unit corresponding to an external device is also called an input / output memory management unit (IOMMU). The first external device can be any external device connected to the processing system.

[0043] External devices can be broadly classified into three categories: human-computer interaction devices (such as printers, monitors, plotters, and speech synthesizers), computer information storage devices (such as disks, optical discs, and magnetic tapes), and machine-to-machine communication devices (such as modems).

[0044] The memory module 320 can be RAM or ROM, etc. Memory access operations, such as reading data and writing data, can be performed on the memory module 320 based on its physical address.

[0045] Processor 330 is used to process instructions, such as receiving and processing arithmetic instructions and page table creation instructions from application programs. Processor 330 can be a single-core processor or a multi-core processor, such as a quad-core or octa-core processor.

[0046] A multi-core processor integrates two or more complete computing cores into a single processor. In this case, the processor can support multiple processors on the system bus, with all bus control and command signals provided by the bus controller.

[0047] Cache 340 typically stores data that the CPU frequently accesses. Cache 340 is typically located within CPU 330. In some embodiments, cache 340 may also be located outside CPU 330. Page tables can be created within cache 340 for faster access. Cache 340 can be a standalone cache or a shared cache. For example, in a multi-core processor system, cache 340 can be a shared cache for the entire multi-core processor system.

[0048] In some implementations, the three levels of cache are integrated into the CPU, including L1 (Level 1), L2 (Level 2), and L3 (Level 3). Their function is to serve as a high-speed data buffer between the CPU and memory, with L1 being the closest to the CPU core, followed by L2, and then L3. In terms of speed, L1 is the fastest, L2 is the second fastest, and L3 is the slowest; in terms of capacity, L1 is the smallest, L2 is the largest, and L3 is the largest.

[0049] In multi-core processor systems, each core typically has its own L1 and L2 caches, while the L3 cache is generally shared. The use of an L3 cache can further reduce memory latency and improve processor performance during large-scale data computations.

[0050] The processor 330 runs an operating system, such as Android or Linux. The operating system typically manages memory space based on virtual addresses. When the operating system creates new mapped data, the instructions can come from application software or applications, and the processor 330 can perform the following steps:

[0051] In step one, first mapping data is generated. This first mapping data indicates the mapping relationship between the operating system's first virtual address and the memory 320's first physical address. A virtual address is the address used by an accessor (e.g., the CPU) to access the chip's storage space; it is also called a logical address or effective address. The first virtual address can be any address in the virtual address space. A physical address is the actual address in the chip's storage space; the first physical address can be any address in the chip's physical address space.

[0052] In some implementations, the first mapping data can be, for example, a page table. A page table is a data structure that defines the rules for mapping virtual addresses to physical addresses. Logical addresses are addresses generated by the CPU. CPU-generated logical addresses can be divided into page numbers and page offsets. The page number contains the base address of each page in physical memory and is used as an index for the page table. The page offset, combined with the base address, is used to determine the physical address in memory. The set of all logical addresses forms the logical address space.

[0053] A physical address is the actual address in memory. The set of all physical addresses in memory that correspond to logical addresses is called the physical address space.

[0054] Page tables typically contain page table entries (PTEs) to map virtual addresses to physical addresses. Page tables can be single-level or multi-level, depending on the base page size, the number of page table entries at each level, and the number of bits in the supported virtual address space.

[0055] In step two, the first mapped data is stored in cache 340. This also allows processor 330 to quickly access the data.

[0056] In step three, if the memory management unit 310 does not retrieve the first mapping data from the cache 340, the cache 340 is controlled so that the first mapping data is not replaced into the memory 320.

[0057] The processor 330 controls the cache 340 to prevent the first mapped data from being replaced into the memory 320. This avoids repeated memory accesses between the memory management unit and memory when accessing the first mapped data, reducing power consumption waste.

[0058] In some implementations, such as Figure 3 As shown by the dashed lines, when the CPU accesses newly created first-mapped data in the cache, such as a page table, it needs to go through the following steps:

[0059] In step one, CPU330 responds to the instruction to create a new page table by placing the newly created page table in an address space that can be cached, such as creating a new page table in cache 340. The instruction can come from application software or an application program.

[0060] In step two, the memory management unit 310 retrieves the new page table from the cache 340. If the memory management unit 310 fails to retrieve the page table in a timely manner, the page table must not be replaced from the cache 340 to the memory 320 before the memory management unit 310 retrieves the page table.

[0061] In step three, the CPU 330 reads and writes memory 320 because the process involves data in the new page table. The data is transferred through the memory management unit 310, which completes the translation of the virtual address to the physical address of the new page table.

[0062] In step four, the memory management unit 330 transmits the memory access instruction to the memory 320 and performs read and write operations on the memory 320 according to the translated physical address. At this point, the transmission of the entire memory access instruction is complete.

[0063] In some implementations, to facilitate checking whether the first mapped data in the cache has been retrieved by the memory management unit (MMU), the MMU can set flag information, such as a specific flag bit, for the first mapped data to be retrieved. This flag information is used to indicate whether the first mapped data has been retrieved by the MMU. The flag bit can indicate different states of whether the first mapped data has been retrieved by the MMU. For example, the flag bit can show a normal state where the page table has not been retrieved as "0". If the flag bit indicates that the page table has been retrieved by the MMU, the page table can be set. After being retrieved by the MMU, it can be set to "1", and resetting it is equivalent to setting it to "0". Page tables that are not set must not be replaced in memory. In some embodiments, the flag bit can also show a normal state where the page table has not been retrieved as "1", and can switch to "0" after being retrieved by the MMU.

[0064] Flag information can be set in the cache line. The first mapped data is stored in the first cache line, which contains flag information. The flag information indicates whether the first mapped data has been retrieved by the memory management unit.

[0065] The first cache line can be any cache line within the cache line. A cache line, also known as a cache cache line, is the smallest unit of cached data, including a storage block and other information (valid bit and tag bit). Typically, each cache line includes a valid bit indicating whether the line contains meaningful information, and a tag bit of length T, which uniquely identifies the memory address of the block stored in this cache line.

[0066] In some implementations, a cache line can only be set if the flag information indicates that the cache line of the first mapped data has been taken by the MMU. For example, the normal state of the flag when it has not been taken is "0", it can be set to "1" after being taken by the MMU, and it can be reset to "0" when reset. Cache lines that have not been set should not be replaced into memory by the cache hardware.

[0067] Typically, cache space is small and used frequently, so newly created page tables should not occupy cache space for too long. In some implementations, the processor 330 can also proactively trigger the memory management unit 310 to retrieve the newly created first mapping data, such as the page table. For example, the processor 330 can proactively trigger the memory management unit corresponding to the CPU 330 to promptly retrieve the newly created page table to prevent it from occupying cache space for too long. Similarly, the processor 330 can also proactively trigger the memory management unit corresponding to the first external device to promptly retrieve the newly created page table.

[0068] In this embodiment, first mapping data is created in the cache. Before the memory management unit retrieves the first mapping data, it must not be replaced from the cache to memory. This embodiment avoids the first mapping data being replaced from the cache to memory, thereby preventing repeated memory accesses between the memory management unit and memory, helping to reduce memory power consumption and improve system performance.

[0069] Figure 4 yes Figure 3 The diagram shows a possible implementation of the processing system. Figure 4 As shown, the processor is a multi-core processor, and the processor system includes a memory management unit 410, memory 420, processor 430, and cache 440.

[0070] The memory management unit 410 can translate the virtual address in the first mapped data into the physical address of the data. The memory management unit 410 can be the memory management unit corresponding to the processor or the memory management unit corresponding to the first external device.

[0071] The memory 420 is connected to the memory management unit 410. Based on the physical address, memory access operations such as reading data and writing data can be performed on the memory 420.

[0072] Processor 430 is used to process instructions. Processor 410 can be a multi-core processor, such as a quad-core or octa-core processor. Each core processor has its own L1 and L2 cache.

[0073] Cache 440, located within processor 430, typically stores data frequently accessed by the CPU. Page tables can be created within cache 440 for faster access. Cache 440 is a shared cache in multi-core processor systems, specifically the L3 cache. The use of L3 caching can further reduce memory latency and improve processor performance during large-scale data computations.

[0074] For newly created page tables, a flag bit can be set in the cache line. For example, the normal state of the flag bit indicating that the page table has not been fetched is "0". If the page table has been fetched by the MMU, the flag bit can be set to "1". If the cache line is not set, it must not be replaced by the cache 440 hardware into memory 420.

[0075] After creating a new page table, the processor 430 can also proactively trigger the memory management unit 410 to retrieve the newly created page table in a timely manner. For example, it can proactively trigger the memory management unit corresponding to the processor 430 to retrieve the newly created page table in a timely manner to prevent it from occupying cache space for too long. Alternatively, it can proactively trigger the memory management unit corresponding to the first external device to retrieve the newly created page table in a timely manner.

[0076] like Figure 4 As shown, the memory management unit 410 retrieves the page table and completes a memory access instruction, which requires the following steps:

[0077] In step one, processor 430 responds to the application software's instruction to create a new page table and places the newly created page table in the address space of the CPU's cache, such as creating a new page table in the L3 cache 440.

[0078] In step two, when a new page table is created in cache 440, a flag is set for the newly created page table in the cache line. The flag is not set before the memory management unit 410 retrieves the page table, and the page table must not be replaced from cache 440 to memory 420.

[0079] In step three, the processor 430 actively triggers the memory management unit 410 to promptly retrieve newly created page tables, such as page tables whose flag bits are not set.

[0080] In step four, the memory management unit 410 retrieves the new page table from the cache 440. When a process reads or writes to memory 420, for example, if the process involves data in the new page table, the access and transfer occur via the memory management unit 410, which performs the translation from the virtual address to the physical address of the new page table.

[0081] In step five, the memory management unit 430 transmits the access instruction to the memory 440 to translate the corresponding physical address and perform read / write operations on the memory 340. At this point, the entire instruction transmission is complete.

[0082] In this embodiment, a flag is set for newly created page tables in the cache. The flag is not set until the memory management unit (MMU) retrieves the page table, preventing the page table from being swapped from the cache to memory. The CPU can also proactively trigger the MMU to retrieve newly created page tables whose flag is not set. This embodiment avoids repeated memory accesses between the MMU and memory, helping to reduce memory power consumption and improve the performance of the CPU and peripherals in acquiring page tables.

[0083] The above text combined Figures 1-4 The system embodiments of this application are described in detail below, in conjunction with... Figures 5-6 The present application describes in detail the method embodiments. It should be understood that the description of the method embodiments corresponds to the description of the system embodiments; therefore, any parts not described in detail can be referred to the foregoing system embodiments.

[0084] Figure 5 This is a flowchart illustrating a control method provided in an embodiment of this application. Figure 5 The method can be applied to the processing system described in any of the preceding embodiments. The processing system may include: a memory management unit for managing memory; and a processor running an operating system thereon, the processor being configured to perform the following operations: generate first mapping data, the first mapping data indicating a mapping relationship between a first virtual address of the operating system and a first physical address of the memory; store the first mapping data in a cache; and if the memory management unit does not retrieve the first mapping data from the cache, control the cache so that the first mapping data is not replaced into the memory.

[0085] Figure 5 The method includes steps S510 to S530, which are described in detail below.

[0086] In step S510, first mapping data is generated, which is used to indicate the mapping relationship between the first virtual address of the operating system and the first physical address of the memory.

[0087] In step S520, the first mapping data is stored in the cache.

[0088] In step S530, if the memory management unit does not retrieve the first mapping data from the cache, the cache is controlled so that the first mapping data is not replaced into memory.

[0089] Figure 6 yes Figure 5 A flowchart illustrating one possible implementation of the method. The memory management unit retrieves the page table and completes a memory access instruction. Figure 6 The method may include steps S610 to S640, which are described in detail below.

[0090] In step S610, a new page table is created in the cache, and a flag is set for the new page table.

[0091] In step S620, if the memory management unit fails to retrieve the page table from the cache, the cache is controlled to prevent the page table from being swapped into memory. The memory management unit is proactively triggered to retrieve page tables whose flags are not set.

[0092] In step S630, the storage management unit retrieves the page table from the cache and converts the virtual address in the page table into a physical address.

[0093] In step S640, a memory access operation is performed on the main memory based on the physical address.

[0094] Figure 7 This is a schematic diagram of the chip provided in an embodiment of this application. For example... Figure 7 As shown, the chip 700 may include a processing system 710 as described above.

[0095] The control methods described in the embodiments of this application above, including methods for obtaining and managing page tables, are usually described in the relevant module configurations of the chip, such as in the register configurations of the relevant modules.

[0096] This application also provides a computer-readable storage medium having a computer program stored thereon, the computer program being used to execute the control method as described in any of the preceding descriptions.

[0097] It should be understood that the computer-readable storage medium mentioned in the embodiments of this application can be any usable medium that a computer can read, or a data storage device such as a server or data center that integrates one or more usable media. The usable medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., digital video disc (DVD)), or a semiconductor medium (e.g., solid state disk (SSD)).

[0098] It should be understood that in the various embodiments of this application, "first," "second," etc., are used to distinguish different objects, rather than to describe a specific order. The order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0099] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0100] In the embodiments provided in this application, it should be understood that when a part is referred to as "connected" or "linked" to another part, it means that the part can be "directly connected" and also "electrically connected," with another element involved. Furthermore, the term "connected" also means that the parts are "physically connected" and "wirelessly connected." Additionally, when a part is referred to as "containing" an element, unless otherwise stated, it means that the part may include, but does not exclude, the other element.

[0101] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0102] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0103] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A processing system, characterized in that, include: The memory management unit is used for memory management; A processor, on which an operating system runs, is used to perform the following operations: Generate first mapping data, which is used to indicate the mapping relationship between the first virtual address of the operating system and the first physical address of the memory; Store the first mapped data in a cache; If the memory management unit does not retrieve the first mapped data from the cache, it controls the cache so that the first mapped data is not replaced into the memory. The cache in question is a CPU cache.

2. The processing system according to claim 1, characterized in that, The first mapped data is stored in the first cache line of the cache, and the first cache line has identification information, which is used to indicate whether the first mapped data has been taken by the memory management unit.

3. The processing system according to claim 1, characterized in that, The processor is also used to perform the following operations: The memory management unit is actively triggered to retrieve the first mapping data from the cache.

4. The processing system according to any one of claims 1-3, characterized in that, The first mapping data is a page table.

5. A control method, characterized in that, include: Generate first mapping data, which is used to indicate the mapping relationship between the first virtual address of the operating system and the first physical address of memory; Store the first mapped data in a cache; If the memory management unit does not retrieve the first mapped data from the cache, the cache is controlled so that the first mapped data is not replaced into the memory; The cache in question is a CPU cache.

6. The control method according to claim 5, characterized in that, The first mapped data is stored in the first cache line of the cache, and the first cache line has identification information, which is used to indicate whether the first mapped data has been taken by the memory management unit.

7. The control method according to claim 5, characterized in that, The control method further includes: The memory management unit is actively triggered to retrieve the first mapping data from the cache.

8. The control method according to any one of claims 5-7, characterized in that, The first mapping data is a page table.

9. A chip, characterized in that, Includes the processing system as described in any one of claims 1-4.

10. A computer-readable storage medium, characterized in that, It stores a computer program that is used to execute the control method as described in any one of claims 5-8.

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