Dual-edge sampling circuits and data sampling methods, apparatus and systems used therein

Abstract

This application relates to the field of non-volatile memory technology and discloses a dual-edge sampling circuit, including a decoding circuit. The decoding circuit includes: a first decoding shift register configured to sample external data from a bidirectional data output device using the rising edge of an external clock to obtain rising edge data; a second decoding shift register configured to sample external data from the bidirectional data output device using the falling edge of an external clock to obtain falling edge data; a bitwise concatenation unit configured to use bitwise concatenation operations to combine the rising edge data and the falling edge data into two bits, obtaining data from two clock edges; and an address register configured to use an external clock to perform address concatenation of the data from the two clock edges. The dual-edge sampling circuit uses dual-edge sampling for data communication, which can effectively improve the data transmission rate. This application also discloses a data sampling method, apparatus, and system for a dual-edge sampling circuit.

Description

Technical Field

[0001] This application relates to the field of non-volatile memory technology, for example to a dual-edge sampling circuit and a data sampling method, apparatus and system therefor. Background Technology

[0002] Traditional non-volatile memory chips typically employ a single-edge-triggered serial communication protocol. This protocol uses a set of data signal lines, a clock signal line, and a chip select signal line for data transmission between master and slave devices. The data signal lines are used for writing / reading data, the clock signal line drives the internal timing logic circuitry of the memory chip, and the chip select signal line selects or deselects the memory chip. The clock signal is generally a fixed-frequency square wave. During data transmission, the data signal lines transition on the rising or falling edge of the clock signal to achieve the purpose of data transmission.

[0003] In the process of implementing the embodiments of this disclosure, it was found that at least the following problems exist in the related technology: non-volatile memory chips use a single-edge triggered serial communication protocol for data communication, resulting in a slow data transmission rate. Summary of the Invention

[0004] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0005] This disclosure provides a dual-edge sampling circuit and a data sampling method, apparatus, and system therefor. The dual-edge sampling circuit can effectively improve the data transmission rate by using dual-edge sampling for data communication.

[0006] In some embodiments, the dual-edge sampling circuit includes a decoding circuit, which includes a first decoding shift register, a second decoding shift register, a bitwise operation unit, and an address register. Specifically: the first decoding shift register is electrically connected to a bidirectional data output device via a bidirectional data port and to an external clock via a clock port, and is configured to sample external data from the bidirectional data output device using the rising edge of the external clock to obtain rising edge data; the second decoding shift register is electrically connected to the bidirectional data output device via a bidirectional data port and to an external clock via a clock port, and is configured to sample external data from the bidirectional data output device using the falling edge of the external clock to obtain falling edge data; the bitwise operation unit is electrically connected to the first and second decoding shift registers and is configured to use bitwise operation to combine the rising edge data and the falling edge data into two bits, obtaining data from two clock edges; the address register is electrically connected to the bitwise operation unit and to an external clock via a clock port, and is configured to use the external clock to perform address concatenation of the data from the two clock edges.

[0007] In some embodiments, the data sampling method for the dual-edge sampling circuit includes: in the dual-edge sampling output mode, sampling external data of the bidirectional data output device using the rising edge of the external clock to obtain rising edge data; sampling external data using the falling edge of the external clock to obtain falling edge data; using bitwise operations to concatenate the rising edge data and the falling edge data into two bits to obtain data for two clock edges; and using the external clock to complete the address concatenation of the data for the two clock edges.

[0008] In some embodiments, the data sampling device for a dual-edge sampling circuit includes a processor and a memory storing program instructions, the processor being configured to execute the aforementioned data sampling method for a dual-edge sampling circuit when executing the program instructions.

[0009] In some embodiments, the data sampling system for the dual-edge sampling circuit includes: a decoding circuit, an encoding circuit, a bidirectional data output device, an external clock, and the aforementioned data sampling device for the dual-edge sampling circuit; wherein the encoding circuit is electrically connected to the decoding circuit, the bidirectional data output device is electrically connected to the decoding circuit through a bidirectional data port, and the external clock is electrically connected to the decoding circuit through a clock port and to the encoding circuit through a clock port.

[0010] The dual-edge sampling circuit and the data sampling method, apparatus and system therefor provided in the embodiments of this disclosure can achieve the following technical effects:

[0011] The dual-edge sampling circuit of this disclosure uses a first decoding shift register to sample external data from the bidirectional data output device using the rising edge of the external clock, and a second decoding shift register to sample external data from the bidirectional data output device using the falling edge of the external clock. Then, a bit-merging unit uses bit-merging operations to combine the rising and falling edge data obtained from the two sets of shift registers into two bits, resulting in data from two clock edges. The address register uses the external clock to perform address concatenation of the data from the two clock edges. In this way, the dual-edge sampling circuit uses two sets of shift registers to sample data at the rising and falling edges of the external clock, respectively, and generates data that transitions at the rising and falling edges of the clock. By using dual-edge sampling for data communication, the data transmission rate is doubled while reducing or maintaining the communication clock frequency, significantly improving the data read rate of non-volatile memory, while the lower communication clock frequency ensures signal quality.

[0012] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0013] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein:

[0014] Figure 1 This is a schematic diagram of the structure of a decoding circuit for a dual-edge sampling circuit provided in an embodiment of this disclosure;

[0015] Figure 2 This is a schematic diagram of the decoding circuit structure of another dual-edge sampling circuit provided in this embodiment of the present disclosure;

[0016] Figure 3 This is a signal timing diagram of a decoding circuit for a dual-edge sampling circuit provided in an embodiment of this disclosure;

[0017] Figure 4 This is a schematic diagram of the structure of an encoding circuit for a dual-edge sampling circuit provided in an embodiment of this disclosure;

[0018] Figure 5 This is a schematic diagram of the encoding circuit of another dual-edge sampling circuit provided in this embodiment of the present disclosure;

[0019] Figure 6 This is a schematic flowchart of a data sampling method for a dual-edge sampling circuit provided in an embodiment of this disclosure;

[0020] Figure 7 This is a schematic flowchart of another data sampling method for a dual-edge sampling circuit provided in an embodiment of this disclosure;

[0021] Figure 8 This is a schematic diagram of another data sampling device for a dual-edge sampling circuit provided in an embodiment of this disclosure. Detailed Implementation

[0022] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0023] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0024] Unless otherwise stated, the term "multiple" means two or more. In embodiments of this disclosure, the character " / " indicates that the preceding and following objects are in an "OR" relationship. For example, A / B means: A or B. The term "and / or" describes an association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B. The term "correspondence" can refer to an association or binding relationship; A corresponding to B means that there is an association or binding relationship between A and B.

[0025] Combination Figure 1As shown, this disclosure provides a dual-edge sampling circuit including a decoding circuit. The decoding circuit includes a first decoding shift register, a second decoding shift register, a bitwise operation unit, and an address register. The first decoding shift register is electrically connected to a bidirectional data output device via a bidirectional data port and to an external clock via a clock port. It is configured to sample external data from the bidirectional data output device using the rising edge of the external clock to obtain rising edge data. The second decoding shift register is also electrically connected to the bidirectional data output device via a bidirectional data port and to an external clock via a clock port. It is configured to sample external data from the bidirectional data output device using the falling edge of the external clock to obtain falling edge data. The bitwise operation unit is electrically connected to both the first and second decoding shift registers and is configured to use bitwise operations to combine the rising edge data and the falling edge data into two bits, obtaining data from two clock edges. The address register is electrically connected to the bitwise operation unit and to an external clock via a clock port. It is configured to use the external clock to perform address concatenation of the data from the two clock edges.

[0026] The following explanation uses a dual-edge sampling address circuit as an example, specifically a 24-bit address sampling circuit. Figure 2 As shown, the decoding circuit requires 12 first decoding shift registers (rising edge shift registers) and 12 second decoding shift registers (falling edge shift registers). The bidirectional data port of the bidirectional data output device is simultaneously connected to the least significant bit input of both the rising edge shift register and the falling edge shift register. Each clock cycle, the rising edge shift register and the falling edge shift register sample the port data at the rising and falling edges, respectively, and in the next clock cycle, shift the sampled data to the higher-order shift registers. After 12 clock cycles, the address sampling is complete. The outputs of the two sets of 12-bit shift registers are arranged according to Table 1 (Table 1 shows the arrangement order of the 24-bit address code) to complete the address concatenation, and then output to the address register for address retrieval in the internal non-volatile memory unit.

[0027] Table 1

[0028] register High 0 Low 0 Grade 11 Low 1 Grade 11 Low 2 Grade 3 … Low 9 10 High 10 lower Grade 11 Low 11 address 0 1 2 3 4 5 6 … 19 20 21 22 23

[0029] Figure 3 This is a signal timing diagram of a decoding circuit for a dual-edge sampling circuit provided in an embodiment of this disclosure. For example... Figure 3As shown, the rising edge register samples the rising edge data "1000_1000_1011", and the falling edge register samples the falling edge data "1011_0010_1011". The rising edge data and the falling edge data are concatenated and combined in the order of Table 1 to obtain the data "1100_0101_1000_0100_1100_1111", which is the address data sent on the external data line.

[0030] The dual-edge sampling circuit of this disclosure uses a first decoding shift register to sample external data from the bidirectional data output device using the rising edge of an external clock, and a second decoding shift register to sample external data from the bidirectional data output device using the falling edge of an external clock. Then, a bitwise concatenation unit uses concatenation operations to combine the rising and falling edge data obtained from the two sets of shift registers into two bits, resulting in data from two clock edges. The address register uses the external clock to perform address concatenation of the data from the two clock edges. Thus, the dual-edge sampling circuit uses two sets of shift registers to sample data at the rising and falling edges of the external clock, respectively, and generates data that transitions at the rising and falling edges of the clock. By employing dual-edge sampling for data communication, the data transmission rate is doubled while reducing or maintaining the communication clock frequency, significantly improving the data read rate of non-volatile memory. Simultaneously, the lower communication clock frequency ensures signal quality. Furthermore, since the dual-edge sampling circuit of this disclosure only uses an external clock signal, it is applicable to non-volatile memory.

[0031] In some embodiments, such as Figure 4 As shown, the dual-edge sampling circuit also includes an encoding circuit electrically connected to the decoding circuit. This encoding circuit includes a first encoding shift register, a second encoding shift register, and a selector. Specifically: the first encoding shift register is electrically connected to the address register and to an external clock via a clock port, and is configured to use the external clock to store high-level data from the two clock edges of the address register; the second encoding shift register is electrically connected to the address register and to an external clock via a clock port, and is configured to use the external clock to store low-level data from the two clock edges of the address register; the selector is electrically connected to both the first and second encoding shift registers and to an external clock via a clock port, and is configured to output high-level data from the first encoding shift register when the external clock signal is high, and output low-level data from the second encoding shift register when the external clock signal is low.

[0032] Figure 5 This is a schematic diagram of the encoding circuit of another dual-edge sampling circuit provided in this embodiment of the disclosure. (Combined with...) Figure 5As shown, if 32 bits of data can be read from the internal non-volatile memory cell each time, the encoding circuit requires 16 first encoding shift registers (high-level data shift registers) and 16 second encoding shift registers (low-level data shift registers). The mapping relationship between 32 bits of data and shift registers is shown in Table 2 below. Table 2 shows the encoding order for generating 4 bytes of 8 bits of data.

[0033] Table 2

[0034] 32-bit data 0 1 2 3 4 5 6 … 27 28 29 30 31 register Low 0 High 0 Low 1 Grade 11 Low 2 Grade 11 Low 3 … 13 Low 14 14 15 lower 15 High

[0035] If each output is 8 bits of data (one byte) and outputs from the most significant bit to the least significant bit, then the high-level data register "High 3" and the low-level data register "Low 3" are connected to the two inputs of the selector, respectively. Since the selector's selection port is controlled by a clock signal, when the first clock cycle is high, the "High 3" register first outputs the 7th bit of data, which is the most significant bit of the first byte; when the first clock cycle is low, the "Low 3" register outputs the 6th bit of data, and so on. After 16 clock cycles, all 32 bits of data are output.

[0036] Using the dual-edge sampling circuit of this disclosure, high-level data read from the address register of the internal memory unit is stored in the first encoding shift register, and low-level data read from the address register of the internal memory unit is stored in the second encoding shift register. The first and second encoding shift registers use the same clock and are updated simultaneously. The outputs of the first and second encoding shift registers are respectively connected to the two inputs of a 2-to-1 selector. The selector uses the same clock signal as the first and second encoding shift registers. When the clock signal is high, the selector outputs high-level data; when the clock signal is low, the selector outputs low-level data. In this way, the dual-edge sampling circuit achieves the output of sampled data, doubling the data transmission rate while reducing or maintaining the communication clock, thus improving the data read and output rate of the non-volatile memory.

[0037] Combination Figure 6 As shown, this disclosure provides a data sampling method for a dual-edge sampling circuit, including the following steps:

[0038] S601, in dual-edge sampling output mode, uses the rising edge of the external clock to sample the external data of the bidirectional data output device to obtain rising edge data.

[0039] S602 uses the falling edge of an external clock to sample external data to obtain falling edge data.

[0040] S603 uses bitwise operations to combine rising edge data and falling edge data into two bits, resulting in data from two clock edges.

[0041] Optionally, bitwise operations are used to combine the rising edge data and falling edge data into two bits to obtain data from two clock edges, including: sequentially determining the signal timing bits of each data in the rising edge data and falling edge data; determining the signal timing bit S in the rising edge data. n Data D up-n ; Determine the signal timing bit in the falling edge data as S n Data D down-n ; data D down-n spliced ​​from data D up-n Then, the data D from the two clock edges is obtained. up-nDdown-n .

[0042] For example, if the rising edge data is "1000_1000_1011", then from left to right, the signal timing bits of the rising edge data are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11; if the falling edge data is "1011_0010_1011", then from left to right, the signal timing bits of the falling edge data are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11.

[0043] Determine the data D with signal timing bit S0 in the rising edge data. up-0 If the value is 1, then the data D with signal timing bit S0 in the falling edge data is determined. down-0 If the value is 1, then the data D will be... down-0 (1) spliced ​​into data D up-0 (1) After that, the data D from the two clock edges is obtained. up-0 D down-0 It is "11".

[0044] When the rising edge data and falling edge data are each 1 bit, the data D on both clock edges up-0 D down-0 This refers to the data from the final two clock edges. When the rising and falling edge data are multiple bits, it is also necessary to concatenate the data from the two clock edges into a single data set (D). up-nDdown-n The data is sorted to determine the final two clock edges.

[0045] Optionally, the rising edge data and falling edge data are concatenated into two bits using bitwise operations to obtain data from two clock edges. This also includes obtaining the data D from the two clock edges. up-nDdown-n Then, the data D from the two clock edges of the multiple spliced ​​data blocks are arranged in ascending order of signal timing bits. up-nDdown-n Sort the data to obtain the data from the two clock edges.

[0046] For example, obtaining data D from two clock edgesup-0 D down-0 D up-1 D down-1 D up-2 D down-2 D up-3 D down-3 Then, the data from the two clock edges of the multiple spliced ​​data points are sorted in ascending order of signal timing bits, and D is sequentially... up- 1D down-1 Arranged to D up-0 D down-0 Next, D up-2 D down-2 Arranged to D up-1 D down-1 Next, D up-3 D down-3 Arranged to D up-2 D down-2 Subsequently, the data D from the final two clock edges is obtained. up-0 D down-0 D up-1 D down-1 D up-2 D down-2 D up-3 D down-3 .

[0047] Optionally, the rising edge data and falling edge data are concatenated into two bits using bitwise operations to obtain data from two clock edges. This also includes obtaining the data D from the two clock edges. up-nDdown-n Then, the data D from two adjacent clock edges of the signal timing bits are processed in ascending order. up-n-1 D down-n-1 and D up-nDdown-n By combining the data, we obtain the combined data D from the two clock edges. up-n-1 D down-n-1 D up-n D down-n ; The data D from two clock edges of the combined sequence are processed in ascending order of signal timing bits. up-n-1 D down-n-1 D up-n D down-n Sort the data to obtain the data from the two clock edges.

[0048] For example, obtaining data D from two clock edges up-0 D down-0 D up-1 D down-1 D up-2 D down-2 D up-3 D down-3 Then, the data D from two adjacent clock edges of the signal timing bits are processed in ascending order. up-0D down-0 and D up-1 D down-1 Combining them yields D up-0 D down-0 D up-1 D down-1 The data D from two adjacent clock edges of the signal timing bit. up-2 D down-2 and D up- 3D down-3 Combining them yields D up-2 D down-2 D up-3 D down-3 The data D from two clock edges of the combined sequence are processed in ascending order of signal timing bits. up-0 D down-0 D up-1 D down-1 and D up-2 D down-2 D up-3 D down-3 Sort the data to obtain the data D from the two clock edges. up-0 D down-0 D up-1 D down-1 D up-2 D down-2 D up-3 D down-3 .

[0049] When the data volume on both clock edges is large, and the rising edge data and falling edge data are concatenated, the data D from two clock edges with adjacent signal timing bits are first concatenated in parallel. up-n-1 D down-n-1 and D up-nDdown-n Combine the data from the two clock edges of the combined data, and then combine the data from the two clock edges. up-n-1 D down-n-1 D up-n D down-n Sorting can increase the splicing rate of rising and falling edge data and shorten the splicing time of rising and falling edge data, thereby significantly improving the data read rate of non-volatile memory.

[0050] The S604 uses an external clock to concatenate the addresses of data from two clock edges.

[0051] After obtaining the data from the two clock edges, an external clock is used to arrange the addresses of the data from the two clock edges according to Table 1 above, and then the data is output to the address register.

[0052] The data sampling method for a dual-edge sampling circuit provided in this disclosure uses two sets of shift registers to sample data at the rising and falling edges of an external clock, generating data that transitions at the rising and falling edges of the clock. By employing dual-edge sampling for data communication, the data transmission rate is doubled while reducing or maintaining the communication clock frequency, significantly improving the data read rate of non-volatile memory. Simultaneously, the lower communication clock frequency ensures signal quality. Furthermore, since the dual-edge sampling circuit of this disclosure uses only an external clock signal, it is applicable to non-volatile memory.

[0053] Combination Figure 7 As shown, this disclosure provides a data sampling method for a dual-edge sampling circuit, including the following steps:

[0054] In dual-edge sampling output mode, S701 uses the rising edge of the external clock to sample external data from the bidirectional data output device to obtain rising edge data.

[0055] The S702 uses the falling edge of an external clock to sample external data to obtain falling edge data.

[0056] The S703 uses bitwise operations to combine rising edge data and falling edge data into two bits, resulting in data from two clock edges.

[0057] The S704 uses an external clock to concatenate the addresses of data from two clock edges.

[0058] The S705 uses an external clock to store the high-level and low-level data from two clock edges.

[0059] The S706 outputs high-level data when the external clock signal is high and low-level data when the external clock signal is low.

[0060] Optionally, when the external clock signal is high, high-level data is output, and when the external clock signal is low, low-level data is output, including: determining the number of output bits M for high-level data; determining the number of output bits N for low-level data; when the external clock signal is high, outputting M high-level data in order from high bit to low bit; and when the external clock signal is low, outputting N low-level data in order from high bit to low bit.

[0061] For example, if 8 bits of data (one byte) are output each time, the number of high-level data bits (M) in the output data is determined to be 4, and the number of low-level data bits (N) in the output data is determined to be 4. The high-level data register "High 3" and the low-level data register "Low 3" are connected to the two inputs of the selector, respectively. During the high-level state of the first clock cycle, the "High 3" register first outputs the 7th bit of data, which is the most significant bit of the first byte; during the low-level state of the first clock cycle, the "Low 3" register outputs the 6th bit of data. Thus, four high-level data bits and four low-level data bits are output sequentially from most significant bit to least significant bit, ultimately outputting 8 bits of data.

[0062] The data sampling method for dual-edge sampling circuits disclosed herein doubles the data transmission rate by employing dual-edge sampling for data communication, significantly improving the data read rate of non-volatile memory while maintaining or reducing the communication clock frequency. Simultaneously, the lower communication clock frequency ensures signal quality. Furthermore, when the clock signal is high, the selector outputs high-level data; when the clock signal is low, the selector outputs low-level data, thus achieving the output of sampled data from the dual-edge sampling circuit. This doubles the data transmission rate while maintaining or reducing the communication clock frequency, thereby increasing the data output rate of non-volatile memory.

[0063] In some embodiments, the data sampling method for the dual-edge sampling circuit further includes: in the case of single-edge sampling output mode, a first decoding shift register samples external data of the bidirectional data output device using the rising edge of an external clock to obtain rising edge data; a first encoding shift register stores the rising edge data; and a selector outputs data when the clock signal of the external clock is low.

[0064] The data sampling method for dual-edge sampling circuits disclosed herein can be compatible with single-edge sampling encoding and decoding because it relies solely on an external clock for sampling, thus having a wider range of applications.

[0065] Combination Figure 8 The present disclosure provides a data sampling device for a dual-edge sampling circuit, including a processor 80 and a memory 81, and may further include a communication interface 82 and a bus 83. The processor 80, communication interface 82, and memory 81 can communicate with each other via the bus 83. The communication interface 82 can be used for information transmission. The processor 80 can call logical instructions in the memory 81 to execute the data sampling method for the dual-edge sampling circuit described in the above embodiment.

[0066] Furthermore, the logic instructions in the aforementioned memory 81 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0067] The memory 81, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 80 executes functional applications and data processing by running the program instructions / modules stored in the memory 81, that is, it implements the data sampling method for the dual-edge sampling circuit in the above method embodiments.

[0068] The memory 81 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 81 may include high-speed random access memory and may also include non-volatile memory.

[0069] The data sampling device for a dual-edge sampling circuit provided in this disclosure uses two sets of shift registers to sample data at the rising and falling edges of an external clock, respectively, and generates data that transitions at the rising and falling edges of the clock. By employing dual-edge sampling for data communication, the data transmission rate is doubled while reducing or maintaining the communication clock frequency, which can significantly improve the data read rate of non-volatile memory, while the lower communication clock frequency ensures signal quality.

[0070] This disclosure provides a data sampling system for a dual-edge sampling circuit, comprising: a decoding circuit, an encoding circuit, a bidirectional data output device, an external clock, and the aforementioned data sampling device for the dual-edge sampling circuit; wherein, the encoding circuit is electrically connected to the decoding circuit, the bidirectional data output device is electrically connected to the decoding circuit through a bidirectional data port, and the external clock is electrically connected to the decoding circuit through a clock port and to the encoding circuit through a clock port.

[0071] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured to perform the data sampling method described above for a dual-edge sampling circuit.

[0072] This disclosure provides a computer program product, which includes a computer program stored on a computer-readable storage medium. The computer program includes program instructions that, when executed by a computer, cause the computer to perform the data sampling method described above for a dual-edge sampling circuit.

[0073] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0074] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code; it can also be a transient storage medium.

[0075] The foregoing description and accompanying drawings fully illustrate embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included or substituted for parts and features of other embodiments. The scope of the embodiments of this disclosure includes the entire scope of the claims and all available equivalents of the claims. While the terms “first,” “second,” etc., may be used in this application to describe elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be called a second element without changing the meaning of the description, and similarly, a second element may be called a first element, provided that all occurrences of “first element” are consistently renamed and all occurrences of “second element” are consistently renamed. First and second elements are both elements, but may not be the same element. Moreover, the terminology used in this application is only for describing embodiments and is not intended to limit the claims. As used in the description of the embodiments and claims, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to also include the plural forms. Similarly, the term “and / or” as used herein means including one or more of the associated listed any and all possible combinations. Additionally, when used herein, the terms “comprise” and its variations “comprises” and / or “comprising” refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase “comprising an…” does not exclude the presence of additional identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0076] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0077] The methods and products disclosed in the embodiments herein (including but not limited to devices and equipment) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to implement this embodiment according to actual needs. In addition, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0078] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A dual-edge sampling circuit, characterized in that, Includes a decoding circuit, wherein: The decoding circuit includes: The first decoding shift register is electrically connected to the bidirectional data output device through a bidirectional data port and electrically connected to an external clock through a clock port. It is configured to sample the external data of the bidirectional data output device using the rising edge of the external clock to obtain rising edge data. The second decoding shift register is electrically connected to the bidirectional data output device through the bidirectional data port and electrically connected to the external clock through the clock port. It is configured to use the falling edge of the external clock to sample the external data of the bidirectional data output device to obtain falling edge data. The bit-merging unit, electrically connected to the first decoding shift register and the second decoding shift register, is configured to use bit-merging operations to merge the rising edge data and the falling edge data into two bits to obtain data from two clock edges; The address register is electrically connected to the concatenation unit and to the external clock via the clock port. It is configured to use the external clock to concatenate the addresses of the data on the two clock edges.

2. The dual-edge sampling circuit according to claim 1, characterized in that, It also includes an encoding circuit electrically connected to the decoding circuit, wherein: The encoding circuit includes: A first encoding shift register, electrically connected to the address register and electrically connected to the external clock via the clock port, is configured to use the external clock to store high-level data from the two clock edges of the address register; The second encoding shift register, electrically connected to the address register and electrically connected to the external clock via the clock port, is configured to use the external clock to store low-level data from the two clock edges of the address register; The selector, electrically connected to the first and second encoded shift registers and electrically connected to the external clock via the clock port, is configured to output high-level data in the first encoded shift register when the clock signal of the external clock is high, and to output low-level data in the second encoded shift register when the clock signal of the external clock is low.

3. A data sampling method for a dual-edge sampling circuit as described in claim 1 or 2, characterized in that, include: In the dual-edge sampling output mode, the rising edge of the external clock is used to sample the external data of the bidirectional data output device to obtain the rising edge data. The external data is sampled using the falling edge of the external clock to obtain falling edge data; The rising edge data and the falling edge data are combined into two bits using bitwise operations to obtain data from two clock edges; The external clock is used to concatenate the addresses of the data from the two clock edges.

4. The data sampling method according to claim 3, characterized in that, The step of using bitwise concatenation to combine the rising edge data and the falling edge data into two bits, resulting in data from two clock edges, includes: Sequentially determine the signal timing bits of each data in the rising edge data and the falling edge data; The signal timing bit in the rising edge data is determined to be S. n Data D up-n ; The signal timing bit in the falling edge data is determined to be S. n Data D down-n ; Data D down-n spliced ​​from data D up-n Then, the data D from the two clock edges is obtained. up-nDdown-n .

5. The data sampling method according to claim 4, characterized in that, The step of using bitwise concatenation to combine the rising edge data and the falling edge data into two bits to obtain data from two clock edges also includes: The data D obtained from the two clock edges up-nDdown-n Then, the data D from the two clock edges are processed in ascending order of signal timing bits. up-nDdown-n The data from the two clock edges are sorted to obtain the data.

6. The data sampling method according to claim 4, characterized in that, The step of using bitwise concatenation to combine the rising edge data and the falling edge data into two bits to obtain data from two clock edges also includes: The data D obtained from the two clock edges up-nDdown-n Then, the data D from two adjacent clock edges of the signal timing bits are processed in ascending order. up-n-1 D down-n-1 and D up-nDdown-n By combining the data, we obtain the combined data D from the two clock edges. up-n-1 D down-n-1 D up-n D down-n ; The data D from two clock edges of the combined sequence are processed in ascending order of signal timing bits. up-n-1 D down-n-1 D up- n D down-n The data from the two clock edges are sorted to obtain the data.

7. The data sampling method according to claim 3, characterized in that, After using the external clock to concatenate the addresses of the data from the two clock edges, the method further includes: The external clock is used to store the high-level data and low-level data from the two clock edges; When the external clock signal is high, high-level data is output, and when the external clock signal is low, low-level data is output.

8. The data sampling method according to claim 7, characterized in that, The step of outputting high-level data when the external clock signal is high and outputting low-level data when the external clock signal is low includes: Determine the number of high-level data bits M in the output data; Determine the number of low-level data bits N in the output data; When the external clock signal is high, M high-level data are output in order from high bit to low bit. When the external clock signal is low, N low-level data are output in order from high-order bits to low-order bits.

9. A data sampling device for a dual-edge sampling circuit, comprising a processor and a memory storing program instructions, characterized in that, The processor is configured to, when executing the program instructions, perform the data sampling method for a dual-edge sampling circuit as described in any one of claims 3 to 8.

10. A data sampling system for a dual-edge sampling circuit, characterized in that, include: Decoding circuit; The encoding circuit is electrically connected to the decoding circuit; A bidirectional data output device is electrically connected to the decoding circuit via a bidirectional data port; An external clock is electrically connected to the decoding circuit via a clock port, and also electrically connected to the encoding circuit via the clock port; and... The data sampling device for a dual-edge sampling circuit as described in claim 9.

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