A heterojunction synaptic transistor with unipolar voltage regulation performance and its fabrication method.

Abstract

This invention belongs to the fields of semiconductor technology and neuromorphic hardware, specifically relating to a heterojunction synaptic transistor with unipolar voltage regulation performance and its fabrication method. The heterojunction synaptic transistor of this invention comprises, from bottom to top, a substrate (1), a gate electrode (2), a gate insulating layer (3), a charge trapping layer (4), a P / N heterojunction (5), and source / drain electrodes (6). The P / N heterojunction consists of two layers: a P-type semiconductor layer and an N-type semiconductor layer. This invention utilizes the fabricated P / N heterojunction structure and the charge trapping layer to achieve the bipolar characteristics of the heterojunction synaptic transistor, meaning the heterojunction synaptic transistor can achieve both N-type and P-type characteristics. Furthermore, based on the bipolarity of the heterojunction synaptic transistor, through the synergistic or competitive effects of the P / N heterojunction and the charge trapping layer, combined with a unipolar voltage regulation method, adjustable control of the device's unipolar voltage can be achieved.

Description

Technical Field

[0001] This invention belongs to the fields of semiconductor technology and neuromorphic hardware, specifically relating to a heterojunction synaptic transistor with unipolar voltage regulation performance and its fabrication method. Background Technology

[0002] In recent years, with the rapid development of the information age, artificial intelligence (AI), the Internet of Things (IoT), and big data have become popular research areas with broad application prospects, such as speech recognition, image processing, and automatic driving technology. However, for traditional computers based on the von Neumann architecture, the physical separation of storage units and processors reduces computational efficiency due to data transfer between the two units, gradually failing to meet the demands of storage-based computing. Therefore, expanding the in-memory computing unit using different mechanisms is a necessary step to break through the development of artificial intelligence at the hardware level. Among these, reconfigurable three-terminal synaptic transistors are one of the most promising technologies for constructing neuromorphic hardware devices, and voltage regulation under unipolar conditions has greatly expanded the application prospects of neuromorphic chips.

[0003] Synaptic transistors, such as P / N heterojunction transistors, have two different semiconductor channels under different voltage biases. Under specific structures, they can realize bipolar devices, thus leading to in-depth research on heterojunction transistors. For example, organic transistor memory devices with heterojunction structures have been fabricated using P / N hybrid heterojunctions as semiconductor layers. Under visible light stimulation, the devices have a large storage window, good non-volatile storage characteristics, and can be used as synaptic devices in the field of neuromorphology (ACS Photonics, 2021, 8(10): 3094-3103). Organic phosphorus-nitrogen heterojunctions have been constructed using low-temperature processing methods. By controlling the bipolar voltage, the dual channels of the heterojunction structure can simulate the co-release of different neurotransmitters (Advanced Science, 2022, 9(1): 2102036). Synaptic transistors fabricated using heterojunction nanowire structures can be used to simulate biological synaptic functions. Under the control of bipolar voltage, the device can exhibit either an excited or inhibited state (Advanced Functional Materials, 2021, 31(27): 2101917). Furthermore, bipolar devices have been fabricated using single-component bipolar materials. Under the control of bipolar voltage, these devices also exhibit either an excited or inhibited state (ACS Applied Materials & Interfaces, 2020, 12(13): 15446-15455).

[0004] Unipolar voltage modulation refers to the voltage polarity used to regulate device performance, which can be either positive or negative. Traditional transistor devices require bidirectional voltages (positive and negative) to achieve switching operations, thus enabling write / erase or excitation / inhibition functions. Unipolar synaptic transistors, however, require only a single-polarity voltage. Utilizing the magnitude of the voltage (i.e., unipolar SVDP), they exhibit inhibition under low-voltage stimulation and enhancement under high-voltage stimulation. Unipolar voltage modulation can precisely control the increase or decrease of the device's conductance under a single voltage, simulating the excitation and inhibition behavior of biological synapses under the same voltage polarity. Therefore, unipolar synaptic transistors play a significant role in simulating biological synaptic functions. Unipolar modulation not only has advantages in simulating biological synapses but also holds broad application prospects in neuromorphic computing and intelligence. Therefore, developing new materials, structures, and fabrication processes suitable for unipolar voltage-modulated synaptic transistor devices is particularly important. However, most devices currently only achieve bipolar voltage modulation, and there are no successful examples of unipolar voltage modulation for organic synaptic transistors. Summary of the Invention

[0005] This invention addresses the problems existing in the prior art by providing a heterojunction synaptic transistor with unipolar voltage regulation performance and its fabrication method. The synaptic transistor can achieve multi-level switching characteristics through unipolar voltage regulation, which can be used for simulating synaptic plasticity function.

[0006] The inventors discovered that, in this invention, the bipolar characteristics of a transistor can be achieved through the combination of a P / N heterojunction and a charge trapping layer. Furthermore, in this invention, through the synergistic or competitive interaction of the P / N heterojunction and the charge trapping layer, combined with a unipolar voltage regulation method, a synaptic transistor with bipolar characteristics can achieve unipolar voltage regulation.

[0007] In a first aspect of the invention, a heterojunction synaptic transistor with unipolar voltage regulation performance is provided.

[0008] The heterojunction synaptic transistor comprises, from bottom to top, a substrate, a gate electrode, a gate insulating layer, a charge trapping layer, a P / N heterojunction, and source / drain electrodes. The P / N heterojunction consists of two layers: a P-type semiconductor layer and an N-type semiconductor layer. Specifically, the P / N heterojunction can have either the P-type semiconductor layer on top and the N-type semiconductor layer on the bottom, or vice versa.

[0009] Furthermore, the charge trapping layer is used to achieve high-capacity charge storage. The charge trapping layer is a medium with charge trapping properties, such as poly(2-vinylnaphthalene) (PVN), poly(9-vinylcarbazole) (PVK), poly(4-vinylphenol) (PVP), and polystyrene (PS), and the thickness of the charge trapping layer is 1~50 nm. In a preferred embodiment of the present invention, the material of the charge trapping layer is preferably PVN, and the thickness of the charge trapping layer is 5 nm.

[0010] Further, the material of the P-type semiconductor layer is a P-type organic semiconductor or a P-type inorganic semiconductor, including pentacene, bis(2,3-B:2′,3′-F)thieno[3,2-B]thiophene (DNTT), or 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT), zinc selenide (ZnSe), and zinc sulfide (ZnS), and the thickness of the P-type semiconductor layer is 1~200 nm. In a preferred embodiment of the present invention, the material of the P-type semiconductor layer is pentacene, and the thickness of the P-type semiconductor layer is 50 nm.

[0011] Furthermore, the material of the N-type semiconductor layer is an N-type organic semiconductor or an N-type inorganic semiconductor, including N,N'-tetracarboxylic acid diimide (PTCDI-C). 13 The N-type semiconductor layer is made of copper hexadecyl phthalocyanine (F16CuPc), 1,4,5,8-naphthalenetetracarboxylic anhydride (NTCDA) or naphthalenedimide (NDI), indium gallium zinc oxide (IGZO), or zinc oxide (ZnO), and the thickness of the N-type semiconductor layer is 1~200 nm. In a preferred embodiment of the present invention, the material of the N-type semiconductor layer is preferably PTCDI-C. 13 The thickness of the N-type semiconductor layer is 10 nm.

[0012] Furthermore, the gate electrode is made of any one of conductive metals, oxides, and nitrides such as Al, Au, Pt, ITO, TaN, highly doped silicon, or graphene.

[0013] Furthermore, the gate insulating layer covers the entire surface of the gate electrode, isolating the contact between the gate electrode and the charge trapping layer, which can effectively reduce the gate leakage current. The gate insulating layer is made of dielectric materials such as alumina, silicon dioxide, hafnium oxide, polymethyl methacrylate (PMMA), polyvinylidene fluoride (PVDF) and its derivatives, and the film thickness of the gate insulating layer is 10~300 nm.

[0014] Furthermore, the source and drain electrodes are grown on both sides of the conductive channel, and are made of any one of conductive metals, oxides, and nitrides such as Al, Au, Pt, ITO, TaN, highly doped silicon, or graphene, with a thickness of 20-200 nm. They are prepared using one or more physical or chemical deposition methods, including thermal evaporation, magnetron sputtering, electron beam evaporation, and atomic layer deposition (ALD).

[0015] Furthermore, in the unipolar voltage-controlled heterojunction synaptic transistor, the source and drain are arranged in a coplanar manner, forming a channel structure between the source and drain. The ratio of the channel width W to the channel length L is typically 10 to 30, preferably 10. Additionally, those skilled in the art can adjust the channel width W and channel length L according to the device size, source-drain current, and source-drain voltage requirements.

[0016] In a second aspect of the invention, a method for fabricating a heterojunction synaptic transistor as described in the first aspect is provided.

[0017] The preparation method includes the following steps:

[0018] 1) Clean the substrate with acetone, ethanol and deionized water respectively for 5-20 minutes, and dry it after cleaning.

[0019] 2) Prepare a charge trapping layer solution by dissolving it in an organic solvent until it is fully dissolved;

[0020] 3) Spin-coat the clean substrate film from step 1) with the charge trapping layer solution prepared in step 2);

[0021] 4) On the sample prepared in step 3), a P / N heterojunction and source / drain electrodes are prepared.

[0022] Further, in step 3), the organic solvent is one or more of 1,2-dichloroethane, toluene, or chlorobenzene, solvents capable of dissolving the charge-trapping medium. In a preferred embodiment of the present invention, the organic solvent is toluene.

[0023] Further, in step 4), the P / N heterojunction thin film is prepared using physical or chemical methods, including solution methods such as spin-coating, sol-gel, spraying, silk-screen printing, and inkjet printing, or methods such as thermal evaporation, magnetron sputtering, electron beam evaporation, and atomic layer deposition (ALD). In a preferred embodiment of the present invention, the P / N heterojunction is prepared using thermal evaporation at a deposition rate of 0.2 Å / s.

[0024] Further, in step 4), the source / drain electrodes are prepared using physical or chemical deposition methods, including thermal evaporation, magnetron sputtering, electron beam evaporation, and atomic layer deposition (ALD). In a preferred embodiment of the invention, the source / drain electrodes are prepared using thermal evaporation at a deposition rate of 0.5 Å / s.

[0025] In a third aspect of the invention, a method for controlling a heterojunction synaptic transistor as described in the first aspect is provided.

[0026] The aforementioned control method specifically involves setting the device current level to 10. -12 A ~10 -3 A represents the initial state. By applying a unipolar voltage to the fabricated device, it can be made to exhibit excitation or inhibition functions.

[0027] In this invention, a heterojunction synaptic transistor with unipolar voltage regulation can be used in the process of simulating biological synapses, achieving effective regulation of excitation / inhibition plasticity in biological synaptic function. To simulate synaptic function, the transistor uses an external input signal as stimulation, with the gate acting as the synaptic front end, and the channel and source / drain electrodes as the synaptic back end. The source / drain current level, which is controlled in real time, serves as the synaptic weight, playing a role in signal transmission. The device performance exhibits characteristics similar to biological synapses, meaning that voltages of different polarities can be used to simulate the excitation and inhibition functions of biological synapses.

[0028] The present invention has the following beneficial effects:

[0029] 1) This invention utilizes the fabricated P / N heterojunction and charge-trapping layer structure to achieve the bipolar characteristics of a heterojunction synaptic transistor, meaning the heterojunction synaptic transistor can exhibit both N-type and P-type characteristics. Furthermore, based on the bipolar characteristics of the heterojunction synaptic transistor, through the synergistic or competitive interaction of the P / N heterojunction and the charge-trapping layer, combined with specific control methods, unipolar voltage regulation of the device can be achieved. That is, only a positive or negative voltage needs to be applied, enabling both excitation and inhibition of the synaptic performance of the heterojunction synaptic transistor. However, while some existing heterojunction synaptic transistors can achieve bipolar characteristics, their synaptic performance can only be achieved using bidirectional voltages for excitation and inhibition, and cannot achieve unipolar voltage regulation. Therefore, compared to existing technologies, the heterojunction synaptic transistor with unipolar voltage regulation performance in this invention has unexpected technical advantages.

[0030] 2) The heterojunction synaptic transistor with unipolar voltage regulation performance provided by the present invention can form unipolar voltage regulation characteristics under negative voltage, which makes neuromorphic computing possible and is expected to be applied in fields such as artificial intelligence, new information technology, Internet of Things, computers and bioelectronics. Attached Figure Description

[0031] Figure 1 This is a structural diagram of the unipolar voltage-controlled heterojunction synaptic transistor device described in this invention;

[0032] Wherein, 1 is the substrate, 2 is the gate electrode, 3 is the gate insulating layer, 4 is the charge trapping layer, 5 is the P / N heterojunction, and 6 is the source / drain electrode;

[0033] Figure 2 This is the hysteresis curve of the unipolar voltage-controlled heterojunction synaptic transistor described in this invention when a scanning voltage is applied.

[0034] Figure 3 The PSC curve of the heterojunction synaptic transistor with unipolar voltage regulation described in this invention is obtained by applying a unipolar voltage.

[0035] Figure 4 The present invention relates to a unipolar voltage-controlled heterojunction synaptic transistor that applies a unipolar voltage for multiple cycles of long-term boost / suppression (LTP / LTD). Detailed Implementation

[0036] The present invention will be further described below through specific embodiments. However, it should be noted that these embodiments are not intended to limit the present invention.

[0037] In the method for fabricating a unipolar voltage-controlled heterojunction synaptic transistor of the present invention, a specific heterojunction synaptic transistor device is designed and fabricated by means of layer stacking. The fabrication steps include: fabricating a charge trapping layer on the gate electrode and the gate insulating layer material, then fabricating a P / N heterojunction structure on the charge trapping layer, and finally fabricating source and drain electrodes on the P / N heterojunction structure. Figure 1 The structural diagram for fabricating a unipolar voltage-controlled heterojunction synaptic transistor device.

[0038] Transistors are commonly used to simulate synaptic function. The transistor's gate acts as the synaptic front end, while the channel and source / drain electrodes form the synaptic back end. When stimulation is applied to the gate, the device's operating current acts as the synaptic weight for signal transmission. In other words, transistors can simulate the excitation and inhibition processes of biological synapses. Unipolarity indicates that synaptic weights can be modulated under the same polarity voltage.

[0039] The sources of the raw materials and reagents involved in the embodiments of the present invention are described as follows:

[0040] The charge trapping layer material was purchased from Sigma-Aldrich; the N-type and P-type semiconductors were purchased from J&K Scientific. The substrates with gate electrodes and gate insulating layers were purchased from Aladdin and were used without further purification. Example

[0041] In a specific embodiment of this application, the method for fabricating a heterojunction synaptic transistor with unipolar voltage regulation performance is as follows:

[0042] I. Substrate Preprocessing

[0043] 1) Clean the substrate with acetone, ethanol, and deionized water respectively;

[0044] 2) Place the substrate dried with a nitrogen gun into a drying oven for further drying.

[0045] II. Preparation of Charge Trapping Layer Thin Films by Solution Spin Coating

[0046] 1) Prepare a charge trapping layer solution with PVN as solute and toluene as solvent, such that the concentration of the prepared solution is 2 mg / ml;

[0047] 2) The charge trapping layer was prepared by solution spin coating. The thickness of the film obtained by spin coating was about 5 nm.

[0048] III. Preparation of P / N heterojunctions by thermal evaporation as semiconductor conductive channels

[0049] 1) Place the thin film formed in step 3) above into a thermal evaporation coating apparatus, and add the N-type semiconductor layer material PTCDI-C. 13 An N-type semiconductor layer thin film with a thickness of approximately 10 nm was obtained;

[0050] 2) Place the device formed in the previous step into a thermal evaporation coating device, add P-type semiconductor layer material and pentene; obtain a P-type semiconductor layer thin film with a thickness of about 50 nm, and obtain the prepared P / N heterojunction.

[0051] IV. Preparation of source and drain electrodes by thermal evaporation method

[0052] 1) Place the P / N heterojunction film formed in step 2 into a thermal evaporation coating equipment, using a mask with a channel width W=1500 μm and a length L=150 μm, and add Cu to the metal source.

[0053] 2) A copper electrode with a thickness of approximately 80 nm was obtained;

[0054] 3) That is, the unipolar voltage-controlled heterojunction synaptic transistor of the present invention is obtained.

[0055] Figure 1This is a schematic diagram of the unipolar voltage-controlled heterojunction synaptic transistor. The device structure, from bottom to top, consists of a substrate (1), a gate electrode (2), a gate insulating layer (3), a charge trapping layer (4), a P / N heterojunction (5), and source / drain electrodes (6). In the P / N heterojunction (5), there are two layers: a P-type semiconductor layer and an N-type semiconductor layer. The N-type semiconductor layer is closer to the charge trapping layer (4), and the P-type semiconductor layer is closer to the source / drain electrodes (6).

[0056] V. The performance of the heterojunction synaptic transistor with unipolar voltage regulation capability prepared above is verified.

[0057] The verification method is as follows:

[0058] 1) Apply a scanning voltage of ±35 V to the device to perform a hysteresis scan and obtain the hysteresis curve of the device;

[0059] 2) By applying a voltage of approximately 15 V to the fabricated device, a current level of approximately 10 V is achieved. -8 The initial state around A;

[0060] 3) After the device is adjusted to the initial state, test the synaptic plasticity: Apply voltages from -10 V to -50 V in the same direction to the device, and achieve synaptic plasticity of excitation and inhibition under the same polarity voltage;

[0061] 4) After the device is adjusted to the initial state, test the reconfigurability: apply voltages of the same polarity (-35V and -45V) of a certain magnitude to obtain the LTP / LTD cycle of the device. The device has good reconfigurability.

[0062] 5) Verification test results are shown in [link to test]. Figure 2-4 .

[0063] Figure 2 The hysteresis curve of the unipolar voltage-controlled heterojunction synaptic transistor shows that the device exhibits obvious bipolar characteristics.

[0064] Figure 3 The diagram shows the PSC curve of the unipolar voltage-controlled synaptic transistor under unipolar voltage scanning. As the applied unipolar voltage gradually changes, the device can switch between excitation and inhibition, indicating that the device has the characteristic of unipolar voltage control.

[0065] Therefore, it can be concluded that the device can simulate the excitation and inhibition characteristics of biological synapses when a suitable unipolar voltage modulation is applied, thus realizing unipolar voltage regulation.

[0066] Figure 4The unipolar voltage-controlled heterojunction synaptic transistor exhibited good reconfigurability over 10 consecutive LTP / LTD cycles.

[0067] In summary, this device can achieve synaptic plasticity with unipolar voltage regulation.

[0068] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for controlling a heterojunction synaptic transistor to possess unipolar voltage regulation performance, characterized in that, The heterojunction synaptic transistor is a heterojunction synaptic transistor with unipolar voltage regulation performance. The heterojunction synaptic transistor consists of a substrate (1), a gate electrode (2), a gate insulating layer (3), a charge trapping layer (4), a P / N heterojunction (5), and source / drain electrodes (6) from bottom to top. The P / N heterojunction (5) is divided into two layers: a P-type semiconductor layer and an N-type semiconductor layer. The charge trapping layer is made of a medium with charge trapping properties, and is selected from poly(2-vinylnaphthalene) (PVN), poly(9-vinylcarbazole) (PVK), poly(4-vinylphenol) (PVP) or polystyrene (PS). The thickness of the charge trapping layer is 1~50 nm. The aforementioned control method specifically involves setting the device current level to 10. -12 A ~10 -3 A represents the initial state. By applying a unipolar voltage to the fabricated device, it can be made to exhibit excitation or inhibition functions.

2. The control method according to claim 1, characterized in that, In the heterojunction synaptic transistor, the material of the P-type semiconductor layer is a P-type organic semiconductor or a P-type inorganic semiconductor, such as pentadienylbenzene, bis(2,3-B:2′,3′-F)thiophene[3,2-B]thiophene (DNTT), 2,7-dioctyl[1]benzothiophene[3,2-b][1]benzothiophene (C8-BTBT), zinc selenide (ZnSe) or zinc sulfide (ZnS), and the thickness of the P-type semiconductor layer is 1~200 nm.

3. The control method according to claim 1, characterized in that, In the heterojunction synaptic transistor, the material of the N-type semiconductor layer is an N-type organic semiconductor or an N-type inorganic semiconductor, specifically N,N'-tetracarboxylic acid diimide (PTCDI-C). 13 The N-type semiconductor layer has a thickness of 1~200 nm and may contain copper hexadecyl phthalocyanine (F16CuPc), 1,4,5,8-naphthalenetetracarboxylic anhydride (NTCDA), naphthalimide (NDI), indium gallium zinc oxide (IGZO), or zinc oxide (ZnO).

4. The control method according to claim 1, characterized in that, In the heterojunction synaptic transistor, the source and drain are arranged in the same plane, and a channel structure is formed between the source and drain. The ratio of the channel width W to the channel length L is 10~30.

5. The method for fabricating a heterojunction synaptic transistor as described in any one of claims 1-4, characterized in that, Includes the following steps: 1) Clean the substrate with acetone, ethanol and deionized water respectively for 5-20 minutes, and dry it after cleaning. 2) Prepare the charge trapping layer solution so that the charge trapping medium is fully dissolved in the organic solvent; 3) Prepare a charge-trapping dielectric thin film based on step 2); 4) On the charge trapping dielectric film prepared in step 3), a P / N heterojunction and source / drain electrodes are prepared.

6. The method for fabricating a heterojunction synaptic transistor according to claim 5, characterized in that, In step 2), the organic solvent is a solvent that can dissolve the charge-trapping medium, and 1,2-dichloroethane, toluene, or chlorobenzene are selected.

7. The method for fabricating a heterojunction synaptic transistor according to claim 5, characterized in that, In step 4), the P / N heterojunction thin film is prepared by physical or chemical methods, specifically solution methods, thermal evaporation methods, magnetron sputtering, electron beam evaporation or atomic layer deposition (ALD). The solution methods include spin-coating, sol-gel, spray, silk-screen printing or inkjet printing.

8. The method for fabricating a heterojunction synaptic transistor according to claim 5, characterized in that, In step 4), the source and drain electrodes are prepared by physical or chemical deposition methods, specifically thermal evaporation, magnetron sputtering, electron beam evaporation, or atomic layer deposition (ALD).

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