A W-band AIP package with frequency conversion module

Abstract

The present disclosure provides an AIP package for a W-band frequency conversion module. The method includes a multifunctional chip, a power splitter chip, a packaging substrate and an antenna array; the antenna array is arranged on the top layer of the packaging substrate; the multifunctional chip and the power splitter chip are arranged on the bottom layer of the packaging substrate; the first type of coaxial, the second type of coaxial and the radio frequency strip line are arranged inside the packaging substrate; the multifunctional chip transmits signals to the antenna array through the first type of coaxial, through the radio frequency strip line, and connected to the second type of coaxial. In this way, the difficulty and cost of motherboard production can be reduced, signal loss can be reduced, the number of packaging substrate layers and costs can be reduced, the ease of use and testability can be improved, and it is convenient to form a larger array.

Description

Technical Field

[0001] The present invention relates to the technical field of microwave antennas, and in particular to an AIP package with a W-band frequency conversion module. Background Art

[0002] The RF chip in the traditional W-band AIP package is generally packaged as WLCSP or bare die. In order to be compatible with the production and welding process of PCB, the BGA ball of WLCSP package is generally larger, which leads to serious mismatch of W-band RF signal at BGA, affecting the performance of phased array and even causing oscillation and other problems.

[0003] Traditional W-band AIP packaging does not have a frequency conversion function. The W-band RF signal needs to be transmitted directly on the motherboard, which places high demands on the motherboard's board performance and PCB process accuracy. The motherboard design is more difficult, the quality is more uncontrollable, and the cost is higher. Due to the limitations of the motherboard performance, the W-band RF signal matching is poor and the transmission loss is large.

[0004] Traditional W-band AIP packaging requires more layers to ensure wiring, signal interconnection and sufficient current carrying. However, due to the limitations of substrate manufacturing process, the more layers the substrate has, the lower the yield, so the traditional W-band AIP packaging requires more layers, which makes the substrate manufacturing cost high.

[0005] From the perspective of testing and use, AIP without frequency conversion architecture needs to directly provide or process W-band RF signals when in use. However, W-band equipment is expensive and scarce, resulting in poor usability and testability of AIP.

[0006] The traditional W-band AIP phased array has a low level of integration, generally integrating only one or several multifunctional transceiver chips, and the integrated multifunctional transceiver chips are mostly single-channel or several-channel, resulting in a small number of AIP channels. When forming 256 arrays, 1024 arrays or larger arrays, a large number of AIP units are required, resulting in a large array area and complex structure. At the same time, there are problems such as difficulty in motherboard design, high cost, and poor maintainability. It cannot be used in situations that require large-scale antenna arrays. Summary of the invention

[0007] According to an embodiment of the present disclosure, an AIP package of a W-band frequency conversion module is provided.

[0008] The AIP package of the W-band frequency conversion module includes: a multifunctional chip, a power division chip, a packaging substrate and an antenna array; the antenna array is arranged on the top layer of the packaging substrate; the multifunctional chip and the power division chip are arranged on the bottom layer of the packaging substrate; the first type of coaxial, the second type of coaxial and the radio frequency strip line are arranged inside the packaging substrate; the multifunctional chip transmits signals to the antenna array through the first type of coaxial, via the radio frequency strip line, and connected to the second type of coaxial.

[0009] Furthermore, the antenna array is a 64-channel antenna array formed by antenna units regularly arranged in an 8x8 manner.

[0010] Furthermore, there are four multifunctional chips, which are regularly arranged in a 2x2 manner; each multifunctional chip has a frequency conversion function and a transceiver function, and integrates 16 transceiver shared channels, and four multifunctional chips are chained in the AIP to form a 64-channel array;

[0011] The first power division chip, the second power division chip and the third power division chip are sequentially arranged in the center of the multifunctional chip;

[0012] The second power division chip divides the intermediate frequency and local oscillator signals entering the BGA ball into 1 and 2, realizing primary branching. The intermediate frequency and local oscillator signals after primary branching are then divided into 2 and 4 by the first power division chip on the left and right and the third power division chip for secondary branching to the four multi-functional chips.

[0013] Furthermore, the multifunctional chip includes 2 original multifunctional chips and 2 mirror-image multifunctional chips.

[0014] Furthermore, the multifunctional chip and the power splitter chip are both FC packaged and manufactured through a silicon-based process.

[0015] Furthermore, the power division chip contains two broadband power dividers covering C-band to X-band.

[0016] Furthermore, each of the multifunctional chips has a frequency conversion function, which is 8th harmonic mixing, the local oscillator frequency is within the X band, and the intermediate frequency frequency is within the C band. The multifunctional chip up-converts the intermediate frequency signal of the C band to the W band, or down-converts the radio frequency signal of the W band to the C band.

[0017] Furthermore, the packaging substrate has 6 layers in total; the first type of coaxial lines are provided through the L1-L3 layers, and the first type of coaxial lines are connected to the second type of coaxial lines that run through the L3-L6 layers through the RF strip lines on the L3 layer;

[0018] The antenna feed point of the antenna array is connected to the second type of coaxial;

[0019] The RF signal enters the L3 layer from the transceiver channel pad of the multifunctional chip through the first type of coaxial cable, reaches the corresponding antenna feeding point below the RF strip line, and finally reaches the corresponding antenna feeding point from the L3 layer through the second type of coaxial cable.

[0020] It should be understood that the contents described in the summary of the invention are not intended to limit the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, among which:

[0022] Figure 1 A vertical architectural diagram of an AIP package in which embodiments of the present disclosure can be implemented is shown;

[0023] Figure 2 A table showing the configuration of each layer structure of an AIP package in which the embodiments of the present disclosure can be implemented is shown;

[0024] Figure 3 shows a bottom view of an AIP package in which embodiments of the present disclosure can be implemented;

[0025] Figure 4 shows a top view of an AIP package in which embodiments of the present disclosure can be implemented;

[0026] Figure 5 A layout diagram of an AIP package L3 layer W-band RF stripline in which embodiments of the present disclosure can be implemented is shown. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0028] In addition, the term "and / or" in this article is only a description of the association relationship between the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0029] It should be noted that, for the above-mentioned various method implementations, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should know that the present disclosure is not limited by the order of the actions described, because according to the present disclosure, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the implementations described in the specification are all optional implementations, and the actions and modules involved are not necessarily required by the present disclosure.

[0030] The W-band AIP package with a frequency conversion module disclosed in the present invention integrates a multifunctional chip with a frequency conversion function, a power division chipset capable of secondary branching, a package substrate and an antenna array, which solves the problems of large RF transmission loss, high process difficulty, high cost and poor usability of the AIP phased array in the W-band and higher frequency bands, avoids the high design difficulty and high process difficulty of the W-band AIP motherboard, and has the advantages of high integration, large number of channels, low cost and the ability to form an array arbitrarily.

[0031] Below, refer to Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 The embodiments of the present invention are described below. However, unless otherwise specified, the dimensions, materials, shapes, and relative arrangements of the components described in the embodiments do not limit the scope of the present invention.

[0032] [Structural configuration]

[0033] Figure 1 FIG. 1 is a schematic diagram of a vertical structure of an AIP package according to an embodiment of the present invention. Figure 1 As shown, the AIP package of this embodiment includes: a multifunctional chip (1), a power division chip (2), a packaging substrate (3) and an antenna array (4).

[0034] In this embodiment, the packaging substrate (3) has a total of 6 layers, a multifunctional chip (1) and a power splitter chip (2) are arranged at the bottom of the L1 layer, a first type of coaxial cable (31) of the L1 to L3 layers is arranged below the transceiver channel pad of the multifunctional chip (1), and a W-band radio frequency signal enters the L3 layer from the chip end through the first type of coaxial cable (31), and a radio frequency strip line (32) is arranged on the L3 layer, and the W-band radio frequency signal reaches the corresponding antenna feeding point below the radio frequency strip line (32), and finally a second type of coaxial cable (33) of the L3 to L6 layers is arranged, and the W-band radio frequency signal finally reaches the antenna feeding point through the second type of coaxial cable (33) from the L3 layer strip line, and then reaches the antenna array (4) arranged on the top of the L6 layer.

[0035] Figure 2 It is a table of the structure configuration of each layer of the AIP package according to an embodiment of the present disclosure. Figure 2As shown, in this embodiment, the L1 layer is provided with a multifunctional chip (1), a power splitter chip (2), a BGA solder ball (34) and digital signal wiring. The L2 layer is a large-area ground plane and a power plane. The L3 layer is provided with a W-band RF stripline (32), an intermediate frequency and local oscillator line, a power plane and a large-area ground plane. The L4 is a large-area ground plane. The L5 layer is a grid-shaped ground plane, and the L6 layer is an antenna array (4) and an isolation fence (42). The dielectric between the L1-L2 layer, the L2-L3 layer, the L4-L5 layer, and the L5-L6 layer is PP, and the dielectric between the L3-L4 layer is CORE.

[0036] In this embodiment, a BGA ball (34) is implanted on the bottom layer of the packaging substrate as an interface for interconnecting with the motherboard. The diameter of the BGA ball (34) after reflow soldering is set to be greater than the height of the multifunctional chip (1) and the power division chip (2), ensuring that the customized chip will not interfere with the motherboard when the AIP is soldered to the motherboard.

[0037] Figure 3 FIG. 1 is a top view of an AIP package according to an embodiment of the present invention. Figure 3 As shown, the antenna array (4) of the AIP package of this embodiment is a 64-channel antenna array (4) formed by antenna units (41) regularly arranged in an 8x8 manner.

[0038] In this embodiment, an isolation grid (42) is provided between the antenna units (41), and a through hole is provided on the isolation grid (42). The spacing between the antenna units (41) is 2.1 mm.

[0039] In this embodiment, the overall size of the AIP package is 17 mm x 17 mm.

[0040] Figure 4 FIG. 1 is a bottom view of an AIP package according to an embodiment of the present invention. Figure 4 As shown, the bottom layer of the AIP package of this embodiment is provided with four multifunctional chips (1) arranged in a regular 2x2 manner. Each multifunctional chip (1) has a frequency conversion function and a transceiver function, and integrates 16 transceiver common channels (11). Four multifunctional chips (1) are chained in the AIP package to form a 64-channel array.

[0041] In this embodiment, a first power division chip (21), a second power division chip (22) and a third power division chip (23) are arranged in a row in the horizontal gap between the multifunctional chips (1). The second power division chip (22) can divide the intermediate frequency and local oscillation signals entering the BGA ball (34) into 1 to 2 through CPWG to achieve primary branching. The intermediate frequency and local oscillation signals after primary branching are then divided into 2 to 4 through CPWG by the first power division chip (21) and the third power division chip (23) on the left and right to achieve secondary branching to the four multifunctional chips (1).

[0042] In this embodiment, the first power division chip (21) and the third power division chip (23) are placed horizontally, and the second power division chip (22) is placed vertically.

[0043] In this embodiment, each multifunctional chip (1) has a frequency conversion function, and its frequency conversion function is 8th harmonic mixing. The local oscillator frequency is within the X band, and the intermediate frequency frequency is within the C band. The multifunctional chip (1) can up-convert the intermediate frequency signal of the C band to the W band, or down-convert the radio frequency signal of the W band to the C band.

[0044] In this embodiment, six rows of BGA balls (34) are planted on the left and right sides and the middle of the packaging substrate (3) to serve as interfaces for connecting the power supply, digital signal, local oscillator, intermediate frequency, ground and motherboard in the AIP, wherein the BGA balls (34) of the local oscillator and intermediate frequency are placed on the upper and lower sides of the second power divider chip (22).

[0045] In this embodiment, the multifunctional chips include two original multifunctional chips (12) and two mirror-image multifunctional chips (13), and the arrangement is preferably such that multifunctional chips (1) of the same version are arranged diagonally in a regular 2x2 arrangement.

[0046] In this embodiment, the multifunctional chip (1) and the power splitter chip (2) are both FC packaged and manufactured using a silicon-based process.

[0047] In this embodiment, the power division chip (2) contains two broadband power dividers covering C-band to X-band.

[0048] In this embodiment, the size of the multifunctional chip (1) is 4.8 mm x 6.8 mm, and the size of the power division chip (2) is 0.6 mm x 2.3 mm.

[0049] Figure 5 FIG. 1 is a wiring diagram of a W-band radio frequency stripline (32) of the L3 layer of a package substrate (3) according to an embodiment of the present invention. In this embodiment, the transceiver channel (11) of the multifunctional chip (1) is arranged under the first type coaxial (31) and can be directly connected to the first type coaxial (31) without the need for a radio frequency stripline. Figure 5 Arrangement shown.

[0050] [Working Status]

[0051] When the W-band AIP is in a transmitting state, the second power division chip (22) divides the local oscillator and intermediate frequency signals entering from the BGA ball (34) into 1 and 2, thus realizing primary branching. The intermediate frequency and local oscillator signals after primary branching are then divided into 2 and 4 by the first power division chip (21) and the third power division chip (23), thus realizing secondary branching. The signals enter four multifunctional chips (1) respectively, undergo frequency conversion on the multifunctional chips (1), and then the W-band signals generated by the up-conversion are radiated out by the antenna array (4).

[0052] When the W-band AIP is in a receiving state, the second power division chip (22) divides the local oscillator signal entering from the BGA ball (34) into 1 and 2, realizing primary branching, and then the first power division chip (21) and the third power division chip (23) divide the local oscillator signal into 2 and 4, realizing secondary branching, and the signals enter the four multifunctional chips (1) respectively. At the same time, the W-band signal received by the antenna array (4) enters the multifunctional chip (1), and the multifunctional chip (1) performs down-conversion. Then, the intermediate frequency signal generated by the down-conversion is combined by the power division chip (2) and output from the intermediate frequency pin of the AIP package.

[0053] The structural design of the AIP package disclosed in this specific embodiment has the following technical effects:

[0054] In this embodiment, the power division system is placed in the AIP package in the form of three power division chips (2) used in conjunction with each other, and the power division chip (2) contains two broadband power dividers covering the C band to the X band, which can provide a 1-to-4 splitting or 4-to-1 combining function for the local oscillator and intermediate frequency signals of the multifunctional chip (1). Therefore, even if there are 4 local oscillator and 4 intermediate frequency signals in the proposed AIP package, when a single AIP package is used, only 1 local oscillator and 1 intermediate frequency signal need to be provided on the motherboard, and there is no need to place a power divider, which reduces the design difficulty of the motherboard, reduces the production cost of the motherboard, and is easy to use.

[0055] In this embodiment, there are four multifunctional chips (1) with transceiver and frequency conversion functions in the AIP package. The frequency conversion function is 8th harmonic mixing. The local oscillator frequency is in the X band and the intermediate frequency frequency is in the C band. The multifunctional chip can up-convert the intermediate frequency signal of the C band to the W band, or down-convert the radio frequency signal of the W band to the C band. Both processes are implemented in the AIP package disclosed in the present invention. The external interface only needs to provide the transmission path of the low-frequency local oscillator and the intermediate frequency signal. The radio frequency signal of the W band is only transmitted in the AIP package substrate (3) through the coaxial plus radio frequency strip line method. The package substrate (3) is thin and has a small loss tangent, so the signal transmission path is short and the loss is small. Only the local oscillator and intermediate frequency signals with lower frequencies need to be transmitted on the motherboard, which reduces the design pressure of the motherboard, reduces the requirements for the motherboard material and process, and reduces the production cost of the motherboard.

[0056] In this embodiment, the multifunctional chip (1) and the power splitter chip (2) are both FC packages, with small chip size, a large number of pins available, and a small bump size, resulting in smaller RF mismatch. The FC package can directly plant balls on the bare DIE pads, with a smaller ball diameter, so that the RF signal transmission loss is further reduced. Compared with bare chips, FC packages occupy less space on the surface of the substrate, and digital signals can be routed between chip bumps, which can reduce wiring pressure and reduce the number of layers of the package substrate (3), thereby improving the substrate yield and reducing costs.

[0057] In this embodiment, the four multifunctional chips (1) include two original chips (12) and two mirror-image chips (13), and are arranged in a bilaterally symmetrical manner as a whole, which can greatly reduce the difficulty of layout and wiring of the packaging substrate (3), reduce the number of packaging substrate layers, and reduce costs.

[0058] In this embodiment, the packaging substrate (3) of the AIP package has only 6 layers. The AIP has high integration, a large number of channels, and a large total power consumption. While meeting the requirements of digital signal interconnection and sufficient current carrying capacity, the number of necessary substrate layers is reduced, and a good yield is achieved.

[0059] In this embodiment, the transceiver channel of the multifunctional chip (1) is close to the antenna feeding point, and can be directly connected by straight lines during wiring, without any wiring crossing. In addition, while keeping the RF line wiring distance short, a certain distance is retained between adjacent RF strip lines, thereby ensuring low RF loss, good isolation and high consistency.

[0060] In this embodiment, the power division chip (2) is located in the center of the multifunctional chip, the local oscillator and the intermediate frequency wiring are simple and easy to be symmetrically routed to achieve equal length, thereby ensuring low RF loss, good isolation and high consistency.

[0061] In this embodiment, the external RF interface of the AIP package is the local oscillator and the intermediate frequency, so there is no need to use expensive W-band equipment during use and testing, which reduces the cost of use and improves ease of use and testability.

[0062] In this embodiment, the AIP package size is small, and the arrangement and spacing of the antenna array (4) fully consider the array formation requirements, and after arrangement, 256 arrays, 1024 arrays or larger arrays can be formed.

[0063] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the described module can refer to the corresponding process in the aforementioned method implementation, and will not be repeated here.

[0064] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0065] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A W-band AIP package with frequency conversion module, It is characterized in that include: Multifunctional chips, power splitter chips, packaging substrates and antenna arrays; The antenna array is disposed on the top layer of the packaging substrate; The bottom layer of the packaging substrate is provided with the multifunctional chip and the power division chip; The packaging substrate is provided with a first type of coaxial line, a second type of coaxial line and a radio frequency strip line; The multifunctional chip transmits a signal to the antenna array through the first type of coaxial cable, via the radio frequency strip line, and connected to the second type of coaxial cable; wherein, There are four multifunctional chips, which are arranged regularly in a 2x2 manner; each of the multifunctional chips has a frequency conversion function and a transceiver function, and integrates 16 common transceiver channels, and four multifunctional chips are chained in the AIP to form a 64-channel array; the first power division chip, the second power division chip and the third power division chip are sequentially arranged in the center of the multifunctional chip; the second power division chip divides the intermediate frequency and local oscillator signals entering the BGA ball into 1 and 2 to achieve a primary branch, and the intermediate frequency and local oscillator signals after the primary branch are then divided into 2 and 4 by the first power division chip and the third power division chip on the left and right to perform a secondary branch to the four multifunctional chips; the local oscillator and intermediate frequency are external RF interfaces of the AIP package; the frequency conversion function is 8th harmonic mixing, the local oscillator frequency is in the X band, and the intermediate frequency frequency is in the C band, and the multifunctional chip up-converts the intermediate frequency signal of the C band to the W band, or down-converts the RF signal of the W band to the C band.

2. The AIP package of the W-band frequency conversion module according to claim 1, It is characterized in that The antenna array is a 64-channel antenna array formed by antenna units regularly arranged in an 8x8 manner.

3. The AIP package of the W-band frequency conversion module according to claim 1, It is characterized in that The multifunctional chips include two original multifunctional chips and two mirror-image multifunctional chips.

4. The AIP package of a W-band frequency conversion module according to claim 1, It is characterized in that The multifunctional chip and the power splitter chip are both FC packaged and manufactured through a silicon-based process.

5. The AIP package of the W-band frequency conversion module according to claim 1, It is characterized in that The power division chip contains two broadband power dividers covering C-band to X-band.

6. The AIP package of the W-band frequency conversion module according to claim 1, It is characterized in that The packaging substrate has a total of 6 layers; The first type of coaxial line is disposed through the L1-L3 layers, and the first type of coaxial line is connected to the second type of coaxial line that runs through the L3-L6 layers through the RF strip line on the L3 layer; The antenna feed point of the antenna array is connected to the second type of coaxial; The RF signal enters the L3 layer from the transceiver channel pad of the multifunctional chip through the first type of coaxial cable, reaches the corresponding antenna feeding point below the RF strip line, and finally reaches the corresponding antenna feeding point from the L3 layer through the second type of coaxial cable.

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