Quantum computing array

Abstract

A quantum processing system includes a first set of control electronics operating at a first temperature. A second set of control electronics is communicatively coupled to the first set of control electronics and operates at a second controlled temperature that is lower than the first temperature. The second set of control electronics includes one or more circuits configured to perform write and read operations on one or more qubits. There is a qubit array that includes the one or more qubits and operates at a third controlled temperature that is lower than the second temperature. The qubit array is controlled by the second set of control electronics.

Description

Technical Field

[0001] This disclosure relates generally to superconducting devices, and more specifically to scalable qubit architectures. Background Technology

[0002] Superconducting quantum computing is the realization of a quantum computer within superconducting electronic circuits. Quantum computing studies the application of quantum phenomena in information processing and communication. Different models of quantum computing exist, with the most popular models including the concepts of qubits and quantum gates. A qubit is a generalization of a bit having two possible states, but can be in a quantum superposition of both states. A quantum gate is a generalization of logic gates; however, it describes the transformation that one or more qubits will undergo after the gate is applied to them, given their initial states. Summary of the Invention

[0003] According to various embodiments, a method and system for controlling qubits in a quantum processing system are provided. A first set of control electronics operates at a first temperature. A second set of control electronics is present, communicatively coupled to the first set of control electronics and operating at a second controlled temperature below the first temperature. The second set of control electronics includes one or more circuits configured to perform write operations on one or more qubits, and one or more circuits configured to perform read operations on the one or more qubits. A qubit array is present, including the one or more qubits and operating at a third controlled temperature below the second temperature. The qubit array is controlled by the second set of control electronics.

[0004] In one embodiment, the first temperature is essentially room temperature.

[0005] In one embodiment, a first set of interconnects exists between the first set of control electronics and the second set of control electronics. This first set of interconnects is configured to control, monitor, or provide one or more reference signals to the second set of control electronics, the reference signals including at least one of a voltage reference, a current reference, or a clock reference that is not proportional to the number of qubits in the qubit array. A second set of interconnects may exist between the second set of control electronics and the qubit array. This second set of interconnects is configured to monitor or provide dynamic signals to the one or more qubits of the qubit array, wherein the second set of interconnects includes an interconnect for each of the one or more qubits of the qubit array.

[0006] In one embodiment, the second set of control electronics includes a plurality of write controllers, each of which includes independently programmable qubit control circuitry. A first signal processing element may be present, configured to process common portions of the waveform shape for amplitude and phase, wherein each write controller includes a second signal processing element configured to process portions that are separate for each qubit. Each independently programmable element of the write controller can be configured to process a unique combination of amplitude and phase of the waveform shape of the corresponding qubit in the qubit array.

[0007] In one embodiment, the first signal processing element includes a high-resolution digital-to-analog converter, and the second signal processing element includes a low-resolution digital-to-analog converter with a lower resolution than the first signal processing element.

[0008] In one embodiment, the qubit array comprises multiple clusters, each cluster being arranged to provide the maximum spacing of the resonant frequencies of its corresponding qubits in order to minimize crosstalk between adjacent clusters of the multiple clusters.

[0009] In one embodiment, the second set of control electronics employs complementary metal-oxide-semiconductor (CMOS) technology.

[0010] In one embodiment, a second set of control electronics is also configured to provide power management circuitry for the qubit array.

[0011] In one embodiment, the second controlled temperature is a low temperature between 1 Kelvin and 4 Kelvin.

[0012] In one embodiment, the third controlled temperature is a low temperature of approximately 240 mK.

[0013] In one embodiment, the qubit array is divided into multiple groups, each group including a different set of qubit center frequencies, thereby reducing crosstalk between adjacent qubits.

[0014] In one embodiment, at least one of one or more circuits configured to perform a write operation includes two separate multiplier mixers for obtaining the upper sideband and the lower sideband, respectively.

[0015] According to one embodiment, a method for controlling a qubit array is provided. A first set of control electronics operates at a first temperature. A second set of control electronics, communicatively coupled to the first set of control electronics, operates at a second controlled temperature below the first temperature. The second set of control electronics includes one or more circuits configured to perform write operations on one or more qubits, and one or more circuits configured to perform read operations on the one or more qubits. The qubit array including the one or more qubits operates at a third controlled temperature below the second temperature. The qubit array is controlled by the second set of control electronics.

[0016] In one embodiment, the first temperature is essentially room temperature. The second controlled temperature is a low temperature between 1 Kelvin and 4 Kelvin. The third controlled temperature is a low temperature of approximately 240 mK.

[0017] In one embodiment, a first set of interconnects is provided between the first set of control electronics and the second set of control electronics to perform at least one of the following: controlling, monitoring, or providing one or more reference signals to the second set of control electronics, the reference signals including at least one of a voltage reference, a current reference, or a clock reference that is not proportional to the number of qubits in the qubit array. A second set of interconnects is provided between the second set of control electronics and the qubit array to perform at least one of the following: monitoring or providing dynamic signals to the one or more qubits of the qubit array. One interconnect exists for each of the one or more qubits in the qubit array in the second set of interconnects.

[0018] In one embodiment, a first signal processing element, located outside of a plurality of write controllers, processes the amplitude and phase of the common portion of the waveform shape. Individual portions of the waveform signal are processed by a second signal processing element local to the write controller within the plurality of write controllers.

[0019] In one embodiment, the qubit array is divided into multiple groups, each group including a different set of qubit center frequencies, thereby reducing crosstalk between adjacent qubits.

[0020] These and other features will become apparent from the following detailed description of illustrative embodiments thereof, which will be read in conjunction with the accompanying drawings. Attached Figure Description

[0021] The accompanying drawings are illustrative embodiments. They do not show all embodiments. Other embodiments may be used alternatively or as an alternative. Details that may be obvious or unnecessary may be omitted to save space or for more effective illustration. Some embodiments may be practiced with additional components or steps and / or without all components or steps shown. When the same number appears in different drawings, it refers to the same or similar components or steps.

[0022] Figure 1 An example architecture of a quantum computing system consistent with the illustrative embodiments is shown.

[0023] Figure 2 A qubit system with three main components, consistent with the illustrative embodiments, is described.

[0024] Figure 3A A conventional qubit architecture is shown.

[0025] Figure 3B The standard control and readout hardware is shown.

[0026] Figure 4 This is a block diagram of a programmable qubit array for quantum computing with dynamic range and power optimization, consistent with the illustrative embodiments.

[0027] Figure 5A An exemplary waveform of a conventional method for communicating with qubits is shown.

[0028] Figure 5B A more efficient method for communicating with qubits according to an illustrative embodiment is shown.

[0029] Figure 6 This is a conceptual block diagram of a dynamic range and power-optimized programmable array for quantum computing, consistent with the illustrative embodiments.

[0030] Figure 7 A low-power, single-sideband write controller consistent with the illustrative embodiment is shown.

[0031] Figure 8 A low-power, single-sideband write controller system consistent with the illustrative embodiment is demonstrated.

[0032] Figure 9 This is a block diagram illustrating an example frequency planning of qubits at the center frequency of a qubit array, consistent with the illustrative embodiment. Detailed Implementation

[0033] In the following detailed description, numerous specific details are illustrated by way of examples to provide a thorough understanding of the relevant teachings. However, it should be clear that the teachings can be practiced without such details. In other cases, well-known methods, processes, components, and / or circuits have been described at a relatively high level without detail to avoid unnecessarily obscuring aspects of this teaching.

[0034] This disclosure generally relates to superconducting devices, and more specifically to power-efficient and scalable qubit architectures. The electromagnetic energy associated with a qubit can be stored in a so-called Josephson junction and in capacitive and inductive elements used to form the qubit. In one example, to read out the qubit state, a microwave signal is applied to a microwave readout cavity coupled to the qubit at that cavity frequency. For example, the qubit can be directly excited by an electrical waveform having a predetermined amplitude, phase, and frequency. The frequency of this excitation waveform can be the resonant frequency of the qubit, and the shape of the waveform can be Gaussian or a derivative thereof. Each qubit can also be excited by another qubit weakly coupled using a capacitive mechanism.

[0035] The transmitted microwave signal passes through multiple thermal isolation stages and low-noise amplifiers to block or reduce noise and improve the signal-to-noise ratio. Most of the process is performed in a cold environment (e.g., in a cryogenic chamber), while the microwave signal of the qubit is ultimately measured at room temperature. The amplitude and / or phase of the returned / output microwave signal carry information about the qubit's state, such as whether the qubit has dephased to a ground state or an excited state. The microwave signal carrying quantum information about the qubit's state is typically weak (e.g., on the order of a few microwave photons). To measure this weak signal using room-temperature electronics (i.e., outside of a refrigerated environment), low-noise quantum limiting amplifiers (QLAs) (such as Josephson amplifiers and traveling-wave parametric amplifiers (TWPAs)) can be used as preamplifiers (i.e., the first amplification stage) at the output of the quantum system to amplify the quantum signal while adding a minimum amount of noise specified by quantum mechanics to improve the signal-to-noise ratio of the output chain. In addition to Josephson amplifiers, certain Josephson microwave components that use Josephson amplifiers or Josephson mixers (such as Josephson circulators, Josephson isolators, and Josephson mixers) can be used in scalable quantum processors.

[0036] The ability to include more qubits is significant for the potential of realizing quantum computers. The computing environment is cooled to cryogenic temperatures for the quantum processor to function. Generally, performance increases as the temperature decreases, for example by reducing the remaining thermally excited qubit population and reducing the thermal broadening of the transition frequencies of these qubits. Therefore, the lower the temperature, the better the performance of the quantum processor.

[0037] The applicant has recognized that improvements to increase the computational power and reliability of quantum computers can be made along two main dimensions. First, there is the qubit count itself. The more qubits in a quantum processor, the more states can be manipulated and stored in principle. Second is a low error rate, which involves accurately manipulating qubit states and performing sequential operations, providing consistent results rather than just unreliable data. Therefore, to improve the fault tolerance of quantum computers, a large number of physical qubits should be used to store logical qubits. In this way, the local information is delocalized, making the quantum computer less susceptible to local errors and the performance of measurements in the eigenbase of the qubits, similar to parity checking in classical computers, thus advancing to more fault-tolerant qubits.

[0038] Example Architecture

[0039] Figure 1 An example architecture 100 of a quantum computing system consistent with illustrative embodiments is described. Architecture 100 includes a qubit array 112 comprising a plurality of qubits 114. The qubit array 112 is positioned within a cooling unit 110, which may be a dilution cooler. The cooling unit may also house a control circuit block 113, which is sometimes referred to herein as a second set of control electronics. For example, the control circuit block 113 may be configured to provide various functions, such as performing write and / or read operations on one or more qubits in the qubit array 112. In one embodiment, the control circuit block 113 is also configured to provide power management for the control circuitry and readout circuitry of the control circuit block 113, which in Figure 6 This will be discussed in more detail later.

[0040] It should be noted that implementing a bandgap reference system in such a region is challenging due to the temperature characteristics of the second controlled temperature. Therefore, in one embodiment, the bandgap reference system is implemented at room temperature (T1), while other parts of the power management system (such as voltage-to-current converters, voltage or resistor (V / R) devices, or other custom current generators) are implemented at a lower T using the bandgap reference signal implemented at room temperature. Thus, by using this partitioning of the power management system, the architecture described herein enables high-accuracy bandgap reference while providing a low-noise power management system by providing a significant portion of the power management circuitry in the cryogenic environment of the second controlled temperature (T2).

[0041] In one embodiment, the cooling unit 110 may have multiple chambers or regions, each with a different controlled temperature. For example, the control circuit block 113 may be at a controlled temperature of 1K to 4K, while the qubit array 112 may be at a controlled temperature of 240mK or lower. The dilution cooler is a cryogenic device that provides continuous cooling down to temperatures as low as 2mK. A large portion of the physical volume of structure 100 is due to the large size of the cooling unit 110. Optimal performance of these qubits can be obtained at the lowest possible temperature. However, due to thermodynamic efficiency, it may not be easy to achieve the coldest temperature in a single step starting from room temperature. At this point, the applicant has determined that operating the auxiliary electronics at 240mK is energy inefficient and therefore, instead of placing them in a third controlled temperature environment (T2), they are placed in a second controlled temperature environment (T2). The cooling materials / reagents used in each of these temperature ranges (e.g., liquid nitrogen at 77K, liquid He at 4K and lower) may also be different.

[0042] In one embodiment, to achieve near-absolute zero operating temperatures for the system, the refrigeration unit 110 can use liquid helium as a coolant. For example, the "drying" refrigeration unit can operate with two gaseous closed-loop cycles: one using He-4, which lowers the refrigerator to 3K ("pulse tube" cycle); and another using a He-3 / He-4 mixture, which lowers the refrigerator to 10mK, or the lowest temperature ("dilution" cycle). A unique liquid in the system is located inside the refrigerator, where the He-3 / He-4 mixture condenses.

[0043] A measurement and control unit 130 (sometimes referred to herein as the first set of control electronics) is located outside the refrigeration unit 110. For example, the measurement and control unit 130 can operate at room temperature. This measurement and control unit 130 is able to communicate with the quantum processor through an opening 116 (sometimes referred to as the partition of the dilution cooler 110), which also forms a hermetically sealed barrier separating the ambient atmospheric pressure of the cryostat from the vacuum pressure during operation. A practical challenge in known refrigeration devices that accommodate qubits 114 is that the number of qubits that can be accommodated in the refrigeration unit is limited by the number of wires between the measurement and control unit 130 and the qubits 114 thus measured.

[0044] As the number of qubits in the qubit array 114 increases, for example from 53 qubits to hundreds, thousands or more, the opening 116 may not be large enough to accommodate all the lines (e.g., wires) 120 supporting the qubit array 112 in the dilution cooler 110. In other words, access to the vacuum environment of the dilution cooler 110 is limited by the number of connectors that can be assembled through the partition opening 116.

[0045] Therefore, in one aspect, an architecture is provided herein that substantially reduces the number of lines 120 between the measurement and control unit 130 and the qubit array 112 housed in a cooled environment. In one embodiment, the number of lines 120 is reduced to approximately 10 (e.g., power management interfaces, clock interfaces, instrumentation interfaces, digital interfaces, etc.), regardless of the size of the qubit array 112.

[0046] See now Figure 2 It describes a qubit system 200 with three main components, which are divided into three different temperature regions: (i) the first group of control electronics 202 (representing...) Figure 1 (ii) a second set of control electronics 204 (representing...) Figure 1 (iii) Control unit 113, which operates at a second temperature (e.g., 1K to 4K); and qubit array 206 (representing Figure 1 The qubit array 112 operates at a third temperature (e.g., 240 mK) below the second temperature. In one embodiment, the second set of control electronics employs complementary metal-oxide-semiconductor (CMOS) technology.

[0047] A first set of interconnects 203 exists between the first set of control electronics and the second set of control electronics. This first set of interconnects is operable for controlling, monitoring, or providing at least one of one or more reference signals, including at least one of a voltage reference, a current reference, or a clock reference that is not scaled to the number of qubits in the qubit array 206. A second set of interconnects 205 exists between the second set of control electronics 204 and the qubit array 206. This second set of interconnects is operable for monitoring or providing dynamic signals to one or more qubits of the qubit array, wherein the second set of interconnects includes an interconnect for each of the one or more qubits of the qubit array.

[0048] This partitioning and interconnection of different circuit components provides advantageous use of electronics 202 and 204 to maximize the dynamic range of system 200 per unit of power consumption.

[0049] Return to reference Figure 1In one embodiment, the measurement and control electronics 130 includes digital I / O. It may further include a power management unit (PMU) comprising one or more bandgap references and reference currents. The control circuit block 113 may include one or more integrated circuits held at a cryo-temperature, which provide high-fidelity signals to qubits 114 in the quantum bit array 112. Many portions of the control circuit block provide excellent performance at cryo-temperature, resulting in significant power reduction within the control circuit block 113. For example, portions of the control circuit may include arbitrary waveform generators, clock circuits, mixer(s), output drivers(s), etc. Transistor mobility increases, transistor on-resistance decreases, and thermal noise decreases at cryo-temperature. Furthermore, the substrate conductivity is reduced, which improves the inductor's quality factor, thus contributing to lower power consumption for the same performance compared to room temperature. Using this multi-temperature zone approach, signaling between the measurement and control electronics block 130 and the control circuit block 113 occurs with a significantly reduced number of connectors, thereby greatly simplifying system design and instrumentation aspects, such as the assembly of fewer cables and components. Furthermore, this multi-temperature zone approach facilitates the scalability of the qubit 114 for large qubit array 112 systems. In one aspect, the interface from the measurement and control electronics block 130 to the control circuit block 113 remains identical, even as the number of 114 increases.

[0050] The control circuit block 113 employs several methods at this first cryogenic temperature to achieve low power and provide high-fidelity signaling to the qubits 114, which will be discussed in more detail later. In one embodiment, the control circuit block includes a digital-to-analog converter (DAC) pair, a mixer pair, an attenuator, and an impedance matching network, which will be discussed in more detail later.

[0051] Example diagram

[0052] To understand the features of this disclosure, it may be helpful to compare them with known techniques. Therefore, Figure 3A and Figure 3B The conventional qubit architecture 300A and the standard control and readout hardware 300B are described separately. For example... Figure 3AAs shown, there are three main operating temperatures: the software and control logic 304 at room temperature, the first control layer 306 at 3K, and the qubit chip 308 at 10mK. The architecture 300A dissipates significant power and involves numerous interfaces between the control logic 304 and the cryogenic environments 306 and 308, thus hindering scalability. For example, each digital-to-analog converter (DAC) consumes a large amount of power and is not scalable at room temperature. In this regard, it is important to note that power is proportional to dynamic range, which is related to the signal-to-noise ratio (SNR). For the same signal, thermal noise is proportional to absolute temperature, thus improving the SNR at lower temperatures for the same signal amplitude. Therefore, achieving a similar SNR at room temperature would involve much higher power consumption.

[0053] and Figure 3A and Figure 3B Compared to known architectures, the teachings herein provide, in various embodiments, one or more of the following: (i) a low sampling frequency for the DAC, resulting in substantially lower power consumption; (ii) increased dynamic range per milliwatt of power consumption through the use of multiple system / circuit / algorithm methods discussed herein (e.g., a combination of waveform features for exciting the waveform for each qubit, and the use of a low-power waveform generator to provide common features); and (iii) built-in calibration for enhancing dynamic range by processing the DAC signal in current mode. For example, each block may use built-in self-calibration. In other words, each block may include its own independent signal analysis process to ensure it consumes the minimum amount of power.

[0054] Now for reference Figure 4 , Figure 4 This is a block diagram of a programmable qubit array for dynamic range and power optimization for quantum computing, consistent with the illustrative embodiment. System 400 includes multiple qubit clusters 402(A) to 402(D). Advantageous clustering will be discussed in more detail later. The system includes local channel low-power phase-locked loops (PLLs), such as 416, for each write / read channel controller 410. A common reference clock exists for the entire system 400. Digital control blocks, such as 420, are present that can be shared between clusters. Each set of local channel low-power PLLs receives signals from the reference clock via its corresponding buffer.

[0055] like Figure 4As shown, architecture 400 provides an arrangement for multiple channels of a qubit array. Each write / read controller (e.g., 410) provides a band-limited single-sideband pulse for a single qubit. Each WR / RD channel controller is connected to its corresponding qubit interface and provides the write pulse and reads the state information of the corresponding cluster. Signal processing is performed using CMOS transistor-level circuitry. In contrast to architecture 400, existing methods utilize direct digitization of the signal. For example, a digital-to-analog converter (DAC) is responsible for providing a frequency offset in addition to the specific waveform used to communicate with each qubit. Conventional methods result in the generation of unique waveforms used to control each qubit, where the center frequency is typically between 4-8 GHz. In conventional methods, both the waveform and the specific frequency offset are implemented using a DAC, thus using higher current.

[0056] For example, a digital-to-analog converter (DAC) can provide a 100MHz signal, which is positioned at 450MHz off-center. Therefore, the maximum bandwidth of the signal is 450 + 0.5 * 100 = 500MHz. According to the Nyquist sampling theorem, the clock frequency should be at least 1000MHz (i.e., twice the signal bandwidth). If this offset is not present, the bandwidth will only be 100MHz, and a 200MHz clock should be sufficient. Thus, for the same bandwidth (i.e., the information content of the signal), the frequency offset results in higher power consumption. This involves higher power DACs and higher sampling frequencies to provide the desired resolution of the DAC (e.g., 12-14 bits). Typically, a higher resolution DAC means many channels communicating between the cryogenic chamber and the control logic outside the cryogenic chamber (e.g., room temperature). Alternatively, there could be a single channel with significant fanout for all qubits. Neither of these is optimal for the power, area, and scalability of the quantum system.

[0057] Compared to known architectures, the teachings in this paper provide signals with a much smaller bandwidth at baseband and upconvert these signals using different offset frequencies generated from a local PLL. Using the previous example, a 100MHz bandwidth is provided at a 450MHz offset relative to 100MHz without offset. In one aspect, the teachings in this paper prevent broadband digitization with high power and are more suitable for low temperatures. In one embodiment, this is implemented using a zero or low frequency offset DAC and using a mixer to convert information from one frequency to another. For example, there are two ways to obtain a 100MHz signal with a center frequency of around 5.5GHz. In the first method, the signal is digitized up to 1GHz and upconverted using a mixer with a local oscillator (LO) frequency of 6.5GHz. In the second method, the signal is digitized up to 200MHz and upconverted using a 5.7GHz LO (lower sideband, 5.7-0.2=5.5GHz) or a 5.3GHz LO (upper sideband, 5.3+0.2=5.5GHz). Therefore, the use of a mixer reduces the clock frequency used in the digital-to-analog converter and lowers power consumption.

[0058] The room-temperature and low-temperature electronics in the cryogenic chamber use very few wires. For example, since the DAC is implemented with low power consumption in one aspect, it can reside in the cryogenic environment T2, and very few interconnects / cables are required between the first temperature region T1 and the cryogenic chamber. All components of the WR / RD controller are integrated into the control circuit block 113 within the cryogenic environment 110, thereby eliminating a large number of wires between the cryogenic environment and the first set of control electronics at room temperature.

[0059] Now for reference Figure 5A , Figure 5A An exemplary waveform 500A of a conventional method for communicating with qubits is shown. Each trapezoid represents the center frequency of the qubit, which can be between 4.5 GHz and 5.5 GHz. Thus, a wide range of resonant frequencies exists for different qubits. In current technology, the center frequency Fc of a qubit may not be precisely known. Qubit technology is still in its early stages, and developing qubits with highly precise predetermined frequencies is challenging. For example, in some scenarios, it is possible to achieve consistent fabrication of qubits with a center frequency of 5.20 GHz without repetition.

[0060] Typically, a center frequency, such as 5 GHz, exists, and a frequency offset is implemented in the digital domain. This center frequency offset (e.g., the difference between the midpoints of a trapezoid) and the information content of the signal (e.g., the width of the trapezoid) are combined (e.g., by multiplying two waveforms) to provide the necessary center frequency for each qubit. The fact that the frequency offset results in higher frequency content being digitized leads to high power consumption. In principle, digitization is more power-intensive than less digitization and subsequent mixing, as follows: Figure 5B This is discussed in the context of [the topic].

[0061] In comparison, Figure 5B A more power-efficient method for communicating with qubits, consistent with the illustrative embodiments, is described. Each qubit can be measured to determine what frequency can be used to excite the qubit (e.g., 5.27 GHz). This determination can be used to logically group these qubits as described herein. In other cases, where the center frequency of the qubits is more easily controlled in the fabrication of the device, these qubits can be physically grouped as illustrated herein.

[0062] Once the center frequency of each qubit in the qubit array is determined, the array is divided into different groups, each group comprising a set of the most distinct qubit center frequencies. This allows each qubit to be provided with a signal that has better fidelity and less interference. For example, a 16-qubit array could include four qubits with a center frequency of 4 GHz, four with a center frequency of 5.5 GHz, four with a center frequency of 6 GHz, and four with a center frequency of 7 GHz. The 16-qubit array can be divided into four groups, each with qubits at center frequencies of 4 GHz, 5.5 GHz, 6 GHz, and 7 GHz. This substantially reduces interference between these qubits. In different embodiments, the grouping discussed here can be logical grouping (based on the determination of the center frequency of each qubit in the array, which are located at different positions on the chip) or physical grouping, where the qubits are precisely configured to have predetermined center frequencies. The latter has become increasingly significant with improvements in qubit manufacturing technology.

[0063] In the architecture associated with waveform 500B, two mixers, 516 and 518, are used. The two mixers 516 and 518 are used to create different combinations of frequencies, including their sum and difference. In this way, power is saved.

[0064] Figure 6This is a conceptual block diagram of a dynamic range and power-optimized programmable array for quantum computing, consistent with the illustrative embodiments. System 600 includes components that operate at three different temperatures. In an exemplary embodiment of system 600, a first set of control electronics 630 operates at a first temperature, which may be room temperature. For example, the first set of control electronics 630 represents... Figure 1 Measurement and control electronics 130. The remaining components are at different levels of cryogenic temperature. In one embodiment, the read controller (RXIQ) 640 is part of a control circuit block that operates at a first cryogenic temperature (e.g., 1 to 4 K) (sometimes referred to herein as a second controlled temperature). Block 608 provides a clock source for phase (I) and quadrature (Q) phase reference frequencies. It includes a phase-locked loop (PLL) coupled to a divider network (e.g., divided by 2). The write controller and read controller require a quadrature clock; therefore, a divide-by-2 circuit is used to provide a division and quadrature generation with a 50% duty cycle.

[0065] The second control temperature includes the various components depicted in block 602, but excludes the qubit array 650 operating at a third control temperature (e.g., 240 mK) below the second control temperature (e.g., 1 K to 4 K). For example, the second control temperature may include a phase-locked loop (PLL) or delay phase-locked loop (DLL) 606, and a power management unit 604 and a write controller 660 for each qubit of the qubit array 650. A clock source 610 may be coupled to the PLL / DLL block 606. A single low-power and low-jitter oscillator 668 may be present. A buffer 670 may be coupled between the PLL / DLL block 606 and the write controller 660. Other components may be present as described in... Figure 6 The other components depicted in box 602 are shown. It will be understood that the components in box 602 are presented only as examples and not as limitations. Alternative and additional components may also be used in the second controlled temperature.

[0066] See now Figure 7 and Figure 8 , Figure 7 and Figure 8 A low-power single-sideband write controller 700 and a controller system having multiple write controllers 800, consistent with the illustrative embodiments, are described. Figure 7 and Figure 8 They are basically similar, the main difference being the description of multiple write controllers 802(1) to 802(N). Figure 8 For simplicity, the main discussion will refer to... Figure 7 What will be understood is that similar concepts also apply. Figure 8 .

[0067] exist Figure 7In this implementation, the write controller has a programmable output amplitude and provides low jitter output. In one embodiment, the jitter is less than 100 fsec. The write controller 700 has an orthogonal architecture because it provides a non-inverting input channel I and a quadrature input channel Q offset by 90 degrees, which are received by a retime circuit (R) 704, respectively. Each channel is provided to a corresponding DAC 706A / B. In one embodiment, each DAC 706A / B is in current mode. Each DAC 706A / B provides a “unique” portion of a waveform to the corresponding qubit. For example, regarding the term “unique,” ​​consider five waveforms: X1, X2, X3, X4, and X5, where each waveform differs in its envelope shape but is similar in other respects. In this case, the unique portion of the waveform is given as the average of these N waveforms. This means that the unique portion is given by Xu = 0.2 * sum(X1:X5), and each DAC channel represents the difference in waveform Xdi = Xi - Xu, where i = 1:1:5.

[0068] In one embodiment, the DACs 706A and 706B are programmable for dynamic range using at least one of parameters related to sampling rate (e.g., speed), resolution (e.g., number of bits), and supply voltage (e.g., influencing the selection of analog current sources).

[0069] Figure 8 Individual write controllers 802(1) to 802(N) in the PLL provide signals to the individual qubits. All write controllers 802(1) to 802(N) use a single clock from this single PLL to ensure that the signals arrive at these individual qubits at substantially similar times. The first block in the write controller includes a digital-to-analog converter (DAC) (i.e., DACS 706A and 706B) for each in-phase (I) and quadrature (Q) path, which converts a digital representation of the waveform received at its corresponding input into a representative analog waveform. In addition to providing a baseband analog representation of the signal, each DAC 706A / B provides an analog signal centered at low to intermediate frequencies. For example, the DAC 706A can provide a signal with a bandwidth of 100 MHz at a frequency offset of 450 MHz. This means that the signal occupies a frequency content of 400-500 MHz. In this process, there are clock spurious tones that should be filtered out using a baseband filter. Therefore, each write controller 802(1) to 802(N) includes a first signal processing element (e.g., 706C and 706D) configured to process the common portion of the waveform shape for amplitude and phase, and a second signal processing element (e.g., 706A and 706B) configured to process the portion that is independent for the qubit. Figure 8 In the examples, these processing elements are described as DACs 706A to 706D.

[0070] The clean signal following the baseband filter (e.g., 708A / B) is fed to a mixer (e.g., 710A-D), which upconverts the signal to the desired frequency for the qubit. After upconversion, a programmable gain function (e.g., 712A-712D) provides the appropriate amplitude for the qubit. Various Nyquist image frequencies are also generated in the system during the digital-to-analog conversion, which should be filtered out using a baseband filter. For signals with bandwidth f... BB and sampling clock frequency f S The signal, the Nyquist image term is located at m*f S ±n*f BB At the location, where m and n are integers, and {m, n} = {1, 2, ...}.

[0071] During the mixing process, single-sideband mixing and double-sideband mixing can be obtained. An example of double-sideband mixing is provided by Equation 1 below:

[0072] Y = G * A BB *cos(ω BB t)*cos(ω LO t)=G*A BB *{cos(ω LO +ω BB )t+cos(ω LO -ω BB )t}。 (Equation 1)

[0073] in:

[0074] G represents the gain of the mixer; and

[0075] A BB This indicates the amplitude of the baseband signal at the mixer input.

[0076] Therefore, in a double-sideband, there are two frequency components (ω). LO +ω BB ) and (ω LO -ω BB To reduce bandwidth, a single sideband can be used, which employs in-phase and quadrature phases from the baseband and LO respectively, resulting in the following output provided in Equation 2:

[0077] Y LSB =G*A BB [cos(ω BB t)*cos(ω LO t)+sin(ω BB t)*sin(ω LO t)]=G*A BB *cos(ω LO -ω BB)t. (Equation 2)

[0078] Another implementation is provided through the following relationship in Equation 3:

[0079] Y LSB =G*A BB [-sin(ω BB t)*cos(ω LO t)+cos(ω BB t)*sin(ω LO t)]=G*A BB *sin(ω LO -ω BB )t。 (Equation 3)

[0080] The relationship in equation 3 above is the lower band, because the obtained frequency (ω) LO -ω BB ) lower than LO frequency ω LO Similarly, the upper sideband can also be achieved by rearranging the phase, as provided by Equation 4 below:

[0081] Y USB =G*A BB [sin(ω BB t)*cos(ω LO t)+cos(ω BB t)*sin(ω LO t)]=G*A BB *sin(ω LO +ω BB )t. (Equation 4)

[0082] Another implementation of the upper band is provided by the following Equation 5:

[0083] Y USB =G*A BB [cos(ω BB t)*cos(ω LO t)-cos(ω BB t)*cos(ω LO t)]=G*A BB *cos(ω LO +ω BB )t. (Equation 5)

[0084] Therefore, by using both the upper and lower sidebands, twice the frequency coverage can be achieved compared to using only one sideband. For example, compared to only being able to provide (ω LO +ω BB (top band) and (ω) LO -ω BB Compared to the system below, it can provide (ω)LO ±ω BB The system coverage of both frequencies is 2ω. BB Frequency range.

[0085] In one embodiment, each output of the DAC 706A / B is filtered by an anti-aliasing filter 708A / B (sometimes referred to herein as a programmable integrated filter). Each filter 708A / B can be programmed for gain, bandwidth, and supply voltage.

[0086] The output of filter 708A is mixed with the corresponding local oscillator signals (e.g., LO2-I and LO2-Q, respectively) (710A), and the local oscillator signals can be summed or subtracted based on the desired center frequency. In one embodiment, each integrated multiplier 710A / B can be programmed for both double-sideband operation for a single sideband. Between these two modes, the integrated multiplier 710A / B provides signal conditioning and gain step size. In different embodiments, each integrated multiplier 710A / B can be configured for both upper and lower sidebands, and / or provide either an upper or lower sideband. In one embodiment, two separate multiplier mixers are used to obtain the upper and lower sidebands, respectively. One of these sidebands is selected to the output with low delay.

[0087] The output of the arithmetic operation is provided to a programmable gain amplifier (PGA) block 714. The programmable gain amplifier 714 is configured to process the unique portions of the waveform shape for amplitude and phase to excite the qubits. For example, instead of... Figure 7 In one embodiment, the PGA 714 is positioned as shown in the diagram, and after the entire mixing operation is completed, a PGA can be coupled to... Figure 8 Each mixer is shown in PGA714A and 714B. Therefore, vector addition can be performed by each write controller 802(1) to 802(N), as exemplified by the following equation 6:

[0088] Y = αXi + βXq (Equation 6)

[0089] Here, X1 and Xq are orthogonal signals that are phase-shifted by 90 degrees from each other.

[0090] Linear driver 716 is connected to the output of PGA 714 to provide additional drive and digitally enable / disable different stages of driver 718. In some embodiments, PGA 714 may be implemented using a single circuit biased with different current levels, wherein the output signal is provided to a driver comprising N stages, with M stages selected using digital control, or a switchable cell array within PGA 714 that scales the input signal and is digitally programmed. A matching network (MN) 718 is present to provide maximum power transfer to the load (i.e., DUT or qubit) coupled to the output of linear driver 716.

[0091] It should be noted that qubits are typically excited using two types of waveforms: (i) symmetric Gaussian and (ii) derivative removal via an adiabatic gate frame (DRAG). DRAG is an anti-adiabatic driven multi-transition variant where multiple low-bit gap states in the adiabatic calculus can be avoided simultaneously, significantly reducing operating time compared to the adiabatic limit. A DRAG pulse can be considered a maximally Gaussian pulse with additional perturbations. If all qubits in the qubit array use the same waveform, only one programmable DAC can be used, which can be shared among N qubits, resulting in lower power consumption. The shared DAC (e.g., with reconfigurable resolution (e.g., bit depth) and power consumption) can provide a maximally Gaussian shape. Such a DAC can be current-mode. In one embodiment, the DAC comprises two parts: (i) an array of current sources and (ii) a set of digital decoders that activate these current sources in the context of a current-guided DAC, where the unit element of the signal is current. Two example implementations of the reconfiguration discussed herein can be implemented. The first approach involves maintaining the same resolution (e.g., bit depth) by adjusting the full-scale current of the DAC. This method results in a change in the total output current and reduces power consumption by decreasing the total current flowing through the analog section.

[0092] The second approach involves maintaining the same full-scale current level (e.g., the maximum current the DAC can provide when all current sources are on), where the number of bits in the DAC can be adjusted. This second approach results in adjustments to the current consumption of both the digital and analog sections.

[0093] In one embodiment, each channel DAC 706 can be programmed independently of a common (e.g., shared) DAC. For example, there is a common DAC 706C for in-phase signals and a common DAC 706D for quadrature signals. These signals are shared among multiple write controllers 802(1) to 802(N). The total baseband current is obtained as the sum of the common shared DAC and the unique DACs for each channel (e.g., 708A and 708B), and this sum is provided to the mixer for upconversion.

[0094] In one embodiment, each cluster of integrated circuit processing elements (e.g., each write controller 802(1) to 802(N)) shares the same clock element (e.g., PLL724) 724. In each cluster of integrated circuit processing elements 802(1) to 802(2) including components 704, 706A / B, 708A / B, 710A-D, 712A-D, 714A / B, 716, 718 and 720, multiple clock elements are shared, switching multiple clock references to clock receive and quadrature generator blocks 722 within unique signal channels.

[0095] In one embodiment, each integrated circuit signal processing element 802(1) to 802(N) includes programmable digital-to-analog converters (DACs) 706A and 706B to process in-phase signals (I) and / or quadrature-phase signals Q. A programmable integrated filter 708A is coupled to the in-phase DAC 706A, and a programmable integrated filter 708B is coupled to the quadrature-phase DAC 706B. A programmable integrated multiplier 710A is coupled to the in-phase analog filter 708A. A programmable integrated multiplier 710B is coupled to the quadrature-phase analog filter 708B. A programmable integrated multiplier 710C is coupled to the quadrature-phase analog filter 708C. A programmable integrated multiplier 710D is coupled to the quadrature-phase analog filter 708D. Variable gain attenuators (e.g., 712A-D) are configured to scale the signals output from the corresponding mixers (e.g., 710A-D). A programmable combiner (e.g., 714A and 714B) is provided for each in-phase (I) and quadrature (Q) path. This programmable combiner is configured to combine signals from the in-phase and quadrature phase multipliers 710A and 710B to create single-sideband signals for the lower sideband (LO-RF) and upper sideband (LO+RF). A low-latency selection element 716 selects between the upper and lower sideband signals and provides them to the final driver 718. The final driver 718 is configured to provide signals to the matching network element 720. In an alternative embodiment, the matching network 720 is shared among channels (i.e., write controllers 802(1) to 802(N)), thereby saving additional area and power.

[0096] In one embodiment, Figure 7 The baseband filter 708 (and Figure 8 The baseband filters 708A / B can be implemented as low-power baseband filters on a channel-by-channel basis, while moderate-power baseband filters can be shared among all channels of the write controller 802(1) to 802(N) to reduce power consumption.

[0097] The tunable network element, sometimes referred to herein as the matched network 720, is configured to provide maximum power transfer between each write controller 802(1) to 802(N) and its corresponding qubit. Figure 8 It is represented by Qx-Qk.

[0098] In one embodiment, the qubit array comprises multiple clusters, each arranged to provide maximum spacing between resonant frequencies to minimize crosstalk between adjacent clusters. See also [link to relevant documentation]. Figure 9 This figure is a block diagram of an example frequency planning of multiple qubits based on the center frequency of a qubit array, consistent with the illustrative embodiment. This equidistant, common centroidal hexagonal arrangement provides an equal amount of physical separation between each qubit and its neighboring qubits. Each box in arrangement 900 represents a qubit. Each box pattern represents a unique center frequency of the qubit. A predetermined physical distance is maintained to minimize crosstalk between these different qubits. The distance between each qubit with a similar center frequency is maximized. In this way, deterministic crosstalk between one qubit and another is reduced.

[0099] In one embodiment, when the manufacturing process is more controlled and the center frequency can be configured, the center frequency can be set by the manufacturing process itself. In other cases, where the manufacturing process cannot determine the exact center frequency of the qubit in advance, the grouping discussed here is logical (i.e., not physical) grouping. For example, the center frequency is determined by providing a waveform of a certain amplitude at the frequency and enabling the readout circuitry system (e.g., ...). Figure 6 The mechanism for tuning the center frequency of a qubit (640) is implemented using flux-coupled arrangements, in which an additional magnetic field is superimposed on the qubit under consideration.

[0100] For example, the determined center frequencies of the qubits are used to group these qubits. More precisely, the center frequency of each qubit in the qubit array is determined, and the qubit array is logically divided into different groups, where each group includes a set of the most distinct qubit center frequencies.

[0101] The pattern of each box representing a qubit represents a different center frequency. In embodiments where the manufacturing process is more controlled and the center frequency can be accurately indicated, these qubits can be spatially arranged to minimize interference between adjacent and alternating adjacent qubits. This improves computational fidelity. In this way, each qubit can be given a signal with better fidelity and less interference. Thus, the qubit chip spatially implements qubits to minimize crosstalk between qubits and provide signal fidelity. These arrangements can follow a uniform spatial placement of these qubit resonators. Each qubit is spaced equidistant from its neighboring qubits. For example, if qubit Qn is surrounded by multiple qubits QA, QB, QC, QD, and QE, the interference terms between each pair {Qn, Qx} remain the same, x = A, B, C, D, E. Therefore, when qubit Qn is active, it is sufficient to send only one cancellation term (e.g., a copy of the main signal). Thus, if the desired signal is Yqn, the cancellation term is given as α*Yqn. This signal (signal = α*Yqn) is sent to each of Qx and added to the corresponding Qx signal to eliminate the x-call effect caused by spatial interference from Qn.

[0102] Given that it is used for Figure 9 The circular arrangement profile for static reciprocating cancellation, because x-talk is a static component, provides deterministic signal coupling that can be easily eliminated in the current domain. Another advantage of this arrangement involves the fact that only one term is sufficient to eliminate crosstalk throughout the array (because the spatial distance between any two box patterns is constant throughout the qubit array). Such an arrangement facilitates crosstalk cancellation terms that can be implemented in the current mode to maintain linearity.

[0103] in conclusion

[0104] Various embodiments of this teaching have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0105] While the content considered to be the best state and / or other instances has been described above, it should be understood that various modifications may be made therein, and the subject matter disclosed herein can be implemented in different forms and instances, and the teachings can be applied to many applications, of which only some have been described herein. The appended claims are intended to claim protection for any and all applications, modifications, and variations falling within the true scope of this teaching.

[0106] The components, steps, features, purposes, benefits, and advantages discussed herein are illustrative only. They, and the discussions associated with them, are not intended to limit the scope of protection. While various advantages have been discussed herein, it will be understood that not all embodiments are necessarily required to include all advantages. Unless otherwise stated, all measurements, values, ratings, locations, amplitudes, sizes, and other specifications set forth in this specification (including in the following claims) are approximate and inaccurate. They are intended to have a reasonable range of functionality associated with them and consistent with functionality customary in the art to which they pertain.

[0107] Many other embodiments are also conceived. These include embodiments with fewer, additional, and / or different components, steps, features, purposes, benefits, and advantages. These also include embodiments in which components and / or steps are arranged and / or ordered differently.

[0108] The calling flows, flowcharts, and block diagrams in this document illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to different embodiments of this disclosure. Each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the diagram. For example, depending on the functions involved, two consecutively shown blocks may actually execute substantially simultaneously, or these blocks may sometimes execute in reverse order. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action or performs a combination of dedicated hardware and computer instructions.

[0109] Although the foregoing has been described in conjunction with exemplary embodiments, it should be understood that the term "exemplary" means only as an example, and not the best or optimal. Nothing stated or shown beyond what is immediately stated above is intended or should be construed as causing dedication or public equivalence to any component, step, feature, object, benefit, advantage, or similarity, whether or not it is stated in the claims.

[0110] It should be understood that the terms and expressions used herein have their general meanings as assigned to their respective corresponding queries and fields of study, unless otherwise specified herein. Relational terms such as "first" and "second" may be used merely to distinguish one entity or action from another, without necessarily requiring or implying any actual such relationship or order between these entities or actions. The terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but may also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element beginning with "a" or "an / a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes that element.

[0111] An abstract of this disclosure is provided to allow the reader to quickly determine the nature of this technical disclosure. It is submitted under the understanding that it is not intended to interpret or limit the scope or meaning of the claims. Furthermore, as can be seen in the above specific embodiments, various features are combined together in various embodiments for the purpose of simplification. The method of this disclosure should not be construed as reflecting an intention to have more features than expressly recited in each claim of a claimed embodiment. Rather, as reflected in the following claims, the inventive subject matter lies in fewer than all features of a single disclosed embodiment. Therefore, the following claims are hereby incorporated into the detailed description, wherein each claim is independently claimed as a separate subject matter.

Claims

1. A quantum processing system, comprising: The first set of control electronics operates at the first temperature; A second set of control electronics, communicatively coupled to the first set of control electronics and operating at a second controlled temperature below the first temperature, the second set of control electronics comprising: One or more circuits are configured to perform a write operation on one or more qubits; and One or more circuits are configured to perform a readout operation on the one or more qubits; and A qubit array comprising one or more qubits and operating at a third controlled temperature below the second controlled temperature, wherein the qubit array is controlled by the second set of control electronics.

2. The quantum processing system according to claim 1, wherein, The first temperature is essentially at room temperature.

3. The quantum processing system according to any one of claims 1 to 2, further comprising a first set of interconnects between the first set of control electronics and the second set of control electronics, the first set of interconnects being configured to control, monitor, or provide one or more reference signals to the second set of control electronics, the one or more reference signals including at least one of a voltage reference, a current reference, or a clock reference not proportional to the number of qubits in the qubit array.

4. The quantum processing system according to any one of claims 1 to 2, further comprising a second set of interconnects between the second set of control electronics and the qubit array, the second set of interconnects being configured to perform at least one of the following: monitoring or providing dynamic signals to one or more qubits of the qubit array, wherein there is one interconnect for each of the one or more qubits of the qubit array in the second set of interconnects.

5. The system according to any one of claims 1 to 2, wherein, The second set of control electronics includes multiple write controllers, each of which includes an independently programmable qubit control circuit.

6. The system of claim 5, further comprising a first signal processing element configured to process a common portion of the waveform shape for amplitude and phase, wherein, Each write controller includes a second signal processing element configured to process a separate part for each qubit.

7. The system according to claim 6, wherein, Each independent programmable element of the write controller is configured to process a unique combination of amplitude and phase for the waveform shape of the corresponding qubit in the qubit array.

8. The system according to claim 6, wherein: The first signal processing element includes a high-resolution digital-to-analog converter; and The second signal processing element includes a low-resolution digital-to-analog converter with a lower resolution than the first signal processing element.

9. The system according to any one of claims 1 to 2, wherein, The qubit array comprises multiple clusters, each cluster being arranged to provide the maximum spacing of the resonant frequencies of its corresponding qubits in order to minimize crosstalk between adjacent clusters.

10. The system according to any one of claims 1 to 2, wherein, The second set of control electronics uses complementary metal-oxide-semiconductor (CMOS) technology.

11. The system according to any one of claims 1 to 2, wherein, The second set of control electronics is also configured to provide power management circuitry for the qubit array.

12. The system according to any one of claims 1 to 2, wherein, The second controlled temperature is a low temperature between 1 Kelvin and 4 Kelvin.

13. The system according to any one of claims 1 to 2, wherein, The third controlled temperature is a low temperature of approximately 240 mK.

14. The quantum processing system according to any one of claims 1 to 2, wherein, The qubit array is divided into multiple groups, each group including a different set of qubit center frequencies, which reduces crosstalk between adjacent qubits.

15. The system according to any one of claims 1 to 2, wherein, At least one of the one or more circuits configured to perform the write operation includes two separate multiplier mixers to obtain the upper sideband and the lower sideband, respectively.

16. A method for controlling a qubit array, comprising: The first set of control electronics is operated at the first temperature. A second set of control electronics, communicatively coupled to the first set of control electronics, operates at a second controlled temperature below the first temperature, wherein the second set of control electronics includes: One or more circuits are configured to perform a write operation on one or more qubits; as well as One or more circuits are configured to perform a readout operation on the one or more qubits; and A qubit array comprising the one or more qubits is operated at a third controlled temperature below the second controlled temperature, wherein the qubit array is controlled by the second set of control electronics.

17. The method of claim 16, wherein: The first temperature is essentially room temperature; The second controlled temperature is a low temperature between 1 Kelvin and 4 Kelvin; and The third controlled temperature is a low temperature of approximately 240 mK.

18. The method according to any one of claims 16 to 17, further comprising: A first set of interconnects is provided between the first set of control electronics and the second set of control electronics to perform at least one of the following: controlling, monitoring, or providing one or more reference signals to the second set of control electronics, the one or more reference signals including at least one of voltage reference, current reference, or clock reference that is not proportional to the number of qubits in the qubit array; as well as A second set of interconnects is provided between the second set of control electronics and the qubit array to perform at least one of the following: monitoring or providing dynamic signals to one or more qubits of the qubit array, wherein in the second set of interconnects there is an interconnect for each of the one or more qubits of the qubit array.

19. The method according to any one of claims 16 to 17, further comprising: The amplitude and phase of the common portion of the waveform shape are processed by a first signal processing element located outside of multiple write controllers; as well as Individual portions of the waveform shape are processed by a second signal processing element local to the write controller in one of the plurality of write controllers.

20. The method according to any one of claims 16 to 17, wherein the qubit array is divided into multiple groups, each group comprising a different set of qubit center frequencies, such that crosstalk between adjacent qubits is reduced.

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