Substrate with integrated passive devices and preparation method thereof

Abstract

The present disclosure provides a substrate integrated with passive devices and a preparation method thereof, belonging to the technical field of radio frequency devices. The preparation method of the substrate integrated with passive devices disclosed in the present disclosure comprises: providing a transparent dielectric layer, the first transparent dielectric layer having a first connection via; the transparent dielectric layer comprises a first surface and a second surface arranged opposite to each other along the thickness direction; integrating passive devices on the transparent dielectric layer; the passive devices at least include an inductor; wherein, integrating the passive devices on the transparent dielectric layer comprises: forming a first substructure on the first surface of the transparent dielectric layer, forming a second substructure on the second surface, and forming a first connection electrode in the first connection via; the first substructure, the first connection electrode and the second substructure are connected to form a coil structure of the inductor.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of radio frequency devices, and in particular relates to a substrate integrated with passive devices and a preparation method thereof. Background Art

[0002] In the contemporary era, the consumer electronics industry is developing rapidly. Mobile communication terminals represented by mobile phones, especially 5G mobile phones, are developing rapidly. Mobile phones need to process more and more signal frequency bands, and the number of RF chips required is also rising. The mobile phone forms that are popular with consumers are constantly developing towards miniaturization, lightness, and long battery life. In traditional mobile phones, there are a large number of discrete devices such as resistors, capacitors, inductors, filters, etc. on the RF PCB board. They have the disadvantages of large size, high power consumption, many solder joints, and large changes in parasitic parameters, which are difficult to meet future needs. The interconnection and matching between RF chips require integrated passive devices with small area, high performance, and good consistency. The integrated passive devices on the market are mainly based on Si (silicon) substrates and GaAs (gallium arsenide) substrates. Si-based integrated passive devices have the advantage of low price, but Si itself has trace impurities (poor insulation), which leads to high microwave loss of the device and general performance; GaAs-based integrated passive devices have the advantage of excellent performance, but are expensive. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art and provides a substrate integrated with passive devices and a preparation method thereof.

[0004] The present disclosure provides a method for preparing a substrate with integrated passive devices, which includes:

[0005] Providing a transparent medium layer, wherein the first transparent medium layer has a first connecting via hole; the transparent medium layer comprises a first surface and a second surface arranged opposite to each other along a thickness direction;

[0006] Passive devices are integrated on the transparent medium layer; the passive devices at least include an inductor; wherein,

[0007] Integrating the passive device on the transparent medium layer comprises:

[0008] A first substructure is formed on the first surface of the transparent medium layer, a second substructure is formed on the second surface, and a first connecting electrode is formed in the first connecting via hole; the first substructure, the first connecting electrode and the second substructure are connected to form an inductor coil structure.

[0009] Wherein, the preparation method comprises:

[0010] Providing a transparent dielectric layer, and processing the transparent dielectric layer to form a first connecting via hole penetrating in a thickness direction thereof;

[0011] forming a first connection electrode located in the first connection via hole; the first connection electrode at least covers an inner wall of the first connection via hole;

[0012] forming a pattern including the second substructure on the second surface through a patterning process;

[0013] Through a patterning process, a pattern of the first substructure is formed on the first surface.

[0014] Wherein, before forming the first connection electrode in the first connection via hole, the method further includes:

[0015] Attaching the first surface of the transparent medium layer to the first substrate;

[0016] The preparation method further comprises:

[0017] Before forming the first substructure, the transparent substrate is peeled off from the first surface side of the transparent medium layer; and the second substrate is attached to the side of the second substructure facing away from the transparent medium layer.

[0018] The step of forming the first connecting via is performed after the step of forming the second substructure.

[0019] The step of forming the first connecting via comprises:

[0020] A transparent dielectric layer is provided, and the transparent dielectric layer is thinned and processed to form a first connecting via hole penetrating in the thickness direction of the transparent dielectric layer.

[0021] Wherein, the passive device further includes a capacitor; and the preparation method further includes:

[0022] A pattern including a second electrode plate of the capacitor is formed on the second surface through a patterning process.

[0023] forming a first interlayer dielectric layer on a side of the second electrode plate of the capacitor away from the transparent dielectric layer;

[0024] Through a patterning process, a pattern including the second electrode plate of the capacitor is formed on a side of the first interlayer dielectric layer away from the transparent dielectric layer.

[0025] Wherein, the second substructure comprises a first conductive film layer and a second conductive film layer sequentially arranged along a direction away from the second surface;

[0026] The first conductive film layer and the first electrode plate of the capacitor are prepared by a single patterning process;

[0027] The preparation method further comprises:

[0028] Forming a second interlayer dielectric layer on a side of the second electrode plate of the capacitor away from the transparent dielectric layer, and forming a second connecting via hole penetrating the first interlayer dielectric layer and the second interlayer dielectric layer;

[0029] The second conductive film layer is formed on a side of the second interlayer dielectric layer away from the transparent dielectric layer, and is connected to the first conductive film layer through a second connecting via.

[0030] Wherein, the preparation method includes the step of grinding the first conductive film layer and the first electrode plate of the capacitor.

[0031] Wherein, the preparation method further comprises:

[0032] A third connection via is formed while the second connection via is formed, penetrating the second interlayer dielectric layer; a second connection electrode is formed while the second conductive film layer is formed, the second connection electrode being connected to the second plate of the capacitor through the third connection via;

[0033] Depositing a first protective layer and a first planarization layer in sequence on a side of the second conductive film layer and the second connecting electrode away from the interlayer dielectric layer;

[0034] forming a fourth connection via hole and a fifth connection via hole penetrating through the first protection layer and the first planarization layer;

[0035] A first connection pad and a second connection pad are formed; the first connection pad is connected to the lead end of the inductor through the four connection vias, and the second connection pad is connected to the second connection electrode through the fifth connection pad.

[0036] When the first connecting electrode does not completely fill the first connecting via hole, a filling structure is formed in the first connecting via hole between the step of forming the first connecting electrode and the step of forming the second substructure.

[0037] Wherein, the preparation method further comprises:

[0038] A second protection layer and a second planarization layer are sequentially formed on a side of the first substructure away from the transparent medium layer.

[0039] Wherein, the transparent medium layer includes a glass base.

[0040] The embodiment of the present disclosure provides a substrate integrated with passive devices, which comprises: a transparent dielectric layer and passive devices integrated on the dielectric layer; wherein:

[0041] The transparent medium layer comprises a first surface and a second surface which are arranged opposite to each other along the thickness direction thereof; the transparent medium layer has a first connecting via hole which penetrates along the thickness direction thereof;

[0042] The passive device at least includes an inductor; the inductor includes a first substructure arranged on the first surface, a second substructure arranged on the second surface, and a first connecting electrode arranged in the first connecting via hole to connect the first substructure and the second substructure in series in sequence.

[0043] The passive device further includes a capacitor, which includes a first electrode plate and a second electrode plate sequentially arranged along a layer away from the second surface, and a first interlayer dielectric layer is arranged between the layers where the first electrode plate and the second electrode plate are located.

[0044] Wherein, the second substructure comprises a first conductive film layer and a second conductive film layer sequentially arranged along a direction away from the second surface;

[0045] The first film layer is arranged in the same layer as the first electrode plate of the capacitor and is made of the same material;

[0046] A second interlayer dielectric layer is arranged on the side of the second plate of the capacitor away from the transparent dielectric layer, and the second conductive film layer is arranged on the side of the second interlayer dielectric layer away from the transparent dielectric layer; the second conductive film layer is connected to the first conductive film layer through a second connecting via that penetrates the first interlayer dielectric layer and the second interlayer dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 FIG. 4 is a top view of an inductor according to an embodiment of the present disclosure.

[0048] Figure 2 This is a LC oscillation circuit diagram.

[0049] Figure 3 It is a schematic diagram of a substrate integrated with passive devices according to an embodiment of the present disclosure.

[0050] Figure 4 It is a schematic diagram of a substrate formed in step S11 of an embodiment of the present disclosure.

[0051] Figure 5 FIG. 1 is a schematic diagram of a substrate formed in step S12 of an embodiment of the present disclosure.

[0052] Figure 6 FIG. 1 is a schematic diagram of a substrate formed in step S12 of an embodiment of the present disclosure.

[0053] Figure 7 FIG. 1 is a schematic diagram of a substrate formed in step S12 of an embodiment of the present disclosure.

[0054] Figure 8 It is a schematic diagram of a substrate formed in step S13 of an embodiment of the present disclosure.

[0055] Fig. 9 Schematic diagram of a substrate formed in steps S14-S16 of an embodiment of the present disclosure.

[0056] Fig.10 Schematic diagram of a substrate formed in steps S17-S18 of an embodiment of the present disclosure.

[0057] Fig.11 It is a schematic diagram of a substrate formed in step S22 of an embodiment of the present disclosure.

[0058] Fig.12 It is a schematic diagram of a substrate formed in step S22 of an embodiment of the present disclosure.

[0059] Fig.13 Schematic diagram of a substrate formed in steps S23 - S24 of an embodiment of the present disclosure.

[0060] Fig.14 It is a schematic diagram of a substrate formed in step S31 of an embodiment of the present disclosure.

[0061] Fig.15 It is a schematic diagram of a substrate formed in step S32 of an embodiment of the present disclosure.

[0062] Fig.16 It is a schematic diagram of a substrate formed in step S32 of an embodiment of the present disclosure. DETAILED DESCRIPTION

[0063] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0064] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0065] The embodiments of the present disclosure provide a substrate integrated with passive devices and a method for preparing the same. The passive devices, such as capacitors, inductors, resistors, etc., are integrated on the substrate to form a circuit structure. In the embodiments of the present disclosure, an LC oscillation circuit integrated on the substrate is taken as an example. That is, at least inductors, capacitors, resistors, etc. are integrated on the substrate.

[0066] Figure 1 is a top view of the inductor of the embodiment of the present disclosure, referring to Figure 1 , each first substructure 211 of the inductor extends along the first direction and is arranged side by side along the second direction; each second substructure 212 of the inductor extends along the third direction and is arranged side by side along the second direction. Among them, the first direction, the second direction, and the third direction are all different directions. In the embodiment of the present disclosure, the first direction and the second direction are perpendicular to each other, and the first direction and the third direction intersect and are arranged non-perpendicularly. Of course, the extension directions of the first substructure 211 and the second substructure 212 can also be interchanged, both within the protection scope of the embodiment of the present disclosure. In addition, in the present embodiment, the inductor includes N first substructures 211 and N-1 second substructures 212 as an example for explanation, wherein N≥2, and N is an integer. The first end and the second end of the first substructure 211 respectively overlap with the positive projection of a first connecting via 11 on the glass substrate 10 at least partially. And the first end and the second end of a first substructure 211 correspond to different first connecting vias 11, that is, the positive projection of a first substructure 211 and two first connecting vias 11 on the glass substrate 10 overlap at least partially. At this time, the first end of the i-th second substructure 212 of the inductor is connected to the first end of the i-th first substructure 211 and the second end of the i+1-th first substructure 211 to form an inductor coil, where 1≤i≤N-1, and i is an integer.

[0067] It should be noted that the first lead terminal 22 is connected to the second end of the first first substructure 211 of the inductor, and the second lead terminal 23 is connected to the first end of the Nth first substructure 211. Further, the first lead terminal 22 and the second lead terminal 23 can be arranged in the same layer as the second substructure 212 and made of the same material. In this case, the first lead terminal 22 can be connected to the second end of the first first substructure 211 through the first connecting via 11, and correspondingly, the second lead terminal 23 can be connected to the first end of the Nth first substructure 211 through the first connecting via 11.

[0068] Figure 2 is a LC oscillation circuit diagram; Figure 2 As shown, the LC oscillator circuit includes two inductors, a capacitor and a resistor. For ease of understanding, the two inductors are respectively referred to as the first inductor L1 and the second inductor L2. Figure 2The first lead end of the first inductor L1 is connected to the first end of the resistor R, the second lead end of the first inductor is connected to the second plate of the capacitor C, the first lead end of the second inductor L2 is connected to the first end of the resistor R, and the second lead end of the second inductor L2 is connected to the first plate of the capacitor C.

[0069] It should be noted that the resistor R can be implemented by a wire, or a high-resistance material such as indium tin oxide (ITO) or nickel-chromium (NiCr) alloy. In the disclosed embodiment, the formation of the resistor R is not limited, and the following mainly introduces the capacitor and the inductor.

[0070] Figure 3 is a cross-sectional view of a substrate integrated with passive devices in an embodiment of the present disclosure; Figure 3 As shown, the passive device is Figure 2 The LC oscillating circuit shown is integrated on a transparent dielectric layer, which includes a first surface and a second surface arranged opposite to each other along the thickness direction thereof, and the transparent dielectric layer has a first connecting via 11 penetrating the thickness direction thereof; a first connecting electrode 213 of the inductor coil is formed in the first connecting via, a first substructure 211 of the inductor coil is formed on the first surface of the transparent dielectric layer, and a second substructure 212 of the inductor coil is formed on the second surface of the transparent dielectric layer. In the embodiment disclosed herein, the transparent dielectric layer includes but is not limited to any one of a glass substrate 10, a flexible substrate, and an interlayer dielectric layer including at least an organic insulating layer. Since the passive device is integrated on the glass substrate 10, it has the advantages of small size, light weight, high performance, and low power consumption. In the embodiment disclosed herein, the transparent dielectric layer preferably adopts a glass substrate 10. The following is an example of a transparent dielectric layer adopting a glass substrate 1010.

[0071] Continue to refer to Figure 3In some examples, the second substructure 212 may include a first conductive film layer 2121 and a second conductive film layer 2122 sequentially arranged in a direction away from the glass substrate 10; wherein the first electrode 31 of the capacitor is arranged on the second surface and is arranged in the same layer as the first conductive film layer 2121 of the second substructure 212 of the inductor coil, a first interlayer dielectric layer 5 is arranged on the side away from the first electrode 31 of the capacitor, and a second electrode 32 of the capacitor is arranged on the side of the first interlayer dielectric layer 5 away from the first electrode 31 of the capacitor; a second interlayer dielectric layer 6 is arranged on a layer away from the second electrode 32 of the capacitor, and a second conductive film layer 2122 and a second connecting electrode 7 are arranged on the side away from the second interlayer dielectric layer 6; the second conductive film layer 2122 is connected to the first conductive film layer 2121 through a second connecting via that penetrates the first interlayer dielectric layer 5 and the second interlayer dielectric layer 6; the second connecting electrode 7 is connected to the second electrode of the capacitor through a third connecting via that penetrates the second interlayer dielectric layer 6. A first protective layer 8 and a first planarization layer 9 are sequentially arranged on the side of the second conductive film layer 2122 and the second connection electrode 7 facing away from the glass substrate 10; and a fourth connection via 91 and a fifth connection via 92 are formed penetrating the first protective layer 8 and the first planarization layer 9. The first connection pad 14 and the second connection pad 15 are respectively formed in the fourth connection via 91 and the fifth connection via 92. The first connection pad 14 and the second connection pad 15 can be solder.

[0072] Continuing with reference to 3 , a third protective layer and a third planarization layer may be formed on the side of the first substructure 211 facing away from the glass substrate 10 , so as to protect the first substructure 211 and prevent corrosion by water and oxygen.

[0073] The structural parameters of each device on the substrate integrated with passive devices in the embodiment of the present disclosure are described one by one in the following preparation method, so they are not described in detail here.

[0074] In an embodiment of the present disclosure, a method for preparing a substrate integrated with passive devices is provided. The substrate may be the above-mentioned substrate. The method for preparing the substrate comprises the following steps:

[0075] A glass substrate 10 is provided and processed to obtain the glass substrate 10 having a first connecting via 11; the glass substrate 10 includes a first surface and a second surface that are oppositely arranged along a thickness direction.

[0076] Passive components are integrated on the glass substrate 10; the passive components at least include an inductor.

[0077] Wherein, integrating passive devices on the glass substrate 10 includes:

[0078] A first substructure 211 is formed on the first surface of the glass substrate 10 , a second substructure 212 is formed on the second surface, and a first connection electrode 213 is formed in the first connection via 11 ; the first substructure 211 , the first connection electrode 213 and the second substructure 212 are connected to form an inductor coil.

[0079] In order to clarify the preparation method in the embodiment of the present disclosure, the preparation method of the substrate integrated with passive devices in the embodiment of the present disclosure is described below with reference to the accompanying drawings and specific embodiments.

[0080] The first example is a preparation method for integrating passive devices on a small-sized substrate such as a 4-inch, 6-inch, 8-inch, or 12-inch substrate. The method specifically includes the following steps:

[0081] S11, providing a glass substrate 10, and processing the glass substrate 10 to form a first connecting via 11 penetrating along the thickness direction thereof, such as Figure 4 shown.

[0082] In some examples, step S11 may include providing a glass substrate 10 , and performing laser modification on a first surface and a second surface of the glass substrate 10 by laser, and forming the glass substrate 10 having the first connecting via 11 by HF etching.

[0083] For example: (1) Cleaning: The glass substrate 10 enters a cleaning machine for cleaning.

[0084] In some examples, the thickness of the glass substrate 10 is about 0.2 mm-0.3 mm.

[0085] (2) Laser drilling: A laser is used to vertically incident laser beams onto the first surface of the glass substrate 10 to modify the surface, so as to form a first sub-via on the first surface side of the glass substrate 10. Similarly, a laser is used to vertically incident laser beams onto the second surface of the glass substrate 10 to modify the surface, so as to form a second sub-via on the second surface side of the glass substrate 10. The second sub-via is connected to the first sub-via to form a first connecting via 11.

[0086] Specifically, when the laser beam interacts with the glass substrate 10, the atoms in the glass substrate 1010 are ionized and ejected out of the first surface of the glass substrate 10 due to the high energy of the laser photons. As time goes by, the hole is gradually deepened until the first sub-via is formed. The glass substrate 10 is turned over and the second sub-via is formed according to the same principle. Among them, the generally available laser wavelength is 532nm, 355nm, 266nm, 248nm, 197nm, etc., the laser pulse width can be selected from 1-100fs, 1-100ps, 1-100ns, etc., and the type of laser can be selected from continuous laser, pulsed laser, etc. The laser drilling method can include but is not limited to the following two methods. In the first method, when the spot diameter is large, the relative position of the laser beam and the glass substrate 10 is fixed, and the glass substrate 10 is directly punched to a preset depth by high energy. At this time, the shape of the first sub-via formed is an inverted cone, and the diameter of the inverted cone decreases from top to bottom (from the second surface to the first surface). In the second method, when the spot diameter is small, the laser beam scans in a circle on the glass substrate 10, the spot focus is constantly changing, the focus depth is also constantly changing, and a spiral line is drawn from the lower surface (first surface) of the glass substrate 10 to the upper surface (second surface) of the glass substrate 10, and the spiral radius decreases from bottom to top. The glass substrate 10 is laser cut into a truncated cone shape to form a first sub-via, and the shape of the first blind hole is the first sub-via; the second sub-via is formed in the same way as the first sub-via, so it will not be repeated. It can be seen that the first connecting via 1111 formed by the first sub-via and the second sub-via is in the shape of an hourglass.

[0087] Of course, the first sub-connection via in the embodiment of the present disclosure may also be formed by irradiating only the first surface or the second surface of the glass substrate 10 with a laser beam to form a truncated cone or cylindrical connection via. The formation method may be the same as the above method, so it will not be repeated here.

[0088] (3) HF etching: Since a stress zone is formed in the area of ​​about 5-20 microns on the upper surface of the inner wall of the first connecting via 11 near the hole during the laser drilling process, the surface of the glass substrate 10 in this area is uneven and presents a molten state with many burrs, and there are a large number of microcracks and macrocracks, and there is residual stress. At this time, a 2%-20% HF etching solution is used, and wet etching is performed at an appropriate temperature for a certain period of time to etch away the glass in the stress zone, so that the interior of the first connecting via 11 and the surface area near the hole are smooth and flat, without microcracks and macrocracks, and the stress zone is completely etched away.

[0089] S12, forming a first connection electrode 213 located at the first connection via hole 11, and forming a first conductive film layer 2121 of the second substructure 212 of the inductor, such as Figure 5 shown.

[0090] In some examples, step S22 may specifically be performed as follows:

[0091] (1) Growing a seed layer: depositing a first metal material on the second surface of the glass substrate 10 by magnetron sputtering, flipping the glass substrate 10, and depositing the first metal material on the first surface by magnetron sputtering. At this time, the first metal material is formed on the side wall of the first connecting via 11 as a seed layer.

[0092] In some examples, the first metal material includes but is not limited to at least one of copper (Cu), aluminum (Al), molybdenum (Mo), and silver (Ag), and the thickness of the first metal material is about 0.2 μm to 10 μm. In the following description, the material of the first metal film layer 201 is copper as an example.

[0093] In some examples, in order to increase the adhesion between the first metal material and the first surface of the glass substrate 10, before forming the first metal material, an auxiliary metal film layer can be formed on the first surface of the glass substrate 10 by a method including but not limited to magnetron sputtering. The material of the auxiliary metal film layer includes but is not limited to at least one of nickel (Ni), molybdenum (Mo) alloy, and titanium (Ti) alloy, for example, MoNb, and the thickness of the auxiliary metal film layer is about 2nm-20nm.

[0094] (2) Electroplating: Place the glass substrate 10 on the electroplating machine carrier, press the power pad, place it in the hole-filling electroplating tank (special hole-filling electrolyte is used in the tank), add current, and keep the electroplating solution flowing rapidly on the first surface of the glass substrate 10. The cations in the electroplating solution on the inner wall of the first connecting via 11 obtain electrons and become atoms deposited on the inner wall. Through the special hole-filling electrolyte with a special ratio, it is possible to deposit metal copper at a high speed mainly in the first blind hole (deposition rate 0.5-3um / min), while the first surface of the glass substrate 1010 is a flat area, and the deposition rate of metal copper on these two surfaces is extremely small (0.005-0.05um / min). As time goes by, the metal copper on the inner wall of the first connecting hole gradually grows thicker to form a first metal film layer. At this time, the first metal film layer grows more than 5μm compared to the first metal material. At this time, the first metal film layer fills the first connecting via 11.

[0095] In some examples, the first metal film layer may not fully fill the first connecting via 11, such as Figure 6 As shown, in this step, it is also necessary to form a filling structure 214 in the first connecting via 11, such as Figure 7As shown, the second surface of the glass substrate 10 is flat. The material of the filling structure 214 may include an organic insulating material, such as a resin material including polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane, etc. For another example, the organic insulating material includes an elastic material, such as urethane, thermoplastic polyurethane (TPU), etc.

[0096] It should be noted that, in the embodiment of the present disclosure, the first metal film layer is taken as an example to fill the first connection via hole 11 completely.

[0097] (3) Patterning of the first surface metal film layer: coating, exposing, developing, and then etching the first metal film layer on the second surface. After etching, stripping to remove the adhesive, the first planarization layer 9 and the first metal film layer on the second surface are patterned. At this time, the first conductive film layer 2121 of the second substructure 212 of the inductor coil and the first electrode 31 of the capacitor are formed on the first surface.

[0098] In some examples, the step of forming the first conductive film layer 2121 and the first electrode plate 31 of the capacitor also includes grinding the two layers to prevent the first conductive film layer 2121 and the first electrode plate 31 of the capacitor from being smooth and having a thickness that meets the capacitor requirement.

[0099] S13, forming a first interlayer dielectric layer 5 on the side of the second substructure 212 of the inductor away from the glass substrate 10, and forming a second electrode plate 32 pattern including a capacitor on the side of the first interlayer dielectric layer 5 away from the glass substrate 10, such as Figure 8 shown.

[0100] In some examples, the material of the first interlayer dielectric layer 5 is an inorganic insulating material. For example, the first interlayer dielectric layer 5 is an inorganic insulating layer formed of silicon nitride (SiNx), or an inorganic insulating layer formed of silicon oxide (SiO2), or a laminated composite film layer of a SiNx inorganic insulating layer and a SiO2 inorganic insulating layer. Of course, the first interlayer dielectric layer 5 also serves as an intermediate dielectric layer of the capacitor.

[0101] In some examples, the second plate 32 of the capacitor can be formed by magnetron sputtering on the side of the first interlayer dielectric layer 5 away from the glass substrate 10 to form a second metal film layer, and then coated, exposed, developed, and then wet etched. After etching, the strip is removed to form a pattern including the second plate 32 of the capacitor.

[0102] S14, forming a second interlayer dielectric layer 6 on the side of the second electrode 32 of the capacitor away from the glass substrate 10, and forming a second connecting via hole penetrating the first dielectric layer and the second interlayer dielectric layer 6, and a third connecting via hole penetrating the second interlayer dielectric layer 6, such as Fig. 9 shown.

[0103] The material of the second interlayer dielectric layer 6 may be the same as that of the first interlayer dielectric layer 5 , and thus will not be described again.

[0104] S15, on the side of the second interlayer dielectric layer 6 away from the glass substrate 10, a second conductive film layer 2122 including a second substructure 212 and a second connecting electrode 7 is formed by a patterning process, the second conductive film layer 2122 is connected to the first conductive film layer 2121 through a second connecting via hole; the second connecting electrode 7 is connected to the second electrode plate 32 of the capacitor through a third connecting via hole, as shown in FIG. Fig. 9 shown.

[0105] In some examples, step S15 may include forming a third metal film layer by magnetron sputtering, applying glue, exposing, developing, and then wet etching, and stripping the glue after etching to form a pattern of a second conductive film layer 2122 including a second substructure 212 and a second connecting electrode 7. The material of the third metal film layer may be the same as that of the first metal film layer, so it will not be described in detail here.

[0106] In some examples, the thickness of the third metal film layer is greater than 5 μm, and the thickness of the formed second conductive film layer 2122 is greater than the thickness of the first conductive film layer 2121 .

[0107] S16, forming a first protective layer 8 and a first planarization layer 9 in sequence on the side of the second conductive film layer 2122 and the second connection electrode 7 away from the glass substrate 10; and forming a fourth connection via hole 91 and a fifth connection via hole 92 penetrating the first protective layer 8 and the first planarization layer 9, such as Fig. 9 shown.

[0108] Among them, the first protective layer 8 is used to prevent water and oxygen from corroding the device formed on the second surface of the glass substrate 10. The thickness of the first protective layer 8 is 0.1μm to 2μm; the material of the first protective layer 8 can be an inorganic insulating material. For example: the first protective layer 8 can be an inorganic insulating layer formed by silicon nitride (SiNx), or an inorganic insulating layer formed by silicon oxide (SiO2), or a laminated composite film layer of several SiNx inorganic insulating layers and SiO2 inorganic insulating layers. The thickness of the first planarization layer 9 is above 2μm; the material of the first planarization layer 9 can include organic insulating materials, such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane and other resin materials. For another example, the organic insulating material includes elastic materials, such as urethane, thermoplastic polyurethane (TPU), etc.

[0109] S17, turning over the glass substrate 10, and forming a first substructure 211 pattern including an inductor coil through a patterning process, such as Fig.10 shown.

[0110] In some examples, step S17 may include forming a fourth metal film layer on the first surface of the glass substrate 10 by magnetron sputtering, and then coating, exposing, developing, and then wet etching, and stripping after etching to form a first substructure 211 pattern including an inductor coil.

[0111] The thickness of the fourth metal film layer is greater than 5 μm. The material of the fourth metal film layer can be the same as that of the first metal film layer, so it will not be described in detail here.

[0112] S18, forming a second protective layer 12 and a second planarization layer 13 in sequence on the side of the first substructure 211 facing away from the glass substrate 10, such as Fig.10 shown.

[0113] In some examples, the material of the second protective layer 12 may be the same as that of the first protective layer 8, so it is not repeated here. The material of the second planarization layer 13 may be the same as that of the first planarization layer 9, so it is not repeated here. The thickness of the second protective layer 12 is substantially the same as that of the first protective layer 8. The thickness of the second planarization layer 13 is substantially the same as that of the first planarization layer 9.

[0114] S19, the glass substrate 10 is turned over again, and the first connection pad 14 and the second connection pad 15 are respectively formed on the fourth connection via hole 91 and the fifth connection via hole 92. The first connection pad 14 and the second connection pad 15 can be solder, such as Figure 3 shown.

[0115] At this point, the preparation of the substrate integrated with passive devices is completed.

[0116] The second example is a preparation method for integrating passive devices on a large-size substrate with a size of 370*470 or more, the method specifically comprises the following steps:

[0117] S21 , providing a glass substrate 10 , and processing the glass substrate 10 to form a first connecting via 11 penetrating along a thickness direction thereof.

[0118] In some examples, step S21 may be the same as the above-mentioned step S11, and thus will not be described in detail here.

[0119] S22, attaching the first surface of the glass base 10 to the first base substrate 101, as shown in Fig.11As shown, the first conductive film layer 2121 and the second conductive film layer 2122 of the second substructure 212 of the inductor, the first electrode plate 31 and the second electrode plate 32 of the capacitor, the first interlayer dielectric layer 5, the second interlayer dielectric layer 6, the connecting pad, the first protective layer 8, and the first planarization layer 9 are formed on the second surface. Fig.12 shown.

[0120] Among them, the first conductive film layer 2121 and the second conductive film layer 2122 of the second substructure 212 of the inductor, the first electrode plate 31 and the second electrode plate 32 of the capacitor, the first interlayer dielectric layer 5, the second interlayer dielectric layer 6, the connecting pad, the first protective layer 8, and the first planarization layer 9 are the same as the above-mentioned steps S12-S16, so they are not repeated here.

[0121] In some examples, the first base substrate 101 may be a glass substrate with a thickness of about 0.4 mm-0.5 mm; the first base substrate 101 and the first surface of the glass base 10 may be bonded together using glue, which may be liquid glue or solid glue.

[0122] S23, after forming the first conductive film layer 2121 and the second conductive film layer 2122 of the second substructure 212 of the inductor located on the second surface, the first electrode plate 31 and the second electrode plate 32 of the capacitor, the first interlayer dielectric layer 5, the second interlayer dielectric layer 6, the connecting pad, the first protective layer 8, and the first planarization layer 9, the first base substrate 101 is peeled off, and the first planarization layer 9 is bonded to the second base substrate 102, as shown in FIG. Fig.13 shown.

[0123] In some examples, the second base substrate 102 may be a glass substrate with a thickness of about 0.4 mm-0.5 mm; the second base substrate 102 and the first planarization layer 9 may be bonded together using glue, which may be liquid glue or solid glue.

[0124] S24, on the first surface of the glass substrate 10, the first substructure 211, the second protective layer 12 and the second planarization layer 13 are formed. Fig.13 shown.

[0125] The steps of forming the first substructure 211 , the second protection layer 12 and the second planarization layer 13 are the same as the above-mentioned steps S17 and S18 , and thus will not be described in detail herein.

[0126] S25, peel off the second base substrate 102, turn over the glass base 10 again, and form the first connection pad 14 and the second connection pad 15 on the fourth connection via hole 91 and the fifth connection via hole 92 respectively. The first connection pad 14 and the second connection pad 15 can be solder, such as Figure 3 shown.

[0127] At this point, the preparation of the substrate integrated with passive devices is completed.

[0128] The third example is a preparation method for integrating passive devices on a large-size substrate with a size of 370*470 or more, the method specifically comprises the following steps:

[0129] S31, providing a first substrate 101, and forming a structure of a first conductive film layer 2121 and a second conductive film layer 2122 of a second substructure 212 of an inductor located on a second surface, a first electrode plate 31 and a second electrode plate 32 of a capacitor, a first interlayer dielectric layer 5, a second interlayer dielectric layer 6, a connecting pad, a first protective layer 8, and a first planarization layer 9 on the first substrate 101, such as Fig.14 shown.

[0130] Among them, the first conductive film layer 2121 and the second conductive film layer 2122 of the second substructure 212 of the inductor, the first electrode plate 31 and the second electrode plate 32 of the capacitor, the first interlayer dielectric layer 5, the second interlayer dielectric layer 6, the connecting pad, the first protective layer 8, and the first planarization layer 9 are the same as the above-mentioned steps S12-S16, so they are not repeated here.

[0131] In some examples, the first substrate 101 may be a glass substrate with a thickness of about 0.4 mm-0.5 mm.

[0132] S32, after forming the first conductive film layer 2121 and the second conductive film layer 2122 of the second substructure 212 of the inductor located on the second surface, the first electrode plate 31 and the second electrode plate 32 of the capacitor, the first interlayer dielectric layer 5, the second interlayer dielectric layer 6, the connecting pad, the first protective layer 8, and the first planarization layer 9, the first base substrate 101 is thinned, and the thinned first base substrate 101 is punched to form a first connecting via 11, so as to form a glass base 10, such as Fig.15 and 16 shown.

[0133] In some examples, the first connection via 11 may be formed in the manner of S11 described above.

[0134] It should be noted here that when thinning the first base substrate 101, a filling layer 16 can be formed on the side of the first planarization layer 9 away from the first base substrate 101 to make the side of the first planarization layer 9 away from the first base substrate 101 flat, so as to thin the first base substrate 101. After the thinning is completed, the filling layer 16 is removed. The filling layer 16 can be made of materials such as photoresist and polyimide.

[0135] S33 , forming a fourth metal film layer on the first surface of the glass substrate 10 , forming a first connection electrode 213 located in the first connection via hole 11 , and forming a first substructure 211 of the inductor coil.

[0136] In some examples, the first connection electrode 213 and the first substructure 211 of the inductor coil may be formed by the same process as the above-mentioned step S12 , and thus will not be described again.

[0137] S34 , forming a second protective layer 12 and a second planarization layer 13 on the side of the first substructure 211 facing away from the glass substrate 10 .

[0138] The steps of forming the second protection layer 12 and the second planarization layer 13 are the same as the above-mentioned step S18 , and thus will not be described again.

[0139] S35, peel off the second base substrate 102, turn over the glass base 10 again, and form the first connection pad 14 and the second connection pad 15 on the fourth connection via hole 91 and the fifth connection via hole 92 respectively. The first connection pad 14 and the second connection pad 15 can be solder, such as Figure 3 shown.

[0140] At this point, the preparation of the substrate integrated with passive devices is completed.

[0141] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A method for preparing a substrate integrated with passive devices, comprising: Providing a transparent dielectric layer, wherein the transparent dielectric layer has a first connecting via hole; The transparent medium layer comprises a first surface and a second surface which are arranged opposite to each other along the thickness direction; Passive devices are integrated on the transparent dielectric layer; the passive devices include inductors and capacitors; wherein, Integrating the passive device on the transparent medium layer comprises: forming a first substructure on a first surface of the transparent medium layer; A second substructure is formed on the second surface, and a first connection electrode is formed in the first connection via hole; the first substructure, the first connection electrode and the second substructure are connected to form an inductor coil structure; the second substructure includes a first conductive film layer and a second conductive film layer sequentially arranged away from the second surface; By a patterning process, a pattern including a first electrode plate of the capacitor is formed on the second surface; forming a first interlayer dielectric layer on a side of the first electrode plate of the capacitor away from the transparent dielectric layer; By means of a patterning process, a pattern including a second electrode plate of the capacitor is formed on a side of the first interlayer dielectric layer away from the transparent dielectric layer; Forming a second interlayer dielectric layer on a side of the second electrode plate of the capacitor away from the transparent dielectric layer, and forming a second connecting via hole penetrating the first interlayer dielectric layer and the second interlayer dielectric layer; The second conductive film layer is formed on a side of the second interlayer dielectric layer away from the transparent dielectric layer, and is connected to the first conductive film layer through a second connecting via.

2. The preparation method according to claim 1, wherein The preparation method comprises: Providing a transparent dielectric layer, and processing the transparent dielectric layer to form a first connecting via hole penetrating in a thickness direction thereof; forming a first connection electrode located in the first connection via hole; the first connection electrode at least covers an inner wall of the first connection via hole; forming a pattern including the second substructure on the second surface through a patterning process; Through a patterning process, a pattern of the first substructure is formed on the first surface.

3. The preparation method according to claim 2, wherein Before forming the first connection electrode in the first connection via hole, the method further includes: Attaching the first surface of the transparent medium layer to the first substrate; The preparation method further comprises: Before forming the first substructure, the first substrate is peeled off from the first surface side of the transparent medium layer; and the second substrate is attached to the side of the second substructure facing away from the transparent medium layer.

4. The preparation method according to claim 1, wherein The step of forming the first connecting via is after the step of forming the second substructure.

5. The preparation method according to claim 4, wherein: The step of forming the first connecting via comprises: A transparent dielectric layer is provided, and the transparent dielectric layer is thinned and processed to form a first connecting via hole penetrating in the thickness direction of the transparent dielectric layer.

6. The preparation method according to claim 1, wherein The preparation method comprises the step of grinding the first conductive film layer and the first electrode plate of the capacitor.

7. The preparation method according to claim 1, wherein The preparation method further comprises: A third connection via is formed while the second connection via is formed, penetrating the second interlayer dielectric layer; a second connection electrode is formed while the second conductive film layer is formed, the second connection electrode being connected to the second plate of the capacitor through the third connection via; Depositing a first protective layer and a first planarization layer in sequence on a side of the second conductive film layer and the second connecting electrode away from the interlayer dielectric layer; forming a fourth connection via hole and a fifth connection via hole penetrating through the first protection layer and the first planarization layer; A first connection pad and a second connection pad are formed; the first connection pad is connected to the lead end of the inductor through the fourth connection via, and the second connection pad is connected to the second connection electrode through the fifth connection via.

8. The preparation method according to any one of claims 1 to 7, wherein When the first connection electrode does not completely fill the first connection via hole, a filling structure is formed in the first connection via hole between the step of forming the first connection electrode and the step of forming the second substructure.

9. The preparation method according to any one of claims 1 to 7, wherein The preparation method further comprises: A second protection layer and a second planarization layer are sequentially formed on a side of the first substructure away from the transparent medium layer.

10. The preparation method according to any one of claims 1 to 7, wherein: The transparent medium layer includes a glass base.

11. A substrate integrated with passive devices, comprising: A transparent dielectric layer and passive devices integrated on the dielectric layer; wherein, The transparent medium layer comprises a first surface and a second surface which are arranged opposite to each other along the thickness direction thereof; the transparent medium layer has a first connecting via hole which penetrates along the thickness direction thereof; The passive device includes an inductor and a capacitor; the inductor includes a first substructure arranged on the first surface, a second substructure arranged on the second surface, and a first connecting electrode arranged in the first connecting via hole to connect the first substructure and the second substructure in series in sequence; The capacitor comprises a first electrode plate and a second electrode plate sequentially arranged along a direction away from the second surface, and a first interlayer dielectric layer is arranged between the layers where the first electrode plate and the second electrode plate are located; the second substructure comprises a first conductive film layer and a second conductive film layer sequentially arranged along a direction away from the second surface; The first conductive film layer and the first electrode plate of the capacitor are arranged in the same layer and made of the same material; A second interlayer dielectric layer is arranged on the side of the second plate of the capacitor away from the transparent dielectric layer, and the second conductive film layer is arranged on the side of the second interlayer dielectric layer away from the transparent dielectric layer; the second conductive film layer is connected to the first conductive film layer through a second connecting via that penetrates the first interlayer dielectric layer and the second interlayer dielectric layer.

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