Power control circuit, method and vehicle-mounted electronic device of vehicle-mounted electronic equipment

Abstract

The present application provides a power control circuit, a method, and an in-vehicle electronic device for an in-vehicle electronic device. The power control circuit includes a power interface, a power supply circuit, a controller, and a sleep / wake-up circuit. The power supply circuit includes a hard-wired signal enable terminal and a bus signal enable terminal. The controller is electrically connected to the power supply circuit. The sleep / wake-up circuit is electrically connected to the power interface and the bus signal enable terminal, and includes a bus connection terminal for connecting to a network bus to receive a bus wake-up signal input by the network bus, and the bus wake-up signal is used to wake up the power supply circuit; the sleep / wake-up circuit is configured to generate a disable signal when the bus connection terminal does not receive the bus wake-up signal within an initial set duration after the power interface is connected to the power supply; the power supply circuit is configured not to output electrical energy to the controller and prevent the controller from being powered on and starting when the hard-wired signal enable terminal does not receive a hard-wired signal and the bus signal enable terminal receives the disable signal. Embodiments of the present application can reduce power consumption.

Description

Technical Field

[0001] The present application relates to the technical field of power control, and particularly to a power control circuit, a method and a vehicle-mounted electronic device for a vehicle-mounted electronic device. Background Art

[0002] With the continuous development of modern automotive industry and electronics, the degree of automotive electronics is getting higher and higher, and the number of vehicle-mounted electronic devices is increasing continuously. When the vehicle-mounted electronic device in the related technology accesses the power supply, when no external wake-up signal is received, the controller of the vehicle-mounted electronic device also powers on and starts up, which is not allowed in the vehicle factory and consumes the power of the vehicle battery. There is no better solution to this situation at present and it needs to be solved. Summary of the Invention

[0003] The present application provides an improved power control circuit, a method and a vehicle-mounted electronic device for a vehicle-mounted electronic device.

[0004] The present application provides a power control circuit for a vehicle-mounted electronic device, including:

[0005] A power interface for electrically connecting to a power supply;

[0006] A power circuit electrically connected to the power interface for converting the voltage of the power supply; the power circuit includes a hard wire signal enable terminal and a bus signal enable terminal, the hard wire signal enable terminal is used for receiving a hard wire signal, and the hard wire signal is used for waking up the power circuit;

[0007] A controller electrically connected to the power circuit; and

[0008] A sleep wake-up circuit electrically connected to the power interface and the bus signal enable terminal, and including a bus connection terminal, the bus connection terminal is used for connecting to a network bus and receiving a bus wake-up signal input by the network bus, the bus wake-up signal is used for waking up the power circuit; the sleep wake-up circuit is used for generating a disenable signal when the bus connection terminal does not receive the bus wake-up signal within an initial set duration after the power interface accesses the power supply; the power circuit is used for not outputting electric energy to the controller and not powering on and starting up the controller when the hard wire signal enable terminal does not receive the hard wire signal and the bus signal enable terminal receives the disenable signal.

[0009] Optionally, the sleep wake-up circuit includes a signal transceiver and a signal trigger circuit, the signal transceiver includes a transceiver power supply terminal and the bus connection terminal, and the transceiver power supply terminal is electrically connected to the power interface; the signal trigger circuit is electrically connected between the signal transceiver and the bus signal enable terminal;

[0010] The signal transceiver is used to generate a first signal within an initial set duration when the power supply is connected to the power supply interface and the bus wake-up signal is not received at the bus connection terminal; the signal trigger circuit is used to generate the disable signal when receiving the first signal, and the power supply circuit is used to not output electrical energy to the controller when the hard wire signal enable terminal does not receive the hard wire signal and the bus signal enable terminal receives the disable signal, so that the controller does not power on and start.

[0011] Optionally, the signal trigger circuit includes a signal trigger and a delay circuit. The signal trigger includes a trigger signal input terminal, an enable signal output terminal, and a clear terminal. The trigger signal input terminal is electrically connected to the interrupt signal output terminal of the signal transceiver, the enable signal output terminal is electrically connected to the bus signal enable terminal, the clear terminal is electrically connected to the delay circuit, the delay circuit is electrically connected to the output terminal of the power supply circuit, the power supply circuit is used to supply power to the delay circuit, and the delay circuit is used to provide voltage to the clear terminal;

[0012] The delay circuit is used to provide a reset voltage to the clear terminal within a delay duration starting from the initial moment of receiving the first signal, so that the enable signal output terminal generates the disable signal.

[0013] Optionally, the delay circuit includes a pull-up resistor and a charging capacitor connected in series between the output terminal of the power supply circuit and the ground terminal. The charging capacitor is electrically connected between the pull-up resistor and the ground terminal, and the clear terminal is electrically connected between the pull-up resistor and the charging capacitor.

[0014] Optionally, the sleep wake-up circuit is used to generate an enable signal when the bus wake-up signal is received at the bus connection terminal after the initial set duration when the power supply is connected to the power supply interface; the power supply circuit is used to convert the voltage of the power supply and supply power to the controller when the hard wire signal enable terminal receives the hard wire signal and / or the bus signal enable terminal receives the enable signal, so that the controller powers on and starts.

[0015] Optionally, the controller is electrically connected to the bus connection terminal, the hard wire signal enable terminal, and is also electrically connected to the signal transceiver;

[0016] The controller is used to detect the electrical signals of the bus connection terminal and the hard wire signal enable terminal after powering on and starting. When it detects that there is no bus wake-up signal at the bus connection terminal and no hard wire signal at the hard wire signal enable terminal, it controls the signal transceiver to enter the sleep mode.

[0017] Optionally, the signal trigger circuit further includes a clearing circuit, which is electrically connected between the clearing terminal and the controller;

[0018] When the signal transceiver is in the sleep mode, the controller is configured to control the clearing circuit to make the voltage at the clearing terminal be the reset voltage, so that the enable signal output terminal of the signal trigger generates the disable signal.

[0019] Optionally, the controller is electrically connected to the power supply circuit; after power-on startup, the controller is configured to output a latch signal to the power supply circuit to make the power supply circuit continuously supply power to the controller; and when the signal transceiver is in the sleep mode, the controller is configured to output a non-latch signal to the power supply circuit and control the clearing circuit to make the voltage at the clearing terminal be the reset voltage, so that the power supply circuit does not supply power to the controller.

[0020] Optionally, the clearing circuit includes a reset switch, which is electrically connected between the ground terminal and the clearing terminal, and the controller is electrically connected to the reset switch to control the on / off of the reset switch. When the reset switch is controlled to conduct, the voltage at the clearing terminal is the reset voltage.

[0021] Optionally, the power supply circuit includes a first power conversion circuit, a second power conversion circuit and a switch circuit. The first power conversion circuit is electrically connected to the power supply interface and is electrically connected to the controller through the switch circuit. The first power conversion circuit is configured to convert the voltage of the power supply;

[0022] The second power conversion circuit is electrically connected to the hardwire signal enable terminal, is electrically connected to the sleep wake-up circuit through the bus signal enable terminal, and is electrically connected to the power supply interface and the switch circuit;

[0023] When the bus signal enable terminal receives the disable signal and the hardwire signal enable terminal does not receive the hardwire signal, the second power conversion circuit is in the disabled state, causing the switch circuit to disconnect; and when the hardwire signal enable terminal receives the hardwire signal and / or the bus signal enable terminal receives the enable signal output by the sleep wake-up circuit, the second power conversion circuit is in the enabled state, converts the voltage of the power supply, controls the switch circuit to conduct, and enables the first power conversion circuit to supply power to the controller through the switch circuit.

[0024] The present application further provides a vehicle-mounted electronic device, including: the power supply control circuit according to any one of the above.

[0025] The present application also provides a power control method for an in-vehicle electronic device, which is applied to a power control circuit of the in-vehicle electronic device. The power control circuit includes a power interface, a power supply circuit, a controller, and a sleep / wake-up circuit. The power supply circuit is electrically connected to the power interface; the controller is electrically connected to the power supply circuit; the sleep / wake-up circuit is electrically connected to the power interface and the power supply circuit, and is connected to a network bus; the power control method includes:

[0026] Within an initial set duration after the power supply is connected to the power interface, if a bus wake-up signal from the network bus is not received, the sleep / wake-up circuit generates a disenable signal;

[0027] If the power supply circuit does not receive a hard-wired signal and receives the disenable signal, the power supply circuit does not output electrical energy to the controller, so that the controller does not power on and start.

[0028] Optionally, the sleep / wake-up circuit includes a signal transceiver and a signal trigger circuit. The signal transceiver is electrically connected to the power interface and the network bus; the signal trigger circuit is electrically connected between the signal transceiver and the power supply circuit;

[0029] The step that within an initial set duration after the power supply is connected to the power interface, if a bus wake-up signal from the network bus is not received, the sleep / wake-up circuit generates a disenable signal includes:

[0030] Within an initial set duration after the power supply is connected to the power interface, if the bus wake-up signal is not received, the signal transceiver generates a first signal;

[0031] The signal trigger circuit generates the disenable signal in response to the first signal.

[0032] Optionally, the signal trigger circuit includes a signal trigger and a delay circuit. The signal trigger includes a clear terminal. The signal trigger is electrically connected to the signal transceiver and the power supply circuit, and the clear terminal is electrically connected to the delay circuit;

[0033] The step that the signal trigger circuit generates the disenable signal in response to the first signal includes:

[0034] Within a delay duration starting from the initial moment when the first signal is received by the signal trigger, the delay circuit provides a reset voltage to the clear terminal, so that the signal trigger generates the disenable signal.

[0035] Optionally, the power control method further includes:

[0036] After an initial set duration for the power supply to be connected to the power interface, if the bus wake-up signal is received, the sleep wake-up circuit generates an enable signal;

[0037] If the power supply circuit receives the hard-wired signal and / or the enable signal, it converts the voltage of the power supply to supply power to the controller, enabling the controller to power on and start up.

[0038] Optionally, the power supply control method further includes:

[0039] After the controller powers on and starts up, it detects the bus wake-up signal and the hard-wired signal;

[0040] If the bus wake-up signal and the hard-wired signal are not detected, the controller controls the signal transceiver to enter the sleep mode.

[0041] Optionally, the signal trigger circuit further includes a clearing circuit, and the clearing circuit is electrically connected between the clearing terminal and the controller;

[0042] The power supply control method further includes:

[0043] When the signal transceiver is in the sleep mode, the controller controls the clearing circuit to make the voltage of the clearing terminal the reset voltage, so that the signal trigger generates the disable signal.

[0044] Optionally, the power supply control method further includes:

[0045] After the controller powers on and starts up, it outputs a latch signal to the power supply circuit to make the power supply circuit continuously supply power to the controller; and

[0046] When the signal transceiver is in the sleep mode, the controller outputs an unlatch signal to the power supply circuit and controls the clearing circuit to make the voltage of the clearing terminal the reset voltage, so that the power supply circuit does not supply power to the controller.

[0047] In the initial set duration when the power supply is connected to the power interface, if the bus connection terminal does not receive the bus wake-up signal, the sleep wake-up circuit of the power supply control circuit provided by the embodiment of the present application generates a disable signal. When the hard-wired signal enable terminal of the power supply circuit does not receive the hard-wired signal and the bus signal enable terminal receives the disable signal, the power supply circuit does not output electrical energy to the controller, so that the controller does not power on and start up. With such a setting, when the power supply is connected to the power interface and no external wake-up signal (bus wake-up signal and hard-wired signal) is received, the controller is prevented from being activated, so that the controller does not power on and start up when it does not need to start, reducing power consumption.

[0048] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and should not limit this application. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The accompanying drawings are incorporated herein and constitute a part of this specification, showing embodiments consistent with this application, and are used together with the specification to explain the principles of this application.

[0050] Figure 1 The principle block diagram of an embodiment of the power control circuit of the in-vehicle electronic device of this application is shown.

[0051] Figure 2 The circuit diagram of the power control circuit of the in-vehicle electronic device of this application is shown.

[0052] Figure 3 Shown as Figure 1 The timing logic diagram of the power control circuit of the in-vehicle electronic device shown.

[0053] Figure 4 Shown as Figure 3 The working state flowchart of the power control circuit of the in-vehicle electronic device shown.

[0054] Figure 5 The step flowchart of an embodiment of the power control method of the in-vehicle electronic device of this application is shown.

[0055] Figure 6 Shown as Figure 5 The step flowchart of an embodiment of step S10 of the power control method of the in-vehicle electronic device shown.

[0056] Figure 7 The step flowchart of another embodiment of the power control method of the in-vehicle electronic device of this application is shown.

[0057] Figure 8 The step flowchart of yet another embodiment of the power control method of the in-vehicle electronic device of this application is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0058] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. On the contrary, they are merely examples of devices and methods consistent with some aspects of this application as detailed in the appended claims.

[0059] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in this application shall have the ordinary meanings as understood by those of ordinary skill in the art to which this application pertains. The terms "first", "second" and similar words used in the specification and claims of this application do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "a" or "an" do not denote a limitation of quantity, but mean that there is at least one. "Plurality" or "several" means two or more. Unless otherwise specified, words such as "front", "rear", "lower" and / or "upper" are for convenience of description only and are not limited to one position or a spatial orientation. Words such as "comprising" or "including" mean that the elements or items appearing before "comprising" or "including" cover the elements or items listed after "comprising" or "including" and their equivalents, and do not exclude other elements or items. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, and may include electrical connections, whether direct or indirect.

[0060] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms "a", "the" and "said" used in this application and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0061] This application provides a power control circuit for a vehicle-mounted electronic device, including a power interface, a power circuit, a controller and a sleep / wake-up circuit. The power interface is used for electrically connecting to a power source. The power circuit is electrically connected to the power interface and is used for converting the voltage of the power source; the power circuit includes a hard-wired signal enable terminal and a bus signal enable terminal, and the hard-wired signal enable terminal is used for receiving a hard-wired signal, and the hard-wired signal is used for waking up the power circuit. The controller is electrically connected to the power circuit. The sleep / wake-up circuit is electrically connected to the power interface and the bus signal enable terminal, and includes a bus connection terminal, and the bus connection terminal is used for connecting to a network bus and receiving a bus wake-up signal input by the network bus, and the bus wake-up signal is used for waking up the power circuit; the sleep / wake-up circuit is used for generating a disable signal when the bus connection terminal does not receive the bus wake-up signal within an initial set duration after the power interface accesses the power source; the power circuit is used for not outputting electric energy to the controller and preventing the controller from powering on and starting when the hard-wired signal enable terminal does not receive the hard-wired signal and the bus signal enable terminal receives the disable signal.

[0062] When the bus connection terminal does not receive a bus wake-up signal within the initial set duration after the power supply interface of the sleep wake-up circuit of the power control circuit provided in the embodiment of the present application is connected to the power supply, a disenable signal is generated. When the hard-wired signal enable terminal of the power supply circuit does not receive a hard-wired signal and the bus signal enable terminal receives a disenable signal, the power supply circuit does not output electrical energy to the controller, so that the controller does not power on and start. With such a setting, when the power supply interface is connected to the power supply and no external wake-up signal (bus wake-up signal and hard-wired signal) is received, the controller is prevented from being activated, so that the controller does not power on and start when it does not need to start, reducing power consumption.

[0063] The present application provides a power control circuit, a method and a vehicle-mounted electronic device for a vehicle-mounted electronic device. The power control circuit, the method and the vehicle-mounted electronic device of the present application will be described in detail below with reference to the accompanying drawings. Without conflict, the features in the following embodiments and implementation manners can be combined with each other.

[0064] Figure 1 The following shows a circuit diagram of an embodiment of the power control circuit 10 of the vehicle-mounted electronic device of the present application. As Figure 1 shown, the power control circuit 10 includes a power supply interface 101, a power supply circuit 102, a controller 103 and a sleep wake-up circuit 104. Among them, the power supply interface 101 is used for electrically connecting to the power supply 20. In this embodiment, the power supply 20 may be a vehicle-mounted battery. The power supply circuit 102 is electrically connected to the power supply interface 101 and is used for converting the voltage of the power supply. In this embodiment, the power supply circuit 102 is electrically connected to the power supply 20 through the power supply interface 101. The power supply circuit 102 may be a DC power supply circuit and is used for converting the output voltage of the vehicle-mounted battery.

[0065] The power supply circuit 102 includes a hard-wired signal enable terminal 105 and a bus signal enable terminal 106. The hard-wired signal enable terminal 105 is used for receiving a hard-wired signal. The hard-wired signal is used for waking up the power supply circuit 102. In the control system of automotive electronic devices, the hard-wired signal may be a control signal for ignition and / or control, etc. to implement basic control functions. The controller 103 is electrically connected to the power supply circuit 102. When the power supply circuit 102 is enabled, the power supply circuit 102 can supply power to the controller 103. When the power supply circuit 102 is not enabled, the power supply circuit 102 does not supply power to the controller 103. The power supply circuit 102 is used for supplying power to the controller 103 and can also supply power to other circuits.

[0066] The sleep wake-up circuit 104 is electrically connected to the power interface 101 and the bus signal enable terminal 106, and includes a bus connection terminal 107. The bus connection terminal 107 is used to connect to the network bus 30 and receive the bus wake-up signal input by the network bus 30, and the bus wake-up signal is used to wake up the power supply circuit 102. The sleep wake-up circuit 104 is electrically connected to the power supply 20 through the power interface 101. The sleep wake-up circuit 104 is electrically connected to the power supply circuit 102 through the bus signal enable terminal 106. In the control system of automotive electronic devices, the bus wake-up signal is a network data signal for in-vehicle intelligent control, and the amount of data it carries is relatively large.

[0067] The sleep wake-up circuit 104 is used to generate a disenable signal when the bus connection terminal 107 does not receive the bus wake-up signal within the initial set duration after the power supply 20 is connected to the power interface 101. In this embodiment, the disenable signal controls the power supply circuit 102 to be disabled, the power supply circuit 102 is not woken up, and does not supply power to the controller 103. The power supply circuit 102 is used to not output electrical energy to the controller 103 when the hard wire signal enable terminal 105 does not receive the hard wire signal and the bus signal enable terminal 106 receives the disenable signal, so that the controller 103 does not power on and start. In the related art, at the moment when the power supply is connected, the voltage changes, causing the sleep wake-up circuit 104 to power on and output an enable signal (such as a high level), enabling the power supply circuit 102 and causing the controller 103 to power on and start. At this time, even if no external wake-up signal is received, the controller 103 still powers on and starts. In this application, when the power supply 20 is connected to the power interface 101 within the initial set duration and the bus wake-up signal is not received, the sleep wake-up circuit 104 generates a disenable signal. And if the power supply circuit 102 also does not receive the hard wire signal, the power supply circuit 102 is disabled, so that the controller 103 does not power on and is not activated, causing the controller 103 not to power on and start when the power control circuit 10 powers on (when the power supply is connected), thereby reducing power consumption and reducing the power consumption of the in-vehicle battery. After the initial set duration, if the bus wake-up signal is not received, the sleep wake-up circuit 104 can enter the sleep state until the bus wake-up signal is received. Within the initial set duration, if the bus wake-up signal and / or the hard wire signal are received, the power supply circuit 102 is enabled, activated, and the controller 103 starts.

[0068] Figure 2 The circuit diagram of the power control circuit 10 of the in-vehicle electronic device of this application is shown. In Figure 2In the illustrated embodiment, the sleep / wake-up circuit 104 includes a signal transceiver 109 and a signal trigger circuit 110. The signal transceiver 109 includes a transceiver power supply terminal 111 and a bus connection terminal 107. The transceiver power supply terminal 111 is electrically connected to the power supply interface 101. The transceiver power supply terminal 111 is used to connect to the power supply 20 through the power supply interface 101. The bus connection terminal 107 is used to connect to the network bus 30 and receive the bus wake-up signal input by the network bus 30. The network bus 30 sends the bus wake-up signal to the signal transceiver 109 through the bus connection terminal 107. The signal transceiver 109 receives the bus wake-up signal input from the network bus 30 through the bus connection terminal 107. The signal trigger circuit 110 is electrically connected between the signal transceiver 109 and the bus signal enable terminal 106. The signal trigger circuit 110 is used to receive the output signal of the signal transceiver 109 and control the power supply circuit 102 through the bus signal enable terminal 106 according to the output signal of the signal transceiver 109.

[0069] The signal transceiver 109 is used to generate a first signal within an initial set duration when the power supply 20 is connected to the power supply interface 101 and the bus connection terminal 107 does not receive the bus wake-up signal. The initial set duration includes the moment when the transceiver power supply terminal 111 of the signal transceiver 109 disconnects from the power supply 20 and then connects to the power supply 20 through the power supply interface 101. Within this initial set duration, the output terminal of the signal transceiver 109 continuously outputs the first signal. In some embodiments, the first signal output when the transceiver power supply terminal 111 of the signal transceiver 109 disconnects from the power supply 20 and then connects to the power supply 20 through the power supply interface 101 is a high level. The signal trigger circuit 110 is used to generate a disenable signal when receiving the first signal (high level). In some embodiments, the disenable signal is a low-level signal, which controls the power supply circuit 102 to be disenabled. The enable signal is a high level. The power supply circuit 102 is used to not output electrical energy to the controller 103 and prevent the controller 103 from powering on and starting when the hard wire signal enable terminal 105 does not receive the hard wire signal and the bus signal enable terminal 106 receives the disenable signal.

[0070] In this embodiment, the signal transceiver 109 is a positive edge trigger. When the transceiver power supply terminal 111 of the signal transceiver 109 disconnects from the power supply 20 and then connects to the power supply 20 through the power supply interface 101, the signal transceiver 109 is in the standby mode. In the standby mode, the first signal output by the signal transceiver 109 is a trigger signal and is a high level. If the output terminal of the signal transceiver 109 is directly electrically connected to the power supply circuit 102, when the transceiver power supply terminal 111 of the signal transceiver 109 connects to the power supply 20, the first signal will be output, which will wake up the power supply circuit 102 and cause the controller 103 to power on and start. However, at this time, without an external wake-up signal and without the need for the controller 103 to start, the power-on start of the controller 103 will cause power consumption.

[0071] Therefore, in the present application, to avoid the situation where the controller 103 is directly awakened by the signal transceiver 109 powered on without an external wake-up signal, which causes unnecessary power-on startup of the controller 103, a signal trigger circuit 110 is provided between the signal transceiver 109 and the power supply circuit 102. Within a set time period, the signal trigger circuit 110 outputs a disenable signal according to the first signal output by the signal transceiver 109, so that the power supply circuit 102 cannot be awakened and the controller 103 is not powered on, avoiding the activation of the controller 103 when it does not need to be activated and preventing the controller 103 from powering on and starting when it does not need to start, thereby reducing power consumption.

[0072] In some embodiments, the signal transceiver 109 includes an interrupt signal output terminal 112. The signal trigger circuit 110 is electrically connected to the signal transceiver 109 through the interrupt signal output terminal 112. In some embodiments, the signal trigger circuit 110 includes a signal trigger 113 and a delay circuit 114. The signal trigger 113 includes a trigger signal input terminal 115, an enable signal output terminal 116, and a clear terminal 117. The trigger signal input terminal 115 is electrically connected to the interrupt signal output terminal 112 of the signal transceiver 109. The signal transceiver 109 is electrically connected to the signal trigger 113 through the interrupt signal output terminal 112. The signal trigger 113 receives the first signal from the signal transceiver 109 through the trigger signal input terminal 115. The enable signal output terminal 116 is electrically connected to the bus signal enable terminal 106. The signal trigger 113 is electrically connected to the bus signal enable terminal 106 of the power supply circuit 102 through the enable signal output terminal 116. The power supply circuit 102 receives the bus wake-up signal output from the enable signal output terminal 116 of the signal trigger 113 through the bus enable terminal 106. The clear terminal 117 is electrically connected to the delay circuit 114, and the delay circuit 114 is electrically connected to the output terminal of the power supply circuit 102. The clear terminal 117 is electrically connected to the power supply circuit 102 through the delay circuit 114. The power supply circuit 102 is used to supply power to the delay circuit 114, and the delay circuit 114 is used to provide voltage to the clear terminal 117. The delay circuit 114 is used to provide a reset voltage to the clear terminal 117 within a delay time period starting from the initial moment when the first signal is received, so that the enable signal output terminal 116 generates a disenable signal.

[0073] In some embodiments, the signal trigger 113 is triggered when a signal change (such as a rising edge) is received at the trigger signal input terminal 115. If the reset voltage (low level) is not received at the clear terminal 117, the signal trigger 113 outputs an enable signal (high level). At the moment of the signal change at the trigger signal input terminal 115 of the signal trigger 113, a reset voltage (low level) is provided to the clear terminal 117 through the delay circuit 114, and the signal trigger 113 is not triggered and outputs a non-enable signal (low level). After the delay duration, a voltage corresponding to the level opposite to the reset voltage (high level) is provided to the clear terminal 117. Since the moment of the signal change received at the trigger signal input terminal 115 has passed (the rising edge moment has passed) and the signal is a stable level, the signal trigger 113 is not triggered and continues to output a non-enable signal. The delay circuit 114 delays and supplies the voltage output by the power supply circuit 102 to the zero-crossing terminal 117.

[0074] In this embodiment, the delay circuit 114 is configured to provide a reset voltage to the clear terminal 117 within 90 ms from the initial moment of receiving the first signal. This reset voltage is a low level. When the delay circuit 114 provides a low level to the clear terminal 117, a non-enable signal is generated at the enable signal output terminal 116 of the signal trigger 113. This non-enable signal is a low-level signal, and the low-level signal cannot enable the wake-up power supply circuit 102 and cannot supply power to the controller 103. Therefore, when the power supply circuit 102 does not receive a hard-wired signal and receives a non-enable signal, the wake-up power supply circuit 102 cannot be enabled and power cannot be supplied to the controller 103. With such a setting, within 90 ms after the power supply interface 101 is connected to the power supply 20 and no hard-wired signal is received, it is avoided that the controller 103 is activated when it does not need to be activated, so that the controller 103 does not power on and start when it does not need to be started, reducing power consumption.

[0075] In some embodiments, the delay circuit 114 includes a pull-up resistor R1 and a charging capacitor C1 connected in series between the output terminal of the power supply circuit 102 and the ground terminal GND. The charging capacitor C1 is electrically connected between the pull-up resistor R1 and the ground terminal GND, and the clear terminal 117 is electrically connected between the pull-up resistor R1 and the charging capacitor C1. In this embodiment, the pull-up resistor R1 is electrically connected to the output terminal of the power supply circuit 102. When the power supply interface 101 accesses the power supply 20, the power supply circuit 102 is powered on, converts the voltage of the power supply 20, and the power supply circuit 102 charges the charging capacitor C1 through the pull-up resistor R1. The delay time is the charging time of the charging capacitor C1. During the period when the charging capacitor C1 is being charged, the voltage of the clear terminal 117 is pulled low, causing the clear terminal 117 to output a low level, and this low level is the reset voltage. According to the attributes of the signal trigger 113, when the clear terminal 117 of the signal trigger 113 receives the reset voltage (low level), the enable signal output terminal 116 of the signal trigger 113 generates a disenable signal, and this disenable signal is a low-level signal. With such a setting, within the delay time when the power supply interface 101 accesses the power supply 20 and no hard-wired signal is received, the controller 103 is prevented from being activated, so that the controller 103 does not power on and start when it does not need to be started, reducing power consumption. After the charging is completed, the voltage of the charging capacitor C1 rises, and the clear terminal 117 is at a high level. The delay is achieved through the charging capacitor C1.

[0076] In Figure 2 In the illustrated embodiment, the power supply circuit 102 includes a power conversion circuit 130 and a logic circuit 108. The logic circuit 108 includes a hard-wired signal enable terminal 105 and a bus signal enable terminal 106, and is electrically connected to the power conversion circuit 130. The hard-wired signal enable terminal 105 and the bus signal enable terminal 106 are connected to the input terminal of the logic circuit 108. The power conversion circuit 130 is connected to the output terminal of the logic circuit 108 and is electrically connected to the controller 103 for supplying power to the controller 103. The hard-wired signal enable terminal 105 and the bus signal enable terminal 106 control the power conversion circuit 130 to be enabled or disabled through the logic circuit 108.

[0077] In this embodiment, the logic circuit 108 can be an OR gate logic circuit. When the hard-wired signal enabling terminal 105 does not receive a hard-wired signal and the bus signal enabling terminal 106 receives a disabling signal, the power conversion circuit 130 cannot be awakened. At this time, the power conversion circuit 130 is in the sleep mode and cannot output electrical energy to the controller 103, so that the controller 103 is not powered on and started. When the hard-wired signal enabling terminal 105 receives a hard-wired signal and / or the bus signal enabling terminal 106 receives an enabling signal, the power conversion circuit 130 can be awakened. At this time, the power conversion circuit 130 switches from the sleep mode to the working mode. After awakening the power conversion circuit 130, the power conversion circuit 130 can convert the voltage of the power supply 20 and output electrical energy to the controller 103 to power on and start the controller 103. With such a setting, the power control circuit 10 can realize the wake-up function of awakening the power conversion circuit 130 by using the hard-wired signal and / or the bus wake-up signal.

[0078] In this embodiment, the power supply 20 is a vehicle-mounted battery, and the voltage of the vehicle-mounted battery is 12V. The power conversion circuit 130 includes a first power conversion circuit 118, a second power conversion circuit 119, and a switch circuit 120. The first power conversion circuit 118 and the second power conversion circuit 119 can be DC conversion circuits for converting the voltage of the power supply 20. The first power conversion circuit 118 can convert 12V to 3.3V. The second power conversion circuit 119 can convert 12V to 5V. The switch circuit 120 includes an electronic control switch. The first power conversion circuit 118 is electrically connected to the power interface 101 and is electrically connected to the controller 103 through the switch circuit 120. The first power conversion circuit 118 is electrically connected to the power supply 20 through the power interface 101 for converting the voltage of the power supply 20. For example, the conversion output is 3.3V. The second power conversion circuit 119 is electrically connected to the hard-wired signal enabling terminal 105, is electrically connected to the sleep wake-up circuit 104 through the bus signal enabling terminal 106, and is electrically connected to the power interface 101 and the switch circuit 120. The second power conversion circuit 119 is electrically connected to the hard-wired signal enabling terminal 105 and the bus signal enabling terminal 106 through the logic circuit 108. In this embodiment, the second power conversion circuit 119 is electrically connected to the signal trigger 113 of the sleep wake-up circuit 104 through the bus signal enabling terminal 106. The second power conversion circuit 119 is electrically connected to the signal transceiver 109. When the second power conversion circuit 119 is in the enabled state, it supplies power to the signal transceiver 109; when the second power conversion circuit 119 is in the disabled state, it does not supply power to the signal transceiver 109.

[0079] In some embodiments, when the second power conversion circuit 119 receives a disenable signal at the bus signal enable terminal 106 and does not receive a hardwired signal at the hardwired signal enable terminal 105, the second power conversion circuit 119 is disabled, the control switch circuit 120 is turned off, the first power conversion circuit 118 is disconnected from the controller 103, and the controller 103 cannot be powered. In some embodiments, when the second power conversion circuit 119 receives a hardwired signal at the hardwired signal enable terminal 105 and / or receives an enable signal output by the sleep wake-up circuit 104 at the bus signal enable terminal 106, the second power conversion circuit 119 is enabled, the voltage of the power supply 20 is converted to control the switch circuit 120 to be turned on, and the first power conversion circuit 118 supplies power to the controller 103 through the switch circuit 120. In some embodiments, the first power conversion circuit 118 is electrically connected to the signal transceiver 109 through the switch circuit 120. When the switch circuit 120 is turned on, the first power conversion circuit 118 supplies power to the signal transceiver 109.

[0080] The first power conversion circuit 118 and the second power conversion circuit 119 are arranged in parallel, and at least one of the hardwired signal enable terminal 105 and the bus signal enable terminal 106 is used to enable and control the second power conversion circuit 119 to control the on / off of the switch circuit 120, thereby controlling the on / off of the first power conversion circuit 118 and the controller 103. With such an arrangement, when the controller 103 does not need to be powered on and started, the second power conversion circuit 119 is disabled, the first power conversion circuit 118 does not supply power to the controller 103, the controller 103 is prevented from being activated when it does not need to be activated, the controller 103 is not powered on and started when it does not need to be started, and the power consumption is reduced. When the controller 103 needs to be powered on and started, the second power conversion circuit 119 is enabled, the first power conversion circuit 118 supplies power to the controller 103, and the normal power-on operation of the controller 103 is ensured.

[0081] In some embodiments, the sleep wake-up circuit 104 is configured to generate an enable signal when the bus connection end 107 receives a bus wake-up signal after an initial set duration when the power supply interface 101 is connected to the power supply 20. The power supply circuit 102 is configured to convert the voltage of the power supply 20 and supply power to the controller 103 to power on and start the controller 103 when the hard-wired signal enable terminal 105 receives a hard-wired signal and / or the bus signal enable terminal 106 receives an enable signal. In some embodiments, the power supply circuit 102 converts the voltage of the power supply 20 and supplies power to the controller 103 to power on and start the controller 103 when the hard-wired signal enable terminal 105 receives a hard-wired signal. The power supply circuit 102 converts the voltage of the power supply 20 and supplies power to the controller 103 to power on and start the controller 103 when the bus signal enable terminal 106 receives an enable signal. The power supply circuit 102 converts the voltage of the power supply 20 and supplies power to the controller 103 to power on and start the controller 103 when the hard-wired signal enable terminal 105 receives a hard-wired signal and the bus signal enable terminal 106 receives an enable signal.

[0082] In this embodiment, the signal transceiver 109 is configured to generate a second signal at the interrupt signal output terminal 112 of the signal transceiver 109 when the bus connection end 107 receives a bus wake-up signal after an initial set duration when the power supply interface 101 is connected to the power supply 20. The second signal may be a high-level signal. The signal trigger circuit 110 is configured to generate an enable signal when receiving the second signal (high level). The power supply circuit 102 is configured to output electrical energy to the controller 103 to power on and start the controller 103 when the hard-wired signal enable terminal 105 receives a hard-wired signal and / or the bus signal enable terminal 106 receives an enable signal. With such a setting, it can be ensured that after the initial set duration, the external wake-up signal can wake up the controller 103 to make the controller 103 work, ensuring that the controller 103 is normally woken up when it needs to work.

[0083] In some embodiments, the controller 103 is electrically connected to the bus connection terminal 107, the hardwired signal enabling terminal 105, and is also electrically connected to the signal transceiver 109. The controller 103 is configured to, after power-on startup, detect the electrical signals of the bus connection terminal 107 and the hardwired signal enabling terminal 105. When it detects that there is no bus wake-up signal at the bus connection terminal 107 and no hardwired signal at the hardwired signal enabling terminal 105, it controls the signal transceiver 109 to enter the sleep mode. In this embodiment, after power-on startup, the controller 103 can detect the electrical signals of the bus connection terminal 107 and the hardwired signal enabling terminal 105 in real time or periodically. If it detects that there is no bus wake-up signal at the bus connection terminal 107 and no hardwired signal at the hardwired signal enabling terminal 105, it indicates that there is no wake-up requirement from the outside. At this time, it can control the signal transceiver 109 to enter the sleep mode. If it detects that there is a bus wake-up signal at the bus connection terminal 107 and / or a hardwired signal at the hardwired signal enabling terminal 105, it indicates that there is a wake-up requirement from the outside. At this time, it controls the signal transceiver 109 to enter the working mode. In this way, the power consumption is reduced and the service life of the signal transceiver 109 is extended.

[0084] In some embodiments, the signal trigger circuit 110 further includes a clearing circuit 121, and the clearing circuit 121 is electrically connected between the clearing terminal 117 and the controller 103. The controller 103 is configured to, when the signal transceiver 109 is in the sleep mode, control the clearing circuit 121 to make the voltage of the clearing terminal 117 the reset voltage, so as to cause the enabling signal output terminal 116 of the signal trigger 113 to generate a non-enabling signal. In this embodiment, when the signal transceiver 109 is in the sleep mode, the clearing circuit 121 can be controlled to make the voltage of the clearing terminal 117 the reset voltage. This reset voltage is a low level, and this low level can cause the enabling signal output terminal 116 to generate a non-enabling signal. When the controller 103 detects that there is no bus wake-up signal at the bus connection terminal 107 and no hardwired signal at the hardwired signal enabling terminal 105, it controls the signal transceiver 109 to enter the sleep mode, and controls the clearing circuit 121 to make the voltage of the clearing terminal 117 the reset voltage, causing the signal trigger 113 to generate a non-enabling signal, thereby controlling the power supply circuit 102 to be non-enabled and stopping supplying power to the controller 103. In this way, the controller 103 is in the sleep mode, reducing the power consumption.

[0085] In some embodiments, the clearing circuit 121 includes a reset switch Q1. The reset switch Q1 is electrically connected between the ground terminal and the clearing terminal 117. The controller 103 is electrically connected to the reset switch Q1 to control the on / off of the reset switch Q1. When the reset switch Q1 is controlled to conduct, the voltage of the clearing terminal 117 is the reset voltage. In this embodiment, the reset switch Q1 is a triode. The clearing circuit 121 further includes a resistor R2 and a resistor R3. The base of the triode is electrically connected to the controller 103 through the resistor R2, and the resistor R2 functions as a current limiter. The collector of the triode is electrically connected to the clearing terminal 117. The emitter of the triode is grounded. The resistor R3 is electrically connected between the base and the emitter of the triode. When the signal transceiver 109 is in the sleep mode, the controller 103 controls the reset switch Q1 to conduct, grounding the clearing terminal 117 and making the voltage of the clearing terminal 117 the low-level voltage. Thus, the power supply circuit 102 can be powered down, and the controller 103 can be in the sleep mode. The charging capacitor C1 is electrically connected to the reset switch Q1. When the reset switch Q1 conducts, the charging capacitor C1 discharges through the reset switch Q1.

[0086] In some embodiments, the controller 103 is electrically connected to the power supply circuit 102. The controller 103 is configured to output a latch signal to the power supply circuit 102 after power-on startup, ensuring that the power supply circuit 102 is always enabled and not affected by the signals of the hard-wired signal enable terminal 105 and the bus signal enable terminal 106, so that the power supply circuit 102 continuously supplies power to the controller 103. With such a setting, the voltage of the power supply circuit 102 can be self-locked to ensure a constant output of electrical energy to the controller 103. In some embodiments, the controller 103 is electrically connected to the logic circuit 108 and is configured to output a latch signal (MCU_HOLD) to the logic circuit 108, ensuring that the enable terminal of the second power conversion circuit 119 always receives a level that enables it, ensuring that the second power conversion circuit 119 remains enabled, thereby providing power continuously and stably. The second power conversion circuit 119 can be enabled by a high level. The latch signal is at a high level. The logic circuit 108 is an OR gate logic circuit. Any one of the latch signal, the hard-wired enable signal of the hard-wired signal enable terminal 105, and the signal of the bus signal enable terminal 106 being at a high level enables the second power conversion circuit 119. In some embodiments, when the signal transceiver 109 is in the sleep mode, the controller 103 is configured to output a non-latch signal to the power supply circuit 102 and control the clearing circuit 121 to make the voltage of the clearing terminal 117 the reset voltage, so that the power supply circuit 102 does not supply power to the controller. The level of the non-latch signal is opposite to the level of the latch signal. When not latched, the hard-wired enable signal of the hard-wired signal enable terminal 105 and the signal of the bus signal enable terminal 106 can control the second power conversion circuit 119. Therefore, the disable signal output by the signal trigger circuit 110 can control the second power conversion circuit 119 to be disabled. With such a setting, when the signal transceiver 109 is in the sleep mode, the power supply circuit 102 does not supply power to the controller, and the controller 103 is also in the sleep mode. This reduces power consumption and extends the service life of the controller 103.

[0087] In Figure 2In the illustrated embodiment, the signal trigger 113 further includes a D pin, a / PRE pin, a VCC pin, and a ground pin. The D pin, the / PRE pin, and the VCC pin are respectively electrically connected to the first power conversion circuit 118 through a switch circuit 120. In some embodiments, the signal trigger circuit 110 further includes a resistor R4, which is electrically connected between the output terminal of the first power conversion circuit 118 and the D pin, and functions to limit the current. In some embodiments, the signal trigger circuit 110 further includes a capacitor C2, which is respectively electrically connected between the / PRE pin, the VCC pin, and the ground terminal, and is electrically connected to the output terminal of the first power conversion circuit 118, and functions to filter. In some embodiments, the signal trigger circuit 110 further includes a resistor R5, a capacitor C3, and a zener diode D1. The resistor R5, the capacitor C3, and the zener diode D1 are electrically connected between the trigger signal input terminal 115 and the ground terminal. The resistor R5 functions to limit the current, the capacitor C3 functions to filter, and the zener diode D1 functions to regulate the voltage.

[0088] In Figure 2 In the illustrated embodiment, the power control circuit 10 further includes a system power module 131, and the controller 103 is further configured to supply power to the system power module 131. In some embodiments, the in-vehicle electronic device further includes a system module 132, which is electrically connected to the system power module 131, and the system power module 131 supplies power to the system module 132. In some embodiments, the system power module 131 includes a system power control circuit 133 and a system power conversion circuit 134, which are respectively electrically connected to the system module 132, and can provide different power supply voltages to the components within the system module 132. With such a setting, different components of the system module of the in-vehicle electronic device can be normally powered, ensuring normal operation. In this embodiment, the system module 132 includes different electronic components of the in-vehicle electronic device, which are not limited in this application.

[0089] Figure 3 As shown is Figure 1 The timing logic diagram of the power control circuit 10 of the in-vehicle electronic device shown. In this embodiment, the signal trigger 113 is a positive edge trigger. When the signal input at the trigger signal input terminal 115 of the signal trigger 113 is a rising edge, the trigger enable signal output terminal 116 outputs an enable signal. In this embodiment, the non-enable signal is a low-level signal, and the enable signal is a high-level signal. That is, when the signal input at the trigger signal input terminal 115 of the signal trigger 113 is a rising edge, the output of the trigger enable signal output terminal 116 will switch from a low level to a high level. When the signal input at the trigger signal input terminal 115 of the signal trigger 113 is not a rising edge, the output of the trigger enable signal output terminal 116 will maintain the level signal of the previous state.

[0090] In Figure 3In the illustrated embodiment, the first timing diagram S1 shown is the timing diagram of the signal output from the interrupt signal output terminal 112 of the signal transceiver 109, and the second timing diagram S2 shown is the timing diagram of the signal output from the enable signal output terminal 116 of the signal trigger 113. In Figure 2 In the illustrated embodiment, the signal trigger 113 further includes a D pin, a / PRE pin, and a VCC pin. The D pin, the / PRE pin, and the VCC pin are respectively electrically connected to the first power conversion circuit 118 through a switch circuit 120.

[0091] Combined with Figures 1 to 4 As shown, during the time periods T1 to T3, at time T1, the power control circuit 10 is connected to the power supply 20 (vehicle battery). The signal output from the interrupt signal output terminal 112 of the signal transceiver 109 changes from low level to high level. However, when there is no bus wake-up signal and hard-wire signal, the enable signal output from the enable signal output terminal 116 of the signal trigger 113 is a non-enable signal, which is a low-level signal in the figure. The controller 103 is not powered on and will not start.

[0092] The specific process includes steps S30 to S32. Specifically as follows:

[0093] Step S30: At time T1, the power control circuit 10 is connected to the power supply 20 (vehicle battery) through the power interface 101. The transceiver power supply terminal 111 of the signal transceiver 109 is powered on, and the signal transceiver 109 is activated. The signal transceiver 109 operates in the standby mode. At this time, the signal output from the interrupt signal output terminal 112 of the signal transceiver 109 is at a high level. That is, the signal input to the trigger signal input terminal 115 (CLK, as shown in Table 2) of the signal trigger 113 is a rising edge (↑, as shown in Table 2). During this process, when the power supply 20 is connected, the first power conversion circuit 118 outputs a working voltage of 3.3V, which can supply power to the VCC pin of the signal trigger 113. The / PRE pin ( / PRE, as shown in Table 2) of the signal trigger 113 is at a high level (H, as shown in Table 2), and the D pin (D, as shown in Table 2) of the signal trigger 113 is at a high level (H, as shown in Table 2). The clear terminal 117 of the signal trigger 113 is powered on with a delay through the delay circuit 114. From time T1 to time T2 is the delay duration, and the clear terminal 117 ( / CLR, as shown in Table 2) of the signal trigger 113 is at a low level (L, as shown in Table 2).

[0094] Referring to the truth table of the signal flip-flop 113 (as shown in Table 1), at this time, the enable signal output terminal 116 (Q, as shown in Table 2) of the signal flip-flop 113 outputs a low level (L, as shown in Table 2), that is, the electrical signal of the bus signal enable terminal 106 (EN, as shown in Table 2) is a low level (L, as shown in Table 2). At this time, when there is no hardwired signal at the hardwired signal enable terminal 105, the second power conversion circuit 119 controls the switch circuit 120 to disconnect, so that the first power conversion circuit 118 cannot output electrical energy to the controller 103, and the controller 103 will not power on and start running.

[0095] Step S31: At time T2, after the charging capacitor C1 of the delay circuit 114 at the clear terminal 117 of the signal flip-flop 113 is fully charged (as Figure 3 shown, the parameter is designed with a delay of 90 ms), since the input signal at the transceiver power supply terminal 111 of the signal transceiver 109 is not at the rising edge, the output of the interrupt signal output terminal 112 of the signal transceiver 109 remains the previous level and is still high, that is, the trigger signal input terminal 115 of the signal flip-flop 113 inputs a high level (H, as shown in Table 2), the D pin of the signal flip-flop 113 is high level (H, as shown in Table 2), the / PRE pin of the signal flip-flop 113 is high level (H, as shown in Table 2), and after the charging capacitor C1 is fully charged, it is high level. Therefore, the clear terminal 117 of the signal flip-flop 113 is high level (H, as shown in Table 2).

[0096] Referring to the truth table of the signal flip-flop 113 (as shown in Table 1), it can be seen that the signal flip-flop 113 maintains the previous state, the output does not change, and it is still the level state during the period from T1 to T2. The electrical signal of the bus signal enable terminal 106 is still low level (L, as shown in Table 2). At this time, when there is no hardwired signal at the hardwired signal enable terminal 105, the second power conversion circuit 119 controls the switch circuit 120 to disconnect, so that the first power conversion circuit 118 cannot output electrical energy to the controller 103, and the controller 103 will not power on and start running.

[0097] Step S32: At time T3, since the power supply circuit 102 does not output, the VCC pin and VIO pin of the signal transceiver 109 are not powered on. According to the attributes of the signal transceiver 109, within a set time period (for example, 200 ms), the signal transceiver 109 will switch from the standby mode to the sleep mode. At this time, the interrupt signal output terminal 112 of the signal transceiver 109 becomes low level, the trigger signal input terminal 115 of the signal flip-flop 113 inputs low (L, as shown in Table 2), the D pin of the signal flip-flop 113 is high level (H, as shown in Table 2), the / PRE pin of the signal flip-flop 113 is high level (H, as shown in Table 2), and the clear terminal 117 of the signal flip-flop 113 is still high level (H, as shown in Table 2).

[0098] Combined with the truth table of the signal trigger 113 (as shown in Table 1), it can be seen that at this time, the trigger enable signal output terminal 116 of the signal trigger 113 outputs Q0, and Q0 represents the level signal maintaining the previous state (during the time period from T2 to T3), that is, the trigger enable signal output terminal 116 of the signal trigger 113 still outputs a low level (L, as shown in Table 2), that is, the electrical signal of the bus signal enable terminal 106 is still a low level (L, as shown in Table 2). At this time, when there is no hardwired signal at the hardwired signal enable terminal 105, the second power conversion circuit 119 controls the switch circuit 120 to disconnect, so that the first power conversion circuit 118 cannot output electrical energy to the controller 103, and the controller 103 will not power on and start running.

[0099] In the above steps S30 to S32, at time T1, the power control circuit 10 is connected to the power supply 20 (vehicle-mounted battery), and the signal output from the interrupt signal output terminal 112 of the signal transceiver 109 changes from low level to high level. Then, when there is no bus wake-up signal and hardwired signal, the enable signal output terminal 116 of the signal trigger 113 outputs a non-enable signal, and the device is in the sleep mode.

[0100] Further, in step S33, during the sleep process of the device, the controller 103 can detect in real time or periodically whether there is an external wake-up signal. For example, a network wake-up signal or a hardwired signal. If there is no wake-up signal, the device continues to be in the sleep mode. If there is one of the wake-up signals, the power control circuit 10 enters time T4.

[0101] Combined with Figures 1 to 4 As shown, during the time period from T4 to T7, the hardwired signal enable terminal 105 of the power supply circuit 102 receives an external wake-up signal for waking up. For example, it can be a hardwired signal or a bus wake-up signal. When the hardwired signal enable terminal 105 of the power supply circuit 102 receives a hardwired signal or the bus signal enable terminal 106 receives an enable signal, the voltage of the power supply 20 is converted to supply power to the controller 103, so that the controller 103 powers on and starts. The specific process includes steps S34 to S38. Specifically as follows:

[0102] Step S34, in some embodiments, at time T4, when the bus connection terminal 107 of the signal transceiver 109 receives a bus wake-up signal input from the network bus 30, the signal input to the transceiver power supply terminal 111 of the signal transceiver 109 is a rising edge, that is, the signal input to the trigger signal input terminal 115 of the signal trigger 113 is a rising edge (↑, as shown in Table 2), the D pin of the signal trigger 113 is at a high level (H, as shown in Table 2), the / PRE pin of the signal trigger 113 is at a high level (H, as shown in Table 2), and the clear terminal 117 is still at a high level (H, as shown in Table 2).

[0103] Combined with the truth table of the signal trigger 113 (as shown in Table 1), it can be seen that at this time, the enable signal output terminal 116 of the signal trigger 113 outputs a high level (H, as shown in Table 2). Since the signal input at the transceiver power supply terminal 111 of the signal transceiver 109 is a rising edge (↑, as shown in Table 2), the interrupt signal output terminal 112 of the signal transceiver 109 is triggered at the rising edge and switches from a low level (L) to a high level (H), that is, the electrical signal at the bus signal enable terminal 106 is still a high level (H, as shown in Table 2). At this time, the second power conversion circuit 119 is enabled to control the switch circuit 120 to conduct, so that the first power conversion circuit 118 outputs a voltage to supply power to the controller 103. The second power conversion circuit 119 converts the 12V voltage and outputs 5V voltage to power on the VCC terminal and VIO terminal of the signal transceiver 109. The first power conversion circuit 118 converts the 12V voltage and outputs 3.3V to power on the controller 103. The controller 103 powers on and works. The controller 103 outputs a signal to pull up the MCU_HOLD signal and outputs a latch signal to enable and self-lock the second power conversion circuit 119. At the same time, the controller 103 controls the power-on of other modules to complete, and the device starts to run.

[0104] In some embodiments, when the hard-wired signal enable terminal 105 of the power supply circuit 102 receives a hard-wired signal, the input of the hard-wired signal enable terminal 105 is a high level. The second power conversion circuit 119 is enabled to control the switch circuit 120 to conduct, so that the first power conversion circuit 118 outputs a voltage to supply power to the controller 103. The second power conversion circuit 119 converts the 12V voltage and outputs 5V voltage to power on the VCC terminal and VIO terminal of the signal transceiver 109. The first power conversion circuit 118 converts the 12V voltage and outputs 3.3V to power on the controller 103. The controller 103 powers on and works. The controller 103 outputs a signal to pull up the MCU_HOLD signal and enables and self-locks the second power conversion circuit 119. At the same time, the controller 103 controls the power-on of other modules to complete, and the device starts to run.

[0105] Further, in step S35, during the operation of the device, the controller 103 can detect in real time or periodically whether there is an external sleep signal, for example, a network sleep signal or a hard-wired sleep signal. If there is no sleep signal, the device continues to operate. If there is one of the sleep signals, the power control circuit 10 enters the T5 moment.

[0106] Step S36: At time T5, the power control circuit 10 prepares to enter the sleep mode. When the controller 103 detects that there is no hard-wired signal and no bus wake-up signal externally, it causes the power control circuit 10 to prepare to enter the sleep mode. During the preparation for sleep, the controller 103 first controls the signal transceiver 109 to enter the sleep mode, causing the interrupt signal output terminal 112 of the signal transceiver 109 to output a low level, that is, the trigger signal input terminal 115 of the signal flip-flop 113 inputs a low level (L, as shown in Table 2), the D pin of the signal flip-flop 113 is at a high level (H, as shown in Table 2), the / PRE pin of the signal flip-flop 113 is at a high level (H, as shown in Table 2), and the clear terminal 117 of the signal flip-flop 113 remains at a high level (H, as shown in Table 2).

[0107] Combined with the truth table of the signal flip-flop 113 (as shown in Table 1), it can be seen that at this time, the trigger enable signal output terminal 116 of the signal flip-flop 113 outputs Q0, and Q0 represents a level signal that maintains the previous state, that is, the trigger enable signal output terminal 116 of the signal flip-flop 113 still outputs a high level (H, as shown in Table 2), that is, the electrical signal of the bus signal enable terminal 106 is still at a high level (H, as shown in Table 2). The controller 103 remains powered on and running, and the device remains running.

[0108] Step S37: At time T6, the power control circuit 10 enters the sleep mode. The controller 103 controls the output of the MCU_HOLD signal and pulls down the MCU_HOLD signal. At the same time, the controller 103 controls the output of the MCU_Clear signal to perform a clear operation on the clear terminal 117 of the signal flip-flop 113. The capacitance C1 of the charging capacitor at the clear terminal 117 of the signal flip-flop 113 is discharged to the ground through the reset switch Q1, and the level of the clear terminal 117 of the signal flip-flop 113 becomes a low level (L, as shown in Table 2). Since the signal transceiver 109 has already entered the sleep mode, the trigger signal input terminal 115 of the signal flip-flop 113 is at a low level (L, as shown in Table 2), and the D pin of the signal flip-flop 113 is at a high level (H, as shown in Table 2).

[0109] Combined with the truth table of the signal trigger 113 (as shown in Table 1), it can be seen that at this time, the trigger enable signal output terminal 116 of the signal trigger 113 outputs a low level (L, as shown in Table 2), that is, the electrical signal output of the bus signal enable terminal 106 is a low level (L, as shown in Table 2). The second power conversion circuit 119 is disabled and powered off, the controller 103 is powered off, and the power control circuit 10 enters the sleep mode. From time T5 to time T6, the power control circuit 10 switches from preparing to sleep to the fully sleep mode. In the fully sleep mode, the controller 103 needs to pull down both the MCU_HOLD signal and the MCU_Clear signal simultaneously. Or, first pull down the MCU_Clear signal, and then pull down the MCU_HOLD signal. With such settings, it is ensured that the in-vehicle electronic device fully enters the sleep mode and the power consumption is reduced.

[0110] Step S38: At time T7, the power control circuit 10 is in the sleep mode, and the charging capacitor C1 starts to charge. After the charging capacitor C1 is fully charged, the level state of the clear terminal 117 of the signal trigger 113 becomes a high level (H, as shown in Table 2). At this time, the input of the trigger signal input terminal 115 of the signal trigger 113 is still a low level (L, as shown in Table 2), the / PRE pin of the signal trigger 113 is a high level (H, as shown in Table 2), and the D pin of the signal trigger 113 is a high level (H, as shown in Table 2).

[0111] Combined with the truth table of the signal trigger 113 (as shown in Table 1), it can be seen that the enable signal output terminal 116 of the signal trigger 113 outputs Q0, and Q0 represents the level signal maintaining the previous state, that is, the trigger enable signal output terminal 116 of the signal trigger 113 still outputs a low level (L, as shown in Table 2), that is, the electrical signal of the bus signal enable terminal 106 is still a low level (L, as shown in Table 2). The controller 103 is still in the sleep mode, and the device is still in the sleep mode.

[0112] Similarly, time T8 is the process when the in-vehicle electronic device is awakened again by the wake-up source. The timing logic at time T8 is the same as that at time T4, and the signal states at time T8 are the same as those at time T4. Refer to the description at time T4 above and will not be elaborated here.

[0113] In the above solution, when the power control circuit 10 enters the sleep mode, the controller 103 and other modules all adopt the power-off scheme. In the sleep mode, the signal transceiver 109 is only electrically connected to the power supply through the power interface 101, and the power supply supplies power to the signal transceiver 109. The signal transceiver 109 is in the sleep mode, and the maximum current of the power supply in the sleep mode is 30 uA. The power supply circuit 102 outputs constant power. The power supply circuit 102 selects a linear voltage regulator with an ultra-low power supply current, and the power supply current is 2.2 uA. The signal trigger 113 selects a low-power single-channel positive-edge-triggered D-type flip-flop, and the maximum current of the signal trigger 113 is 0.9 uA. In the sleep mode of the device, powered by the 12V power supply of the vehicle battery, the device can meet the total static current of less than 100 uA, and the power consumption is low.

[0114] Table 1: Truth table of the signal trigger 113

[0115]

[0116] In Table 1, "X" indicates that the level is not restricted and can be either a high level or a low level.

[0117] Table 2: Signal states of the signal trigger 113 at various times

[0118] Moment / PRE / CLR CLK D Q EN T1 H L ↑ H L L T2 H H H H L L T3 H H L H L L T4 H H ↑ H H H T5 H H L H H H T6 H L L H L L T7 H H L H L L T8 H H ↑ H H H

[0119] It should be noted that the signal trigger 113 in this embodiment can be a D-type flip-flop. The D-type flip-flop has a memory function and is an information storage device with two stable states, and is triggered by the rising edge. When the clear terminal 117 ( / CLR) is at a low level (L), the enable signal output terminal 116 (Q) outputs a low level (L). With such a setting, using this characteristic, within the initial set duration when the power supply 20 is connected to the power interface 101 and no hard-wired signal is received, the controller 103 is prevented from being activated, so that the controller 103 does not power on and start when it does not need to start, reducing power consumption.

[0120] This application also provides a vehicle-mounted electronic device, including Figures 1 to 3 the power control circuit 10 shown in the embodiment. The vehicle-mounted electronic device can support the sleep wake-up function of the bus wake-up signal and the hard-wired signal, and can also meet the requirement that the static current of the vehicle-mounted electronic device is less than 100 uA under 12V power supply, and can achieve low power consumption. At the same time, when the vehicle-mounted electronic device is first connected to the vehicle battery, without the bus wake-up signal and the hard-wired signal, the controller will not start randomly and can be powered on normally.

[0121] This application also provides a power control method for a vehicle-mounted electronic device, which is applied to the Figures 1 to 4 power control circuit 10 of the vehicle-mounted electronic device shown in the above Figure 5In the illustrated embodiment, the power control method includes steps S10 to S20. Among them,

[0122] Step S10: Within the initial set duration when the power supply interface 101 is connected to the power supply 20, if the bus wake-up signal from the network bus 30 is not received, the sleep wake-up circuit 104 generates a disenable signal.

[0123] Step S20: If the power supply circuit 102 does not receive the hard-wired signal and receives the disenable signal, the power supply circuit 102 does not output electrical energy to the controller 103, so that the controller 103 does not power on and start.

[0124] Combined with Figures 2 to 5 As shown, in this embodiment, the disenable signal controls the power supply circuit 102 to be disenabled, the power supply circuit 102 is not woken up, and does not supply power to the controller 103. The power supply circuit 102 is used to not output electrical energy to the controller 103 when the hard-wired signal enable terminal 105 does not receive the hard-wired signal and the bus signal enable terminal 106 receives the disenable signal, so that the controller 103 does not power on and start.

[0125] In the related art, at the moment of connecting to the power supply, the voltage changes, causing the sleep wake-up circuit 104 to be powered on and output an enable signal (such as a high level), enabling the power supply circuit 102, and the controller 103 powers on and starts. At this time, even if no external wake-up signal is received, the controller 103 still powers on and starts.

[0126] In this application, within the initial set duration when the power supply interface 101 is connected to the power supply 20 and the bus wake-up signal is not received, the sleep wake-up circuit 104 generates a disenable signal, and if the power supply circuit 102 also does not receive the hard-wired signal, the power supply circuit 102 is disenabled, so that the controller 103 does not power on and is not activated, making the controller 103 not power on and start when the power control circuit 10 is powered on (when connecting to the power supply), thereby reducing power consumption and reducing the power consumption of the vehicle-mounted battery. After the initial set duration, if the bus wake-up signal is not received, the sleep wake-up circuit 104 can enter the sleep state until the bus wake-up signal is received. Within the initial set duration, if the bus wake-up signal and / or the hard-wired signal is received, the power supply circuit 102 is enabled and activated, and the controller 103 starts.

[0127] In Figure 6 the illustrated embodiment, step S10 includes steps S101 to S102. Among them,

[0128] Step S101: Within the initial set duration when the power supply interface 101 is connected to the power supply 20, if the bus wake-up signal is not received, the signal transceiver 109 generates a first signal.

[0129] Step S102: The signal trigger circuit 110 generates a disenable signal in response to the first signal.

[0130] Combined Figures 2 to 6 As shown, in this embodiment, the initial set duration includes the moment when the transceiver power supply terminal 111 of the signal transceiver 109 disconnects from the power supply 20 and then accesses the power supply 20 through the power interface 101. During this initial set duration, the output terminal of the signal transceiver 109 continuously outputs the first signal. In some embodiments, the first signal output when the transceiver power supply terminal 111 of the signal transceiver 109 disconnects from the power supply 20 and then accesses the power supply 20 through the power interface 101 is a high level. The signal trigger circuit 110 is used to generate a disenable signal when receiving the first signal (high level). In some embodiments, this disenable signal is a low level signal, which controls the power supply circuit 102 to be disenabled. The enable signal is a high level. The power supply circuit 102 is used to not output electrical energy to the controller 103 when the hard wire signal enable terminal 105 does not receive a hard wire signal and the bus signal enable terminal 106 receives a disenable signal, so that the controller 103 does not power on and start up.

[0131] In this embodiment, the signal transceiver 109 is a positive edge trigger. When the transceiver power supply terminal 111 of the signal transceiver 109 disconnects from the power supply 20 and then accesses the power supply 20 through the power interface 101, the signal transceiver 109 is in the standby mode. In the standby mode, the first signal output by the signal transceiver 109 is a trigger signal and is a high level. If the output terminal of the signal transceiver 109 is directly electrically connected to the power supply circuit 102, at the moment when the transceiver power supply terminal 111 of the signal transceiver 109 accesses the power supply 20, the first signal will be output, which will wake up the power supply circuit 102 and cause the controller 103 to power on and start up. However, at this time, without an external wake-up signal and without the need for the controller 103 to start, the power-on startup of the controller 103 will cause power consumption.

[0132] Therefore, in this application, to avoid the situation where the controller 103 is directly woken up by the signal transceiver 109 that powers on without an external wake-up signal, causing unnecessary power-on startup of the controller 103, by setting the signal trigger circuit 110 between the signal transceiver 109 and the power supply circuit 102, within the set duration, the signal trigger circuit 110 outputs a disenable signal according to the first signal output by the signal transceiver 109, so that the power supply circuit 102 cannot be woken up, the controller 103 does not power on, avoiding the controller 103 being activated when it does not need to be activated, and making the controller 103 not power on and start up when it does not need to start, reducing power consumption.

[0133] In some embodiments, in step S102, within the delay duration starting from the initial moment when the signal trigger 113 receives the first signal, the delay circuit 114 provides a reset voltage to the clear terminal 117, causing the signal trigger 113 to generate a disenable signal.

[0134] In this embodiment, the signal trigger 113 is triggered when a signal change (such as a rising edge) is received at the trigger signal input terminal 115. If the reset terminal 117 does not receive a reset voltage (low level), the signal trigger 113 will output an enable signal (high level). At the moment of the signal change at the trigger signal input terminal 115 of the signal trigger 113, a reset voltage (low level) is provided to the reset terminal 117 through the delay circuit 114, and the signal trigger 113 is not triggered and outputs a non-enable signal (low level). After the delay duration, a voltage corresponding to the level opposite to the reset voltage (high level) is provided to the reset terminal 117. Since the moment of the signal change received at the trigger signal input terminal 115 has passed (the rising edge moment has passed) and the signal is a stable level, the signal trigger 113 is not triggered and continues to output a non-enable signal. The delay circuit 114 delays the voltage output by the power supply circuit 102 and provides it to the zero-crossing terminal 117.

[0135] In this embodiment, the delay circuit 114 is configured to provide a reset voltage to the reset terminal 117 within 90 ms starting from the initial moment when the first signal is received. This reset voltage is a low level. When the delay circuit 114 provides a low level to the reset terminal 117, a non-enable signal is generated at the enable signal output terminal 116 of the signal trigger 113. This non-enable signal is a low level signal, and the low level signal cannot enable the wake-up power supply circuit 102 and cannot supply power to the controller 103. Therefore, when the power supply circuit 102 does not receive a hard-wired signal and receives a non-enable signal, the wake-up power supply circuit 102 cannot be enabled and cannot supply power to the controller 103. With such a setting, within 90 ms after the power supply interface 101 is connected to the power supply 20 and no hard-wired signal is received, it is avoided that the controller 103 is activated when it does not need to be activated, so that the controller 103 does not power on and start when it does not need to start, reducing power consumption.

[0136] In Figure 7 the embodiment shown, the power control method further includes steps S11 to S12. Among them,

[0137] Step S11: After the initial set duration when the power supply interface 101 is connected to the power supply 20, if a bus wake-up signal is received, the sleep wake-up circuit 104 generates an enable signal.

[0138] Step S21: If the power supply circuit 102 receives a hard-wired signal and / or an enable signal, the voltage of the power supply 20 is converted to supply power to the controller 103, enabling the controller 103 to power on and start.

[0139] Combined with Figures 2 to 7As shown, in this embodiment, the signal transceiver 109 is configured to generate a second signal at the interrupt signal output terminal 112 of the signal transceiver 109 when the bus connection terminal 107 receives a bus wake-up signal after an initial set duration when the power supply interface 101 is connected to the power supply 20. This second signal can be a high-level signal. The signal trigger circuit 110 is configured to generate an enable signal when receiving the second signal (high level). The power supply circuit 102 is configured to output electrical energy to the controller 103 when the hard wire signal enable terminal 105 receives a hard wire signal and / or the bus signal enable terminal 106 receives an enable signal, so that the controller 103 is powered on and starts. With such a setting, it can be ensured that after the initial set duration, the external wake-up signal can wake up the controller 103 and make the controller 103 work, ensuring that the controller 103 is normally woken up when it needs to work.

[0140] In Figure 8 the embodiment shown, the power supply control method further includes steps S12 to S22. Among them,

[0141] Step S12: After the controller 103 is powered on and starts, detect the bus wake-up signal and the hard wire signal.

[0142] Step S22: If the bus wake-up signal and the hard wire signal are not detected, the controller 103 controls the signal transceiver 109 to enter the sleep mode.

[0143] Combined with Figures 2 to 8 As shown, in this embodiment, after the controller 103 is powered on and starts, it can detect the electrical signals of the bus connection terminal 107 and the hard wire signal enable terminal 105 in real time or periodically. If it is detected that there is no bus wake-up signal at the bus connection terminal 107 and no hard wire signal at the hard wire signal enable terminal 105, it means that there is no external wake-up requirement. At this time, the signal transceiver 109 can be controlled to enter the sleep mode. If it is detected that there is a bus wake-up signal at the bus connection terminal 107 and / or a hard wire signal at the hard wire signal enable terminal 105, it means that there is an external wake-up requirement. At this time, the signal transceiver 109 is controlled to enter the working mode. In this way, the power consumption is reduced and the service life of the signal transceiver 109 is extended.

[0144] In Figure 8 the embodiment shown, the power supply control method further includes step S32. Step S32 is executed after step S22. Among them,

[0145] Step S32: When the signal transceiver 109 is in the sleep mode, the controller 103 controls the clearing circuit 121 to make the voltage at the clearing terminal 117 the reset voltage, so that the signal trigger 113 generates a disenable signal.

[0146] Combined with Figures 2 to 8As shown, in this embodiment, when the signal transceiver 109 is in the sleep mode, the clearing circuit 121 can be controlled to make the voltage at the clearing terminal 117 the reset voltage. This reset voltage is a low level, and this low level can cause the enable signal output terminal 116 to generate a non-enable signal. When the controller 103 detects that there is no bus wake-up signal at the bus connection terminal 107 and there is no hard-wired signal at the hard-wired signal enable terminal 105, it controls the signal transceiver 109 to enter the sleep mode, and controls the clearing circuit 121 to make the voltage at the clearing terminal 117 the reset voltage, causing the signal flip-flop 113 to generate a non-enable signal, thereby controlling the power supply circuit 102 not to be enabled and stopping power supply to the controller 103. In this way, the controller 103 is in the sleep mode, reducing power consumption.

[0147] In Figure 8 the embodiment shown, in step S12, after the controller 103 is powered on and starts up, it outputs a latch signal to the power supply circuit 102 to make the power supply circuit 102 continuously supply power to the controller 103. Combining Figures 2 to 8 As shown, in this embodiment, after the controller 103 is powered on and starts up, it outputs a latch signal to the power supply circuit 102 to ensure that the power supply circuit 102 is always enabled and is not affected by the signals at the hard-wired signal enable terminal 105 and the bus signal enable terminal 106, making the power supply circuit 102 continuously supply power to the controller 103. With such a setting, the voltage of the power supply circuit 102 can be self-locked to ensure a constant output of electrical energy to the controller 103.

[0148] In Figure 8 the embodiment shown, in step S32, when the signal transceiver 109 is in the sleep mode, the controller 103 outputs a non-latch signal to the power supply circuit 102, and controls the clearing circuit 121 to make the voltage at the clearing terminal 117 the reset voltage, so that the power supply circuit 102 does not supply power to the controller 103. Combining Figures 2 to 8 As shown, in this embodiment, the level of the non-latch signal is opposite to the level of the latch signal. When not latched, the hard-wired signal at the hard-wired signal enable terminal 105 and the signal at the bus signal enable terminal 106 can control the second power conversion circuit 119. Therefore, the non-enable signal output by the signal trigger circuit 110 can control the second power conversion circuit 119 not to be enabled. With such a setting, when the signal transceiver 109 is in the sleep mode, the power supply circuit 102 does not supply power to the controller, and the controller 103 is also in the sleep mode. Power consumption can be reduced and the service life of the controller 103 can be extended.

[0149] Other embodiments of the present application will be readily apparent to those skilled in the art upon consideration of the specification and practice of the application disclosed herein. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include known common knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present application are pointed out by the following claims.

[0150] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A power control circuit for a vehicle-mounted electronic device, characterized in that, Comprising: A power interface for electrically connecting to a power source; A power circuit electrically connected to the power interface for converting the voltage of the power source; The power circuit includes a hard-wired signal enable terminal and a bus signal enable terminal. The hard-wired signal enable terminal is used to receive a hard-wired signal, and the hard-wired signal is used to wake up the power circuit; A controller electrically connected to the power circuit; And A sleep wake-up circuit electrically connected to the power interface and the bus signal enable terminal, and includes a bus connection terminal. The bus connection terminal is used to connect to a network bus to receive a bus wake-up signal input by the network bus, and the bus wake-up signal is used to wake up the power circuit; The sleep wake-up circuit is used to generate a disenable signal when the bus connection terminal does not receive the bus wake-up signal within an initial set duration after the power interface accesses the power source. The power circuit is used to not output electrical energy to the controller and prevent the controller from powering on and starting when the hard-wired signal enable terminal does not receive the hard-wired signal and the bus signal enable terminal receives the disenable signal; Wherein, the sleep wake-up circuit includes a signal transceiver and a signal trigger circuit. The signal transceiver includes a transceiver power supply terminal and the bus connection terminal, and the transceiver power supply terminal is electrically connected to the power interface. The signal trigger circuit is electrically connected between the signal transceiver and the bus signal enable terminal; The signal transceiver is used to generate a first signal when the power interface accesses the power source within an initial set duration and the bus connection terminal does not receive the bus wake-up signal. The signal trigger circuit is used to generate the disenable signal when receiving the first signal. The power circuit is used to not output electrical energy to the controller and prevent the controller from powering on and starting when the hard-wired signal enable terminal does not receive the hard-wired signal and the bus signal enable terminal receives the disenable signal.

2. The power control circuit according to claim 1, wherein The signal trigger circuit includes a signal trigger and a delay circuit. The signal trigger includes a trigger signal input terminal, an enable signal output terminal, and a clear terminal. The trigger signal input terminal is electrically connected to the interrupt signal output terminal of the signal transceiver. The enable signal output terminal is electrically connected to the bus signal enable terminal. The clear terminal is electrically connected to the delay circuit. The delay circuit is electrically connected to the output terminal of the power circuit. The power circuit is used to supply power to the delay circuit, and the delay circuit is used to provide a voltage to the clear terminal; The delay circuit is used to provide a reset voltage to the clear terminal within a delay duration starting from the initial moment of receiving the first signal, so that the enable signal output terminal generates the disenable signal.

3. The power control circuit according to claim 2, wherein The delay circuit includes a pull-up resistor and a charging capacitor connected in series between the output terminal of the power circuit and the ground terminal. The charging capacitor is electrically connected between the pull-up resistor and the ground terminal. The clear terminal is electrically connected between the pull-up resistor and the charging capacitor.

4. The power control circuit according to claim 2, wherein The sleep wake-up circuit is used to generate an enable signal when the bus connection terminal receives the bus wake-up signal after an initial set duration when the power supply interface accesses the power supply; the power supply circuit is used to convert the voltage of the power supply when the hard wire signal enable terminal receives the hard wire signal and / or the bus signal enable terminal receives the enable signal, and supply power to the controller to power on and start the controller.

5. The power control circuit according to claim 4, characterized in that The controller is electrically connected to the bus connection terminal and the hard wire signal enable terminal, and is also electrically connected to the signal transceiver; After powering on and starting, the controller is used to detect the electrical signals of the bus connection terminal and the hard wire signal enable terminal, and when it detects that there is no bus wake-up signal at the bus connection terminal and no hard wire signal at the hard wire signal enable terminal, it controls the signal transceiver to enter the sleep mode.

6. The power control circuit according to claim 5, wherein The signal trigger circuit further includes a clearing circuit, and the clearing circuit is electrically connected between the clearing terminal and the controller; When the signal transceiver is in the sleep mode, the controller is used to control the clearing circuit to make the voltage of the clearing terminal the reset voltage, so that the enable signal output terminal of the signal trigger generates the non-enable signal.

7. The power control circuit according to claim 6, wherein The controller is electrically connected to the power supply circuit; after powering on and starting, the controller is used to output a latch signal to the power supply circuit to make the power supply circuit continuously supply power to the controller; and when the signal transceiver is in the sleep mode, it is used to output a non-latch signal to the power supply circuit and control the clearing circuit to make the voltage of the clearing terminal the reset voltage, so that the power supply circuit does not supply power to the controller.

8. The power control circuit according to claim 7, wherein The clearing circuit includes a reset switch, the reset switch is electrically connected between the ground terminal and the clearing terminal, and the controller is electrically connected to the reset switch to control the on / off of the reset switch. When the reset switch is controlled to conduct, the voltage of the clearing terminal is the reset voltage.

9. The power control circuit according to claim 1, wherein The power supply circuit includes a first power conversion circuit, a second power conversion circuit and a switch circuit. The first power conversion circuit is electrically connected to the power supply interface and is electrically connected to the controller through the switch circuit. The first power conversion circuit is used to convert the voltage of the power supply; The second power conversion circuit is electrically connected to the hard wire signal enable terminal, is electrically connected to the sleep wake-up circuit through the bus signal enable terminal, and is also electrically connected to the power supply interface and the switch circuit; When the bus signal enable terminal receives the non-enable signal and the hard wire signal enable terminal does not receive the hard wire signal, the second power conversion circuit is in a non-enabled state, causing the switch circuit to disconnect; and when the hard wire signal enable terminal receives the hard wire signal and / or the bus signal enable terminal receives the enable signal output by the sleep wake-up circuit, it is in an enabled state, converts the voltage of the power supply, controls the switch circuit to conduct, and enables the first power conversion circuit to supply power to the controller through the switch circuit.

10. An in-vehicle electronic device, characterized in that, Comprising: The power supply control circuit according to any one of claims 1 to 9.

11. A power control method for an in-vehicle electronic device, characterized in that, A power control circuit applied to an in-vehicle electronic device as described in any one of claims 1 to 9, the power control circuit comprising a power interface, a power circuit, a controller and a sleep / wake-up circuit, the power circuit being electrically connected to the power interface; the controller being electrically connected to the power circuit; The sleep / wake-up circuit, being electrically connected to the power interface and the power circuit, and being connected to a network bus; The power control method includes: Within an initial set duration when power is connected to the power interface, if a bus wake-up signal from the network bus is not received, the sleep / wake-up circuit generates a disenable signal; If the power circuit does not receive a hardwire signal and receives the disenable signal, the power circuit does not output electrical energy to the controller, causing the controller not to power on and start.

Images