Array substrate, display panel and method for manufacturing array substrate

Abstract

The present application provides an array substrate, a display panel and a method for manufacturing the array substrate, comprising a substrate, a thin film transistor layer, a passivation layer, a pixel electrode layer and a color filter layer which are sequentially stacked; the thin film transistor layer comprises at least one thin film transistor, and the thin film transistor comprises a first conductive layer; the passivation layer comprises a thin film transistor region corresponding to the thin film transistor, and a first through hole and a second through hole are arranged in the thin film transistor region; the pixel electrode layer comprises a pixel electrode, an opening is arranged on the color filter layer, the first through hole corresponds to the opening, the second through hole is staggered with the opening, and the pixel electrode passes through the first through hole and the second through hole to connect with the first conductive layer respectively. By arranging the first through hole and the second through hole on the passivation layer, and connecting the pixel electrode to the first conductive layer through the two through holes, the electrical connection between the pixel electrode and the first conductive layer is ensured, and the grayscale dark spot problem caused by the breakage of the pixel electrode at the connection with the first conductive layer is avoided.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel, and a method for preparing the array substrate. Background Art

[0002] Thin Film Transistor (TFT) liquid crystal display panels have the advantages of small size and high contrast, and their applications are becoming more and more widespread. The pixel electrode layer in the TFT liquid crystal display panel is made of indium tin oxide (ITO) thin film, and the ITO thin film is connected to the metal electrode layer in the TFT liquid crystal display panel through vias. However, in existing TFT liquid crystal display panels, the ITO thin film is prone to breakage or poor film quality at the via connection with the metal electrode layer, resulting in poor overlap between the pixel electrode layer and the metal electrode layer, resulting in grayscale dark spots on the display panel, affecting the quality of the display panel. Summary of the invention

[0003] The present application provides an array substrate, a display panel and a method for preparing the array substrate, aiming to solve the problem of grayscale dark spots easily appearing in existing TFT liquid crystal display panels.

[0004] The present application provides an array substrate, comprising:

[0005] substrate;

[0006] A thin film transistor layer, disposed on the substrate, the thin film transistor layer includes a thin film transistor component, the thin film transistor component includes at least one thin film transistor, and the thin film transistor is electrically connected to the first conductive layer;

[0007] A passivation layer is provided on the thin film transistor layer, wherein the passivation layer includes a thin film transistor region corresponding to the thin film transistor, the thin film transistor region includes a first sub-region and a second sub-region, and the passivation layer is provided with a first through hole and a second through hole in the thin film transistor region;

[0008] a pixel electrode layer, disposed on the passivation layer, the pixel electrode layer comprising a pixel electrode, the pixel electrode comprising a first sub-pixel electrode and a second sub-pixel electrode, the pixel electrode respectively passing through the first through hole and the second through hole to be connected to the first conductive layer;

[0009] The passivation layer is provided with the first through hole and the second through hole in the first sub-region, and the first sub-pixel electrode is connected to the first conductive layer through the first through hole and the second through hole in the first sub-region respectively; and / or,

[0010] The passivation layer is provided with the first through hole and the second through hole in the second sub-region, and the second sub-pixel electrode is connected to the first conductive layer through the first through hole and the second through hole in the second sub-region respectively.

[0011] Optionally, in some embodiments provided in the present application, the thin film transistor component includes a first thin film transistor, the first thin film transistor corresponds to the first sub-region, the pixel electrode layer includes a plurality of first conductive lines electrically connected to the first sub-pixel electrode, and the first sub-pixel electrode is connected to the first conductive layer of the first thin film transistor through at least two of the first conductive lines.

[0012] Optionally, in some embodiments provided in the present application, the thin film transistor component also includes a second thin film transistor, the second thin film transistor corresponds to the second sub-region, the pixel electrode layer includes a plurality of second conductive lines electrically connected to the second sub-pixel electrode, and the second sub-pixel electrode is connected to the first conductive layer of the second thin film transistor through at least two of the second conductive lines.

[0013] Optionally, in some embodiments provided in the present application, the first thin film transistor and the second thin film transistor are further electrically connected to a second conductive layer, respectively, and the second conductive layer is located between the substrate and the first conductive layer;

[0014] The first conductive layer corresponding to the first thin film transistor includes a first electrode, and the second conductive layer corresponding to the first thin film transistor includes a second electrode. A first storage capacitor is formed between the first electrode and the second electrode. The first storage capacitor is located in the first sub-region and corresponds to the position of the first through hole.

[0015] Optionally, in some embodiments provided in the present application, the first conductive layer corresponding to the second thin film transistor includes a third electrode, the second conductive layer corresponding to the second thin film transistor includes a fourth electrode, a second storage capacitor is formed between the third electrode and the fourth electrode, and the second storage capacitor is located in the second sub-region and corresponds to the position of the first through hole.

[0016] Optionally, in some embodiments provided in the present application, the first conductive layer corresponding to the first thin film transistor further includes a first connecting line located in the first sub-region, one end of the first connecting line is electrically connected to the drain of the first thin film transistor, and the other end of the first connecting line passes through a first through hole and a second through hole in the first sub-region and is electrically connected to the first sub-pixel electrode;

[0017] The first conductive layer corresponding to the second thin film transistor also includes a second connecting line located in the second sub-region, one end of the second connecting line is electrically connected to the drain of the second thin film transistor, and the other end of the second connecting line passes through the first through hole and the second through hole in the second sub-region and is electrically connected to the second sub-pixel electrode.

[0018] Optionally, in some embodiments provided in the present application, the array substrate further includes a color filter layer disposed on the pixel electrode layer, the color filter layer is provided with an opening, the first through hole corresponds to the opening, and the second through hole is staggered with the opening.

[0019] Optionally, in some embodiments provided in the present application, the depth of the second through hole is less than or equal to the depth of the first through hole.

[0020] Correspondingly, an embodiment of the present application further provides a display panel, which includes the above-mentioned array substrate.

[0021] Accordingly, an embodiment of the present application further provides a method for manufacturing an array substrate, the method comprising the following steps:

[0022] providing a substrate;

[0023] Manufacturing a thin film transistor layer on the substrate, wherein the thin film transistor layer includes a thin film transistor, and the thin film transistor is electrically connected to the first conductive layer;

[0024] A passivation layer is formed on the thin film transistor layer, wherein the passivation layer includes a thin film transistor region corresponding to the thin film transistor, and the thin film transistor region includes a first sub-region and a second sub-region;

[0025] Opening a first through hole and a second through hole in the thin film transistor region of the passivation layer;

[0026] A pixel electrode layer is manufactured on the passivation layer, wherein the pixel electrode layer includes a pixel electrode, wherein the pixel electrode includes a first sub-pixel electrode and a second sub-pixel electrode, wherein the pixel electrode is electrically connected to the first conductive layer through the first through hole and the second through hole respectively, wherein the passivation layer is provided with the first through hole and the second through hole in the first sub-region, wherein the first sub-pixel electrode is connected to the first conductive layer through the first through hole and the second through hole in the first sub-region respectively; and / or wherein the passivation layer is provided with the first through hole and the second through hole in the second sub-region, wherein the second sub-pixel electrode is connected to the first conductive layer through the first through hole and the second through hole in the second sub-region respectively.

[0027] The array substrate provided by the present application includes a substrate, a thin film transistor layer, a passivation layer, a pixel electrode layer and a color filter layer which are stacked in sequence; the thin film transistor layer includes at least one thin film transistor, and the thin film transistor includes a first conductive layer; the passivation layer includes a thin film transistor area corresponding to the thin film transistor, and a first through hole and a second through hole are provided in the thin film transistor area; the pixel electrode layer includes a pixel electrode, and an opening is provided on the color filter layer, the first through hole corresponds to the opening, and the second through hole is staggered with the opening, and the pixel electrode passes through the first through hole and the second through hole to connect with the first conductive layer respectively. By providing the first through hole and the second through hole on the passivation layer, and connecting the pixel electrode to the first conductive layer through the two through holes, the electrical connection between the pixel electrode and the first conductive layer is ensured, and the grayscale dark spot problem caused by the break of the pixel electrode at the connection with the first conductive layer is avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0029] Figure 1 A schematic diagram of a first planar structure of an array substrate provided in an embodiment of the present application;

[0030] Figure 2 A schematic diagram of a second planar structure of an array substrate provided in an embodiment of the present application;

[0031] Figure 3 for Figure 2 Schematic diagram of the structure at the middle section A and section B;

[0032] Figure 4 A schematic diagram of a third planar structure of an array substrate provided in an embodiment of the present application;

[0033] Figure 5 for Figure 4 Schematic diagram of the structure at the middle section C;

[0034] Figure 6 for Figure 4 Schematic diagram of the structure at the middle section D;

[0035] Figure 7 for Figure 4 Schematic diagram of the structure at the middle section E;

[0036] Figure 8 A fourth planar structural schematic diagram of the array substrate provided in an embodiment of the present application;

[0037] Fig. 9 A schematic diagram of a method for manufacturing an array substrate provided in an embodiment of the present application;

[0038] Fig.10A schematic diagram of the structure of a display panel provided in an embodiment of the present application.

[0039]

[0040] DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words such as "upper" and "lower" used generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device.

[0042] The embodiments of the present application provide an array substrate, a display panel and a method for manufacturing the array substrate, which are described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

[0043] See also Figures 1 to 6 The array substrate 1 provided in the present application includes a substrate 10, a thin film transistor layer 11, a passivation layer 12, a pixel electrode layer 13 and a color filter layer 15 which are stacked in sequence; the thin film transistor layer 11 includes at least one thin film transistor, and the thin film transistor is electrically connected to the first conductive layer 141, such as Figure 3 As shown, the thin film transistor layer 11 includes a gate 1101 , a source 1103 , a drain 1102 , an active layer 1105 and a gate insulating layer 1104 , wherein the drain 1102 and the source 1103 of the thin film transistor are formed by patterning the first conductive layer 141 .

[0044] The passivation layer 12 includes a thin film transistor area 120 corresponding to the thin film transistor, and a first through hole 121 and a second through hole 122 are provided in the thin film transistor area 120; the pixel electrode layer 13 includes a pixel electrode 130, and an opening 150 is provided on the color filter layer 15, the first through hole 121 corresponds to the opening 150, and the second through hole 122 is staggered with the opening 150, and the pixel electrode 130 passes through the first through hole 121 and the second through hole 122 respectively to be connected to the first conductive layer 141.

[0045] By providing a first through hole 121 and a second through hole 122 on the passivation layer 12, and allowing the pixel electrode 130 to be connected to the first conductive layer 141 through the two through holes, the risk of poor connection with the first conductive layer 141 due to breakage of the pixel electrode 130 at the through hole when the pixel electrode 130 is connected to the first conductive layer 141 through only one through hole is reduced, thereby ensuring the electrical connection between the pixel electrode 130 and the first conductive layer 141 and avoiding the problem of grayscale dark spots.

[0046] In the embodiment of the present application, the material of the pixel electrode layer 13 is indium tin oxide (ITO), which ensures that it has good light transmittance and conductivity. The material of the first conductive layer 141 is a metal with good conductivity such as aluminum or copper.

[0047] In the second embodiment of the present application, Figure 1 As shown, the thin film transistor assembly 110 includes a first thin film transistor 111 and a second thin film transistor 112 , the pixel electrode 130 includes a first sub-pixel electrode 1301 and a second sub-pixel electrode 1302 , and the thin film transistor region 120 includes a first sub-region 1201 corresponding to the first thin film transistor 111 and a second sub-region 1202 corresponding to the second thin film transistor 112 .

[0048] By dividing the pixel electrode 130 into two independent first sub-pixel electrodes 1301 and second sub-pixel electrodes 1302 , the visual color shift or visual color difference phenomenon of the display panel under a wide viewing angle can be improved.

[0049] It should be noted that the first sub-pixel electrode 1301 or the second sub-pixel electrode 1302 can be connected to the first conductive layer 141 through the first through hole 121 and the second through hole 122 respectively, or the first sub-pixel electrode 1301 and the second sub-pixel electrode 1302 can be connected to the first conductive layer 141 through the first through hole 121 and the second through hole 122 respectively.

[0050] Preferably, in the embodiments provided in this application, Figures 4 to 7 The passivation layer 12 is provided with a first through hole 121 and a second through hole 122 in the first sub-region 1201, and the first sub-pixel electrode 1301 passes through the first through hole 121 and the second through hole 122 in the first sub-region 1201 to be connected to the first conductive layer 141 of the first thin film transistor 111 respectively; the passivation layer 12 is also provided with a first through hole 121 and a second through hole 122 in the second sub-region 1202, and the second sub-pixel electrode 1302 passes through the first through hole 121 and the second through hole 122 in the second sub-region 1202 to be connected to the first conductive layer 141 of the second thin film transistor 112.

[0051] By making the first sub-pixel electrode 1301 pass through the first through hole 121 and the second through hole 122 to connect with the first conductive layer 141 of the first thin film transistor 111, and making the second sub-pixel electrode 1302 pass through the first through hole 121 and the second through hole 122 to connect with the first conductive layer 141 of the second thin film transistor 112, when the pixel electrode 130 is divided into two independent first sub-pixel electrodes 1301 and second sub-pixel electrodes 1302, the electrical connection between the first sub-pixel electrode 1301 and the second sub-pixel electrode 1302 and the first conductive layer 141 can be ensured at the same time, thereby reducing the risk of grayscale dark spot problems.

[0052] In the embodiments provided in this application, Figure 1 , Figure 2 , Figure 3 and Figure 8 The first thin film transistor 111 and the second thin film transistor 112 are also electrically connected to the second conductive layer 142, respectively. The second conductive layer 142 is located between the substrate 10 and the first conductive layer 141. The second conductive layer 142 includes a scan line 1422, a gate 1101 of the first thin film transistor 111, a gate 1101 of the second thin film transistor 112, and a gate common electrode line 1421. The gate common electrode line 1421 includes a first gate common electrode line 1421a and a second gate common electrode line 1421b. The gate 1101 of the first thin film transistor 111, the gate 1101 of the second thin film transistor 112, and the gate common electrode line 1421 are formed by patterning the second conductive layer 142. Preferably, the material of the second conductive layer 142 is a metal with good electrical conductivity, such as aluminum or copper.

[0053] Combination Figure 1 , Figure 2 , Figure 4 and Figure 5 The first conductive layer 141 corresponding to the first thin film transistor 111 includes a drain 1102 and a first electrode 1411 electrically connected to each other, and the second conductive layer 142 corresponding to the first thin film transistor 111 includes a second electrode 1412. A first storage capacitor 1401 is formed between the first electrode 1411 and the second electrode 1412. The first storage capacitor 1401 is located in the first sub-region 1201 and corresponds to the position of the first through hole 121.

[0054] Preferably, in the embodiments of the present application, Figures 1 to 3, the drain electrode 1102 of the first thin film transistor 111 is arranged in the same layer as the first electrode 1411, that is, the first conductive layer 141 includes the drain electrode 1102 of the first thin film transistor 111 and the first electrode 1411, thereby simplifying the structure of the array substrate 1. In addition, the first conductive layer 141 also includes the data line 1416 and the source electrode 1103 of the first thin film transistor 111, and the data line 1416, the drain electrode 1102 and the source electrode 1103 of the first thin film transistor 111 are formed by patterning the first conductive layer 141.

[0055] Combination Figure 1 , Figure 4 , Figure 5 and Figure 6 , the first sub-pixel electrode 1301 passes through the first through hole 121 and the second through hole 122 in the first sub-region 1201 to be connected to the first conductive layer 141; in the first sub-region 1201, the first through hole 121 corresponds to the first storage capacitor 1401, and the second through hole 122 is located adjacent to the first storage capacitor 1401; at the second through hole 122, the first sub-pixel electrode 1301 transmits the electrical signal to the first conductive layer 141, and the first conductive layer 141 then transmits the electrical signal to the first storage capacitor 1401.

[0056] Since the first electrode 1411 of the first storage capacitor 1401 also belongs to the first conductive layer 141, the conduction of electrical signals in the same layer ensures the effectiveness of electrical signal conduction, avoiding the problem of poor grayscale dark spot display caused by the breakage of the first sub-pixel electrode 1301 at the first through hole 121 or poor film quality.

[0057] Combination Figure 1 , Figure 4 and Figure 7 The first conductive layer 141 corresponding to the second thin film transistor 112 includes a drain 1102 and a third electrode 1413 electrically connected to each other, and the second conductive layer 142 corresponding to the second thin film transistor 112 includes a fourth electrode 1414. A second storage capacitor 1402 is formed between the third electrode 1413 and the fourth electrode 1414. The second storage capacitor 1402 is located in the second sub-region 1202 and corresponds to the position of the first through hole 121.

[0058] Preferably, in the embodiments of the present application, Figure 1 , Figure 2 , Figure 3 and Figure 7, the drain electrode 1102 of the second thin film transistor 112 is arranged in the same layer as the first electrode 1411, that is, the first conductive layer 141 includes the drain electrode 1102 of the second thin film transistor 112 and the third electrode 1413, thereby simplifying the structure and manufacturing process of the array substrate 1. In addition, the first conductive layer 141 also includes the source electrode 1103 of the second thin film transistor 112, and the drain electrode 1102 and the source electrode 1103 of the second thin film transistor 112 are formed by patterning the first conductive layer 141.

[0059] Combination Figure 1 , Figure 4 and Figure 7 , the second sub-pixel electrode 1302 passes through the first through hole 121 and the second through hole 122 in the second sub-area 1202 to be connected to the first conductive layer 141; in the second sub-area 1202, the first through hole 121 corresponds to the second storage capacitor 1402, and the second through hole 122 is located adjacent to the second storage capacitor 1402; at the second through hole 122, the first sub-pixel electrode 1301 transmits the electrical signal to the first conductive layer 141, and the first conductive layer 141 then transmits the electrical signal to the second storage capacitor 1402.

[0060] Since the third electrode 1413 of the second storage capacitor 1402 also belongs to the first conductive layer 141, the conduction of electrical signals in the same layer ensures the effectiveness of electrical signal conduction, avoiding the problem of poor grayscale dark spot display caused by the breakage of the second sub-pixel electrode 1302 at the first through hole 121 or poor film quality.

[0061] To avoid the first conductive layer 141 from breaking, preferably, in the embodiment provided in the present application, the thickness of the first conductive layer 141 is greater than or equal to 430 nm.

[0062] In the embodiment provided in the present application, the first conductive layer 141 corresponding to the first thin film transistor 111 also includes a first connecting line 1415a located in the first sub-region 1201, one end of the first connecting line 1415a is electrically connected to the drain 1102 of the first thin film transistor 111, and the other end of the first connecting line 1415a passes through the first through hole 121 and the second through hole 122 in the first sub-region 1201 and is electrically connected to the first sub-pixel electrode 1301.

[0063] The first conductive layer 141 corresponding to the second thin film transistor 112 also includes a second connecting line 1415b located in the second sub-region 1202, one end of the second connecting line 1415b is electrically connected to the drain 1102 of the second thin film transistor 112, and the other end of the second connecting line 1415b passes through the first through hole 121 and the second through hole 122 in the second sub-region 1202 and is electrically connected to the second sub-pixel electrode 1302.

[0064] Combination Figure 1 and Figure 4 The first end a of the first connecting line 1415a is electrically connected to the drain 1102 of the second thin film transistor 112, and the second end b of the first connecting line 1415a passes through the first through hole 121 and the second through hole 122 in the first sub-region 1201 and is electrically connected to the first sub-pixel electrode 1301; at the second through hole 122 in the first sub-region 1201, the first sub-pixel electrode 1301 transmits the electrical signal to the first electrode 1411 of the first storage capacitor 1401.

[0065] The first end a of the second connecting line 1415b is electrically connected to the drain 1102 of the second thin film transistor 112, and the second end b of the second connecting line 1415b passes through the first through hole 121 and the second through hole 122 in the second sub-region 1202 to be electrically connected to the second sub-pixel electrode 1302; at the second through hole 122 in the second sub-region 1202, the second sub-pixel electrode 1302 transmits the electrical signal first to the drain 1102 of the second thin film transistor 112, and then to the third electrode 1413 of the second storage capacitor 1402.

[0066] Preferably, in the embodiment provided in the present application, the drain 1102 of the second thin film transistor 112 is arranged on the same layer as the third electrode 1413, which simplifies the structure of the array substrate 1. In addition, the conduction of electrical signals on the same layer ensures the effectiveness of electrical signal conduction, thereby avoiding the problem of poor grayscale dark spot display caused by the breakage of the second sub-pixel electrode 1302 at the first through hole 121 or poor film forming quality.

[0067] In the embodiment provided in the present application, the pixel electrode layer 13 includes a plurality of first conductive lines 1311 electrically connected to the first sub-pixel electrode 1301. In order to prevent the first sub-pixel electrode 1301 from being broken at the connection with the first conductive layer 141, resulting in poor connection, preferably, Figure 1 and Figure 4 In the embodiment provided in the present application, the first sub-pixel electrode 1301 is connected to the first conductive layer 141 of the first thin film transistor 111 through two first conductive lines 1311. It should be noted that the number of the first conductive lines 1311 may be greater than two, and the number may be increased according to actual conditions.

[0068] In the embodiment provided in the present application, the pixel electrode layer 13 includes a plurality of second conductive lines 1312 electrically connected to the second sub-pixel electrode 1302. It is understandable that in order to prevent the second sub-pixel electrode 1302 from being broken at the connection with the first conductive layer 141, resulting in poor connection, preferably, the second sub-pixel electrode 1302 is connected to the first conductive layer 141. Figure 1 and Figure 4In the embodiment provided in the present application, the second sub-pixel electrode 1302 is connected to the second conductive layer 142 of the second thin film transistor 112 through two second conductive lines 1312. The number of the second conductive lines 1312 between the second sub-pixel electrode 1302 and the first conductive layer 141 may also be greater than two, and the specific value may be determined according to actual conditions.

[0069] In order to ensure effective overlap between the pixel electrode 130 and the first conductive layer 141, in the embodiment provided in the present application, the depth of the second through hole 122 is less than or equal to the depth of the first through hole 121, that is, the second through hole 122 is set to a shallow hole, thereby reducing the risk of climbing fracture of the pixel electrode 130 at the second through hole 122 and avoiding the grayscale dark spot problem.

[0070] On the other hand, the present application provides a display panel 4, comprising the array substrate 1 in the embodiment of the present application. Fig.10 As shown, the display panel 4 includes an array substrate 1 , a color filter substrate 2 and a liquid crystal layer 3 . The array substrate 1 and the color filter substrate 2 are arranged opposite to each other, and the liquid crystal layer 3 is arranged between the array substrate 1 and the color filter substrate 2 .

[0071] Finally, the present application provides a method for manufacturing an array substrate 1, such as Fig. 9 As shown, the following steps are included:

[0072] S1. providing a substrate;

[0073] S2, manufacturing a thin film transistor layer on the substrate, wherein the thin film transistor layer includes a thin film transistor, and the thin film transistor is electrically connected to the first conductive layer;

[0074] S3, forming a passivation layer on the thin film transistor layer, wherein the passivation layer includes a thin film transistor region corresponding to the thin film transistor;

[0075] S4, opening a first through hole and a second through hole in the thin film transistor region of the passivation layer;

[0076] S5. Fabricate a pixel electrode layer on the passivation layer, wherein the pixel electrode layer includes a pixel electrode, and the pixel electrode passes through the first through hole and the second through hole to be electrically connected to the first conductive layer.

[0077] The first through hole 121 and the second through hole 122 can be formed on the passivation layer 12 by a photolithography process, and the pixel electrode 130 is made of ITO, and is connected to the first conductive layer 141 through a via hole.

[0078] By adding a second through hole 122 at a position adjacent to the first through hole 121, and making the pixel electrode 130 electrically connected to the first conductive layer 141 through the first through hole 121 and the second through hole 122 respectively, the risk of poor overlap caused by breakage of the pixel electrode 130 at the through hole when the pixel electrode 130 is connected to the first conductive layer 141 through only one through hole is reduced, thereby ensuring the electrical connection between the pixel electrode 130 and the first conductive layer 141 and avoiding the problem of grayscale dark spots.

[0079] The above is a detailed introduction to an array substrate, a display panel and a method for preparing an array substrate provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solution and its core idea of ​​the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of each embodiment of the present application.

Claims

1. An array substrate, characterized in that: The array substrate comprises: substrate; A thin film transistor layer, disposed on the substrate, the thin film transistor layer includes a thin film transistor component, the thin film transistor component includes at least one thin film transistor, and the thin film transistor is electrically connected to the first conductive layer; A passivation layer is provided on the thin film transistor layer, wherein the passivation layer includes a thin film transistor region corresponding to the thin film transistor, the thin film transistor region includes a first sub-region and a second sub-region, and the passivation layer is provided with a first through hole and a second through hole in the thin film transistor region; a pixel electrode layer, disposed on the passivation layer, the pixel electrode layer comprising a pixel electrode, the pixel electrode comprising a first sub-pixel electrode and a second sub-pixel electrode, the pixel electrode respectively passing through the first through hole and the second through hole to be connected to the first conductive layer; The passivation layer is provided with the first through hole and the second through hole in the first sub-region, and the first sub-pixel electrode is connected to the first conductive layer through the first through hole and the second through hole in the first sub-region respectively; and / or, The passivation layer is provided with the first through hole and the second through hole in the second sub-region, and the second sub-pixel electrode is connected to the first conductive layer through the first through hole and the second through hole in the second sub-region respectively.

2. The array substrate according to claim 1, characterized in that: The thin film transistor assembly includes a first thin film transistor, which corresponds to the first sub-region. The pixel electrode layer includes a plurality of first conductive lines electrically connected to the first sub-pixel electrode, and the first sub-pixel electrode is connected to the first conductive layer of the first thin film transistor through at least two of the first conductive lines.

3. The array substrate according to claim 2, characterized in that: The thin film transistor assembly also includes a second thin film transistor, which corresponds to the second sub-region. The pixel electrode layer includes a plurality of second conductive lines electrically connected to the second sub-pixel electrode, and the second sub-pixel electrode is connected to the first conductive layer of the second thin film transistor through at least two of the second conductive lines.

4. The array substrate according to claim 3, characterized in that: The first thin film transistor and the second thin film transistor are also electrically connected to a second conductive layer respectively, and the second conductive layer is located between the substrate and the first conductive layer; The first conductive layer corresponding to the first thin film transistor includes a first electrode, and the second conductive layer corresponding to the first thin film transistor includes a second electrode. A first storage capacitor is formed between the first electrode and the second electrode. The first storage capacitor is located in the first sub-region and corresponds to the position of the first through hole.

5. The array substrate according to claim 4, characterized in that: The first conductive layer corresponding to the second thin film transistor includes a third electrode, and the second conductive layer corresponding to the second thin film transistor includes a fourth electrode. A second storage capacitor is formed between the third electrode and the fourth electrode. The second storage capacitor is located in the second sub-region and corresponds to the position of the first through hole.

6. The array substrate according to claim 3, characterized in that: The first conductive layer corresponding to the first thin film transistor further includes a first connecting line located in the first sub-region, one end of the first connecting line is electrically connected to the drain of the first thin film transistor, and the other end of the first connecting line passes through a first through hole and a second through hole in the first sub-region and is electrically connected to the first sub-pixel electrode; The first conductive layer corresponding to the second thin film transistor also includes a second connecting line located in the second sub-region, one end of the second connecting line is electrically connected to the drain of the second thin film transistor, and the other end of the second connecting line passes through the first through hole and the second through hole in the second sub-region and is electrically connected to the second sub-pixel electrode.

7. The array substrate according to claim 1, characterized in that: The array substrate further includes a color filter layer disposed on the pixel electrode layer. The color filter layer is provided with an opening. The first through hole corresponds to the opening, and the second through hole is staggered with the opening.

8. The array substrate according to any one of claims 1 to 7, characterized in that: A depth of the second through hole is less than or equal to a depth of the first through hole.

9. A display panel, characterized in that: The display panel comprises the array substrate as claimed in any one of claims 1 to 8.

10. A method for manufacturing an array substrate, characterized in that: The production method comprises the following steps: providing a substrate; Manufacturing a thin film transistor layer on the substrate, wherein the thin film transistor layer includes a thin film transistor, and the thin film transistor is electrically connected to the first conductive layer; A passivation layer is formed on the thin film transistor layer, wherein the passivation layer includes a thin film transistor region corresponding to the thin film transistor, and the thin film transistor region includes a first sub-region and a second sub-region; Opening a first through hole and a second through hole in the thin film transistor region of the passivation layer; A pixel electrode layer is manufactured on the passivation layer, wherein the pixel electrode layer includes a pixel electrode, wherein the pixel electrode includes a first sub-pixel electrode and a second sub-pixel electrode, wherein the pixel electrode is electrically connected to the first conductive layer through the first through hole and the second through hole respectively, wherein the passivation layer is provided with the first through hole and the second through hole in the first sub-region, wherein the first sub-pixel electrode is connected to the first conductive layer through the first through hole and the second through hole in the first sub-region respectively; and / or wherein the passivation layer is provided with the first through hole and the second through hole in the second sub-region, wherein the second sub-pixel electrode is connected to the first conductive layer through the first through hole and the second through hole in the second sub-region respectively.

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