Substrate management controller system and multi-node computer system using the same

Abstract

A baseboard management controller (BMC) is adapted to support multiple computer platforms. The BMC system has a BMC CPU chip that includes a processor that executes firmware. The BMC CPU chip is coupled to an interface chip via an external bus. The interface chip includes input / output interfaces for different communication protocols to connect components on a computer node.

Description

Technical Field

[0001] In general, this disclosure relates to a baseboard management controller (BMC) for a multi-node computer system. Specifically, aspects of this disclosure relate to a BMC-based system that uses an interface chip (I / O chip) without firmware, enabling the BMC system to be scaled for multi-node configurations. Background Technology

[0002] Servers are widely used in high-demand applications, such as network-based systems or data centers. The emergence of cloud computing applications has increased the demand for data centers. A data center has multiple servers that store data and run applications accessible to remotely connected computer users. A typical data center has a physical rack structure with power and communication connections. Each rack can house multiple computing and storage servers. Generally, each server includes hardware components such as processors, memory devices, network interface cards, power supplies, and other purpose-specific hardware. Typically, a server includes a Baseboard Management Controller (BMC) that manages the operation of the hardware and support components (such as power supplies and fans). The BMC also communicates operational data to a central management station that manages the servers in the rack. The BMC allows the server's central processing unit (CPU) to operate without monitoring the server's operation. Therefore, the BMC must be able to connect to the various hardware components on a given server.

[0003] For example, a baseboard management controller (BMC) can be a single chip with a complex processor, such as, but not limited to, products sold by ASPEED Technology, Nuvoton Technology, and Texas Instruments (TI). Such a BMC requires firmware to program the complex processor to perform different functions. Currently known BMCs also include multiple input / output interface circuits to communicate with various hardware components using different communication protocols.

[0004] Figure 1AThis is a block diagram showing a known BMC chip 10. The BMC chip 10 is a system-on-a-chip (SoC) including a processor 12, an internal bus 14, and a series of input / output interfaces, each with individually designed hardware obtained from a vendor. All the different interfaces are designed to be contained within the SoC BMC chip 10, enabling different devices to communicate with the BMC chip 10. In this example, these interfaces include a Universal Serial Bus (USB) interface 20, an Integrated Bus Circuit (I2C) or Modified Integrated Bus Circuit (I3C) interface 22, a High-Speed ​​Peripheral Component Interconnect Standard (PCIe) interface 24, a General Purpose Input / Output (GPIO) interface 26, a Universal Asynchronous Receiver / Transmitter (UART) interface 28, Local Processing Inter-Serial Communication (LPC) / Enhanced Serial Peripheral Interface (eSPI) 30, a network interface 32, an SPI / Microsoft Management Console (MMC) interface 34, a Pulse Width Modulation (PWM) / Tachometer interface 36, and an Analog-to-Digital Converter (ADC) interface 38. Other interfaces can also be provided for use by other communication protocols.

[0005] Currently, the lifespan of a BMC chip is approximately 5 to 6 years. However, BMC chips must now be designed to support increasingly sophisticated platforms, leading to a demand for various input / output interfaces. As platforms evolve, BMC hardware and / or firmware must be continuously upgraded, and the lifespan of the BMC is shortened when new demands exceed its current capabilities. Furthermore, the known BMC chip 10 is not expandable due to its hardwired input / output interfaces, resulting in limited scalability. For example, if the number of sensors on the substrate exceeds the number of channels that can communicate with the required interfaces, the BMC chip 10 will not function.

[0006] Figure 1B show Figure 1A This example illustrates a known use case of the BMC chip 10 on a single node. The node has a motherboard 40, including a central processing unit (CPU) 42 and a platform path controller (PCH) 44. In this example, the BMC chip 10 communicates with the CPU 42 and PCH 44 using different interfaces and various communication protocols. The CPU 42 communicates with the BMC chip 10 via I2C / I3C interface 22, PCIe interface 24, and LPC / SPI interface 30. The PCH 44 communicates with the BMC chip 10 via USB interface 20, PCIe interface 24, and LPC / SPI interface 30. A GPIO interface 26 can be used for visual indicators, such as light-emitting diodes (LEDs). A UART interface 28 can be used for host serial connections over a network. In this example, the firmware for the BMC chip 10 must be developed specifically for the CPU 42 and PCH 44.

[0007] Figure 1C This illustrates another use case of the known BMC chip 10, which has a single-chip system-on-a-chip (SOC) CPU 50 located on a motherboard 52. In this example, Figure 1B The functions of PCH 44 are integrated into the single-chip system CPU 50. BMC chip 10 can communicate with SOC CPU 50 using different interfaces, such as USB interface 20, I2C / I3C interface 22, PCIe interface 24, and LPC / SPI interface 30. Figure 1C The firmware for the BMC chip 10 must be developed for the SOC CPU 50, therefore... Figure 1B The firmware of the BMC chip 10 is different.

[0008] Figure 1D This illustrates a multi-node design with a BMC chip 10 located at the far end of a series of nodes (e.g., a first node 60 and another Nth node 62). Although Figure 1D Only two nodes are shown in the image; however, such a system can also have more than two nodes. This multi-node design can be a chassis with a base plate for mounting the BMC chip 10 and multiple single-board computers (blades, or nodes) with processors containing different hardware components. The BMC chip 10 communicates with the mini BMC 64 on each node 60 and 62 via a bus (e.g., I2C / I3C bus 66). The mini BMC 64 is a lower-cost BMC (compared to the conventional BMC chip 10) and includes several interfaces.

[0009] In this example, each node 60 and 62 can have a different circuit layout, requiring the mini BMC 64 to be configured differently to communicate with the components on that node. Therefore, each of these mini BMCs 64 may require firmware specifically designed for the components on that particular node. For example, the mini BMC 64 on node 60 communicates with the host SOC CPU 70 via LPC / SPI, UART, I2C / I3C, and USB interfaces. The sensor 74 on node 60 communicates with the mini BMC 64 via I2C / I3C and GPIO interfaces. The fan module 72 communicates with the mini BMC 64 via a PWM / tachometer interface. The mini BMC 64 on node 62 may need to communicate with other components and requires different firmware designed for those components. Therefore, Figure 1D The multi-node design requires maintaining the firmware of the BMC chip 10 and the firmware of each mini BMC 64. This multiple firmware set is not easy to maintain and develop.

[0010] Therefore, among these many needs, we urgently require a BMC system that can support various hardware configurations across different nodes. We also urgently need a BMC system that can be scaled for systems with multiple nodes. Furthermore, we urgently need a BMC system whose fixed interface chip does not require firmware, thus minimizing firmware resource requirements. Summary of the Invention

[0011] The term “embodiment” and similar terms such as “implementation,” “configuration,” “aspect,” “example,” and “option” are intended to broadly refer to the entire subject matter of this disclosure and the following claims. The inclusion of such terms in a description is not intended to limit the subject matter of this disclosure or to limit the meaning or scope of the following claims. The embodiments described in this disclosure are defined by the following claims, not by the content of this section. This section provides a general overview of the various aspects of this disclosure and introduces some concepts that will be detailed in the “Implementation” section below. This section is not intended to identify key or essential features of the claimed subject matter. Nor is it intended to be used alone to determine the scope of the claimed subject matter. Understanding of the subject matter should be made by referring to the entire specification of this disclosure, any or all of the accompanying drawings, and the appropriate portions of each claim.

[0012] According to certain aspects of this disclosure, a Baseboard Management Controller (BMC) system is disclosed, configurable to support multiple computer platforms. The BMC system has a CPU chip within the BMC, including a processor for executing firmware. The BMC CPU chip is coupled to an interface chip via an external bus. The interface chip includes input / output interfaces for use with different communication protocols for communicating with components on the computer node.

[0013] A further application of this exemplary system is a communication protocol that includes at least one of the following: Universal Serial Bus (USB), Integrated Bus Circuit (I2C), Modified Integrated Bus Circuit (I3C), High-Speed ​​Peripheral Component Interconnect Standard (PCIe), General Purpose Input / Output (GPIO), Universal Asynchronous Receiver / Transmitter (UART), Local Processing Inter-Serial Communication (LPC) / Enhanced Serial Peripheral Interface (eSPI), network, pulse width modulation signals, analog-to-digital converter signals, and SPI / Microsoft Management Console (MMC) embodiments. Another application is in which these input / output interfaces of the interface chip operate independently of the firmware. Another application is in which the system also includes a memory accessible by the BMC CPU chip, wherein the memory stores the firmware. Another application is in which the BMC CPU chip includes multiple input / output interfaces coupled to the processor via an internal bus. Another application is in which the system also includes a second interface chip coupled to the BMC CPU chip via an external bus, the second interface chip including multiple input / output interfaces for communication with components on the computer node using different communication protocols. Another application involves a BMC CPU chip located on a substrate, with the first and second interface chips located on separate computer nodes. Another application involves the first and second interface chips having the same input / output interface. Another application involves the first and second BMC interface chips having different input / output interfaces. Yet another application involves a BMC CPU chip located on a substrate, with both the first and second interface chips located on a single computer node.

[0014] Another disclosed example is a multi-node computer system including a substrate having a Baseboard Management Controller (BMC) CPU chip and memory storing firmware for use by the BMC CPU chip. The BMC CPU chip has a processor and an external bus interface. The external bus is coupled to the external bus interface of the BMC CPU chip. A first computer node has a first BMC interface chip coupled to the external bus and components on the first computer node. A second computer node has a second BMC interface chip coupled to the external bus and components on the second computer node.

[0015] A further application of this exemplary system is a communication protocol including at least one of the following: Universal Serial Bus (USB), Integrated Bus Circuit (I2C), High-Speed ​​Peripheral Component Interconnect Standard (PCIe), General Purpose Input / Output (GPIO), Universal Asynchronous Receiver / Transmitter (UART), Local Processing Inter-Serial Communication (LPC) / Enhanced Serial Peripheral Interface (eSPI), network, pulse width modulation signals, analog-to-digital converter signals, and SPI / Microsoft Management Console (MMC) embodiments. Another application is in which these input / output interfaces of the interface chip operate independently of firmware. Another application is in which the system also includes a memory accessible by the BMC CPU chip, wherein the memory stores the firmware. Another application is in which the BMC CPU chip includes multiple input / output interfaces coupled to a processor via an internal bus. Another application is in which the first and second interface chips have the same input / output interfaces. Another application is in which the first and second interface chips have different input / output interfaces.

[0016] This section is not intended to represent every embodiment or aspect of this disclosure. Rather, it provides examples of some of the novel aspects and features of this disclosure. The foregoing features and advantages, as well as other features and advantages of this disclosure, will become apparent upon reading the representative embodiments and modes for implementing the invention described in the following "Description" section, in conjunction with the accompanying drawings and appended claims. Those skilled in the art to which this disclosure pertains will readily recognize additional aspects of this disclosure upon reading the embodiments described in the following "Description" section, in conjunction with the accompanying drawings. The accompanying drawings will be briefly described in the following "Brief Description of the Drawings" section. Attached Figure Description

[0017] This disclosure, its advantages, and the accompanying drawings will be best understood upon reading the representative embodiments described in the following "Description" section in conjunction with the accompanying drawings. These drawings are merely illustrative of representative embodiments and should not be construed as limiting the scope of the embodiments or the claims.

[0018] Figure 1A This is a block diagram showing a prior art board management controller (BMC) chip;

[0019] Figure 1B It is a block diagram, showing Figure 1A The existing BMC chip shown is used in a single-node computer system;

[0020] Figure 1C It is a block diagram, showing Figure 1A The existing BMC chip shown is used in another single-node computer system;

[0021] Figure 1DIt is a block diagram, showing Figure 1A The existing BMC chip shown is used in a multi-node computer system;

[0022] Figure 2 As a block diagram, based on certain aspects of this disclosure, an exemplary BMC system is shown having discrete interface chips; and

[0023] Figure 3 As a block diagram, in accordance with certain aspects of this disclosure, it shows Figure 2 The example BMC system is configured in a multi-node system. Detailed Implementation

[0024] The embodiments are described with reference to the accompanying drawings, wherein the same reference numerals in the different drawings are used to denote similar or equivalent elements. The drawings are not necessarily drawn to scale and are only used to illustrate aspects and features of this disclosure. Various specific details, relationships, and methods described herein are provided to give a complete understanding of certain aspects and features of this disclosure, and those skilled in the art will recognize that these aspects and features can be implemented without these specific details or in other relationships and methods. In some examples, known structures or operations are not shown in detail for clarity. The embodiments disclosed herein are not limited to the order of the operations or events described, as some operations may be performed in different orders and / or simultaneously with other operations or events. Furthermore, not all of the described operations or events must implement certain aspects or features of this disclosure.

[0025] In this section, unless otherwise expressly indicated, singular terms include plural terms where appropriate, and vice versa. The word “including” means “including but not limited to”. Furthermore, terms indicating approximation, such as “about,” “nearly,” “roughly,” “approximately,” etc., may be used in this section to mean “located in,” “close to,” “nearly,” “within 3-5% tolerance,” “within permissible manufacturing tolerance,” or logical combinations of the above. Similarly, terms such as “vertical” or “horizontal” are intended to also include “within 3-5% tolerance” in the vertical or horizontal direction, respectively. Furthermore, terms indicating direction, such as “top,” “bottom,” “left,” “right,” “above,” “below,” are intended to refer to the equivalent direction illustrated in the accompanying drawings; to be interpreted according to the context of the reference object or element, such as from its usual position of use; or to be interpreted in other ways as described herein.

[0026] This disclosure relates to a BMC system, including a BMC CPU chip and multiple external interface chips (I / O chips) connected to the BMC CPU chip via an external bus. The BMC CPU chip has a basic interface and executes firmware to perform computer system operation functions. The interface chips have multiple input / output interfaces and transmit and receive data with different hardware components on a node according to specific communication protocols. The interface chips communicate data with the BMC CPU chip via the external bus. This ability to connect multiple external interface chips gives the BMC system scalability to adapt to different platforms and configurations. Using external interface chips with minimal (or no) firmware eliminates the need to track and update the different firmware on each node in a multi-node system.

[0027] Figure 2 This illustration shows an example of a Baseboard Management Controller (BMC) system 100. The BMC system 100 manages the operation of a computer system, such as power management and temperature management. Therefore, the BMC system 100 controls the power supply and fan module based on data received from power and temperature sensors within the computer system. The BMC system also receives operational data from various hardware components of the computer system and provides setpoints to these hardware components. In this example, the BMC system 100 includes a BMC CPU chip 110 and a series of modular interface chips, such as interface chips (I / O chips) 112 and 114, connected to an external bus 116. Interface chips 112 and 114 include input / output interfaces for use with various communication protocols. Depending on the specific design application required by the computer system, any number and type of interface chips can be connected to the external bus 116. The memory device, such as flash memory device 118, stores firmware executed by BMC CPU chip 110 to perform various functions, such as event logging, power management, temperature management, system startup, remote KVM (keyboard, graphics and mouse), remote media (such as CD-ROM, USB, DVD-ROM storage devices), asset management, and power sequence detection.

[0028] In this example, the BMC CPU chip 110 includes a relatively powerful programmable control device, such as a CPU 120, an internal bus 122, and a set of interfaces 124 or basic interfaces. The BMC CPU chip 110 is disposed on a substrate 126, which is connected via an external bus 116 to nodes associated with interface chips 112 and 114. The BMC CPU chip 110 includes an external bus interface enabling communication with the external bus 116. Interface 124 includes a basic set of interfaces that allow the BMC CPU chip 110 to monitor basic hardware functions. For example, this basic set of interfaces 124 may include GPIO interfaces, UART interfaces, I2C / I3C interfaces, memory bus interfaces, and pulse width modulation (PWM) interfaces. In this example, these interfaces may have limited bandwidth, as they are primarily used for monitoring basic functions on the substrate. Therefore, the GPIO interface can be used for LED control and button input; the SPI interface can be used to control flash memory devices; the memory bus can be used to read and write fourth-generation double data rate synchronous dynamic random access memory (DDR4) devices; the PWM interface can be used to monitor fan speed; and the I2C / I3C bus can be used to read electrically erasable programmable read-only memory (EEPROM) devices.

[0029] When the BMC system 100 is configured to monitor the operation of other computer nodes, these interface chips may have high-bandwidth input / output interfaces to provide operational data to the BMC CPU chip 110 via external bus 116. Therefore, external bus 116 has high-bandwidth and high-speed communication capabilities. Thus, external bus 116 may be a PCIe x4, USB 3, or a similar high-bandwidth / high-speed bus. CPU 120 preferably provides sufficient power to process large amounts of data and transmit instructions to different components on multiple nodes.

[0030] BMC CPU chip 110 is coupled to any number of interface chips, such as interface chip 112, via external bus 116. Therefore, the exemplary BMC system 100 moves most of the interface functionality to external interface chips with input / output interfaces for specific communication protocols. Due to the node design, these interface chips do not require dedicated firmware to operate; therefore, during functional upgrades, only the firmware of BMC CPU chip 110 needs to be modified. This eliminates the need for... Figure 1D The firmware requirements for the mini BMC 64 are known on each node. Furthermore, the scalability of the BMC system 100 is relatively... Figure 1AThe known SOC BMC chip 10 is superior because when the number of nodes increases, only the interface chip needs to be added. Alternatively, different types of interface chips can be used to adapt to the communication needs of specific nodes.

[0031] In this example, the external interface chip 112 includes a Universal Serial Bus (USB) interface 130, an Integrated Bus Circuit (I2C) / I3C interface 132, a High-Speed ​​Peripheral Component Interconnect Standard (PCIe) interface 134, a General Purpose Input / Output (GPIO) interface 136, a Universal Asynchronous Receiver / Transmitter (UART) interface 138, a Local Processing Inter-Serial Communication (LPC) / Enhanced Serial Peripheral (eSPI) interface 140, a network interface 142, an SPI / Microsoft Management Console (MMC) interface 144, a Pulse Width Modulation (PWM) / Tachometer interface 146, and an Analog-to-Digital Converter (ADC) interface 148. Other input / output interfaces 150 may also be provided for use with other communication protocols.

[0032] Each interface chip's input / output interface can support different hardware components on the node. For example, USB interface 130 can serve as an interface to connect to the PCH or BMC of the SOC processor, operating in OTG (on-the-go) mode. OTG mode can be USB slave mode, emulating any USB device, such as a storage device, keyboard, or mouse. Alternatively, OTG mode can be USB master mode. This setting allows the BMC's USB host port to receive inserted USB devices. In this mode, a USB storage device can be inserted into the BMC's USB port to copy event logs or perform firmware updates. USB interface 130 can also serve as a remote media emulator and a remote keyboard-graphics-mouse (KVM) interface. I2C / I3C interface 132 or System Management Bus (SMBus) can serve as an interface to connect to the host SOC and various sensors (such as temperature sensors, power sensors, etc.). PCIe interface 134 can serve as an interface for connecting to the host CPU or PCH, for supporting Video Graphics Array (VGA) graphics display, Management Component Transfer Protocol (MCTP) features, and for remote KVM communication. GPIO interface 136 can be used to control visual indicators (e.g., LEDs) to indicate BMC heartbeat, BMC health status, BIOS Power-On Self-Test (POST) code, power status, existing device status (e.g., HDD, SSD, NVMe storage device), or any other BMC-monitored status. UART interface 138 can be used for host serial communication or debugging via a local area network (LAN). LPC / eSPI interface 140 can serve as an interface for connecting to the PCH or host SOC, for example, for receiving BIOS POST code. Network interface 142 can be a Network Controller Sideband Interface (NC-SI) for communicating with external devices. SPI / MMC interface 144 can be used for storing BIOS firmware updates or debugging records. The pulse width modulation (PWM) / tachometer interface 146 can communicate with the fan unit. The ADC interface 148 can communicate with various sensors.

[0033] Different interface chips can be designed to support different interfaces while still communicating with the same BMCCPU chip 110 via external bus 116. Alternatively, certain input / output interfaces can be provided with more channels or higher bandwidth depending on the actual application requirements. Alternatively, multiple interface chips can be used to increase the bandwidth of a specific interface.

[0034] For example, some nodes may have fewer sensors, while others may have a relatively larger number. Therefore, designers can choose to use multiple interface chips for nodes with a large number of sensors. Alternatively, dedicated chips with higher-capacity interfaces (such as I2C / I3C interfaces with 20 channels, or GPIO interfaces supporting 100 or 200 pins) can be provided for such nodes.

[0035] Therefore, different nodes can have different general-purpose processors and PCHs, which are supported by the BMC system via interface chips. These interface chips also support integrated SoC CPUs. These interface chips can also support nodes with dedicated functions performed by dedicated processors, such as graphics processing units (GPUs) or field-programmable gate arrays (FPGAs) programmed to perform specific functions (e.g., database searches). Dedicated hardware components on the nodes, such as Serial Advanced Technology Accessories (SATA) devices, Open Compute Project (OCP) devices, PCIe devices, and USB devices, can be supported via these interface chips. These devices may include storage devices, network interface cards (NICs), disk array (RAID) cards, field-programmable gate array (FPGA) cards, and processor cards, such as graphics processing units (GPU) cards.

[0036] In this example, interface chips 112 and 114 do not require a programmable controller, thus eliminating the need for firmware. Since these interface chips connect to different node designs, no firmware update is required when a new node is added; the monitoring performed by the BMC CPU chip 110 can be executed immediately. Therefore, only one set of BMC firmware for the BMC CPU chip 110 needs to be developed and maintained. This configuration shortens the product development cycle because general-purpose interface chips can be used in new node configurations and designs. Alternatively, for specific applications, only interface chips need to be designed, instead of designing the entire BMC chip as is the case with known BMC chips. Because only one set of firmware is required, the maintenance workload for multi-node systems is also reduced.

[0037] Figure 3This is a block diagram showing a computer system 300 with different server nodes 310, 312, 314, and 316. In this example, a BMC CPU chip 110 is mounted on a substrate 318. Each server node 310, 312, 314, and 316 can be a blade server, connected to the substrate 318 and housed in a chassis. The substrate 318 may include a shared power supply and fan module for use by all connected blade servers. Although four nodes are shown in the diagram, it should be understood that any number of nodes can be supported by the BMC CPU chip 110. Furthermore, these nodes may have the same or different designs in terms of hardware components and functionality.

[0038] In this example, each node 310, 312, 314, and 316 includes the same interface chip 320. Interface chip 320 is similar to... Figure 2 The interface chip 312 in the example includes multiple input / output interfaces for use with different communication protocols. Depending on the specific node design, each interface chip 320 may use some or all of the interfaces. For example, node 310 may include CPU 332 and Platform Path Controller (PCH) 334 to facilitate communication between other components and CPU 332. In this example, interface chip 320 communicates with CPU 332 and PCH 334 using different interfaces. CPU 332 communicates with interface chip 320 via I2C / I3C, PCIe, and LPC / SPI interfaces. PCH 334 communicates with interface chip 320 via USB, PCIe, and LPC / SPI interfaces.

[0039] Node 312 features a System-on-a-Chip (SOC) CPU 340, which integrates the PCH functionality. Interface chip 320 can communicate with the SOC CPU 340 using various interfaces, such as USB, I2C / I3C, and LPC / SPI interfaces. Although the design of Node 312 differs from that of Node 310, no additional firmware is required for the BMC CPU chip 110.

[0040] Node 314 may include a dedicated controller 350. The dedicated controller 350 may be a switch controller, FPGA, network interface controller, general-purpose GPU, host bus adapter (HBA) controller, or disk array (RAID) controller. The dedicated controller 350 can be used with different input / output interfaces of the interface chip 320. Although the design of node 314 differs from nodes 310 and 312, no additional firmware is required for the BMC CPU chip 110.

[0041] In this example, node 316 has a dedicated interface chip 360, which has a different design from the other interface chip 320. Node 316 has a dedicated controller 362 that requires a higher bandwidth interface, such as a PCIe interface. Therefore, the dedicated interface chip 360 has a higher bandwidth PCIe interface to handle the higher bandwidth required by the controller 362. The dedicated interface chip 360 operates without firmware. Alternatively, if cost-effective, two or more interface chips 320 may be used to provide PCIe interfaces for the dedicated controller 362.

[0042] Figure 2 The BMC system 100 can also be used in single-board computer systems, such as standalone servers. The motherboard of such a system only needs to be modified to provide the socket used by the BMC CPU chip 110, and one or more interface chips, such as interface chip 112.

[0043] Although one or more embodiments of this disclosure have been illustrated and described, those skilled in the art to which this disclosure pertains will be able to recognize equivalent modifications or alterations upon reading and understanding this specification and the accompanying drawings. Furthermore, although a particular feature of this disclosure may be disclosed only in one of several embodiments, such feature may also be combined with other features in one or more other embodiments if desired or advantageous for any given or particular application.

[0044] Although several embodiments of this disclosure have been described above, it should be noted that these embodiments are presented as examples only and not as limitations. Various modifications can be made to the disclosed embodiments based on this disclosure without departing from the spirit and scope of this disclosure. Therefore, the breadth and scope of this disclosure should not be limited to any of the foregoing embodiments. Rather, the scope of this disclosure should be defined by the following claims and their equivalents.

[0045] Symbol explanation:

[0046] 10: BMC chip

[0047] 12: Processor

[0048] 14: Internal Bus

[0049] 20: Universal Serial Bus (USB) interface

[0050] 22: Integrated bus circuit (I2C) or modified integrated bus circuit (I3C) interface

[0051] 24: High-speed peripheral component interconnect standard (PCIe) interface

[0052] 26: General Purpose Input / Output (GPIO) Interface

[0053] 28: Universal Asynchronous Receiver / Transmitter (UART) Interface

[0054] 30: Locally Handled Inter-Serial Communication (LPC) / Enhanced Serial Peripheral Interface (eSPI)

[0055] 32: Network Interface

[0056] 34: SPI / Microsoft Management Console (MMC) Interface

[0057] 36: Pulse Width Modulation (PWM) / Tachometer Interface

[0058] 38: Analog-to-Digital Converter (ADC) Interface

[0059] 40: Motherboard

[0060] 42: Central Processing Unit (CPU)

[0061] 44: Platform Path Controller (PCH)

[0062] 50: System-on-a-Chip (SoC) CPU

[0063] 52: Motherboard

[0064] 60: First Node

[0065] 62: Node N

[0066] 64: Mini BMC

[0067] 66: I2C / I3C bus

[0068] 70: Host SOC CPU

[0069] 72: Fan Module

[0070] 74: Sensors

[0071] 100: Baseboard Management Controller (BMC) System

[0072] 110: BMC CPU chip

[0073] 112, 114: Interface chips

[0074] 116: External Bus

[0075] 118: Flash memory device

[0076] 120: CPU

[0077] 122: Internal Bus

[0078] 124: Interface

[0079] 126: Substrate

[0080] 130: Universal Serial Bus (USB) interface

[0081] 132: Integrated bus circuit (I2C) interface or modified integrated bus circuit (I3C) interface

[0082] 134: High-speed peripheral component interconnect standard (PCIe) interface

[0083] 136: General Purpose Input / Output (GPIO) Interface

[0084] 138: Universal Asynchronous Receiver / Transmitter (UART) Interface

[0085] 140: Local Inter-Serial Communication (LPC) / Enhanced Serial Peripheral Interface (eSPI)

[0086] 142: Network Interface

[0087] 144: SPI / Microsoft Management Console (MMC) Interface

[0088] 146: Pulse Width Modulation (PWM) / Tachometer Interface

[0089] 148: Analog-to-Digital Converter (ADC) Interface

[0090] 150: Other Input / Output Interfaces

[0091] 310, 312, 314, 316: Server nodes

[0092] 318: Substrate

[0093] 320: Interface chip

[0094] 332: CPU

[0095] 334: Platform Path Controller (PCH)

[0096] 340: System-on-a-Chip (SoC) CPU

[0097] 350: Dedicated Controller

[0098] 360: Dedicated interface chip

[0099] 362: Dedicated Controller

Claims

1. A baseboard management controller (BMC) system suitable for supporting multiple computer nodes, the BMC system comprising: BMC central processing unit (CPU) chip, including a processor, for executing a set of firmware; as well as A first interface chip, coupled to the BMC CPU chip via an external bus, includes multiple input / output interfaces for use with multiple different communication protocols and connects to multiple components on the first computer node. A second interface chip, also coupled to the BMC CPU chip via an external bus, includes multiple input / output interfaces for use with multiple different communication protocols and connects to multiple components on the second computer node. The input / output interfaces of the first interface chip and the second interface chip operate independently of the firmware, and the first interface chip and the second interface chip do not require firmware. The first interface chip and the second interface chip transmit data obtained by the input / output interface through different communication protocols to the BMC CPU chip via the external bus. The BMC CPU chip monitors the operation of the multiple computer nodes based on the same set of firmware.

2. The BMC system of claim 1, wherein the communication protocols include at least one of the following: Universal Serial Bus (USB), Integrated Bus Circuit (I2C) interface, Modified Integrated Bus Circuit (I3C) interface, High-Speed ​​Peripheral Component Interconnect Standard (PCIe), General Purpose Input / Output (GPIO), Universal Asynchronous Receiver / Transmitter (UART), Local Processing Inter-Serial Communication (LPC) / Enhanced Serial Peripheral Interface (eSPI), network, pulse width modulation signal, analog-to-digital converter signal, and SPI / Microsoft Management Console (MMC).

3. The BMC system of claim 1 further includes a memory accessible by the BMC CPU chip, wherein the memory stores the firmware.

4. The BMC system of claim 1, wherein the BMC CPU chip includes a plurality of input / output interfaces, which are coupled to the processor via an internal bus.

5. The BMC system of claim 1 further includes a second interface chip coupled to the BMC CPU chip via the external bus, the second interface chip including multiple input / output interfaces for use by these different communication protocols, and connected to multiple components on the computer node or another computer node.

6. A multi-node computer system, comprising: The substrate has a baseboard management controller (BMC) central processing unit (CPU) chip and a memory, the memory storing firmware for use by the BMC CPU chip, the BMC CPU chip including a processor and an external bus interface. An external bus is coupled to the external bus interface of the BMC CPU chip; The first computer node has a first BMC interface chip, which is coupled to the external bus and multiple components on the first computer node. The first BMC interface chip includes multiple input / output interfaces for use by multiple different communication protocols. as well as The second computer node has a second BMC interface chip, which is coupled to the external bus and multiple components on the second computer node. The second BMC interface chip includes multiple input / output interfaces for use with multiple different communication protocols. The input / output interfaces of the first BMC interface chip and the second BMC interface chip operate independently of the firmware, and neither the first BMC interface chip nor the second BMC interface chip requires firmware. The first BMC interface chip and the second BMC interface chip transmit data obtained by the input / output interface through different communication protocols to the BMC CPU chip via the external bus. The BMC CPU chip monitors the operation of the first computer node and the second computer node based on the same set of firmware.

7. The multi-node computer system of claim 6, wherein the first BMC interface chip and the second BMC interface chip include a plurality of input / output interfaces, which operate independently of the firmware.

8. The multi-node computer system of claim 6, wherein the substrate includes a memory that stores the firmware, the firmware being accessible by the BMC CPU chip.

9. The multi-node computer system of claim 6, wherein the BMC CPU chip includes multiple interfaces coupled to the processor via an internal bus.

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